1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Copyright 2011 Tilera Corporation. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation, version 2. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef __DOXYGEN__ 17 18#ifndef __ARCH_SPR_DEF_64_H__ 19#define __ARCH_SPR_DEF_64_H__ 20 21#define SPR_AUX_PERF_COUNT_0 0x2105 22#define SPR_AUX_PERF_COUNT_1 0x2106 23#define SPR_AUX_PERF_COUNT_CTL 0x2107 24#define SPR_AUX_PERF_COUNT_STS 0x2108 25#define SPR_CMPEXCH_VALUE 0x2780 26#define SPR_CYCLE 0x2781 27#define SPR_DONE 0x2705 28#define SPR_DSTREAM_PF 0x2706 29#define SPR_EVENT_BEGIN 0x2782 30#define SPR_EVENT_END 0x2783 31#define SPR_EX_CONTEXT_0_0 0x2580 32#define SPR_EX_CONTEXT_0_1 0x2581 33#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 34#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 35#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 36#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 37#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 38#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 39#define SPR_EX_CONTEXT_1_0 0x2480 40#define SPR_EX_CONTEXT_1_1 0x2481 41#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 42#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 43#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 44#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 45#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 46#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 47#define SPR_EX_CONTEXT_2_0 0x2380 48#define SPR_EX_CONTEXT_2_1 0x2381 49#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 50#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 51#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 52#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 53#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 54#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 55#define SPR_FAIL 0x2707 56#define SPR_IDN_AVAIL_EN 0x1a05 57#define SPR_IDN_DATA_AVAIL 0x0a80 58#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 59#define SPR_IDN_DEMUX_COUNT_0 0x0a05 60#define SPR_IDN_DEMUX_COUNT_1 0x0a06 61#define SPR_IDN_DIRECTION_PROTECT 0x1405 62#define SPR_IDN_PENDING 0x0a08 63#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 64#define SPR_INTCTRL_0_STATUS 0x2505 65#define SPR_INTCTRL_1_STATUS 0x2405 66#define SPR_INTCTRL_2_STATUS 0x2305 67#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 68#define SPR_INTERRUPT_MASK_0 0x2506 69#define SPR_INTERRUPT_MASK_1 0x2406 70#define SPR_INTERRUPT_MASK_2 0x2306 71#define SPR_INTERRUPT_MASK_RESET_0 0x2507 72#define SPR_INTERRUPT_MASK_RESET_1 0x2407 73#define SPR_INTERRUPT_MASK_RESET_2 0x2307 74#define SPR_INTERRUPT_MASK_SET_0 0x2508 75#define SPR_INTERRUPT_MASK_SET_1 0x2408 76#define SPR_INTERRUPT_MASK_SET_2 0x2308 77#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 78#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 79#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 80#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 81#define SPR_IPI_EVENT_0 0x1f05 82#define SPR_IPI_EVENT_1 0x1e05 83#define SPR_IPI_EVENT_2 0x1d05 84#define SPR_IPI_EVENT_RESET_0 0x1f06 85#define SPR_IPI_EVENT_RESET_1 0x1e06 86#define SPR_IPI_EVENT_RESET_2 0x1d06 87#define SPR_IPI_EVENT_SET_0 0x1f07 88#define SPR_IPI_EVENT_SET_1 0x1e07 89#define SPR_IPI_EVENT_SET_2 0x1d07 90#define SPR_IPI_MASK_0 0x1f08 91#define SPR_IPI_MASK_1 0x1e08 92#define SPR_IPI_MASK_2 0x1d08 93#define SPR_IPI_MASK_RESET_0 0x1f09 94#define SPR_IPI_MASK_RESET_1 0x1e09 95#define SPR_IPI_MASK_RESET_2 0x1d09 96#define SPR_IPI_MASK_SET_0 0x1f0a 97#define SPR_IPI_MASK_SET_1 0x1e0a 98#define SPR_IPI_MASK_SET_2 0x1d0a 99#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 100#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 101#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 102#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 103#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 104#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 105#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 106#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 107#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 108#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 109#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 110#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 111#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 112#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 113#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 114#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 115#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 116#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 117#define SPR_MPL_IDN_TIMER_SET_0 0x1800 118#define SPR_MPL_IDN_TIMER_SET_1 0x1801 119#define SPR_MPL_IDN_TIMER_SET_2 0x1802 120#define SPR_MPL_INTCTRL_0_SET_0 0x2500 121#define SPR_MPL_INTCTRL_0_SET_1 0x2501 122#define SPR_MPL_INTCTRL_0_SET_2 0x2502 123#define SPR_MPL_INTCTRL_1_SET_0 0x2400 124#define SPR_MPL_INTCTRL_1_SET_1 0x2401 125#define SPR_MPL_INTCTRL_1_SET_2 0x2402 126#define SPR_MPL_INTCTRL_2_SET_0 0x2300 127#define SPR_MPL_INTCTRL_2_SET_1 0x2301 128#define SPR_MPL_INTCTRL_2_SET_2 0x2302 129#define SPR_MPL_IPI_0 0x1f04 130#define SPR_MPL_IPI_0_SET_0 0x1f00 131#define SPR_MPL_IPI_0_SET_1 0x1f01 132#define SPR_MPL_IPI_0_SET_2 0x1f02 133#define SPR_MPL_IPI_1 0x1e04 134#define SPR_MPL_IPI_1_SET_0 0x1e00 135#define SPR_MPL_IPI_1_SET_1 0x1e01 136#define SPR_MPL_IPI_1_SET_2 0x1e02 137#define SPR_MPL_IPI_2 0x1d04 138#define SPR_MPL_IPI_2_SET_0 0x1d00 139#define SPR_MPL_IPI_2_SET_1 0x1d01 140#define SPR_MPL_IPI_2_SET_2 0x1d02 141#define SPR_MPL_PERF_COUNT_SET_0 0x2000 142#define SPR_MPL_PERF_COUNT_SET_1 0x2001 143#define SPR_MPL_PERF_COUNT_SET_2 0x2002 144#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00 145#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01 146#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02 147#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00 148#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01 149#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02 150#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600 151#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601 152#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602 153#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500 154#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501 155#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502 156#define SPR_MPL_UDN_TIMER_SET_0 0x1900 157#define SPR_MPL_UDN_TIMER_SET_1 0x1901 158#define SPR_MPL_UDN_TIMER_SET_2 0x1902 159#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700 160#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701 161#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702 162#define SPR_PASS 0x2709 163#define SPR_PERF_COUNT_0 0x2005 164#define SPR_PERF_COUNT_1 0x2006 165#define SPR_PERF_COUNT_CTL 0x2007 166#define SPR_PERF_COUNT_DN_CTL 0x2008 167#define SPR_PERF_COUNT_STS 0x2009 168#define SPR_PROC_STATUS 0x2784 169#define SPR_SIM_CONTROL 0x2785 170#define SPR_SINGLE_STEP_CONTROL_0 0x0405 171#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1 172#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2 173#define SPR_SINGLE_STEP_CONTROL_1 0x0305 174#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1 175#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2 176#define SPR_SINGLE_STEP_CONTROL_2 0x0205 177#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1 178#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2 179#define SPR_SINGLE_STEP_EN_0_0 0x250a 180#define SPR_SINGLE_STEP_EN_0_1 0x240a 181#define SPR_SINGLE_STEP_EN_0_2 0x230a 182#define SPR_SINGLE_STEP_EN_1_0 0x250b 183#define SPR_SINGLE_STEP_EN_1_1 0x240b 184#define SPR_SINGLE_STEP_EN_1_2 0x230b 185#define SPR_SINGLE_STEP_EN_2_0 0x250c 186#define SPR_SINGLE_STEP_EN_2_1 0x240c 187#define SPR_SINGLE_STEP_EN_2_2 0x230c 188#define SPR_SYSTEM_SAVE_0_0 0x2582 189#define SPR_SYSTEM_SAVE_0_1 0x2583 190#define SPR_SYSTEM_SAVE_0_2 0x2584 191#define SPR_SYSTEM_SAVE_0_3 0x2585 192#define SPR_SYSTEM_SAVE_1_0 0x2482 193#define SPR_SYSTEM_SAVE_1_1 0x2483 194#define SPR_SYSTEM_SAVE_1_2 0x2484 195#define SPR_SYSTEM_SAVE_1_3 0x2485 196#define SPR_SYSTEM_SAVE_2_0 0x2382 197#define SPR_SYSTEM_SAVE_2_1 0x2383 198#define SPR_SYSTEM_SAVE_2_2 0x2384 199#define SPR_SYSTEM_SAVE_2_3 0x2385 200#define SPR_TILE_COORD 0x270b 201#define SPR_TILE_RTF_HWM 0x270c 202#define SPR_TILE_TIMER_CONTROL 0x1605 203#define SPR_UDN_AVAIL_EN 0x1b05 204#define SPR_UDN_DATA_AVAIL 0x0b80 205#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906 206#define SPR_UDN_DEMUX_COUNT_0 0x0b05 207#define SPR_UDN_DEMUX_COUNT_1 0x0b06 208#define SPR_UDN_DEMUX_COUNT_2 0x0b07 209#define SPR_UDN_DEMUX_COUNT_3 0x0b08 210#define SPR_UDN_DIRECTION_PROTECT 0x1505 211#define SPR_UDN_PENDING 0x0b0a 212#define SPR_WATCH_MASK 0x200a 213#define SPR_WATCH_VAL 0x200b 214 215#endif /* !defined(__ARCH_SPR_DEF_64_H__) */ 216 217#endif /* !defined(__DOXYGEN__) */ 218