LXR linux/arch/x86/include/asm/microcode.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_MICROCODE_H
   3#define _ASM_X86_MICROCODE_H
   4
   5#include <asm/cpu.h>
   6#include <linux/earlycpio.h>
   7#include <linux/initrd.h>
   8
   9#define native_rdmsr(msr, val1, val2)                   \
  10do {                                                    \
  11        u64 __val = __rdmsr((msr));                     \
  12        (void)((val1) = (u32)__val);                    \
  13        (void)((val2) = (u32)(__val >> 32));            \
  14} while (0)
  15
  16#define native_wrmsr(msr, low, high)                    \
  17        __wrmsr(msr, low, high)
  18
  19#define native_wrmsrl(msr, val)                         \
  20        __wrmsr((msr), (u32)((u64)(val)),               \
  21                       (u32)((u64)(val) >> 32))
  22
  23struct ucode_patch {
  24        struct list_head plist;
  25        void *data;             /* Intel uses only this one */
  26        u32 patch_id;
  27        u16 equiv_cpu;
  28};
  29
  30extern struct list_head microcode_cache;
  31
  32struct cpu_signature {
  33        unsigned int sig;
  34        unsigned int pf;
  35        unsigned int rev;
  36};
  37
  38struct device;
  39
  40enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
  41
  42struct microcode_ops {
  43        enum ucode_state (*request_microcode_user) (int cpu,
  44                                const void __user *buf, size_t size);
  45
  46        enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
  47                                                  bool refresh_fw);
  48
  49        void (*microcode_fini_cpu) (int cpu);
  50
  51        /*
  52         * The generic 'microcode_core' part guarantees that
  53         * the callbacks below run on a target cpu when they
  54         * are being called.
  55         * See also the "Synchronization" section in microcode_core.c.
  56         */
  57        int (*apply_microcode) (int cpu);
  58        int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
  59};
  60
  61struct ucode_cpu_info {
  62        struct cpu_signature    cpu_sig;
  63        int                     valid;
  64        void                    *mc;
  65};
  66extern struct ucode_cpu_info ucode_cpu_info[];
  67struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
  68
  69#ifdef CONFIG_MICROCODE_INTEL
  70extern struct microcode_ops * __init init_intel_microcode(void);
  71#else
  72static inline struct microcode_ops * __init init_intel_microcode(void)
  73{
  74        return NULL;
  75}
  76#endif /* CONFIG_MICROCODE_INTEL */
  77
  78#ifdef CONFIG_MICROCODE_AMD
  79extern struct microcode_ops * __init init_amd_microcode(void);
  80extern void __exit exit_amd_microcode(void);
  81#else
  82static inline struct microcode_ops * __init init_amd_microcode(void)
  83{
  84        return NULL;
  85}
  86static inline void __exit exit_amd_microcode(void) {}
  87#endif
  88
  89#define MAX_UCODE_COUNT 128
  90
  91#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
  92#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
  93#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
  94#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
  95#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
  96#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
  97#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
  98
  99#define CPUID_IS(a, b, c, ebx, ecx, edx)        \
 100                (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
 101
 102/*
 103 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
 104 * x86_cpuid_vendor() gets vendor id for BSP.
 105 *
 106 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
 107 * coding, we still use x86_cpuid_vendor() to get vendor id for AP.
 108 *
 109 * x86_cpuid_vendor() gets vendor information directly from CPUID.
 110 */
 111static inline int x86_cpuid_vendor(void)
 112{
 113        u32 eax = 0x00000000;
 114        u32 ebx, ecx = 0, edx;
 115
 116        native_cpuid(&eax, &ebx, &ecx, &edx);
 117
 118        if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
 119                return X86_VENDOR_INTEL;
 120
 121        if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
 122                return X86_VENDOR_AMD;
 123
 124        return X86_VENDOR_UNKNOWN;
 125}
 126
 127static inline unsigned int x86_cpuid_family(void)
 128{
 129        u32 eax = 0x00000001;
 130        u32 ebx, ecx = 0, edx;
 131
 132        native_cpuid(&eax, &ebx, &ecx, &edx);
 133
 134        return x86_family(eax);
 135}
 136
 137#ifdef CONFIG_MICROCODE
 138int __init microcode_init(void);
 139extern void __init load_ucode_bsp(void);
 140extern void load_ucode_ap(void);
 141void reload_early_microcode(void);
 142extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
 143extern bool initrd_gone;
 144#else
 145static inline int __init microcode_init(void)                   { return 0; };
 146static inline void __init load_ucode_bsp(void)                  { }
 147static inline void load_ucode_ap(void)                          { }
 148static inline void reload_early_microcode(void)                 { }
 149static inline bool
 150get_builtin_firmware(struct cpio_data *cd, const char *name)    { return false; }
 151#endif
 152
 153#endif /* _ASM_X86_MICROCODE_H */
 154