1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * x86 TSC related functions 4 */ 5#ifndef _ASM_X86_TSC_H 6#define _ASM_X86_TSC_H 7 8#include <asm/processor.h> 9 10#define NS_SCALE 10 /* 2^10, carefully chosen */ 11#define US_SCALE 32 /* 2^32, arbitralrily chosen */ 12 13/* 14 * Standard way to access the cycle counter. 15 */ 16typedef unsigned long long cycles_t; 17 18extern unsigned int cpu_khz; 19extern unsigned int tsc_khz; 20 21extern void disable_TSC(void); 22 23static inline cycles_t get_cycles(void) 24{ 25#ifndef CONFIG_X86_TSC 26 if (!boot_cpu_has(X86_FEATURE_TSC)) 27 return 0; 28#endif 29 30 return rdtsc(); 31} 32 33extern struct system_counterval_t convert_art_to_tsc(u64 art); 34 35extern void tsc_init(void); 36extern void mark_tsc_unstable(char *reason); 37extern int unsynchronized_tsc(void); 38extern int check_tsc_unstable(void); 39extern unsigned long native_calibrate_cpu(void); 40extern unsigned long native_calibrate_tsc(void); 41extern unsigned long long native_sched_clock_from_tsc(u64 tsc); 42 43extern int tsc_clocksource_reliable; 44 45/* 46 * Boot-time check whether the TSCs are synchronized across 47 * all CPUs/cores: 48 */ 49#ifdef CONFIG_X86_TSC 50extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); 51extern void tsc_verify_tsc_adjust(bool resume); 52extern void check_tsc_sync_source(int cpu); 53extern void check_tsc_sync_target(void); 54#else 55static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } 56static inline void tsc_verify_tsc_adjust(bool resume) { } 57static inline void check_tsc_sync_source(int cpu) { } 58static inline void check_tsc_sync_target(void) { } 59#endif 60 61extern int notsc_setup(char *); 62extern void tsc_save_sched_clock_state(void); 63extern void tsc_restore_sched_clock_state(void); 64 65unsigned long cpu_khz_from_msr(void); 66 67#endif /* _ASM_X86_TSC_H */ 68