linux/arch/x86/pci/mmconfig-shared.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * mmconfig-shared.c - Low-level direct PCI config space access via
   4 *                     MMCONFIG - common code between i386 and x86-64.
   5 *
   6 * This code does:
   7 * - known chipset handling
   8 * - ACPI decoding and validation
   9 *
  10 * Per-architecture code takes care of the mappings and accesses
  11 * themselves.
  12 */
  13
  14#include <linux/pci.h>
  15#include <linux/init.h>
  16#include <linux/sfi_acpi.h>
  17#include <linux/bitmap.h>
  18#include <linux/dmi.h>
  19#include <linux/slab.h>
  20#include <linux/mutex.h>
  21#include <linux/rculist.h>
  22#include <asm/e820/api.h>
  23#include <asm/pci_x86.h>
  24#include <asm/acpi.h>
  25
  26#define PREFIX "PCI: "
  27
  28/* Indicate if the mmcfg resources have been placed into the resource table. */
  29static bool pci_mmcfg_running_state;
  30static bool pci_mmcfg_arch_init_failed;
  31static DEFINE_MUTEX(pci_mmcfg_lock);
  32
  33LIST_HEAD(pci_mmcfg_list);
  34
  35static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
  36{
  37        if (cfg->res.parent)
  38                release_resource(&cfg->res);
  39        list_del(&cfg->list);
  40        kfree(cfg);
  41}
  42
  43static void __init free_all_mmcfg(void)
  44{
  45        struct pci_mmcfg_region *cfg, *tmp;
  46
  47        pci_mmcfg_arch_free();
  48        list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
  49                pci_mmconfig_remove(cfg);
  50}
  51
  52static void list_add_sorted(struct pci_mmcfg_region *new)
  53{
  54        struct pci_mmcfg_region *cfg;
  55
  56        /* keep list sorted by segment and starting bus number */
  57        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
  58                if (cfg->segment > new->segment ||
  59                    (cfg->segment == new->segment &&
  60                     cfg->start_bus >= new->start_bus)) {
  61                        list_add_tail_rcu(&new->list, &cfg->list);
  62                        return;
  63                }
  64        }
  65        list_add_tail_rcu(&new->list, &pci_mmcfg_list);
  66}
  67
  68static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
  69                                                   int end, u64 addr)
  70{
  71        struct pci_mmcfg_region *new;
  72        struct resource *res;
  73
  74        if (addr == 0)
  75                return NULL;
  76
  77        new = kzalloc(sizeof(*new), GFP_KERNEL);
  78        if (!new)
  79                return NULL;
  80
  81        new->address = addr;
  82        new->segment = segment;
  83        new->start_bus = start;
  84        new->end_bus = end;
  85
  86        res = &new->res;
  87        res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
  88        res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
  89        res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  90        snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
  91                 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
  92        res->name = new->name;
  93
  94        return new;
  95}
  96
  97static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
  98                                                        int end, u64 addr)
  99{
 100        struct pci_mmcfg_region *new;
 101
 102        new = pci_mmconfig_alloc(segment, start, end, addr);
 103        if (new) {
 104                mutex_lock(&pci_mmcfg_lock);
 105                list_add_sorted(new);
 106                mutex_unlock(&pci_mmcfg_lock);
 107
 108                pr_info(PREFIX
 109                       "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
 110                       "(base %#lx)\n",
 111                       segment, start, end, &new->res, (unsigned long)addr);
 112        }
 113
 114        return new;
 115}
 116
 117struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 118{
 119        struct pci_mmcfg_region *cfg;
 120
 121        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 122                if (cfg->segment == segment &&
 123                    cfg->start_bus <= bus && bus <= cfg->end_bus)
 124                        return cfg;
 125
 126        return NULL;
 127}
 128
 129static const char *__init pci_mmcfg_e7520(void)
 130{
 131        u32 win;
 132        raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
 133
 134        win = win & 0xf000;
 135        if (win == 0x0000 || win == 0xf000)
 136                return NULL;
 137
 138        if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
 139                return NULL;
 140
 141        return "Intel Corporation E7520 Memory Controller Hub";
 142}
 143
 144static const char *__init pci_mmcfg_intel_945(void)
 145{
 146        u32 pciexbar, mask = 0, len = 0;
 147
 148        raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 149
 150        /* Enable bit */
 151        if (!(pciexbar & 1))
 152                return NULL;
 153
 154        /* Size bits */
 155        switch ((pciexbar >> 1) & 3) {
 156        case 0:
 157                mask = 0xf0000000U;
 158                len  = 0x10000000U;
 159                break;
 160        case 1:
 161                mask = 0xf8000000U;
 162                len  = 0x08000000U;
 163                break;
 164        case 2:
 165                mask = 0xfc000000U;
 166                len  = 0x04000000U;
 167                break;
 168        default:
 169                return NULL;
 170        }
 171
 172        /* Errata #2, things break when not aligned on a 256Mb boundary */
 173        /* Can only happen in 64M/128M mode */
 174
 175        if ((pciexbar & mask) & 0x0fffffffU)
 176                return NULL;
 177
 178        /* Don't hit the APIC registers and their friends */
 179        if ((pciexbar & mask) >= 0xf0000000U)
 180                return NULL;
 181
 182        if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 183                return NULL;
 184
 185        return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 186}
 187
 188static const char *__init pci_mmcfg_amd_fam10h(void)
 189{
 190        u32 low, high, address;
 191        u64 base, msr;
 192        int i;
 193        unsigned segnbits = 0, busnbits, end_bus;
 194
 195        if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 196                return NULL;
 197
 198        address = MSR_FAM10H_MMIO_CONF_BASE;
 199        if (rdmsr_safe(address, &low, &high))
 200                return NULL;
 201
 202        msr = high;
 203        msr <<= 32;
 204        msr |= low;
 205
 206        /* mmconfig is not enable */
 207        if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 208                return NULL;
 209
 210        base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 211
 212        busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 213                         FAM10H_MMIO_CONF_BUSRANGE_MASK;
 214
 215        /*
 216         * only handle bus 0 ?
 217         * need to skip it
 218         */
 219        if (!busnbits)
 220                return NULL;
 221
 222        if (busnbits > 8) {
 223                segnbits = busnbits - 8;
 224                busnbits = 8;
 225        }
 226
 227        end_bus = (1 << busnbits) - 1;
 228        for (i = 0; i < (1 << segnbits); i++)
 229                if (pci_mmconfig_add(i, 0, end_bus,
 230                                     base + (1<<28) * i) == NULL) {
 231                        free_all_mmcfg();
 232                        return NULL;
 233                }
 234
 235        return "AMD Family 10h NB";
 236}
 237
 238static bool __initdata mcp55_checked;
 239static const char *__init pci_mmcfg_nvidia_mcp55(void)
 240{
 241        int bus;
 242        int mcp55_mmconf_found = 0;
 243
 244        static const u32 extcfg_regnum __initconst      = 0x90;
 245        static const u32 extcfg_regsize __initconst     = 4;
 246        static const u32 extcfg_enable_mask __initconst = 1 << 31;
 247        static const u32 extcfg_start_mask __initconst  = 0xff << 16;
 248        static const int extcfg_start_shift __initconst = 16;
 249        static const u32 extcfg_size_mask __initconst   = 0x3 << 28;
 250        static const int extcfg_size_shift __initconst  = 28;
 251        static const int extcfg_sizebus[] __initconst   = {
 252                0x100, 0x80, 0x40, 0x20
 253        };
 254        static const u32 extcfg_base_mask[] __initconst = {
 255                0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
 256        };
 257        static const int extcfg_base_lshift __initconst = 25;
 258
 259        /*
 260         * do check if amd fam10h already took over
 261         */
 262        if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
 263                return NULL;
 264
 265        mcp55_checked = true;
 266        for (bus = 0; bus < 256; bus++) {
 267                u64 base;
 268                u32 l, extcfg;
 269                u16 vendor, device;
 270                int start, size_index, end;
 271
 272                raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 273                vendor = l & 0xffff;
 274                device = (l >> 16) & 0xffff;
 275
 276                if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 277                        continue;
 278
 279                raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 280                                  extcfg_regsize, &extcfg);
 281
 282                if (!(extcfg & extcfg_enable_mask))
 283                        continue;
 284
 285                size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 286                base = extcfg & extcfg_base_mask[size_index];
 287                /* base could > 4G */
 288                base <<= extcfg_base_lshift;
 289                start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 290                end = start + extcfg_sizebus[size_index] - 1;
 291                if (pci_mmconfig_add(0, start, end, base) == NULL)
 292                        continue;
 293                mcp55_mmconf_found++;
 294        }
 295
 296        if (!mcp55_mmconf_found)
 297                return NULL;
 298
 299        return "nVidia MCP55";
 300}
 301
 302struct pci_mmcfg_hostbridge_probe {
 303        u32 bus;
 304        u32 devfn;
 305        u32 vendor;
 306        u32 device;
 307        const char *(*probe)(void);
 308};
 309
 310static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
 311        { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 312          PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 313        { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 314          PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 315        { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 316          0x1200, pci_mmcfg_amd_fam10h },
 317        { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 318          0x1200, pci_mmcfg_amd_fam10h },
 319        { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 320          0x0369, pci_mmcfg_nvidia_mcp55 },
 321};
 322
 323static void __init pci_mmcfg_check_end_bus_number(void)
 324{
 325        struct pci_mmcfg_region *cfg, *cfgx;
 326
 327        /* Fixup overlaps */
 328        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 329                if (cfg->end_bus < cfg->start_bus)
 330                        cfg->end_bus = 255;
 331
 332                /* Don't access the list head ! */
 333                if (cfg->list.next == &pci_mmcfg_list)
 334                        break;
 335
 336                cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
 337                if (cfg->end_bus >= cfgx->start_bus)
 338                        cfg->end_bus = cfgx->start_bus - 1;
 339        }
 340}
 341
 342static int __init pci_mmcfg_check_hostbridge(void)
 343{
 344        u32 l;
 345        u32 bus, devfn;
 346        u16 vendor, device;
 347        int i;
 348        const char *name;
 349
 350        if (!raw_pci_ops)
 351                return 0;
 352
 353        free_all_mmcfg();
 354
 355        for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 356                bus =  pci_mmcfg_probes[i].bus;
 357                devfn = pci_mmcfg_probes[i].devfn;
 358                raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 359                vendor = l & 0xffff;
 360                device = (l >> 16) & 0xffff;
 361
 362                name = NULL;
 363                if (pci_mmcfg_probes[i].vendor == vendor &&
 364                    pci_mmcfg_probes[i].device == device)
 365                        name = pci_mmcfg_probes[i].probe();
 366
 367                if (name)
 368                        pr_info(PREFIX "%s with MMCONFIG support\n", name);
 369        }
 370
 371        /* some end_bus_number is crazy, fix it */
 372        pci_mmcfg_check_end_bus_number();
 373
 374        return !list_empty(&pci_mmcfg_list);
 375}
 376
 377static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
 378{
 379        struct resource *mcfg_res = data;
 380        struct acpi_resource_address64 address;
 381        acpi_status status;
 382
 383        if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 384                struct acpi_resource_fixed_memory32 *fixmem32 =
 385                        &res->data.fixed_memory32;
 386                if (!fixmem32)
 387                        return AE_OK;
 388                if ((mcfg_res->start >= fixmem32->address) &&
 389                    (mcfg_res->end < (fixmem32->address +
 390                                      fixmem32->address_length))) {
 391                        mcfg_res->flags = 1;
 392                        return AE_CTRL_TERMINATE;
 393                }
 394        }
 395        if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 396            (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 397                return AE_OK;
 398
 399        status = acpi_resource_to_address64(res, &address);
 400        if (ACPI_FAILURE(status) ||
 401           (address.address.address_length <= 0) ||
 402           (address.resource_type != ACPI_MEMORY_RANGE))
 403                return AE_OK;
 404
 405        if ((mcfg_res->start >= address.address.minimum) &&
 406            (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
 407                mcfg_res->flags = 1;
 408                return AE_CTRL_TERMINATE;
 409        }
 410        return AE_OK;
 411}
 412
 413static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
 414                                        void *context, void **rv)
 415{
 416        struct resource *mcfg_res = context;
 417
 418        acpi_walk_resources(handle, METHOD_NAME__CRS,
 419                            check_mcfg_resource, context);
 420
 421        if (mcfg_res->flags)
 422                return AE_CTRL_TERMINATE;
 423
 424        return AE_OK;
 425}
 426
 427static bool is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 428{
 429        struct resource mcfg_res;
 430
 431        mcfg_res.start = start;
 432        mcfg_res.end = end - 1;
 433        mcfg_res.flags = 0;
 434
 435        acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 436
 437        if (!mcfg_res.flags)
 438                acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 439                                 NULL);
 440
 441        return mcfg_res.flags;
 442}
 443
 444typedef bool (*check_reserved_t)(u64 start, u64 end, unsigned type);
 445
 446static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,
 447                                     struct pci_mmcfg_region *cfg,
 448                                     struct device *dev, int with_e820)
 449{
 450        u64 addr = cfg->res.start;
 451        u64 size = resource_size(&cfg->res);
 452        u64 old_size = size;
 453        int num_buses;
 454        char *method = with_e820 ? "E820" : "ACPI motherboard resources";
 455
 456        while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {
 457                size >>= 1;
 458                if (size < (16UL<<20))
 459                        break;
 460        }
 461
 462        if (size < (16UL<<20) && size != old_size)
 463                return 0;
 464
 465        if (dev)
 466                dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
 467                         &cfg->res, method);
 468        else
 469                pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
 470                       &cfg->res, method);
 471
 472        if (old_size != size) {
 473                /* update end_bus */
 474                cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
 475                num_buses = cfg->end_bus - cfg->start_bus + 1;
 476                cfg->res.end = cfg->res.start +
 477                    PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
 478                snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
 479                         "PCI MMCONFIG %04x [bus %02x-%02x]",
 480                         cfg->segment, cfg->start_bus, cfg->end_bus);
 481
 482                if (dev)
 483                        dev_info(dev,
 484                                "MMCONFIG "
 485                                "at %pR (base %#lx) (size reduced!)\n",
 486                                &cfg->res, (unsigned long) cfg->address);
 487                else
 488                        pr_info(PREFIX
 489                                "MMCONFIG for %04x [bus%02x-%02x] "
 490                                "at %pR (base %#lx) (size reduced!)\n",
 491                                cfg->segment, cfg->start_bus, cfg->end_bus,
 492                                &cfg->res, (unsigned long) cfg->address);
 493        }
 494
 495        return 1;
 496}
 497
 498static bool __ref
 499pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int early)
 500{
 501        if (!early && !acpi_disabled) {
 502                if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
 503                        return 1;
 504
 505                if (dev)
 506                        dev_info(dev, FW_INFO
 507                                 "MMCONFIG at %pR not reserved in "
 508                                 "ACPI motherboard resources\n",
 509                                 &cfg->res);
 510                else
 511                        pr_info(FW_INFO PREFIX
 512                               "MMCONFIG at %pR not reserved in "
 513                               "ACPI motherboard resources\n",
 514                               &cfg->res);
 515        }
 516
 517        /*
 518         * e820__mapped_all() is marked as __init.
 519         * All entries from ACPI MCFG table have been checked at boot time.
 520         * For MCFG information constructed from hotpluggable host bridge's
 521         * _CBA method, just assume it's reserved.
 522         */
 523        if (pci_mmcfg_running_state)
 524                return 1;
 525
 526        /* Don't try to do this check unless configuration
 527           type 1 is available. how about type 2 ?*/
 528        if (raw_pci_ops)
 529                return is_mmconf_reserved(e820__mapped_all, cfg, dev, 1);
 530
 531        return 0;
 532}
 533
 534static void __init pci_mmcfg_reject_broken(int early)
 535{
 536        struct pci_mmcfg_region *cfg;
 537
 538        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 539                if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
 540                        pr_info(PREFIX "not using MMCONFIG\n");
 541                        free_all_mmcfg();
 542                        return;
 543                }
 544        }
 545}
 546
 547static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 548                                        struct acpi_mcfg_allocation *cfg)
 549{
 550        int year;
 551
 552        if (cfg->address < 0xFFFFFFFF)
 553                return 0;
 554
 555        if (!strncmp(mcfg->header.oem_id, "SGI", 3))
 556                return 0;
 557
 558        if (mcfg->header.revision >= 1) {
 559                if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 560                    year >= 2010)
 561                        return 0;
 562        }
 563
 564        pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
 565               "is above 4GB, ignored\n", cfg->pci_segment,
 566               cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 567        return -EINVAL;
 568}
 569
 570static int __init pci_parse_mcfg(struct acpi_table_header *header)
 571{
 572        struct acpi_table_mcfg *mcfg;
 573        struct acpi_mcfg_allocation *cfg_table, *cfg;
 574        unsigned long i;
 575        int entries;
 576
 577        if (!header)
 578                return -EINVAL;
 579
 580        mcfg = (struct acpi_table_mcfg *)header;
 581
 582        /* how many config structures do we have */
 583        free_all_mmcfg();
 584        entries = 0;
 585        i = header->length - sizeof(struct acpi_table_mcfg);
 586        while (i >= sizeof(struct acpi_mcfg_allocation)) {
 587                entries++;
 588                i -= sizeof(struct acpi_mcfg_allocation);
 589        }
 590        if (entries == 0) {
 591                pr_err(PREFIX "MMCONFIG has no entries\n");
 592                return -ENODEV;
 593        }
 594
 595        cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 596        for (i = 0; i < entries; i++) {
 597                cfg = &cfg_table[i];
 598                if (acpi_mcfg_check_entry(mcfg, cfg)) {
 599                        free_all_mmcfg();
 600                        return -ENODEV;
 601                }
 602
 603                if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 604                                   cfg->end_bus_number, cfg->address) == NULL) {
 605                        pr_warn(PREFIX "no memory for MCFG entries\n");
 606                        free_all_mmcfg();
 607                        return -ENOMEM;
 608                }
 609        }
 610
 611        return 0;
 612}
 613
 614#ifdef CONFIG_ACPI_APEI
 615extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
 616                                     void *data), void *data);
 617
 618static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
 619                                     void *data), void *data)
 620{
 621        struct pci_mmcfg_region *cfg;
 622        int rc;
 623
 624        if (list_empty(&pci_mmcfg_list))
 625                return 0;
 626
 627        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 628                rc = func(cfg->res.start, resource_size(&cfg->res), data);
 629                if (rc)
 630                        return rc;
 631        }
 632
 633        return 0;
 634}
 635#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
 636#else
 637#define set_apei_filter()
 638#endif
 639
 640static void __init __pci_mmcfg_init(int early)
 641{
 642        pci_mmcfg_reject_broken(early);
 643        if (list_empty(&pci_mmcfg_list))
 644                return;
 645
 646        if (pcibios_last_bus < 0) {
 647                const struct pci_mmcfg_region *cfg;
 648
 649                list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 650                        if (cfg->segment)
 651                                break;
 652                        pcibios_last_bus = cfg->end_bus;
 653                }
 654        }
 655
 656        if (pci_mmcfg_arch_init())
 657                pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 658        else {
 659                free_all_mmcfg();
 660                pci_mmcfg_arch_init_failed = true;
 661        }
 662}
 663
 664static int __initdata known_bridge;
 665
 666void __init pci_mmcfg_early_init(void)
 667{
 668        if (pci_probe & PCI_PROBE_MMCONF) {
 669                if (pci_mmcfg_check_hostbridge())
 670                        known_bridge = 1;
 671                else
 672                        acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 673                __pci_mmcfg_init(1);
 674
 675                set_apei_filter();
 676        }
 677}
 678
 679void __init pci_mmcfg_late_init(void)
 680{
 681        /* MMCONFIG disabled */
 682        if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 683                return;
 684
 685        if (known_bridge)
 686                return;
 687
 688        /* MMCONFIG hasn't been enabled yet, try again */
 689        if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
 690                acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 691                __pci_mmcfg_init(0);
 692        }
 693}
 694
 695static int __init pci_mmcfg_late_insert_resources(void)
 696{
 697        struct pci_mmcfg_region *cfg;
 698
 699        pci_mmcfg_running_state = true;
 700
 701        /* If we are not using MMCONFIG, don't insert the resources. */
 702        if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 703                return 1;
 704
 705        /*
 706         * Attempt to insert the mmcfg resources but not with the busy flag
 707         * marked so it won't cause request errors when __request_region is
 708         * called.
 709         */
 710        list_for_each_entry(cfg, &pci_mmcfg_list, list)
 711                if (!cfg->res.parent)
 712                        insert_resource(&iomem_resource, &cfg->res);
 713
 714        return 0;
 715}
 716
 717/*
 718 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 719 * misprogrammed MCFG tables that state larger sizes but actually conflict
 720 * with other system resources.
 721 */
 722late_initcall(pci_mmcfg_late_insert_resources);
 723
 724/* Add MMCFG information for host bridges */
 725int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
 726                        phys_addr_t addr)
 727{
 728        int rc;
 729        struct resource *tmp = NULL;
 730        struct pci_mmcfg_region *cfg;
 731
 732        if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
 733                return -ENODEV;
 734
 735        if (start > end)
 736                return -EINVAL;
 737
 738        mutex_lock(&pci_mmcfg_lock);
 739        cfg = pci_mmconfig_lookup(seg, start);
 740        if (cfg) {
 741                if (cfg->end_bus < end)
 742                        dev_info(dev, FW_INFO
 743                                 "MMCONFIG for "
 744                                 "domain %04x [bus %02x-%02x] "
 745                                 "only partially covers this bridge\n",
 746                                  cfg->segment, cfg->start_bus, cfg->end_bus);
 747                mutex_unlock(&pci_mmcfg_lock);
 748                return -EEXIST;
 749        }
 750
 751        if (!addr) {
 752                mutex_unlock(&pci_mmcfg_lock);
 753                return -EINVAL;
 754        }
 755
 756        rc = -EBUSY;
 757        cfg = pci_mmconfig_alloc(seg, start, end, addr);
 758        if (cfg == NULL) {
 759                dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
 760                rc = -ENOMEM;
 761        } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
 762                dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
 763                         &cfg->res);
 764        } else {
 765                /* Insert resource if it's not in boot stage */
 766                if (pci_mmcfg_running_state)
 767                        tmp = insert_resource_conflict(&iomem_resource,
 768                                                       &cfg->res);
 769
 770                if (tmp) {
 771                        dev_warn(dev,
 772                                 "MMCONFIG %pR conflicts with "
 773                                 "%s %pR\n",
 774                                 &cfg->res, tmp->name, tmp);
 775                } else if (pci_mmcfg_arch_map(cfg)) {
 776                        dev_warn(dev, "fail to map MMCONFIG %pR.\n",
 777                                 &cfg->res);
 778                } else {
 779                        list_add_sorted(cfg);
 780                        dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
 781                                 &cfg->res, (unsigned long)addr);
 782                        cfg = NULL;
 783                        rc = 0;
 784                }
 785        }
 786
 787        if (cfg) {
 788                if (cfg->res.parent)
 789                        release_resource(&cfg->res);
 790                kfree(cfg);
 791        }
 792
 793        mutex_unlock(&pci_mmcfg_lock);
 794
 795        return rc;
 796}
 797
 798/* Delete MMCFG information for host bridges */
 799int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
 800{
 801        struct pci_mmcfg_region *cfg;
 802
 803        mutex_lock(&pci_mmcfg_lock);
 804        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 805                if (cfg->segment == seg && cfg->start_bus == start &&
 806                    cfg->end_bus == end) {
 807                        list_del_rcu(&cfg->list);
 808                        synchronize_rcu();
 809                        pci_mmcfg_arch_unmap(cfg);
 810                        if (cfg->res.parent)
 811                                release_resource(&cfg->res);
 812                        mutex_unlock(&pci_mmcfg_lock);
 813                        kfree(cfg);
 814                        return 0;
 815                }
 816        mutex_unlock(&pci_mmcfg_lock);
 817
 818        return -ENOENT;
 819}
 820