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35#ifndef _AHCI_H
36#define _AHCI_H
37
38#include <linux/pci.h>
39#include <linux/clk.h>
40#include <linux/libata.h>
41#include <linux/phy/phy.h>
42#include <linux/regulator/consumer.h>
43
44
45#define EM_CTRL_MSG_TYPE 0x000f0000
46
47
48#define EM_MSG_LED_HBA_PORT 0x0000000f
49#define EM_MSG_LED_PMP_SLOT 0x0000ff00
50#define EM_MSG_LED_VALUE 0xffff0000
51#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
52#define EM_MSG_LED_VALUE_OFF 0xfff80000
53#define EM_MSG_LED_VALUE_ON 0x00010000
54
55enum {
56 AHCI_MAX_PORTS = 32,
57 AHCI_MAX_CLKS = 5,
58 AHCI_MAX_SG = 168,
59 AHCI_DMA_BOUNDARY = 0xffffffff,
60 AHCI_MAX_CMDS = 32,
61 AHCI_CMD_SZ = 32,
62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_RX_FIS_SZ = 256,
64 AHCI_CMD_TBL_CDB = 0x40,
65 AHCI_CMD_TBL_HDR_SZ = 0x80,
66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_RX_FIS_SZ,
70 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
71 AHCI_CMD_TBL_AR_SZ +
72 (AHCI_RX_FIS_SZ * 16),
73 AHCI_IRQ_ON_SG = (1 << 31),
74 AHCI_CMD_ATAPI = (1 << 5),
75 AHCI_CMD_WRITE = (1 << 6),
76 AHCI_CMD_PREFETCH = (1 << 7),
77 AHCI_CMD_RESET = (1 << 8),
78 AHCI_CMD_CLR_BUSY = (1 << 10),
79
80 RX_FIS_PIO_SETUP = 0x20,
81 RX_FIS_D2H_REG = 0x40,
82 RX_FIS_SDB = 0x58,
83 RX_FIS_UNK = 0x60,
84
85
86 HOST_CAP = 0x00,
87 HOST_CTL = 0x04,
88 HOST_IRQ_STAT = 0x08,
89 HOST_PORTS_IMPL = 0x0c,
90 HOST_VERSION = 0x10,
91 HOST_EM_LOC = 0x1c,
92 HOST_EM_CTL = 0x20,
93 HOST_CAP2 = 0x24,
94
95
96 HOST_RESET = (1 << 0),
97 HOST_IRQ_EN = (1 << 1),
98 HOST_MRSM = (1 << 2),
99 HOST_AHCI_EN = (1 << 31),
100
101
102 HOST_CAP_SXS = (1 << 5),
103 HOST_CAP_EMS = (1 << 6),
104 HOST_CAP_CCC = (1 << 7),
105 HOST_CAP_PART = (1 << 13),
106 HOST_CAP_SSC = (1 << 14),
107 HOST_CAP_PIO_MULTI = (1 << 15),
108 HOST_CAP_FBS = (1 << 16),
109 HOST_CAP_PMP = (1 << 17),
110 HOST_CAP_ONLY = (1 << 18),
111 HOST_CAP_CLO = (1 << 24),
112 HOST_CAP_LED = (1 << 25),
113 HOST_CAP_ALPM = (1 << 26),
114 HOST_CAP_SSS = (1 << 27),
115 HOST_CAP_MPS = (1 << 28),
116 HOST_CAP_SNTF = (1 << 29),
117 HOST_CAP_NCQ = (1 << 30),
118 HOST_CAP_64 = (1 << 31),
119
120
121 HOST_CAP2_BOH = (1 << 0),
122 HOST_CAP2_NVMHCI = (1 << 1),
123 HOST_CAP2_APST = (1 << 2),
124 HOST_CAP2_SDS = (1 << 3),
125 HOST_CAP2_SADM = (1 << 4),
126 HOST_CAP2_DESO = (1 << 5),
127
128
129 PORT_LST_ADDR = 0x00,
130 PORT_LST_ADDR_HI = 0x04,
131 PORT_FIS_ADDR = 0x08,
132 PORT_FIS_ADDR_HI = 0x0c,
133 PORT_IRQ_STAT = 0x10,
134 PORT_IRQ_MASK = 0x14,
135 PORT_CMD = 0x18,
136 PORT_TFDATA = 0x20,
137 PORT_SIG = 0x24,
138 PORT_CMD_ISSUE = 0x38,
139 PORT_SCR_STAT = 0x28,
140 PORT_SCR_CTL = 0x2c,
141 PORT_SCR_ERR = 0x30,
142 PORT_SCR_ACT = 0x34,
143 PORT_SCR_NTF = 0x3c,
144 PORT_FBS = 0x40,
145 PORT_DEVSLP = 0x44,
146
147
148 PORT_IRQ_COLD_PRES = (1 << 31),
149 PORT_IRQ_TF_ERR = (1 << 30),
150 PORT_IRQ_HBUS_ERR = (1 << 29),
151 PORT_IRQ_HBUS_DATA_ERR = (1 << 28),
152 PORT_IRQ_IF_ERR = (1 << 27),
153 PORT_IRQ_IF_NONFATAL = (1 << 26),
154 PORT_IRQ_OVERFLOW = (1 << 24),
155 PORT_IRQ_BAD_PMP = (1 << 23),
156
157 PORT_IRQ_PHYRDY = (1 << 22),
158 PORT_IRQ_DEV_ILCK = (1 << 7),
159 PORT_IRQ_CONNECT = (1 << 6),
160 PORT_IRQ_SG_DONE = (1 << 5),
161 PORT_IRQ_UNK_FIS = (1 << 4),
162 PORT_IRQ_SDB_FIS = (1 << 3),
163 PORT_IRQ_DMAS_FIS = (1 << 2),
164 PORT_IRQ_PIOS_FIS = (1 << 1),
165 PORT_IRQ_D2H_REG_FIS = (1 << 0),
166
167 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
168 PORT_IRQ_IF_ERR |
169 PORT_IRQ_CONNECT |
170 PORT_IRQ_PHYRDY |
171 PORT_IRQ_UNK_FIS |
172 PORT_IRQ_BAD_PMP,
173 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
174 PORT_IRQ_TF_ERR |
175 PORT_IRQ_HBUS_DATA_ERR,
176 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
177 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
178 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
179
180
181 PORT_CMD_ASP = (1 << 27),
182 PORT_CMD_ALPE = (1 << 26),
183 PORT_CMD_ATAPI = (1 << 24),
184 PORT_CMD_FBSCP = (1 << 22),
185 PORT_CMD_ESP = (1 << 21),
186 PORT_CMD_HPCP = (1 << 18),
187 PORT_CMD_PMP = (1 << 17),
188 PORT_CMD_LIST_ON = (1 << 15),
189 PORT_CMD_FIS_ON = (1 << 14),
190 PORT_CMD_FIS_RX = (1 << 4),
191 PORT_CMD_CLO = (1 << 3),
192 PORT_CMD_POWER_ON = (1 << 2),
193 PORT_CMD_SPIN_UP = (1 << 1),
194 PORT_CMD_START = (1 << 0),
195
196 PORT_CMD_ICC_MASK = (0xf << 28),
197 PORT_CMD_ICC_ACTIVE = (0x1 << 28),
198 PORT_CMD_ICC_PARTIAL = (0x2 << 28),
199 PORT_CMD_ICC_SLUMBER = (0x6 << 28),
200
201
202 PORT_FBS_DWE_OFFSET = 16,
203 PORT_FBS_ADO_OFFSET = 12,
204 PORT_FBS_DEV_OFFSET = 8,
205 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET),
206 PORT_FBS_SDE = (1 << 2),
207 PORT_FBS_DEC = (1 << 1),
208 PORT_FBS_EN = (1 << 0),
209
210
211 PORT_DEVSLP_DM_OFFSET = 25,
212 PORT_DEVSLP_DM_MASK = (0xf << 25),
213 PORT_DEVSLP_DITO_OFFSET = 15,
214 PORT_DEVSLP_MDAT_OFFSET = 10,
215 PORT_DEVSLP_DETO_OFFSET = 2,
216 PORT_DEVSLP_DSP = (1 << 1),
217 PORT_DEVSLP_ADSE = (1 << 0),
218
219
220
221#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
222
223 AHCI_HFLAG_NO_NCQ = (1 << 0),
224 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1),
225 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2),
226 AHCI_HFLAG_32BIT_ONLY = (1 << 3),
227 AHCI_HFLAG_MV_PATA = (1 << 4),
228 AHCI_HFLAG_NO_MSI = (1 << 5),
229 AHCI_HFLAG_NO_PMP = (1 << 6),
230 AHCI_HFLAG_SECT255 = (1 << 8),
231 AHCI_HFLAG_YES_NCQ = (1 << 9),
232 AHCI_HFLAG_NO_SUSPEND = (1 << 10),
233 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11),
234
235 AHCI_HFLAG_NO_SNTF = (1 << 12),
236 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13),
237 AHCI_HFLAG_YES_FBS = (1 << 14),
238 AHCI_HFLAG_DELAY_ENGINE = (1 << 15),
239
240
241 AHCI_HFLAG_NO_DEVSLP = (1 << 17),
242 AHCI_HFLAG_NO_FBS = (1 << 18),
243
244#ifdef CONFIG_PCI_MSI
245 AHCI_HFLAG_MULTI_MSI = (1 << 20),
246#else
247
248 AHCI_HFLAG_MULTI_MSI = 0,
249#endif
250 AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22),
251 AHCI_HFLAG_YES_ALPM = (1 << 23),
252 AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24),
253
254
255
256
257 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
258 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
259
260 ICH_MAP = 0x90,
261
262
263 EM_MAX_SLOTS = 8,
264 EM_MAX_RETRY = 5,
265
266
267 EM_CTL_RST = (1 << 9),
268 EM_CTL_TM = (1 << 8),
269 EM_CTL_MR = (1 << 0),
270 EM_CTL_ALHD = (1 << 26),
271 EM_CTL_XMT = (1 << 25),
272 EM_CTL_SMB = (1 << 24),
273 EM_CTL_SGPIO = (1 << 19),
274 EM_CTL_SES = (1 << 18),
275 EM_CTL_SAFTE = (1 << 17),
276 EM_CTL_LED = (1 << 16),
277
278
279 EM_MSG_TYPE_LED = (1 << 0),
280 EM_MSG_TYPE_SAFTE = (1 << 1),
281 EM_MSG_TYPE_SES2 = (1 << 2),
282 EM_MSG_TYPE_SGPIO = (1 << 3),
283};
284
285struct ahci_cmd_hdr {
286 __le32 opts;
287 __le32 status;
288 __le32 tbl_addr;
289 __le32 tbl_addr_hi;
290 __le32 reserved[4];
291};
292
293struct ahci_sg {
294 __le32 addr;
295 __le32 addr_hi;
296 __le32 reserved;
297 __le32 flags_size;
298};
299
300struct ahci_em_priv {
301 enum sw_activity blink_policy;
302 struct timer_list timer;
303 unsigned long saved_activity;
304 unsigned long activity;
305 unsigned long led_state;
306};
307
308struct ahci_port_priv {
309 struct ata_link *active_link;
310 struct ahci_cmd_hdr *cmd_slot;
311 dma_addr_t cmd_slot_dma;
312 void *cmd_tbl;
313 dma_addr_t cmd_tbl_dma;
314 void *rx_fis;
315 dma_addr_t rx_fis_dma;
316
317 unsigned int ncq_saw_d2h:1;
318 unsigned int ncq_saw_dmas:1;
319 unsigned int ncq_saw_sdb:1;
320 spinlock_t lock;
321 u32 intr_mask;
322 bool fbs_supported;
323 bool fbs_enabled;
324 int fbs_last_dev;
325
326 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
327 char *irq_desc;
328};
329
330struct ahci_host_priv {
331
332 unsigned int flags;
333 u32 force_port_map;
334 u32 mask_port_map;
335
336 void __iomem * mmio;
337 u32 cap;
338 u32 cap2;
339 u32 version;
340 u32 port_map;
341 u32 saved_cap;
342 u32 saved_cap2;
343 u32 saved_port_map;
344 u32 em_loc;
345 u32 em_buf_sz;
346 u32 em_msg_type;
347 bool got_runtime_pm;
348 struct clk *clks[AHCI_MAX_CLKS];
349 struct regulator **target_pwrs;
350
351
352
353
354 struct phy **phys;
355 unsigned nports;
356 void *plat_data;
357 unsigned int irq;
358
359
360
361
362
363 void (*start_engine)(struct ata_port *ap);
364 irqreturn_t (*irq_handler)(int irq, void *dev_instance);
365
366
367 int (*get_irq_vector)(struct ata_host *host,
368 int port);
369};
370
371extern int ahci_ignore_sss;
372
373extern struct device_attribute *ahci_shost_attrs[];
374extern struct device_attribute *ahci_sdev_attrs[];
375
376
377
378
379
380#define AHCI_SHT(drv_name) \
381 ATA_NCQ_SHT(drv_name), \
382 .can_queue = AHCI_MAX_CMDS - 1, \
383 .sg_tablesize = AHCI_MAX_SG, \
384 .dma_boundary = AHCI_DMA_BOUNDARY, \
385 .shost_attrs = ahci_shost_attrs, \
386 .sdev_attrs = ahci_sdev_attrs
387
388extern struct ata_port_operations ahci_ops;
389extern struct ata_port_operations ahci_platform_ops;
390extern struct ata_port_operations ahci_pmp_retry_srst_ops;
391
392unsigned int ahci_dev_classify(struct ata_port *ap);
393void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
394 u32 opts);
395void ahci_save_initial_config(struct device *dev,
396 struct ahci_host_priv *hpriv);
397void ahci_init_controller(struct ata_host *host);
398int ahci_reset_controller(struct ata_host *host);
399
400int ahci_do_softreset(struct ata_link *link, unsigned int *class,
401 int pmp, unsigned long deadline,
402 int (*check_ready)(struct ata_link *link));
403
404int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
405 unsigned long deadline, bool *online);
406
407unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
408int ahci_stop_engine(struct ata_port *ap);
409void ahci_start_fis_rx(struct ata_port *ap);
410void ahci_start_engine(struct ata_port *ap);
411int ahci_check_ready(struct ata_link *link);
412int ahci_kick_engine(struct ata_port *ap);
413int ahci_port_resume(struct ata_port *ap);
414void ahci_set_em_messages(struct ahci_host_priv *hpriv,
415 struct ata_port_info *pi);
416int ahci_reset_em(struct ata_host *host);
417void ahci_print_info(struct ata_host *host, const char *scc_s);
418int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
419void ahci_error_handler(struct ata_port *ap);
420u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
421
422static inline void __iomem *__ahci_port_base(struct ata_host *host,
423 unsigned int port_no)
424{
425 struct ahci_host_priv *hpriv = host->private_data;
426 void __iomem *mmio = hpriv->mmio;
427
428 return mmio + 0x100 + (port_no * 0x80);
429}
430
431static inline void __iomem *ahci_port_base(struct ata_port *ap)
432{
433 return __ahci_port_base(ap->host, ap->port_no);
434}
435
436static inline int ahci_nr_ports(u32 cap)
437{
438 return (cap & 0x1f) + 1;
439}
440
441#endif
442