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20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25
26
27#define USIAU0_RSTCTRL 0x094
28#define USIBU1_RSTCTRL 0x0ac
29#define USIBU2_RSTCTRL 0x0b0
30#define USIBU3_RSTCTRL 0x0b4
31#define IIC0_RSTCTRL 0x0dc
32#define IIC1_RSTCTRL 0x0e0
33#define STI_RSTCTRL 0x124
34#define STI_CLKSEL 0x688
35
36static DEFINE_SPINLOCK(lock);
37
38
39static void __iomem *smu_base;
40
41static void __init emev2_smu_write(unsigned long value, int offs)
42{
43 BUG_ON(!smu_base || (offs >= PAGE_SIZE));
44 writel_relaxed(value, smu_base + offs);
45}
46
47static const struct of_device_id smu_id[] __initconst = {
48 { .compatible = "renesas,emev2-smu", },
49 {},
50};
51
52static void __init emev2_smu_init(void)
53{
54 struct device_node *np;
55
56 np = of_find_matching_node(NULL, smu_id);
57 BUG_ON(!np);
58 smu_base = of_iomap(np, 0);
59 BUG_ON(!smu_base);
60 of_node_put(np);
61
62
63 emev2_smu_write(0, STI_CLKSEL);
64 emev2_smu_write(1, STI_RSTCTRL);
65
66
67 emev2_smu_write(2, USIAU0_RSTCTRL);
68 emev2_smu_write(2, USIBU1_RSTCTRL);
69 emev2_smu_write(2, USIBU2_RSTCTRL);
70 emev2_smu_write(2, USIBU3_RSTCTRL);
71
72
73 emev2_smu_write(1, IIC0_RSTCTRL);
74 emev2_smu_write(1, IIC1_RSTCTRL);
75}
76
77static void __init emev2_smu_clkdiv_init(struct device_node *np)
78{
79 u32 reg[2];
80 struct clk *clk;
81 const char *parent_name = of_clk_get_parent_name(np, 0);
82 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
83 return;
84 if (!smu_base)
85 emev2_smu_init();
86 clk = clk_register_divider(NULL, np->name, parent_name, 0,
87 smu_base + reg[0], reg[1], 8, 0, &lock);
88 of_clk_add_provider(np, of_clk_src_simple_get, clk);
89 clk_register_clkdev(clk, np->name, NULL);
90 pr_debug("## %s %s %p\n", __func__, np->name, clk);
91}
92CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
93 emev2_smu_clkdiv_init);
94
95static void __init emev2_smu_gclk_init(struct device_node *np)
96{
97 u32 reg[2];
98 struct clk *clk;
99 const char *parent_name = of_clk_get_parent_name(np, 0);
100 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
101 return;
102 if (!smu_base)
103 emev2_smu_init();
104 clk = clk_register_gate(NULL, np->name, parent_name, 0,
105 smu_base + reg[0], reg[1], 0, &lock);
106 of_clk_add_provider(np, of_clk_src_simple_get, clk);
107 clk_register_clkdev(clk, np->name, NULL);
108 pr_debug("## %s %s %p\n", __func__, np->name, clk);
109}
110CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
111