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14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/gpio-pxa.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/io.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/syscore_ops.h>
30#include <linux/slab.h>
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52
53#define GPLR_OFFSET 0x00
54#define GPDR_OFFSET 0x0C
55#define GPSR_OFFSET 0x18
56#define GPCR_OFFSET 0x24
57#define GRER_OFFSET 0x30
58#define GFER_OFFSET 0x3C
59#define GEDR_OFFSET 0x48
60#define GAFR_OFFSET 0x54
61#define ED_MASK_OFFSET 0x9C
62
63#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
64
65int pxa_last_gpio;
66static int irq_base;
67
68struct pxa_gpio_bank {
69 void __iomem *regbase;
70 unsigned long irq_mask;
71 unsigned long irq_edge_rise;
72 unsigned long irq_edge_fall;
73
74#ifdef CONFIG_PM
75 unsigned long saved_gplr;
76 unsigned long saved_gpdr;
77 unsigned long saved_grer;
78 unsigned long saved_gfer;
79#endif
80};
81
82struct pxa_gpio_chip {
83 struct device *dev;
84 struct gpio_chip chip;
85 struct pxa_gpio_bank *banks;
86 struct irq_domain *irqdomain;
87
88 int irq0;
89 int irq1;
90 int (*set_wake)(unsigned int gpio, unsigned int on);
91};
92
93enum pxa_gpio_type {
94 PXA25X_GPIO = 0,
95 PXA26X_GPIO,
96 PXA27X_GPIO,
97 PXA3XX_GPIO,
98 PXA93X_GPIO,
99 MMP_GPIO = 0x10,
100 MMP2_GPIO,
101 PXA1928_GPIO,
102};
103
104struct pxa_gpio_id {
105 enum pxa_gpio_type type;
106 int gpio_nums;
107};
108
109static DEFINE_SPINLOCK(gpio_lock);
110static struct pxa_gpio_chip *pxa_gpio_chip;
111static enum pxa_gpio_type gpio_type;
112
113static struct pxa_gpio_id pxa25x_id = {
114 .type = PXA25X_GPIO,
115 .gpio_nums = 85,
116};
117
118static struct pxa_gpio_id pxa26x_id = {
119 .type = PXA26X_GPIO,
120 .gpio_nums = 90,
121};
122
123static struct pxa_gpio_id pxa27x_id = {
124 .type = PXA27X_GPIO,
125 .gpio_nums = 121,
126};
127
128static struct pxa_gpio_id pxa3xx_id = {
129 .type = PXA3XX_GPIO,
130 .gpio_nums = 128,
131};
132
133static struct pxa_gpio_id pxa93x_id = {
134 .type = PXA93X_GPIO,
135 .gpio_nums = 192,
136};
137
138static struct pxa_gpio_id mmp_id = {
139 .type = MMP_GPIO,
140 .gpio_nums = 128,
141};
142
143static struct pxa_gpio_id mmp2_id = {
144 .type = MMP2_GPIO,
145 .gpio_nums = 192,
146};
147
148static struct pxa_gpio_id pxa1928_id = {
149 .type = PXA1928_GPIO,
150 .gpio_nums = 224,
151};
152
153#define for_each_gpio_bank(i, b, pc) \
154 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
155
156static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
157{
158 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
159
160 return pxa_chip;
161}
162
163static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
164{
165 struct pxa_gpio_chip *p = gpiochip_get_data(c);
166 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
167
168 return bank->regbase;
169}
170
171static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
172 unsigned gpio)
173{
174 return chip_to_pxachip(c)->banks + gpio / 32;
175}
176
177static inline int gpio_is_pxa_type(int type)
178{
179 return (type & MMP_GPIO) == 0;
180}
181
182static inline int gpio_is_mmp_type(int type)
183{
184 return (type & MMP_GPIO) != 0;
185}
186
187
188
189
190static inline int __gpio_is_inverted(int gpio)
191{
192 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
193 return 1;
194 return 0;
195}
196
197
198
199
200
201
202
203static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
204{
205 void __iomem *base;
206 unsigned long gafr = 0, gpdr = 0;
207 int ret, af = 0, dir = 0;
208
209 base = gpio_bank_base(&pchip->chip, gpio);
210 gpdr = readl_relaxed(base + GPDR_OFFSET);
211
212 switch (gpio_type) {
213 case PXA25X_GPIO:
214 case PXA26X_GPIO:
215 case PXA27X_GPIO:
216 gafr = readl_relaxed(base + GAFR_OFFSET);
217 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
218 dir = gpdr & GPIO_bit(gpio);
219
220 if (__gpio_is_inverted(gpio))
221 ret = (af != 1) || (dir == 0);
222 else
223 ret = (af != 0) || (dir != 0);
224 break;
225 default:
226 ret = gpdr & GPIO_bit(gpio);
227 break;
228 }
229 return ret;
230}
231
232int pxa_irq_to_gpio(int irq)
233{
234 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
235 int irq_gpio0;
236
237 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
238 if (irq_gpio0 > 0)
239 return irq - irq_gpio0;
240
241 return irq_gpio0;
242}
243
244static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
245{
246 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
247
248 return irq_find_mapping(pchip->irqdomain, offset);
249}
250
251static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
252{
253 void __iomem *base = gpio_bank_base(chip, offset);
254 uint32_t value, mask = GPIO_bit(offset);
255 unsigned long flags;
256 int ret;
257
258 ret = pinctrl_gpio_direction_input(chip->base + offset);
259 if (!ret)
260 return 0;
261
262 spin_lock_irqsave(&gpio_lock, flags);
263
264 value = readl_relaxed(base + GPDR_OFFSET);
265 if (__gpio_is_inverted(chip->base + offset))
266 value |= mask;
267 else
268 value &= ~mask;
269 writel_relaxed(value, base + GPDR_OFFSET);
270
271 spin_unlock_irqrestore(&gpio_lock, flags);
272 return 0;
273}
274
275static int pxa_gpio_direction_output(struct gpio_chip *chip,
276 unsigned offset, int value)
277{
278 void __iomem *base = gpio_bank_base(chip, offset);
279 uint32_t tmp, mask = GPIO_bit(offset);
280 unsigned long flags;
281 int ret;
282
283 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
284
285 ret = pinctrl_gpio_direction_output(chip->base + offset);
286 if (ret)
287 return ret;
288
289 spin_lock_irqsave(&gpio_lock, flags);
290
291 tmp = readl_relaxed(base + GPDR_OFFSET);
292 if (__gpio_is_inverted(chip->base + offset))
293 tmp &= ~mask;
294 else
295 tmp |= mask;
296 writel_relaxed(tmp, base + GPDR_OFFSET);
297
298 spin_unlock_irqrestore(&gpio_lock, flags);
299 return 0;
300}
301
302static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
303{
304 void __iomem *base = gpio_bank_base(chip, offset);
305 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
306
307 return !!(gplr & GPIO_bit(offset));
308}
309
310static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
311{
312 void __iomem *base = gpio_bank_base(chip, offset);
313
314 writel_relaxed(GPIO_bit(offset),
315 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
316}
317
318#ifdef CONFIG_OF_GPIO
319static int pxa_gpio_of_xlate(struct gpio_chip *gc,
320 const struct of_phandle_args *gpiospec,
321 u32 *flags)
322{
323 if (gpiospec->args[0] > pxa_last_gpio)
324 return -EINVAL;
325
326 if (flags)
327 *flags = gpiospec->args[1];
328
329 return gpiospec->args[0];
330}
331#endif
332
333static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
334{
335 return pinctrl_request_gpio(chip->base + offset);
336}
337
338static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
339{
340 pinctrl_free_gpio(chip->base + offset);
341}
342
343static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
344 struct device_node *np, void __iomem *regbase)
345{
346 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
347 struct pxa_gpio_bank *bank;
348
349 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
350 GFP_KERNEL);
351 if (!pchip->banks)
352 return -ENOMEM;
353
354 pchip->chip.label = "gpio-pxa";
355 pchip->chip.direction_input = pxa_gpio_direction_input;
356 pchip->chip.direction_output = pxa_gpio_direction_output;
357 pchip->chip.get = pxa_gpio_get;
358 pchip->chip.set = pxa_gpio_set;
359 pchip->chip.to_irq = pxa_gpio_to_irq;
360 pchip->chip.ngpio = ngpio;
361 pchip->chip.request = pxa_gpio_request;
362 pchip->chip.free = pxa_gpio_free;
363#ifdef CONFIG_OF_GPIO
364 pchip->chip.of_node = np;
365 pchip->chip.of_xlate = pxa_gpio_of_xlate;
366 pchip->chip.of_gpio_n_cells = 2;
367#endif
368
369 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
370 bank = pchip->banks + i;
371 bank->regbase = regbase + BANK_OFF(i);
372 }
373
374 return gpiochip_add_data(&pchip->chip, pchip);
375}
376
377
378
379
380static inline void update_edge_detect(struct pxa_gpio_bank *c)
381{
382 uint32_t grer, gfer;
383
384 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
385 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
386 grer |= c->irq_edge_rise & c->irq_mask;
387 gfer |= c->irq_edge_fall & c->irq_mask;
388 writel_relaxed(grer, c->regbase + GRER_OFFSET);
389 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
390}
391
392static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
393{
394 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
395 unsigned int gpio = irqd_to_hwirq(d);
396 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
397 unsigned long gpdr, mask = GPIO_bit(gpio);
398
399 if (type == IRQ_TYPE_PROBE) {
400
401
402
403 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
404 return 0;
405
406 if (__gpio_is_occupied(pchip, gpio))
407 return 0;
408
409 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
410 }
411
412 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
413
414 if (__gpio_is_inverted(gpio))
415 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
416 else
417 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
418
419 if (type & IRQ_TYPE_EDGE_RISING)
420 c->irq_edge_rise |= mask;
421 else
422 c->irq_edge_rise &= ~mask;
423
424 if (type & IRQ_TYPE_EDGE_FALLING)
425 c->irq_edge_fall |= mask;
426 else
427 c->irq_edge_fall &= ~mask;
428
429 update_edge_detect(c);
430
431 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
432 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
433 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
434 return 0;
435}
436
437static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
438{
439 int loop, gpio, n, handled = 0;
440 unsigned long gedr;
441 struct pxa_gpio_chip *pchip = d;
442 struct pxa_gpio_bank *c;
443
444 do {
445 loop = 0;
446 for_each_gpio_bank(gpio, c, pchip) {
447 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
448 gedr = gedr & c->irq_mask;
449 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
450
451 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
452 loop = 1;
453
454 generic_handle_irq(
455 irq_find_mapping(pchip->irqdomain,
456 gpio + n));
457 }
458 }
459 handled += loop;
460 } while (loop);
461
462 return handled ? IRQ_HANDLED : IRQ_NONE;
463}
464
465static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
466{
467 struct pxa_gpio_chip *pchip = d;
468
469 if (in_irq == pchip->irq0) {
470 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
471 } else if (in_irq == pchip->irq1) {
472 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
473 } else {
474 pr_err("%s() unknown irq %d\n", __func__, in_irq);
475 return IRQ_NONE;
476 }
477 return IRQ_HANDLED;
478}
479
480static void pxa_ack_muxed_gpio(struct irq_data *d)
481{
482 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
483 unsigned int gpio = irqd_to_hwirq(d);
484 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
485
486 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
487}
488
489static void pxa_mask_muxed_gpio(struct irq_data *d)
490{
491 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
492 unsigned int gpio = irqd_to_hwirq(d);
493 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
494 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
495 uint32_t grer, gfer;
496
497 b->irq_mask &= ~GPIO_bit(gpio);
498
499 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
500 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
501 writel_relaxed(grer, base + GRER_OFFSET);
502 writel_relaxed(gfer, base + GFER_OFFSET);
503}
504
505static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
506{
507 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
508 unsigned int gpio = irqd_to_hwirq(d);
509
510 if (pchip->set_wake)
511 return pchip->set_wake(gpio, on);
512 else
513 return 0;
514}
515
516static void pxa_unmask_muxed_gpio(struct irq_data *d)
517{
518 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
519 unsigned int gpio = irqd_to_hwirq(d);
520 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
521
522 c->irq_mask |= GPIO_bit(gpio);
523 update_edge_detect(c);
524}
525
526static struct irq_chip pxa_muxed_gpio_chip = {
527 .name = "GPIO",
528 .irq_ack = pxa_ack_muxed_gpio,
529 .irq_mask = pxa_mask_muxed_gpio,
530 .irq_unmask = pxa_unmask_muxed_gpio,
531 .irq_set_type = pxa_gpio_irq_type,
532 .irq_set_wake = pxa_gpio_set_wake,
533};
534
535static int pxa_gpio_nums(struct platform_device *pdev)
536{
537 const struct platform_device_id *id = platform_get_device_id(pdev);
538 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
539 int count = 0;
540
541 switch (pxa_id->type) {
542 case PXA25X_GPIO:
543 case PXA26X_GPIO:
544 case PXA27X_GPIO:
545 case PXA3XX_GPIO:
546 case PXA93X_GPIO:
547 case MMP_GPIO:
548 case MMP2_GPIO:
549 case PXA1928_GPIO:
550 gpio_type = pxa_id->type;
551 count = pxa_id->gpio_nums - 1;
552 break;
553 default:
554 count = -EINVAL;
555 break;
556 }
557 return count;
558}
559
560static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
561 irq_hw_number_t hw)
562{
563 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
564 handle_edge_irq);
565 irq_set_chip_data(irq, d->host_data);
566 irq_set_noprobe(irq);
567 return 0;
568}
569
570const struct irq_domain_ops pxa_irq_domain_ops = {
571 .map = pxa_irq_domain_map,
572 .xlate = irq_domain_xlate_twocell,
573};
574
575#ifdef CONFIG_OF
576static const struct of_device_id pxa_gpio_dt_ids[] = {
577 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
578 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
579 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
580 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
581 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
582 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
583 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
584 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
585 {}
586};
587
588static int pxa_gpio_probe_dt(struct platform_device *pdev,
589 struct pxa_gpio_chip *pchip)
590{
591 int nr_gpios;
592 const struct of_device_id *of_id =
593 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
594 const struct pxa_gpio_id *gpio_id;
595
596 if (!of_id || !of_id->data) {
597 dev_err(&pdev->dev, "Failed to find gpio controller\n");
598 return -EFAULT;
599 }
600 gpio_id = of_id->data;
601 gpio_type = gpio_id->type;
602
603 nr_gpios = gpio_id->gpio_nums;
604 pxa_last_gpio = nr_gpios - 1;
605
606 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
607 if (irq_base < 0) {
608 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
609 return irq_base;
610 }
611 return irq_base;
612}
613#else
614#define pxa_gpio_probe_dt(pdev, pchip) (-1)
615#endif
616
617static int pxa_gpio_probe(struct platform_device *pdev)
618{
619 struct pxa_gpio_chip *pchip;
620 struct pxa_gpio_bank *c;
621 struct resource *res;
622 struct clk *clk;
623 struct pxa_gpio_platform_data *info;
624 void __iomem *gpio_reg_base;
625 int gpio, ret;
626 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
627
628 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
629 if (!pchip)
630 return -ENOMEM;
631 pchip->dev = &pdev->dev;
632
633 info = dev_get_platdata(&pdev->dev);
634 if (info) {
635 irq_base = info->irq_base;
636 if (irq_base <= 0)
637 return -EINVAL;
638 pxa_last_gpio = pxa_gpio_nums(pdev);
639 pchip->set_wake = info->gpio_set_wake;
640 } else {
641 irq_base = pxa_gpio_probe_dt(pdev, pchip);
642 if (irq_base < 0)
643 return -EINVAL;
644 }
645
646 if (!pxa_last_gpio)
647 return -EINVAL;
648
649 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
650 pxa_last_gpio + 1, irq_base,
651 0, &pxa_irq_domain_ops, pchip);
652 if (!pchip->irqdomain)
653 return -ENOMEM;
654
655 irq0 = platform_get_irq_byname(pdev, "gpio0");
656 irq1 = platform_get_irq_byname(pdev, "gpio1");
657 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
658 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
659 || (irq_mux <= 0))
660 return -EINVAL;
661
662 pchip->irq0 = irq0;
663 pchip->irq1 = irq1;
664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
665 gpio_reg_base = devm_ioremap(&pdev->dev, res->start,
666 resource_size(res));
667 if (!gpio_reg_base)
668 return -EINVAL;
669
670 if (irq0 > 0)
671 gpio_offset = 2;
672
673 clk = clk_get(&pdev->dev, NULL);
674 if (IS_ERR(clk)) {
675 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
676 PTR_ERR(clk));
677 return PTR_ERR(clk);
678 }
679 ret = clk_prepare_enable(clk);
680 if (ret) {
681 clk_put(clk);
682 return ret;
683 }
684
685
686 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
687 gpio_reg_base);
688 if (ret) {
689 clk_put(clk);
690 return ret;
691 }
692
693
694 for_each_gpio_bank(gpio, c, pchip) {
695 writel_relaxed(0, c->regbase + GFER_OFFSET);
696 writel_relaxed(0, c->regbase + GRER_OFFSET);
697 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
698
699 if (gpio_is_mmp_type(gpio_type))
700 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
701 }
702
703 if (irq0 > 0) {
704 ret = devm_request_irq(&pdev->dev,
705 irq0, pxa_gpio_direct_handler, 0,
706 "gpio-0", pchip);
707 if (ret)
708 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
709 ret);
710 }
711 if (irq1 > 0) {
712 ret = devm_request_irq(&pdev->dev,
713 irq1, pxa_gpio_direct_handler, 0,
714 "gpio-1", pchip);
715 if (ret)
716 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
717 ret);
718 }
719 ret = devm_request_irq(&pdev->dev,
720 irq_mux, pxa_gpio_demux_handler, 0,
721 "gpio-mux", pchip);
722 if (ret)
723 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
724 ret);
725
726 pxa_gpio_chip = pchip;
727
728 return 0;
729}
730
731static const struct platform_device_id gpio_id_table[] = {
732 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
733 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
734 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
735 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
736 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
737 { "mmp-gpio", (unsigned long)&mmp_id },
738 { "mmp2-gpio", (unsigned long)&mmp2_id },
739 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
740 { },
741};
742
743static struct platform_driver pxa_gpio_driver = {
744 .probe = pxa_gpio_probe,
745 .driver = {
746 .name = "pxa-gpio",
747 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
748 },
749 .id_table = gpio_id_table,
750};
751
752static int __init pxa_gpio_legacy_init(void)
753{
754 if (of_have_populated_dt())
755 return 0;
756
757 return platform_driver_register(&pxa_gpio_driver);
758}
759postcore_initcall(pxa_gpio_legacy_init);
760
761static int __init pxa_gpio_dt_init(void)
762{
763 if (of_have_populated_dt())
764 return platform_driver_register(&pxa_gpio_driver);
765
766 return 0;
767}
768device_initcall(pxa_gpio_dt_init);
769
770#ifdef CONFIG_PM
771static int pxa_gpio_suspend(void)
772{
773 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
774 struct pxa_gpio_bank *c;
775 int gpio;
776
777 for_each_gpio_bank(gpio, c, pchip) {
778 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
779 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
780 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
781 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
782
783
784 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
785 }
786 return 0;
787}
788
789static void pxa_gpio_resume(void)
790{
791 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
792 struct pxa_gpio_bank *c;
793 int gpio;
794
795 for_each_gpio_bank(gpio, c, pchip) {
796
797 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
798 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
799
800 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
801 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
802 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
803 }
804}
805#else
806#define pxa_gpio_suspend NULL
807#define pxa_gpio_resume NULL
808#endif
809
810struct syscore_ops pxa_gpio_syscore_ops = {
811 .suspend = pxa_gpio_suspend,
812 .resume = pxa_gpio_resume,
813};
814
815static int __init pxa_gpio_sysinit(void)
816{
817 register_syscore_ops(&pxa_gpio_syscore_ops);
818 return 0;
819}
820postcore_initcall(pxa_gpio_sysinit);
821
