LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v3

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Author: Huang Rui
  23 *
  24 */
  25
  26#include <linux/firmware.h>
  27#include <drm/drmP.h>
  28#include "amdgpu.h"
  29#include "amdgpu_psp.h"
  30#include "amdgpu_ucode.h"
  31#include "soc15_common.h"
  32#include "psp_v3_1.h"
  33
  34#include "vega10/soc15ip.h"
  35#include "vega10/MP/mp_9_0_offset.h"
  36#include "vega10/MP/mp_9_0_sh_mask.h"
  37#include "vega10/GC/gc_9_0_offset.h"
  38#include "vega10/SDMA0/sdma0_4_0_offset.h"
  39#include "vega10/NBIO/nbio_6_1_offset.h"
  40
  41MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
  42MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
  43
  44#define smnMP1_FIRMWARE_FLAGS 0x3010028
  45
  46static int
  47psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
  48{
  49        switch(ucode->ucode_id) {
  50        case AMDGPU_UCODE_ID_SDMA0:
  51                *type = GFX_FW_TYPE_SDMA0;
  52                break;
  53        case AMDGPU_UCODE_ID_SDMA1:
  54                *type = GFX_FW_TYPE_SDMA1;
  55                break;
  56        case AMDGPU_UCODE_ID_CP_CE:
  57                *type = GFX_FW_TYPE_CP_CE;
  58                break;
  59        case AMDGPU_UCODE_ID_CP_PFP:
  60                *type = GFX_FW_TYPE_CP_PFP;
  61                break;
  62        case AMDGPU_UCODE_ID_CP_ME:
  63                *type = GFX_FW_TYPE_CP_ME;
  64                break;
  65        case AMDGPU_UCODE_ID_CP_MEC1:
  66                *type = GFX_FW_TYPE_CP_MEC;
  67                break;
  68        case AMDGPU_UCODE_ID_CP_MEC1_JT:
  69                *type = GFX_FW_TYPE_CP_MEC_ME1;
  70                break;
  71        case AMDGPU_UCODE_ID_CP_MEC2:
  72                *type = GFX_FW_TYPE_CP_MEC;
  73                break;
  74        case AMDGPU_UCODE_ID_CP_MEC2_JT:
  75                *type = GFX_FW_TYPE_CP_MEC_ME2;
  76                break;
  77        case AMDGPU_UCODE_ID_RLC_G:
  78                *type = GFX_FW_TYPE_RLC_G;
  79                break;
  80        case AMDGPU_UCODE_ID_SMC:
  81                *type = GFX_FW_TYPE_SMU;
  82                break;
  83        case AMDGPU_UCODE_ID_UVD:
  84                *type = GFX_FW_TYPE_UVD;
  85                break;
  86        case AMDGPU_UCODE_ID_VCE:
  87                *type = GFX_FW_TYPE_VCE;
  88                break;
  89        case AMDGPU_UCODE_ID_MAXIMUM:
  90        default:
  91                return -EINVAL;
  92        }
  93
  94        return 0;
  95}
  96
  97int psp_v3_1_init_microcode(struct psp_context *psp)
  98{
  99        struct amdgpu_device *adev = psp->adev;
 100        const char *chip_name;
 101        char fw_name[30];
 102        int err = 0;
 103        const struct psp_firmware_header_v1_0 *hdr;
 104
 105        DRM_DEBUG("\n");
 106
 107        switch (adev->asic_type) {
 108        case CHIP_VEGA10:
 109                chip_name = "vega10";
 110                break;
 111        default: BUG();
 112        }
 113
 114        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
 115        err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
 116        if (err)
 117                goto out;
 118
 119        err = amdgpu_ucode_validate(adev->psp.sos_fw);
 120        if (err)
 121                goto out;
 122
 123        hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 124        adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
 125        adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
 126        adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
 127        adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
 128                                        le32_to_cpu(hdr->sos_size_bytes);
 129        adev->psp.sys_start_addr = (uint8_t *)hdr +
 130                                le32_to_cpu(hdr->header.ucode_array_offset_bytes);
 131        adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 132                                le32_to_cpu(hdr->sos_offset_bytes);
 133
 134        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 135        err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 136        if (err)
 137                goto out;
 138
 139        err = amdgpu_ucode_validate(adev->psp.asd_fw);
 140        if (err)
 141                goto out;
 142
 143        hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 144        adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
 145        adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
 146        adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 147        adev->psp.asd_start_addr = (uint8_t *)hdr +
 148                                le32_to_cpu(hdr->header.ucode_array_offset_bytes);
 149
 150        return 0;
 151out:
 152        if (err) {
 153                dev_err(adev->dev,
 154                        "psp v3.1: Failed to load firmware \"%s\"\n",
 155                        fw_name);
 156                release_firmware(adev->psp.sos_fw);
 157                adev->psp.sos_fw = NULL;
 158                release_firmware(adev->psp.asd_fw);
 159                adev->psp.asd_fw = NULL;
 160        }
 161
 162        return err;
 163}
 164
 165int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
 166{
 167        int ret;
 168        uint32_t psp_gfxdrv_command_reg = 0;
 169        struct amdgpu_device *adev = psp->adev;
 170        uint32_t sol_reg;
 171
 172        /* Check sOS sign of life register to confirm sys driver and sOS
 173         * are already been loaded.
 174         */
 175        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 176        if (sol_reg)
 177                return 0;
 178
 179        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 180        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 181                           0x80000000, 0x80000000, false);
 182        if (ret)
 183                return ret;
 184
 185        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 186
 187        /* Copy PSP System Driver binary to memory */
 188        memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 189
 190        /* Provide the sys driver to bootrom */
 191        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 192               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 193        psp_gfxdrv_command_reg = 1 << 16;
 194        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 195               psp_gfxdrv_command_reg);
 196
 197        /* there might be handshake issue with hardware which needs delay */
 198        mdelay(20);
 199
 200        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 201                           0x80000000, 0x80000000, false);
 202
 203        return ret;
 204}
 205
 206int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
 207{
 208        int ret;
 209        unsigned int psp_gfxdrv_command_reg = 0;
 210        struct amdgpu_device *adev = psp->adev;
 211        uint32_t sol_reg;
 212
 213        /* Check sOS sign of life register to confirm sys driver and sOS
 214         * are already been loaded.
 215         */
 216        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 217        if (sol_reg)
 218                return 0;
 219
 220        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 221        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 222                           0x80000000, 0x80000000, false);
 223        if (ret)
 224                return ret;
 225
 226        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 227
 228        /* Copy Secure OS binary to PSP memory */
 229        memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 230
 231        /* Provide the PSP secure OS to bootrom */
 232        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 233               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 234        psp_gfxdrv_command_reg = 2 << 16;
 235        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 236               psp_gfxdrv_command_reg);
 237
 238        /* there might be handshake issue with hardware which needs delay */
 239        mdelay(20);
 240        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 241                           RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 242                           0, true);
 243
 244        return ret;
 245}
 246
 247int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
 248{
 249        int ret;
 250        uint64_t fw_mem_mc_addr = ucode->mc_addr;
 251
 252        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 253
 254        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 255        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 256        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 257        cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 258
 259        ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 260        if (ret)
 261                DRM_ERROR("Unknown firmware type\n");
 262
 263        return ret;
 264}
 265
 266int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 267{
 268        int ret = 0;
 269        struct psp_ring *ring;
 270        struct amdgpu_device *adev = psp->adev;
 271
 272        ring = &psp->km_ring;
 273
 274        ring->ring_type = ring_type;
 275
 276        /* allocate 4k Page of Local Frame Buffer memory for ring */
 277        ring->ring_size = 0x1000;
 278        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 279                                      AMDGPU_GEM_DOMAIN_VRAM,
 280                                      &adev->firmware.rbuf,
 281                                      &ring->ring_mem_mc_addr,
 282                                      (void **)&ring->ring_mem);
 283        if (ret) {
 284                ring->ring_size = 0;
 285                return ret;
 286        }
 287
 288        return 0;
 289}
 290
 291int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
 292{
 293        int ret = 0;
 294        unsigned int psp_ring_reg = 0;
 295        struct psp_ring *ring = &psp->km_ring;
 296        struct amdgpu_device *adev = psp->adev;
 297
 298        /* Write low address of the ring to C2PMSG_69 */
 299        psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 300        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 301        /* Write high address of the ring to C2PMSG_70 */
 302        psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 303        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 304        /* Write size of ring to C2PMSG_71 */
 305        psp_ring_reg = ring->ring_size;
 306        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 307        /* Write the ring initialization command to C2PMSG_64 */
 308        psp_ring_reg = ring_type;
 309        psp_ring_reg = psp_ring_reg << 16;
 310        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 311
 312        /* there might be handshake issue with hardware which needs delay */
 313        mdelay(20);
 314
 315        /* Wait for response flag (bit 31) in C2PMSG_64 */
 316        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 317                           0x80000000, 0x8000FFFF, false);
 318
 319        return ret;
 320}
 321
 322int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
 323{
 324        int ret = 0;
 325        struct psp_ring *ring;
 326        unsigned int psp_ring_reg = 0;
 327        struct amdgpu_device *adev = psp->adev;
 328
 329        ring = &psp->km_ring;
 330
 331        /* Write the ring destroy command to C2PMSG_64 */
 332        psp_ring_reg = 3 << 16;
 333        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 334
 335        /* there might be handshake issue with hardware which needs delay */
 336        mdelay(20);
 337
 338        /* Wait for response flag (bit 31) in C2PMSG_64 */
 339        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 340                           0x80000000, 0x80000000, false);
 341
 342        amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 343                              &ring->ring_mem_mc_addr,
 344                              (void **)&ring->ring_mem);
 345
 346        return ret;
 347}
 348
 349int psp_v3_1_cmd_submit(struct psp_context *psp,
 350                        struct amdgpu_firmware_info *ucode,
 351                        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 352                        int index)
 353{
 354        unsigned int psp_write_ptr_reg = 0;
 355        struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 356        struct psp_ring *ring = &psp->km_ring;
 357        struct amdgpu_device *adev = psp->adev;
 358        uint32_t ring_size_dw = ring->ring_size / 4;
 359        uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 360
 361        /* KM (GPCOM) prepare write pointer */
 362        psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 363
 364        /* Update KM RB frame pointer to new frame */
 365        /* write_frame ptr increments by size of rb_frame in bytes */
 366        /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 367        if ((psp_write_ptr_reg % ring_size_dw) == 0)
 368                write_frame = ring->ring_mem;
 369        else
 370                write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
 371
 372        /* Initialize KM RB frame */
 373        memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 374
 375        /* Update KM RB frame */
 376        write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 377        write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 378        write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 379        write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 380        write_frame->fence_value = index;
 381
 382        /* Update the write Pointer in DWORDs */
 383        psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 384        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 385
 386        return 0;
 387}
 388
 389static int
 390psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 391                  unsigned int *sram_data_reg_offset,
 392                  enum AMDGPU_UCODE_ID ucode_id)
 393{
 394        int ret = 0;
 395
 396        switch(ucode_id) {
 397/* TODO: needs to confirm */
 398#if 0
 399        case AMDGPU_UCODE_ID_SMC:
 400                *sram_offset = 0;
 401                *sram_addr_reg_offset = 0;
 402                *sram_data_reg_offset = 0;
 403                break;
 404#endif
 405
 406        case AMDGPU_UCODE_ID_CP_CE:
 407                *sram_offset = 0x0;
 408                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 409                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 410                break;
 411
 412        case AMDGPU_UCODE_ID_CP_PFP:
 413                *sram_offset = 0x0;
 414                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 415                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 416                break;
 417
 418        case AMDGPU_UCODE_ID_CP_ME:
 419                *sram_offset = 0x0;
 420                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 421                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 422                break;
 423
 424        case AMDGPU_UCODE_ID_CP_MEC1:
 425                *sram_offset = 0x10000;
 426                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 427                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 428                break;
 429
 430        case AMDGPU_UCODE_ID_CP_MEC2:
 431                *sram_offset = 0x10000;
 432                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 433                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 434                break;
 435
 436        case AMDGPU_UCODE_ID_RLC_G:
 437                *sram_offset = 0x2000;
 438                *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 439                *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 440                break;
 441
 442        case AMDGPU_UCODE_ID_SDMA0:
 443                *sram_offset = 0x0;
 444                *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 445                *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 446                break;
 447
 448/* TODO: needs to confirm */
 449#if 0
 450        case AMDGPU_UCODE_ID_SDMA1:
 451                *sram_offset = ;
 452                *sram_addr_reg_offset = ;
 453                break;
 454
 455        case AMDGPU_UCODE_ID_UVD:
 456                *sram_offset = ;
 457                *sram_addr_reg_offset = ;
 458                break;
 459
 460        case AMDGPU_UCODE_ID_VCE:
 461                *sram_offset = ;
 462                *sram_addr_reg_offset = ;
 463                break;
 464#endif
 465
 466        case AMDGPU_UCODE_ID_MAXIMUM:
 467        default:
 468                ret = -EINVAL;
 469                break;
 470        }
 471
 472        return ret;
 473}
 474
 475bool psp_v3_1_compare_sram_data(struct psp_context *psp,
 476                                struct amdgpu_firmware_info *ucode,
 477                                enum AMDGPU_UCODE_ID ucode_type)
 478{
 479        int err = 0;
 480        unsigned int fw_sram_reg_val = 0;
 481        unsigned int fw_sram_addr_reg_offset = 0;
 482        unsigned int fw_sram_data_reg_offset = 0;
 483        unsigned int ucode_size;
 484        uint32_t *ucode_mem = NULL;
 485        struct amdgpu_device *adev = psp->adev;
 486
 487        err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
 488                                &fw_sram_data_reg_offset, ucode_type);
 489        if (err)
 490                return false;
 491
 492        WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 493
 494        ucode_size = ucode->ucode_size;
 495        ucode_mem = (uint32_t *)ucode->kaddr;
 496        while (ucode_size) {
 497                fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 498
 499                if (*ucode_mem != fw_sram_reg_val)
 500                        return false;
 501
 502                ucode_mem++;
 503                /* 4 bytes */
 504                ucode_size -= 4;
 505        }
 506
 507        return true;
 508}
 509
 510bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
 511{
 512        struct amdgpu_device *adev = psp->adev;
 513        uint32_t reg;
 514
 515        reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
 516        WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);
 517        reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
 518        return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
 519}
 520