linux/drivers/gpu/drm/amd/amdgpu/si_dpm.c
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   1/*
   2 * Copyright 2013 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <drm/drmP.h>
  25#include "amdgpu.h"
  26#include "amdgpu_pm.h"
  27#include "amdgpu_dpm.h"
  28#include "amdgpu_atombios.h"
  29#include "sid.h"
  30#include "r600_dpm.h"
  31#include "si_dpm.h"
  32#include "atom.h"
  33#include "../include/pptable.h"
  34#include <linux/math64.h>
  35#include <linux/seq_file.h>
  36#include <linux/firmware.h>
  37
  38#define MC_CG_ARB_FREQ_F0           0x0a
  39#define MC_CG_ARB_FREQ_F1           0x0b
  40#define MC_CG_ARB_FREQ_F2           0x0c
  41#define MC_CG_ARB_FREQ_F3           0x0d
  42
  43#define SMC_RAM_END                 0x20000
  44
  45#define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56#define BIOS_SCRATCH_4                                    0x5cd
  57
  58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  59MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  60MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  61MODULE_FIRMWARE("radeon/verde_smc.bin");
  62MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  63MODULE_FIRMWARE("radeon/oland_smc.bin");
  64MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  65MODULE_FIRMWARE("radeon/hainan_smc.bin");
  66MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  67MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
  68
  69union power_info {
  70        struct _ATOM_POWERPLAY_INFO info;
  71        struct _ATOM_POWERPLAY_INFO_V2 info_2;
  72        struct _ATOM_POWERPLAY_INFO_V3 info_3;
  73        struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  74        struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  75        struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  76        struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  77        struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  78};
  79
  80union fan_info {
  81        struct _ATOM_PPLIB_FANTABLE fan;
  82        struct _ATOM_PPLIB_FANTABLE2 fan2;
  83        struct _ATOM_PPLIB_FANTABLE3 fan3;
  84};
  85
  86union pplib_clock_info {
  87        struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  88        struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  89        struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  90        struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  91        struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  92};
  93
  94static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  95{
  96        R600_UTC_DFLT_00,
  97        R600_UTC_DFLT_01,
  98        R600_UTC_DFLT_02,
  99        R600_UTC_DFLT_03,
 100        R600_UTC_DFLT_04,
 101        R600_UTC_DFLT_05,
 102        R600_UTC_DFLT_06,
 103        R600_UTC_DFLT_07,
 104        R600_UTC_DFLT_08,
 105        R600_UTC_DFLT_09,
 106        R600_UTC_DFLT_10,
 107        R600_UTC_DFLT_11,
 108        R600_UTC_DFLT_12,
 109        R600_UTC_DFLT_13,
 110        R600_UTC_DFLT_14,
 111};
 112
 113static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 114{
 115        R600_DTC_DFLT_00,
 116        R600_DTC_DFLT_01,
 117        R600_DTC_DFLT_02,
 118        R600_DTC_DFLT_03,
 119        R600_DTC_DFLT_04,
 120        R600_DTC_DFLT_05,
 121        R600_DTC_DFLT_06,
 122        R600_DTC_DFLT_07,
 123        R600_DTC_DFLT_08,
 124        R600_DTC_DFLT_09,
 125        R600_DTC_DFLT_10,
 126        R600_DTC_DFLT_11,
 127        R600_DTC_DFLT_12,
 128        R600_DTC_DFLT_13,
 129        R600_DTC_DFLT_14,
 130};
 131
 132static const struct si_cac_config_reg cac_weights_tahiti[] =
 133{
 134        { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 135        { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 136        { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 137        { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 138        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 139        { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 140        { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141        { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 142        { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 143        { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 144        { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 145        { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 146        { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 147        { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 148        { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 149        { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150        { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151        { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 152        { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 153        { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 154        { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 155        { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 156        { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157        { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158        { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 159        { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160        { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 162        { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163        { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 164        { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 165        { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 166        { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167        { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168        { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 169        { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171        { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 172        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173        { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 174        { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 175        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180        { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181        { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184        { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185        { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 186        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 187        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 188        { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 189        { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 190        { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 191        { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 192        { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 193        { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 194        { 0xFFFFFFFF }
 195};
 196
 197static const struct si_cac_config_reg lcac_tahiti[] =
 198{
 199        { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 200        { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201        { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 202        { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203        { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 204        { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205        { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 206        { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207        { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208        { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209        { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210        { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211        { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212        { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213        { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214        { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215        { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 216        { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217        { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 218        { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219        { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 220        { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221        { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 222        { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223        { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224        { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225        { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226        { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227        { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228        { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229        { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230        { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231        { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232        { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233        { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234        { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235        { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236        { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237        { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238        { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239        { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 240        { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241        { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 242        { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243        { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 244        { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245        { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 246        { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247        { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248        { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249        { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250        { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251        { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 252        { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253        { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 254        { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255        { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 256        { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257        { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 258        { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259        { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260        { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261        { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262        { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263        { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 264        { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265        { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 266        { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267        { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 268        { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269        { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 270        { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271        { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 272        { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273        { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274        { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275        { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276        { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277        { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 278        { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 279        { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 280        { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 281        { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 282        { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 283        { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 284        { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 285        { 0xFFFFFFFF }
 286
 287};
 288
 289static const struct si_cac_config_reg cac_override_tahiti[] =
 290{
 291        { 0xFFFFFFFF }
 292};
 293
 294static const struct si_powertune_data powertune_data_tahiti =
 295{
 296        ((1 << 16) | 27027),
 297        6,
 298        0,
 299        4,
 300        95,
 301        {
 302                0UL,
 303                0UL,
 304                4521550UL,
 305                309631529UL,
 306                -1270850L,
 307                4513710L,
 308                40
 309        },
 310        595000000UL,
 311        12,
 312        {
 313                0,
 314                0,
 315                0,
 316                0,
 317                0,
 318                0,
 319                0,
 320                0
 321        },
 322        true
 323};
 324
 325static const struct si_dte_data dte_data_tahiti =
 326{
 327        { 1159409, 0, 0, 0, 0 },
 328        { 777, 0, 0, 0, 0 },
 329        2,
 330        54000,
 331        127000,
 332        25,
 333        2,
 334        10,
 335        13,
 336        { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 337        { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 338        { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 339        85,
 340        false
 341};
 342
 343#if 0
 344static const struct si_dte_data dte_data_tahiti_le =
 345{
 346        { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 347        { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 348        0x5,
 349        0xAFC8,
 350        0x64,
 351        0x32,
 352        1,
 353        0,
 354        0x10,
 355        { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 356        { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 357        { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 358        85,
 359        true
 360};
 361#endif
 362
 363static const struct si_dte_data dte_data_tahiti_pro =
 364{
 365        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 366        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 367        5,
 368        45000,
 369        100,
 370        0xA,
 371        1,
 372        0,
 373        0x10,
 374        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 375        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 376        { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 377        90,
 378        true
 379};
 380
 381static const struct si_dte_data dte_data_new_zealand =
 382{
 383        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 384        { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 385        0x5,
 386        0xAFC8,
 387        0x69,
 388        0x32,
 389        1,
 390        0,
 391        0x10,
 392        { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 393        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 394        { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 395        85,
 396        true
 397};
 398
 399static const struct si_dte_data dte_data_aruba_pro =
 400{
 401        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 402        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 403        5,
 404        45000,
 405        100,
 406        0xA,
 407        1,
 408        0,
 409        0x10,
 410        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 411        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 412        { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 413        90,
 414        true
 415};
 416
 417static const struct si_dte_data dte_data_malta =
 418{
 419        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 420        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 421        5,
 422        45000,
 423        100,
 424        0xA,
 425        1,
 426        0,
 427        0x10,
 428        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 429        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 430        { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 431        90,
 432        true
 433};
 434
 435static const struct si_cac_config_reg cac_weights_pitcairn[] =
 436{
 437        { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 438        { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 439        { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 440        { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 441        { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 442        { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 443        { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 444        { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 445        { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 446        { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 447        { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 448        { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 449        { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 450        { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 451        { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 452        { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 453        { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 454        { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 455        { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 456        { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 457        { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 458        { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 459        { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 460        { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 461        { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 462        { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 463        { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 464        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 465        { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 466        { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 467        { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 468        { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469        { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 470        { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471        { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 472        { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 473        { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 474        { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475        { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 476        { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477        { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483        { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484        { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487        { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488        { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 489        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 490        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 491        { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 492        { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 493        { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 494        { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 495        { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 496        { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 497        { 0xFFFFFFFF }
 498};
 499
 500static const struct si_cac_config_reg lcac_pitcairn[] =
 501{
 502        { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 503        { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504        { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 505        { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506        { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 507        { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508        { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 509        { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510        { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 511        { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512        { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 513        { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514        { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 515        { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516        { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 517        { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518        { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 519        { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520        { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 521        { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522        { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 523        { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524        { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 525        { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526        { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 527        { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528        { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 529        { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530        { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 531        { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532        { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 533        { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534        { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 535        { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536        { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 537        { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538        { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 539        { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540        { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 541        { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542        { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 543        { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544        { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 545        { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546        { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 547        { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548        { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549        { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550        { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551        { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552        { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553        { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554        { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 555        { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556        { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 557        { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558        { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 559        { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560        { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 561        { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562        { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563        { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564        { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565        { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566        { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567        { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568        { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 569        { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570        { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 571        { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572        { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 573        { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574        { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 575        { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576        { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577        { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578        { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579        { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580        { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 581        { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 582        { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 583        { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 584        { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 585        { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 586        { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 587        { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 588        { 0xFFFFFFFF }
 589};
 590
 591static const struct si_cac_config_reg cac_override_pitcairn[] =
 592{
 593    { 0xFFFFFFFF }
 594};
 595
 596static const struct si_powertune_data powertune_data_pitcairn =
 597{
 598        ((1 << 16) | 27027),
 599        5,
 600        0,
 601        6,
 602        100,
 603        {
 604                51600000UL,
 605                1800000UL,
 606                7194395UL,
 607                309631529UL,
 608                -1270850L,
 609                4513710L,
 610                100
 611        },
 612        117830498UL,
 613        12,
 614        {
 615                0,
 616                0,
 617                0,
 618                0,
 619                0,
 620                0,
 621                0,
 622                0
 623        },
 624        true
 625};
 626
 627static const struct si_dte_data dte_data_pitcairn =
 628{
 629        { 0, 0, 0, 0, 0 },
 630        { 0, 0, 0, 0, 0 },
 631        0,
 632        0,
 633        0,
 634        0,
 635        0,
 636        0,
 637        0,
 638        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 639        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 641        0,
 642        false
 643};
 644
 645static const struct si_dte_data dte_data_curacao_xt =
 646{
 647        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 648        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 649        5,
 650        45000,
 651        100,
 652        0xA,
 653        1,
 654        0,
 655        0x10,
 656        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 657        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 658        { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 659        90,
 660        true
 661};
 662
 663static const struct si_dte_data dte_data_curacao_pro =
 664{
 665        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 666        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 667        5,
 668        45000,
 669        100,
 670        0xA,
 671        1,
 672        0,
 673        0x10,
 674        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 675        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 676        { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 677        90,
 678        true
 679};
 680
 681static const struct si_dte_data dte_data_neptune_xt =
 682{
 683        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 684        { 0x0, 0x0, 0x0, 0x0, 0x0 },
 685        5,
 686        45000,
 687        100,
 688        0xA,
 689        1,
 690        0,
 691        0x10,
 692        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 693        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 694        { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 695        90,
 696        true
 697};
 698
 699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 700{
 701        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 702        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 703        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 704        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 705        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 706        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 707        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 708        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 709        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 710        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 711        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 712        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 713        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 714        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 716        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 717        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 718        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 719        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 720        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 721        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 722        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 723        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 724        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 725        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 726        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 727        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 728        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 729        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 730        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 731        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 732        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 733        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 734        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 735        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 736        { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 737        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 739        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 740        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 741        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 742        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 743        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 745        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 746        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 747        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 753        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 754        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 755        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 756        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 757        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 758        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 759        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 760        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 761        { 0xFFFFFFFF }
 762};
 763
 764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 765{
 766        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 767        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 768        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 769        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 770        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 771        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 772        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 773        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 774        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 775        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 776        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 777        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 778        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 779        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 781        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 782        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 783        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 784        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 785        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 786        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 787        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 788        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 789        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 790        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 791        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 792        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 793        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 794        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 795        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 796        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 797        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 798        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 799        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 800        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 801        { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 802        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 804        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 805        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 806        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 807        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 808        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 810        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 811        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 812        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 818        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 819        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 820        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 821        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 822        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 823        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 824        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 825        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 826        { 0xFFFFFFFF }
 827};
 828
 829static const struct si_cac_config_reg cac_weights_heathrow[] =
 830{
 831        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 832        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 833        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 834        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 835        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 836        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 837        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 838        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 839        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 840        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 841        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 842        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 843        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 844        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 846        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 847        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 848        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 849        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 850        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 851        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 852        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 853        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 854        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 855        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 856        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 857        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 858        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 859        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 860        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 861        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 862        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 863        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 864        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 865        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 866        { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 867        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 869        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 870        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 871        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 872        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 873        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 875        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 876        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 877        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 883        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 884        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 885        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 886        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 887        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 888        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 889        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 890        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 891        { 0xFFFFFFFF }
 892};
 893
 894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 895{
 896        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 897        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 898        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 899        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 900        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 901        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 902        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 903        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 904        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 905        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 906        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 907        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 908        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 909        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 911        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 912        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 913        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 914        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 915        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 916        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 917        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 918        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 919        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 920        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 921        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 922        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 923        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 924        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 925        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 926        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 927        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 928        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 929        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 930        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 931        { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 932        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 934        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 935        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 936        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 937        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 938        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 939        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 940        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 941        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 942        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 948        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 949        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 950        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 951        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 952        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 953        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 954        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 955        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 956        { 0xFFFFFFFF }
 957};
 958
 959static const struct si_cac_config_reg cac_weights_cape_verde[] =
 960{
 961        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 962        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 963        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 964        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 965        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 966        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 967        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 968        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 969        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 970        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 971        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 972        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 973        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 974        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 975        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 976        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 977        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 978        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 979        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 980        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 981        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 982        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 983        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 984        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 985        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 986        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 987        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 988        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 989        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 990        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 991        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 992        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 993        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 994        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 995        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 996        { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 997        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 999        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },

1001        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021        { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026        { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027        { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028        { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029        { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030        { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031        { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032        { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033        { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034        { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035        { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036        { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037        { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038        { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039        { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040        { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041        { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042        { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043        { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044        { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045        { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046        { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047        { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048        { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049        { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050        { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051        { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052        { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053        { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054        { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055        { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056        { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057        { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058        { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059        { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060        { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061        { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062        { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063        { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064        { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065        { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066        { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067        { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068        { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069        { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070        { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071        { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072        { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073        { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074        { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075        { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076        { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077        { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078        { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079        { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080        { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085    { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090        ((1 << 16) | 0x6993),
1091        5,
1092        0,
1093        7,
1094        105,
1095        {
1096                0UL,
1097                0UL,
1098                7194395UL,
1099                309631529UL,
1100                -1270850L,
1101                4513710L,
1102                100
1103        },
1104        117830498UL,
1105        12,
1106        {
1107                0,
1108                0,
1109                0,
1110                0,
1111                0,
1112                0,
1113                0,
1114                0
1115        },
1116        true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121        { 0, 0, 0, 0, 0 },
1122        { 0, 0, 0, 0, 0 },
1123        0,
1124        0,
1125        0,
1126        0,
1127        0,
1128        0,
1129        0,
1130        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133        0,
1134        false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140        { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141        5,
1142        55000,
1143        0x69,
1144        0xA,
1145        1,
1146        0,
1147        0x3,
1148        { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149        { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150        { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151        90,
1152        true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158        { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159        5,
1160        55000,
1161        0x69,
1162        0xA,
1163        1,
1164        0,
1165        0x3,
1166        { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167        { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168        { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169        90,
1170        true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175        {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176        { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177        5,
1178        55000,
1179        0x69,
1180        0xA,
1181        1,
1182        0,
1183        0x3,
1184        { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185        { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186        { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187        90,
1188        true
1189};
1190
1191static const struct si_cac_config_reg cac_weights_oland[] =
1192{
1193        { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194        { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195        { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196        { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198        { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199        { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200        { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201        { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202        { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203        { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204        { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205        { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206        { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207        { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208        { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209        { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210        { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211        { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212        { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213        { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214        { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215        { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216        { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217        { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218        { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222        { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223        { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224        { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225        { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226        { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227        { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228        { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232        { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233        { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252        { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253        { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258        { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259        { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260        { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261        { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263        { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264        { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265        { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266        { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267        { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268        { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269        { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270        { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271        { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272        { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273        { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274        { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275        { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276        { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277        { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278        { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279        { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280        { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281        { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282        { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283        { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285        { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287        { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288        { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289        { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290        { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291        { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292        { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293        { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297        { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298        { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304        { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305        { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308        { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309        { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317        { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318        { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323        { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324        { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325        { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326        { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328        { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329        { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330        { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331        { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332        { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333        { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334        { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335        { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336        { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337        { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338        { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339        { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340        { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341        { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342        { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343        { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344        { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345        { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346        { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347        { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348        { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350        { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352        { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353        { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354        { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355        { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356        { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357        { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358        { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362        { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363        { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369        { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370        { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373        { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374        { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382        { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383        { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388        { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389        { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390        { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391        { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393        { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394        { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395        { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396        { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397        { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398        { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399        { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400        { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401        { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402        { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403        { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404        { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405        { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406        { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407        { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408        { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409        { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410        { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411        { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412        { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413        { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415        { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417        { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418        { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419        { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420        { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421        { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422        { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423        { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427        { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428        { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434        { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435        { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438        { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439        { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447        { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448        { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453        { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454        { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455        { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456        { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458        { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459        { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460        { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461        { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462        { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463        { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464        { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465        { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466        { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467        { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468        { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469        { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470        { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471        { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472        { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473        { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474        { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475        { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476        { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477        { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478        { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479        { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480        { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481        { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482        { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483        { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484        { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485        { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486        { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487        { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488        { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489        { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490        { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492        { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493        { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494        { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499        { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500        { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501        { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502        { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503        { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504        { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505        { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506        { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512        { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513        { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518        { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519        { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520        { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521        { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522        { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523        { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524        { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525        { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526        { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527        { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528        { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529        { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530        { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531        { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532        { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533        { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534        { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535        { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536        { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537        { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538        { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539        { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540        { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541        { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542        { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543        { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544        { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545        { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546        { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547        { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548        { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549        { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550        { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551        { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552        { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553        { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554        { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555        { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556        { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557        { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558        { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559        { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560        { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565        { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566        { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567        { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568        { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569        { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570        { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571        { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572        { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573        { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574        { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575        { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576        { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577        { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578        { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579        { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580        { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581        { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582        { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583        { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584        { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585        { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586        { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587        { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588        { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589        { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590        { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591        { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592        { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593        { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594        { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595        { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596        { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597        { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598        { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599        { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600        { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601        { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602        { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603        { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604        { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605        { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606        { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607        { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612        { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617        ((1 << 16) | 0x6993),
1618        5,
1619        0,
1620        7,
1621        105,
1622        {
1623                0UL,
1624                0UL,
1625                7194395UL,
1626                309631529UL,
1627                -1270850L,
1628                4513710L,
1629                100
1630        },
1631        117830498UL,
1632        12,
1633        {
1634                0,
1635                0,
1636                0,
1637                0,
1638                0,
1639                0,
1640                0,
1641                0
1642        },
1643        true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648        ((1 << 16) | 0x6993),
1649        5,
1650        0,
1651        7,
1652        105,
1653        {
1654                0UL,
1655                0UL,
1656                7194395UL,
1657                309631529UL,
1658                -1270850L,
1659                4513710L,
1660                100
1661        },
1662        117830498UL,
1663        12,
1664        {
1665                0,
1666                0,
1667                0,
1668                0,
1669                0,
1670                0,
1671                0,
1672                0
1673        },
1674        true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679        { 0, 0, 0, 0, 0 },
1680        { 0, 0, 0, 0, 0 },
1681        0,
1682        0,
1683        0,
1684        0,
1685        0,
1686        0,
1687        0,
1688        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691        0,
1692        false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698        { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699        5,
1700        55000,
1701        105,
1702        0xA,
1703        1,
1704        0,
1705        0x10,
1706        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708        { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709        90,
1710        true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715        { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716        { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717        5,
1718        55000,
1719        105,
1720        0xA,
1721        1,
1722        0,
1723        0x10,
1724        { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725        { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726        { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727        90,
1728        true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734        { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735        { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736        { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737        { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738        { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739        { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740        { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741        { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742        { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743        { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744        { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745        { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746        { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747        { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748        { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749        { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750        { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751        { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752        { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753        { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754        { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755        { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756        { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757        { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758        { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759        { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760        { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761        { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762        { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763        { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764        { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765        { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766        { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767        { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768        { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769        { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770        { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771        { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772        { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773        { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774        { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775        { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776        { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777        { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778        { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779        { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780        { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781        { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782        { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783        { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784        { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785        { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786        { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787        { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788        { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789        { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790        { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791        { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792        { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793        { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794        { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799        ((1 << 16) | 0x6993),
1800        5,
1801        0,
1802        9,
1803        105,
1804        {
1805                0UL,
1806                0UL,
1807                7194395UL,
1808                309631529UL,
1809                -1270850L,
1810                4513710L,
1811                100
1812        },
1813        117830498UL,
1814        12,
1815        {
1816                0,
1817                0,
1818                0,
1819                0,
1820                0,
1821                0,
1822                0,
1823                0
1824        },
1825        true
1826};
1827
1828static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834                                     const struct atom_voltage_table *table,
1835                                     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837                                    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838                                    u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840                                      u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842                                         struct rv7xx_pl *pl,
1843                                         SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845                                    u32 engine_clock,
1846                                    SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854{
1855        struct si_power_info *pi = adev->pm.dpm.priv;
1856        return pi;
1857}
1858
1859static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860                                                     u16 v, s32 t, u32 ileakage, u32 *leakage)
1861{
1862        s64 kt, kv, leakage_w, i_leakage, vddc;
1863        s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864        s64 tmp;
1865
1866        i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867        vddc = div64_s64(drm_int2fixp(v), 1000);
1868        temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870        t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871        t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872        av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873        bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874        t_ref = drm_int2fixp(coeff->t_ref);
1875
1876        tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877        kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878        kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879        kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881        leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883        *leakage = drm_fixp2int(leakage_w * 1000);
1884}
1885
1886static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887                                             const struct ni_leakage_coeffients *coeff,
1888                                             u16 v,
1889                                             s32 t,
1890                                             u32 i_leakage,
1891                                             u32 *leakage)
1892{
1893        si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894}
1895
1896static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897                                               const u32 fixed_kt, u16 v,
1898                                               u32 ileakage, u32 *leakage)
1899{
1900        s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902        i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903        vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905        kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906        kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907                          drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909        leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911        *leakage = drm_fixp2int(leakage_w * 1000);
1912}
1913
1914static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915                                       const struct ni_leakage_coeffients *coeff,
1916                                       const u32 fixed_kt,
1917                                       u16 v,
1918                                       u32 i_leakage,
1919                                       u32 *leakage)
1920{
1921        si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922}
1923
1924
1925static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926                                   struct si_dte_data *dte_data)
1927{
1928        u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929        u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930        u32 k = dte_data->k;
1931        u32 t_max = dte_data->max_t;
1932        u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933        u32 t_0 = dte_data->t0;
1934        u32 i;
1935
1936        if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937                dte_data->tdep_count = 3;
1938
1939                for (i = 0; i < k; i++) {
1940                        dte_data->r[i] =
1941                                (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942                                (p_limit2  * (u32)100);
1943                }
1944
1945                dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947                for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948                        dte_data->tdep_r[i] = dte_data->r[4];
1949                }
1950        } else {
1951                DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952        }
1953}
1954
1955static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956{
1957        struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959        return pi;
1960}
1961
1962static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963{
1964        struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966        return pi;
1967}
1968
1969static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970{
1971        struct  si_ps *ps = aps->ps_priv;
1972
1973        return ps;
1974}
1975
1976static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977{
1978        struct ni_power_info *ni_pi = ni_get_pi(adev);
1979        struct si_power_info *si_pi = si_get_pi(adev);
1980        bool update_dte_from_pl2 = false;
1981
1982        if (adev->asic_type == CHIP_TAHITI) {
1983                si_pi->cac_weights = cac_weights_tahiti;
1984                si_pi->lcac_config = lcac_tahiti;
1985                si_pi->cac_override = cac_override_tahiti;
1986                si_pi->powertune_data = &powertune_data_tahiti;
1987                si_pi->dte_data = dte_data_tahiti;
1988
1989                switch (adev->pdev->device) {
1990                case 0x6798:
1991                        si_pi->dte_data.enable_dte_by_default = true;
1992                        break;
1993                case 0x6799:
1994                        si_pi->dte_data = dte_data_new_zealand;
1995                        break;
1996                case 0x6790:
1997                case 0x6791:
1998                case 0x6792:
1999                case 0x679E:
2000                        si_pi->dte_data = dte_data_aruba_pro;

2001                        update_dte_from_pl2 = true;
2002                        break;
2003                case 0x679B:
2004                        si_pi->dte_data = dte_data_malta;
2005                        update_dte_from_pl2 = true;
2006                        break;
2007                case 0x679A:
2008                        si_pi->dte_data = dte_data_tahiti_pro;
2009                        update_dte_from_pl2 = true;
2010                        break;
2011                default:
2012                        if (si_pi->dte_data.enable_dte_by_default == true)
2013                                DRM_ERROR("DTE is not enabled!\n");
2014                        break;
2015                }
2016        } else if (adev->asic_type == CHIP_PITCAIRN) {
2017                si_pi->cac_weights = cac_weights_pitcairn;
2018                si_pi->lcac_config = lcac_pitcairn;
2019                si_pi->cac_override = cac_override_pitcairn;
2020                si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022                switch (adev->pdev->device) {
2023                case 0x6810:
2024                case 0x6818:
2025                        si_pi->dte_data = dte_data_curacao_xt;
2026                        update_dte_from_pl2 = true;
2027                        break;
2028                case 0x6819:
2029                case 0x6811:
2030                        si_pi->dte_data = dte_data_curacao_pro;
2031                        update_dte_from_pl2 = true;
2032                        break;
2033                case 0x6800:
2034                case 0x6806:
2035                        si_pi->dte_data = dte_data_neptune_xt;
2036                        update_dte_from_pl2 = true;
2037                        break;
2038                default:
2039                        si_pi->dte_data = dte_data_pitcairn;
2040                        break;
2041                }
2042        } else if (adev->asic_type == CHIP_VERDE) {
2043                si_pi->lcac_config = lcac_cape_verde;
2044                si_pi->cac_override = cac_override_cape_verde;
2045                si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047                switch (adev->pdev->device) {
2048                case 0x683B:
2049                case 0x683F:
2050                case 0x6829:
2051                case 0x6835:
2052                        si_pi->cac_weights = cac_weights_cape_verde_pro;
2053                        si_pi->dte_data = dte_data_cape_verde;
2054                        break;
2055                case 0x682C:
2056                        si_pi->cac_weights = cac_weights_cape_verde_pro;
2057                        si_pi->dte_data = dte_data_sun_xt;
2058                        update_dte_from_pl2 = true;
2059                        break;
2060                case 0x6825:
2061                case 0x6827:
2062                        si_pi->cac_weights = cac_weights_heathrow;
2063                        si_pi->dte_data = dte_data_cape_verde;
2064                        break;
2065                case 0x6824:
2066                case 0x682D:
2067                        si_pi->cac_weights = cac_weights_chelsea_xt;
2068                        si_pi->dte_data = dte_data_cape_verde;
2069                        break;
2070                case 0x682F:
2071                        si_pi->cac_weights = cac_weights_chelsea_pro;
2072                        si_pi->dte_data = dte_data_cape_verde;
2073                        break;
2074                case 0x6820:
2075                        si_pi->cac_weights = cac_weights_heathrow;
2076                        si_pi->dte_data = dte_data_venus_xtx;
2077                        break;
2078                case 0x6821:
2079                        si_pi->cac_weights = cac_weights_heathrow;
2080                        si_pi->dte_data = dte_data_venus_xt;
2081                        break;
2082                case 0x6823:
2083                case 0x682B:
2084                case 0x6822:
2085                case 0x682A:
2086                        si_pi->cac_weights = cac_weights_chelsea_pro;
2087                        si_pi->dte_data = dte_data_venus_pro;
2088                        break;
2089                default:
2090                        si_pi->cac_weights = cac_weights_cape_verde;
2091                        si_pi->dte_data = dte_data_cape_verde;
2092                        break;
2093                }
2094        } else if (adev->asic_type == CHIP_OLAND) {
2095                si_pi->lcac_config = lcac_mars_pro;
2096                si_pi->cac_override = cac_override_oland;
2097                si_pi->powertune_data = &powertune_data_mars_pro;
2098                si_pi->dte_data = dte_data_mars_pro;
2099
2100                switch (adev->pdev->device) {
2101                case 0x6601:
2102                case 0x6621:
2103                case 0x6603:
2104                case 0x6605:
2105                        si_pi->cac_weights = cac_weights_mars_pro;
2106                        update_dte_from_pl2 = true;
2107                        break;
2108                case 0x6600:
2109                case 0x6606:
2110                case 0x6620:
2111                case 0x6604:
2112                        si_pi->cac_weights = cac_weights_mars_xt;
2113                        update_dte_from_pl2 = true;
2114                        break;
2115                case 0x6611:
2116                case 0x6613:
2117                case 0x6608:
2118                        si_pi->cac_weights = cac_weights_oland_pro;
2119                        update_dte_from_pl2 = true;
2120                        break;
2121                case 0x6610:
2122                        si_pi->cac_weights = cac_weights_oland_xt;
2123                        update_dte_from_pl2 = true;
2124                        break;
2125                default:
2126                        si_pi->cac_weights = cac_weights_oland;
2127                        si_pi->lcac_config = lcac_oland;
2128                        si_pi->cac_override = cac_override_oland;
2129                        si_pi->powertune_data = &powertune_data_oland;
2130                        si_pi->dte_data = dte_data_oland;
2131                        break;
2132                }
2133        } else if (adev->asic_type == CHIP_HAINAN) {
2134                si_pi->cac_weights = cac_weights_hainan;
2135                si_pi->lcac_config = lcac_oland;
2136                si_pi->cac_override = cac_override_oland;
2137                si_pi->powertune_data = &powertune_data_hainan;
2138                si_pi->dte_data = dte_data_sun_xt;
2139                update_dte_from_pl2 = true;
2140        } else {
2141                DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2142                return;
2143        }
2144
2145        ni_pi->enable_power_containment = false;
2146        ni_pi->enable_cac = false;
2147        ni_pi->enable_sq_ramping = false;
2148        si_pi->enable_dte = false;
2149
2150        if (si_pi->powertune_data->enable_powertune_by_default) {
2151                ni_pi->enable_power_containment = true;
2152                ni_pi->enable_cac = true;
2153                if (si_pi->dte_data.enable_dte_by_default) {
2154                        si_pi->enable_dte = true;
2155                        if (update_dte_from_pl2)
2156                                si_update_dte_from_pl2(adev, &si_pi->dte_data);
2157
2158                }
2159                ni_pi->enable_sq_ramping = true;
2160        }
2161
2162        ni_pi->driver_calculate_cac_leakage = true;
2163        ni_pi->cac_configuration_required = true;
2164
2165        if (ni_pi->cac_configuration_required) {
2166                ni_pi->support_cac_long_term_average = true;
2167                si_pi->dyn_powertune_data.l2_lta_window_size =
2168                        si_pi->powertune_data->l2_lta_window_size_default;
2169                si_pi->dyn_powertune_data.lts_truncate =
2170                        si_pi->powertune_data->lts_truncate_default;
2171        } else {
2172                ni_pi->support_cac_long_term_average = false;
2173                si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2174                si_pi->dyn_powertune_data.lts_truncate = 0;
2175        }
2176
2177        si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2178}
2179
2180static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2181{
2182        return 1;
2183}
2184
2185static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2186{
2187        u32 xclk;
2188        u32 wintime;
2189        u32 cac_window;
2190        u32 cac_window_size;
2191
2192        xclk = amdgpu_asic_get_xclk(adev);
2193
2194        if (xclk == 0)
2195                return 0;
2196
2197        cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2198        cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2199
2200        wintime = (cac_window_size * 100) / xclk;
2201
2202        return wintime;
2203}
2204
2205static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2206{
2207        return power_in_watts;
2208}
2209
2210static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2211                                            bool adjust_polarity,
2212                                            u32 tdp_adjustment,
2213                                            u32 *tdp_limit,
2214                                            u32 *near_tdp_limit)
2215{
2216        u32 adjustment_delta, max_tdp_limit;
2217
2218        if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2219                return -EINVAL;
2220
2221        max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2222
2223        if (adjust_polarity) {
2224                *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2225                *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2226        } else {
2227                *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2228                adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2229                if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2230                        *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2231                else
2232                        *near_tdp_limit = 0;
2233        }
2234
2235        if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2236                return -EINVAL;
2237        if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2238                return -EINVAL;
2239
2240        return 0;
2241}
2242
2243static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2244                                      struct amdgpu_ps *amdgpu_state)
2245{
2246        struct ni_power_info *ni_pi = ni_get_pi(adev);
2247        struct si_power_info *si_pi = si_get_pi(adev);
2248
2249        if (ni_pi->enable_power_containment) {
2250                SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2251                PP_SIslands_PAPMParameters *papm_parm;
2252                struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2253                u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2254                u32 tdp_limit;
2255                u32 near_tdp_limit;
2256                int ret;
2257
2258                if (scaling_factor == 0)
2259                        return -EINVAL;
2260
2261                memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2262
2263                ret = si_calculate_adjusted_tdp_limits(adev,
2264                                                       false, /* ??? */
2265                                                       adev->pm.dpm.tdp_adjustment,
2266                                                       &tdp_limit,
2267                                                       &near_tdp_limit);
2268                if (ret)
2269                        return ret;
2270
2271                smc_table->dpm2Params.TDPLimit =
2272                        cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2273                smc_table->dpm2Params.NearTDPLimit =
2274                        cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2275                smc_table->dpm2Params.SafePowerLimit =
2276                        cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2277
2278                ret = amdgpu_si_copy_bytes_to_smc(adev,
2279                                                  (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2280                                                   offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2281                                                  (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2282                                                  sizeof(u32) * 3,
2283                                                  si_pi->sram_end);
2284                if (ret)
2285                        return ret;
2286
2287                if (si_pi->enable_ppm) {
2288                        papm_parm = &si_pi->papm_parm;
2289                        memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2290                        papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2291                        papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2292                        papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2293                        papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2294                        papm_parm->PlatformPowerLimit = 0xffffffff;
2295                        papm_parm->NearTDPLimitPAPM = 0xffffffff;
2296
2297                        ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2298                                                          (u8 *)papm_parm,
2299                                                          sizeof(PP_SIslands_PAPMParameters),
2300                                                          si_pi->sram_end);
2301                        if (ret)
2302                                return ret;
2303                }
2304        }
2305        return 0;
2306}
2307
2308static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2309                                        struct amdgpu_ps *amdgpu_state)
2310{
2311        struct ni_power_info *ni_pi = ni_get_pi(adev);
2312        struct si_power_info *si_pi = si_get_pi(adev);
2313
2314        if (ni_pi->enable_power_containment) {
2315                SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2316                u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2317                int ret;
2318
2319                memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2320
2321                smc_table->dpm2Params.NearTDPLimit =
2322                        cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2323                smc_table->dpm2Params.SafePowerLimit =
2324                        cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2325
2326                ret = amdgpu_si_copy_bytes_to_smc(adev,
2327                                                  (si_pi->state_table_start +
2328                                                   offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2329                                                   offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2330                                                  (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2331                                                  sizeof(u32) * 2,
2332                                                  si_pi->sram_end);
2333                if (ret)
2334                        return ret;
2335        }
2336
2337        return 0;
2338}
2339
2340static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2341                                               const u16 prev_std_vddc,
2342                                               const u16 curr_std_vddc)
2343{
2344        u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2345        u64 prev_vddc = (u64)prev_std_vddc;
2346        u64 curr_vddc = (u64)curr_std_vddc;
2347        u64 pwr_efficiency_ratio, n, d;
2348
2349        if ((prev_vddc == 0) || (curr_vddc == 0))
2350                return 0;
2351
2352        n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2353        d = prev_vddc * prev_vddc;
2354        pwr_efficiency_ratio = div64_u64(n, d);
2355
2356        if (pwr_efficiency_ratio > (u64)0xFFFF)
2357                return 0;
2358
2359        return (u16)pwr_efficiency_ratio;
2360}
2361
2362static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2363                                            struct amdgpu_ps *amdgpu_state)
2364{
2365        struct si_power_info *si_pi = si_get_pi(adev);
2366
2367        if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2368            amdgpu_state->vclk && amdgpu_state->dclk)
2369                return true;
2370
2371        return false;
2372}
2373
2374struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2375{
2376        struct evergreen_power_info *pi = adev->pm.dpm.priv;
2377
2378        return pi;
2379}
2380
2381static int si_populate_power_containment_values(struct amdgpu_device *adev,
2382                                                struct amdgpu_ps *amdgpu_state,
2383                                                SISLANDS_SMC_SWSTATE *smc_state)
2384{
2385        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2386        struct ni_power_info *ni_pi = ni_get_pi(adev);
2387        struct  si_ps *state = si_get_ps(amdgpu_state);
2388        SISLANDS_SMC_VOLTAGE_VALUE vddc;
2389        u32 prev_sclk;
2390        u32 max_sclk;
2391        u32 min_sclk;
2392        u16 prev_std_vddc;
2393        u16 curr_std_vddc;
2394        int i;
2395        u16 pwr_efficiency_ratio;
2396        u8 max_ps_percent;
2397        bool disable_uvd_power_tune;
2398        int ret;
2399
2400        if (ni_pi->enable_power_containment == false)
2401                return 0;
2402
2403        if (state->performance_level_count == 0)
2404                return -EINVAL;
2405
2406        if (smc_state->levelCount != state->performance_level_count)
2407                return -EINVAL;
2408
2409        disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2410
2411        smc_state->levels[0].dpm2.MaxPS = 0;
2412        smc_state->levels[0].dpm2.NearTDPDec = 0;
2413        smc_state->levels[0].dpm2.AboveSafeInc = 0;
2414        smc_state->levels[0].dpm2.BelowSafeInc = 0;
2415        smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2416
2417        for (i = 1; i < state->performance_level_count; i++) {
2418                prev_sclk = state->performance_levels[i-1].sclk;
2419                max_sclk  = state->performance_levels[i].sclk;
2420                if (i == 1)
2421                        max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2422                else
2423                        max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2424
2425                if (prev_sclk > max_sclk)
2426                        return -EINVAL;
2427
2428                if ((max_ps_percent == 0) ||
2429                    (prev_sclk == max_sclk) ||
2430                    disable_uvd_power_tune)
2431                        min_sclk = max_sclk;
2432                else if (i == 1)
2433                        min_sclk = prev_sclk;
2434                else
2435                        min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2436
2437                if (min_sclk < state->performance_levels[0].sclk)
2438                        min_sclk = state->performance_levels[0].sclk;
2439
2440                if (min_sclk == 0)
2441                        return -EINVAL;
2442
2443                ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2444                                                state->performance_levels[i-1].vddc, &vddc);
2445                if (ret)
2446                        return ret;
2447
2448                ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2449                if (ret)
2450                        return ret;
2451
2452                ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2453                                                state->performance_levels[i].vddc, &vddc);
2454                if (ret)
2455                        return ret;
2456
2457                ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2458                if (ret)
2459                        return ret;
2460
2461                pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2462                                                                           prev_std_vddc, curr_std_vddc);
2463
2464                smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2465                smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2466                smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2467                smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2468                smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2469        }
2470
2471        return 0;
2472}
2473
2474static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2475                                         struct amdgpu_ps *amdgpu_state,
2476                                         SISLANDS_SMC_SWSTATE *smc_state)
2477{
2478        struct ni_power_info *ni_pi = ni_get_pi(adev);
2479        struct  si_ps *state = si_get_ps(amdgpu_state);
2480        u32 sq_power_throttle, sq_power_throttle2;
2481        bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2482        int i;
2483
2484        if (state->performance_level_count == 0)
2485                return -EINVAL;
2486
2487        if (smc_state->levelCount != state->performance_level_count)
2488                return -EINVAL;
2489
2490        if (adev->pm.dpm.sq_ramping_threshold == 0)
2491                return -EINVAL;
2492
2493        if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2494                enable_sq_ramping = false;
2495
2496        if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2497                enable_sq_ramping = false;
2498
2499        if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2500                enable_sq_ramping = false;
2501
2502        if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2503                enable_sq_ramping = false;
2504
2505        if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2506                enable_sq_ramping = false;
2507
2508        for (i = 0; i < state->performance_level_count; i++) {
2509                sq_power_throttle = 0;
2510                sq_power_throttle2 = 0;
2511
2512                if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2513                    enable_sq_ramping) {
2514                        sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2515                        sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2516                        sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2517                        sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2518                        sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2519                } else {
2520                        sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2521                        sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2522                }
2523
2524                smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2525                smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2526        }
2527
2528        return 0;
2529}
2530
2531static int si_enable_power_containment(struct amdgpu_device *adev,
2532                                       struct amdgpu_ps *amdgpu_new_state,
2533                                       bool enable)
2534{
2535        struct ni_power_info *ni_pi = ni_get_pi(adev);
2536        PPSMC_Result smc_result;
2537        int ret = 0;
2538
2539        if (ni_pi->enable_power_containment) {
2540                if (enable) {
2541                        if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2542                                smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2543                                if (smc_result != PPSMC_Result_OK) {
2544                                        ret = -EINVAL;
2545                                        ni_pi->pc_enabled = false;
2546                                } else {
2547                                        ni_pi->pc_enabled = true;
2548                                }
2549                        }
2550                } else {
2551                        smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2552                        if (smc_result != PPSMC_Result_OK)
2553                                ret = -EINVAL;
2554                        ni_pi->pc_enabled = false;
2555                }
2556        }
2557
2558        return ret;
2559}
2560
2561static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2562{
2563        struct si_power_info *si_pi = si_get_pi(adev);
2564        int ret = 0;
2565        struct si_dte_data *dte_data = &si_pi->dte_data;
2566        Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2567        u32 table_size;
2568        u8 tdep_count;
2569        u32 i;
2570
2571        if (dte_data == NULL)
2572                si_pi->enable_dte = false;
2573
2574        if (si_pi->enable_dte == false)
2575                return 0;
2576
2577        if (dte_data->k <= 0)
2578                return -EINVAL;
2579
2580        dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2581        if (dte_tables == NULL) {
2582                si_pi->enable_dte = false;
2583                return -ENOMEM;
2584        }
2585
2586        table_size = dte_data->k;
2587
2588        if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2589                table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2590
2591        tdep_count = dte_data->tdep_count;
2592        if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2593                tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2594
2595        dte_tables->K = cpu_to_be32(table_size);
2596        dte_tables->T0 = cpu_to_be32(dte_data->t0);
2597        dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2598        dte_tables->WindowSize = dte_data->window_size;
2599        dte_tables->temp_select = dte_data->temp_select;
2600        dte_tables->DTE_mode = dte_data->dte_mode;
2601        dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2602
2603        if (tdep_count > 0)
2604                table_size--;
2605
2606        for (i = 0; i < table_size; i++) {
2607                dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2608                dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2609        }
2610
2611        dte_tables->Tdep_count = tdep_count;
2612
2613        for (i = 0; i < (u32)tdep_count; i++) {
2614                dte_tables->T_limits[i] = dte_data->t_limits[i];
2615                dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2616                dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2617        }
2618
2619        ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2620                                          (u8 *)dte_tables,
2621                                          sizeof(Smc_SIslands_DTE_Configuration),
2622                                          si_pi->sram_end);
2623        kfree(dte_tables);
2624
2625        return ret;
2626}
2627
2628static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2629                                          u16 *max, u16 *min)
2630{
2631        struct si_power_info *si_pi = si_get_pi(adev);
2632        struct amdgpu_cac_leakage_table *table =
2633                &adev->pm.dpm.dyn_state.cac_leakage_table;
2634        u32 i;
2635        u32 v0_loadline;
2636
2637        if (table == NULL)
2638                return -EINVAL;
2639
2640        *max = 0;
2641        *min = 0xFFFF;
2642
2643        for (i = 0; i < table->count; i++) {
2644                if (table->entries[i].vddc > *max)
2645                        *max = table->entries[i].vddc;
2646                if (table->entries[i].vddc < *min)
2647                        *min = table->entries[i].vddc;
2648        }
2649
2650        if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2651                return -EINVAL;
2652
2653        v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2654
2655        if (v0_loadline > 0xFFFFUL)
2656                return -EINVAL;
2657
2658        *min = (u16)v0_loadline;
2659
2660        if ((*min > *max) || (*max == 0) || (*min == 0))
2661                return -EINVAL;
2662
2663        return 0;
2664}
2665
2666static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2667{
2668        return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2669                SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2670}
2671
2672static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2673                                     PP_SIslands_CacConfig *cac_tables,
2674                                     u16 vddc_max, u16 vddc_min, u16 vddc_step,
2675                                     u16 t0, u16 t_step)
2676{
2677        struct si_power_info *si_pi = si_get_pi(adev);
2678        u32 leakage;
2679        unsigned int i, j;
2680        s32 t;
2681        u32 smc_leakage;
2682        u32 scaling_factor;
2683        u16 voltage;
2684
2685        scaling_factor = si_get_smc_power_scaling_factor(adev);
2686
2687        for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2688                t = (1000 * (i * t_step + t0));
2689
2690                for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2691                        voltage = vddc_max - (vddc_step * j);
2692
2693                        si_calculate_leakage_for_v_and_t(adev,
2694                                                         &si_pi->powertune_data->leakage_coefficients,
2695                                                         voltage,
2696                                                         t,
2697                                                         si_pi->dyn_powertune_data.cac_leakage,
2698                                                         &leakage);
2699
2700                        smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2701
2702                        if (smc_leakage > 0xFFFF)
2703                                smc_leakage = 0xFFFF;
2704
2705                        cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2706                                cpu_to_be16((u16)smc_leakage);
2707                }
2708        }
2709        return 0;
2710}
2711
2712static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2713                                            PP_SIslands_CacConfig *cac_tables,
2714                                            u16 vddc_max, u16 vddc_min, u16 vddc_step)
2715{
2716        struct si_power_info *si_pi = si_get_pi(adev);
2717        u32 leakage;
2718        unsigned int i, j;
2719        u32 smc_leakage;
2720        u32 scaling_factor;
2721        u16 voltage;
2722
2723        scaling_factor = si_get_smc_power_scaling_factor(adev);
2724
2725        for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2726                voltage = vddc_max - (vddc_step * j);
2727
2728                si_calculate_leakage_for_v(adev,
2729                                           &si_pi->powertune_data->leakage_coefficients,
2730                                           si_pi->powertune_data->fixed_kt,
2731                                           voltage,
2732                                           si_pi->dyn_powertune_data.cac_leakage,
2733                                           &leakage);
2734
2735                smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2736
2737                if (smc_leakage > 0xFFFF)
2738                        smc_leakage = 0xFFFF;
2739
2740                for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2741                        cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2742                                cpu_to_be16((u16)smc_leakage);
2743        }
2744        return 0;
2745}
2746
2747static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2748{
2749        struct ni_power_info *ni_pi = ni_get_pi(adev);
2750        struct si_power_info *si_pi = si_get_pi(adev);
2751        PP_SIslands_CacConfig *cac_tables = NULL;
2752        u16 vddc_max, vddc_min, vddc_step;
2753        u16 t0, t_step;
2754        u32 load_line_slope, reg;
2755        int ret = 0;
2756        u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2757
2758        if (ni_pi->enable_cac == false)
2759                return 0;
2760
2761        cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2762        if (!cac_tables)
2763                return -ENOMEM;
2764
2765        reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2766        reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2767        WREG32(CG_CAC_CTRL, reg);
2768
2769        si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2770        si_pi->dyn_powertune_data.dc_pwr_value =
2771                si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2772        si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2773        si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2774
2775        si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2776
2777        ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2778        if (ret)
2779                goto done_free;
2780
2781        vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2782        vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2783        t_step = 4;
2784        t0 = 60;
2785
2786        if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2787                ret = si_init_dte_leakage_table(adev, cac_tables,
2788                                                vddc_max, vddc_min, vddc_step,
2789                                                t0, t_step);
2790        else
2791                ret = si_init_simplified_leakage_table(adev, cac_tables,
2792                                                       vddc_max, vddc_min, vddc_step);
2793        if (ret)
2794                goto done_free;
2795
2796        load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2797
2798        cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2799        cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2800        cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2801        cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2802        cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2803        cac_tables->R_LL = cpu_to_be32(load_line_slope);
2804        cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2805        cac_tables->calculation_repeats = cpu_to_be32(2);
2806        cac_tables->dc_cac = cpu_to_be32(0);
2807        cac_tables->log2_PG_LKG_SCALE = 12;
2808        cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2809        cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2810        cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2811
2812        ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2813                                          (u8 *)cac_tables,
2814                                          sizeof(PP_SIslands_CacConfig),
2815                                          si_pi->sram_end);
2816
2817        if (ret)
2818                goto done_free;
2819
2820        ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2821
2822done_free:
2823        if (ret) {
2824                ni_pi->enable_cac = false;
2825                ni_pi->enable_power_containment = false;
2826        }
2827
2828        kfree(cac_tables);
2829
2830        return ret;
2831}
2832
2833static int si_program_cac_config_registers(struct amdgpu_device *adev,
2834                                           const struct si_cac_config_reg *cac_config_regs)
2835{
2836        const struct si_cac_config_reg *config_regs = cac_config_regs;
2837        u32 data = 0, offset;
2838
2839        if (!config_regs)
2840                return -EINVAL;
2841
2842        while (config_regs->offset != 0xFFFFFFFF) {
2843                switch (config_regs->type) {
2844                case SISLANDS_CACCONFIG_CGIND:
2845                        offset = SMC_CG_IND_START + config_regs->offset;
2846                        if (offset < SMC_CG_IND_END)
2847                                data = RREG32_SMC(offset);
2848                        break;
2849                default:
2850                        data = RREG32(config_regs->offset);
2851                        break;
2852                }
2853
2854                data &= ~config_regs->mask;
2855                data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2856
2857                switch (config_regs->type) {
2858                case SISLANDS_CACCONFIG_CGIND:
2859                        offset = SMC_CG_IND_START + config_regs->offset;
2860                        if (offset < SMC_CG_IND_END)
2861                                WREG32_SMC(offset, data);
2862                        break;
2863                default:
2864                        WREG32(config_regs->offset, data);
2865                        break;
2866                }
2867                config_regs++;
2868        }
2869        return 0;
2870}
2871
2872static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2873{
2874        struct ni_power_info *ni_pi = ni_get_pi(adev);
2875        struct si_power_info *si_pi = si_get_pi(adev);
2876        int ret;
2877
2878        if ((ni_pi->enable_cac == false) ||
2879            (ni_pi->cac_configuration_required == false))
2880                return 0;
2881
2882        ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2883        if (ret)
2884                return ret;
2885        ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2886        if (ret)
2887                return ret;
2888        ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2889        if (ret)
2890                return ret;
2891
2892        return 0;
2893}
2894
2895static int si_enable_smc_cac(struct amdgpu_device *adev,
2896                             struct amdgpu_ps *amdgpu_new_state,
2897                             bool enable)
2898{
2899        struct ni_power_info *ni_pi = ni_get_pi(adev);
2900        struct si_power_info *si_pi = si_get_pi(adev);
2901        PPSMC_Result smc_result;
2902        int ret = 0;
2903
2904        if (ni_pi->enable_cac) {
2905                if (enable) {
2906                        if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2907                                if (ni_pi->support_cac_long_term_average) {
2908                                        smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2909                                        if (smc_result != PPSMC_Result_OK)
2910                                                ni_pi->support_cac_long_term_average = false;
2911                                }
2912
2913                                smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2914                                if (smc_result != PPSMC_Result_OK) {
2915                                        ret = -EINVAL;
2916                                        ni_pi->cac_enabled = false;
2917                                } else {
2918                                        ni_pi->cac_enabled = true;
2919                                }
2920
2921                                if (si_pi->enable_dte) {
2922                                        smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2923                                        if (smc_result != PPSMC_Result_OK)
2924                                                ret = -EINVAL;
2925                                }
2926                        }
2927                } else if (ni_pi->cac_enabled) {
2928                        if (si_pi->enable_dte)
2929                                smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2930
2931                        smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2932
2933                        ni_pi->cac_enabled = false;
2934
2935                        if (ni_pi->support_cac_long_term_average)
2936                                smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2937                }
2938        }
2939        return ret;
2940}
2941
2942static int si_init_smc_spll_table(struct amdgpu_device *adev)
2943{
2944        struct ni_power_info *ni_pi = ni_get_pi(adev);
2945        struct si_power_info *si_pi = si_get_pi(adev);
2946        SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2947        SISLANDS_SMC_SCLK_VALUE sclk_params;
2948        u32 fb_div, p_div;
2949        u32 clk_s, clk_v;
2950        u32 sclk = 0;
2951        int ret = 0;
2952        u32 tmp;
2953        int i;
2954
2955        if (si_pi->spll_table_start == 0)
2956                return -EINVAL;
2957
2958        spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2959        if (spll_table == NULL)
2960                return -ENOMEM;
2961
2962        for (i = 0; i < 256; i++) {
2963                ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2964                if (ret)
2965                        break;
2966                p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2967                fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2968                clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2969                clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2970
2971                fb_div &= ~0x00001FFF;
2972                fb_div >>= 1;
2973                clk_v >>= 6;
2974
2975                if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2976                        ret = -EINVAL;
2977                if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2978                        ret = -EINVAL;
2979                if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2980                        ret = -EINVAL;
2981                if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2982                        ret = -EINVAL;
2983
2984                if (ret)
2985                        break;
2986
2987                tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2988                        ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2989                spll_table->freq[i] = cpu_to_be32(tmp);
2990
2991                tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2992                        ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2993                spll_table->ss[i] = cpu_to_be32(tmp);
2994
2995                sclk += 512;
2996        }
2997
2998
2999        if (!ret)
3000                ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,

3001                                                  (u8 *)spll_table,
3002                                                  sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3003                                                  si_pi->sram_end);
3004
3005        if (ret)
3006                ni_pi->enable_power_containment = false;
3007
3008        kfree(spll_table);
3009
3010        return ret;
3011}
3012
3013static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3014                                                   u16 vce_voltage)
3015{
3016        u16 highest_leakage = 0;
3017        struct si_power_info *si_pi = si_get_pi(adev);
3018        int i;
3019
3020        for (i = 0; i < si_pi->leakage_voltage.count; i++){
3021                if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3022                        highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3023        }
3024
3025        if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3026                return highest_leakage;
3027
3028        return vce_voltage;
3029}
3030
3031static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3032                                    u32 evclk, u32 ecclk, u16 *voltage)
3033{
3034        u32 i;
3035        int ret = -EINVAL;
3036        struct amdgpu_vce_clock_voltage_dependency_table *table =
3037                &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3038
3039        if (((evclk == 0) && (ecclk == 0)) ||
3040            (table && (table->count == 0))) {
3041                *voltage = 0;
3042                return 0;
3043        }
3044
3045        for (i = 0; i < table->count; i++) {
3046                if ((evclk <= table->entries[i].evclk) &&
3047                    (ecclk <= table->entries[i].ecclk)) {
3048                        *voltage = table->entries[i].v;
3049                        ret = 0;
3050                        break;
3051                }
3052        }
3053
3054        /* if no match return the highest voltage */
3055        if (ret)
3056                *voltage = table->entries[table->count - 1].v;
3057
3058        *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3059
3060        return ret;
3061}
3062
3063static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3064{
3065
3066        u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3067        /* we never hit the non-gddr5 limit so disable it */
3068        u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3069
3070        if (vblank_time < switch_limit)
3071                return true;
3072        else
3073                return false;
3074
3075}
3076
3077static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3078                                u32 arb_freq_src, u32 arb_freq_dest)
3079{
3080        u32 mc_arb_dram_timing;
3081        u32 mc_arb_dram_timing2;
3082        u32 burst_time;
3083        u32 mc_cg_config;
3084
3085        switch (arb_freq_src) {
3086        case MC_CG_ARB_FREQ_F0:
3087                mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3088                mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3089                burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3090                break;
3091        case MC_CG_ARB_FREQ_F1:
3092                mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3093                mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3094                burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3095                break;
3096        case MC_CG_ARB_FREQ_F2:
3097                mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3098                mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3099                burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3100                break;
3101        case MC_CG_ARB_FREQ_F3:
3102                mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3103                mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3104                burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3105                break;
3106        default:
3107                return -EINVAL;
3108        }
3109
3110        switch (arb_freq_dest) {
3111        case MC_CG_ARB_FREQ_F0:
3112                WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3113                WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3114                WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3115                break;
3116        case MC_CG_ARB_FREQ_F1:
3117                WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3118                WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3119                WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3120                break;
3121        case MC_CG_ARB_FREQ_F2:
3122                WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3123                WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3124                WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3125                break;
3126        case MC_CG_ARB_FREQ_F3:
3127                WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3128                WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3129                WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3130                break;
3131        default:
3132                return -EINVAL;
3133        }
3134
3135        mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3136        WREG32(MC_CG_CONFIG, mc_cg_config);
3137        WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3138
3139        return 0;
3140}
3141
3142static void ni_update_current_ps(struct amdgpu_device *adev,
3143                          struct amdgpu_ps *rps)
3144{
3145        struct si_ps *new_ps = si_get_ps(rps);
3146        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3147        struct ni_power_info *ni_pi = ni_get_pi(adev);
3148
3149        eg_pi->current_rps = *rps;
3150        ni_pi->current_ps = *new_ps;
3151        eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3152        adev->pm.dpm.current_ps = &eg_pi->current_rps;
3153}
3154
3155static void ni_update_requested_ps(struct amdgpu_device *adev,
3156                            struct amdgpu_ps *rps)
3157{
3158        struct si_ps *new_ps = si_get_ps(rps);
3159        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3160        struct ni_power_info *ni_pi = ni_get_pi(adev);
3161
3162        eg_pi->requested_rps = *rps;
3163        ni_pi->requested_ps = *new_ps;
3164        eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3165        adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3166}
3167
3168static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3169                                           struct amdgpu_ps *new_ps,
3170                                           struct amdgpu_ps *old_ps)
3171{
3172        struct si_ps *new_state = si_get_ps(new_ps);
3173        struct si_ps *current_state = si_get_ps(old_ps);
3174
3175        if ((new_ps->vclk == old_ps->vclk) &&
3176            (new_ps->dclk == old_ps->dclk))
3177                return;
3178
3179        if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3180            current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3181                return;
3182
3183        amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3184}
3185
3186static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3187                                          struct amdgpu_ps *new_ps,
3188                                          struct amdgpu_ps *old_ps)
3189{
3190        struct si_ps *new_state = si_get_ps(new_ps);
3191        struct si_ps *current_state = si_get_ps(old_ps);
3192
3193        if ((new_ps->vclk == old_ps->vclk) &&
3194            (new_ps->dclk == old_ps->dclk))
3195                return;
3196
3197        if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3198            current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3199                return;
3200
3201        amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3202}
3203
3204static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3205{
3206        unsigned int i;
3207
3208        for (i = 0; i < table->count; i++)
3209                if (voltage <= table->entries[i].value)
3210                        return table->entries[i].value;
3211
3212        return table->entries[table->count - 1].value;
3213}
3214
3215static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3216                                u32 max_clock, u32 requested_clock)
3217{
3218        unsigned int i;
3219
3220        if ((clocks == NULL) || (clocks->count == 0))
3221                return (requested_clock < max_clock) ? requested_clock : max_clock;
3222
3223        for (i = 0; i < clocks->count; i++) {
3224                if (clocks->values[i] >= requested_clock)
3225                        return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3226        }
3227
3228        return (clocks->values[clocks->count - 1] < max_clock) ?
3229                clocks->values[clocks->count - 1] : max_clock;
3230}
3231
3232static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3233                              u32 max_mclk, u32 requested_mclk)
3234{
3235        return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3236                                    max_mclk, requested_mclk);
3237}
3238
3239static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3240                              u32 max_sclk, u32 requested_sclk)
3241{
3242        return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3243                                    max_sclk, requested_sclk);
3244}
3245
3246static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3247                                                            u32 *max_clock)
3248{
3249        u32 i, clock = 0;
3250
3251        if ((table == NULL) || (table->count == 0)) {
3252                *max_clock = clock;
3253                return;
3254        }
3255
3256        for (i = 0; i < table->count; i++) {
3257                if (clock < table->entries[i].clk)
3258                        clock = table->entries[i].clk;
3259        }
3260        *max_clock = clock;
3261}
3262
3263static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3264                                               u32 clock, u16 max_voltage, u16 *voltage)
3265{
3266        u32 i;
3267
3268        if ((table == NULL) || (table->count == 0))
3269                return;
3270
3271        for (i= 0; i < table->count; i++) {
3272                if (clock <= table->entries[i].clk) {
3273                        if (*voltage < table->entries[i].v)
3274                                *voltage = (u16)((table->entries[i].v < max_voltage) ?
3275                                           table->entries[i].v : max_voltage);
3276                        return;
3277                }
3278        }
3279
3280        *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3281}
3282
3283static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3284                                          const struct amdgpu_clock_and_voltage_limits *max_limits,
3285                                          struct rv7xx_pl *pl)
3286{
3287
3288        if ((pl->mclk == 0) || (pl->sclk == 0))
3289                return;
3290
3291        if (pl->mclk == pl->sclk)
3292                return;
3293
3294        if (pl->mclk > pl->sclk) {
3295                if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3296                        pl->sclk = btc_get_valid_sclk(adev,
3297                                                      max_limits->sclk,
3298                                                      (pl->mclk +
3299                                                      (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3300                                                      adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3301        } else {
3302                if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3303                        pl->mclk = btc_get_valid_mclk(adev,
3304                                                      max_limits->mclk,
3305                                                      pl->sclk -
3306                                                      adev->pm.dpm.dyn_state.sclk_mclk_delta);
3307        }
3308}
3309
3310static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3311                                          u16 max_vddc, u16 max_vddci,
3312                                          u16 *vddc, u16 *vddci)
3313{
3314        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3315        u16 new_voltage;
3316
3317        if ((0 == *vddc) || (0 == *vddci))
3318                return;
3319
3320        if (*vddc > *vddci) {
3321                if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3322                        new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3323                                                       (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3324                        *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3325                }
3326        } else {
3327                if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3328                        new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3329                                                       (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3330                        *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3331                }
3332        }
3333}
3334
3335static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3336                                               u32 sys_mask,
3337                                               enum amdgpu_pcie_gen asic_gen,
3338                                               enum amdgpu_pcie_gen default_gen)
3339{
3340        switch (asic_gen) {
3341        case AMDGPU_PCIE_GEN1:
3342                return AMDGPU_PCIE_GEN1;
3343        case AMDGPU_PCIE_GEN2:
3344                return AMDGPU_PCIE_GEN2;
3345        case AMDGPU_PCIE_GEN3:
3346                return AMDGPU_PCIE_GEN3;
3347        default:
3348                if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3349                        return AMDGPU_PCIE_GEN3;
3350                else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3351                        return AMDGPU_PCIE_GEN2;
3352                else
3353                        return AMDGPU_PCIE_GEN1;
3354        }
3355        return AMDGPU_PCIE_GEN1;
3356}
3357
3358static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3359                            u32 *p, u32 *u)
3360{
3361        u32 b_c = 0;
3362        u32 i_c;
3363        u32 tmp;
3364
3365        i_c = (i * r_c) / 100;
3366        tmp = i_c >> p_b;
3367
3368        while (tmp) {
3369                b_c++;
3370                tmp >>= 1;
3371        }
3372
3373        *u = (b_c + 1) / 2;
3374        *p = i_c / (1 << (2 * (*u)));
3375}
3376
3377static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3378{
3379        u32 k, a, ah, al;
3380        u32 t1;
3381
3382        if ((fl == 0) || (fh == 0) || (fl > fh))
3383                return -EINVAL;
3384
3385        k = (100 * fh) / fl;
3386        t1 = (t * (k - 100));
3387        a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3388        a = (a + 5) / 10;
3389        ah = ((a * t) + 5000) / 10000;
3390        al = a - ah;
3391
3392        *th = t - ah;
3393        *tl = t + al;
3394
3395        return 0;
3396}
3397
3398static bool r600_is_uvd_state(u32 class, u32 class2)
3399{
3400        if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3401                return true;
3402        if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3403                return true;
3404        if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3405                return true;
3406        if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3407                return true;
3408        if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3409                return true;
3410        return false;
3411}
3412
3413static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3414{
3415        return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3416}
3417
3418static void rv770_get_max_vddc(struct amdgpu_device *adev)
3419{
3420        struct rv7xx_power_info *pi = rv770_get_pi(adev);
3421        u16 vddc;
3422
3423        if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3424                pi->max_vddc = 0;
3425        else
3426                pi->max_vddc = vddc;
3427}
3428
3429static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3430{
3431        struct rv7xx_power_info *pi = rv770_get_pi(adev);
3432        struct amdgpu_atom_ss ss;
3433
3434        pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3435                                                       ASIC_INTERNAL_ENGINE_SS, 0);
3436        pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3437                                                       ASIC_INTERNAL_MEMORY_SS, 0);
3438
3439        if (pi->sclk_ss || pi->mclk_ss)
3440                pi->dynamic_ss = true;
3441        else
3442                pi->dynamic_ss = false;
3443}
3444
3445
3446static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3447                                        struct amdgpu_ps *rps)
3448{
3449        struct  si_ps *ps = si_get_ps(rps);
3450        struct amdgpu_clock_and_voltage_limits *max_limits;
3451        bool disable_mclk_switching = false;
3452        bool disable_sclk_switching = false;
3453        u32 mclk, sclk;
3454        u16 vddc, vddci, min_vce_voltage = 0;
3455        u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3456        u32 max_sclk = 0, max_mclk = 0;
3457        int i;
3458
3459        if (adev->asic_type == CHIP_HAINAN) {
3460                if ((adev->pdev->revision == 0x81) ||
3461                    (adev->pdev->revision == 0x83) ||
3462                    (adev->pdev->revision == 0xC3) ||
3463                    (adev->pdev->device == 0x6664) ||
3464                    (adev->pdev->device == 0x6665) ||
3465                    (adev->pdev->device == 0x6667)) {
3466                        max_sclk = 75000;
3467                }
3468        } else if (adev->asic_type == CHIP_OLAND) {
3469                if ((adev->pdev->revision == 0xC7) ||
3470                    (adev->pdev->revision == 0x80) ||
3471                    (adev->pdev->revision == 0x81) ||
3472                    (adev->pdev->revision == 0x83) ||
3473                    (adev->pdev->revision == 0x87) ||
3474                    (adev->pdev->device == 0x6604) ||
3475                    (adev->pdev->device == 0x6605)) {
3476                        max_sclk = 75000;
3477                }
3478        }
3479
3480        if (rps->vce_active) {
3481                rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3482                rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3483                si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3484                                         &min_vce_voltage);
3485        } else {
3486                rps->evclk = 0;
3487                rps->ecclk = 0;
3488        }
3489
3490        if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3491            si_dpm_vblank_too_short(adev))
3492                disable_mclk_switching = true;
3493
3494        if (rps->vclk || rps->dclk) {
3495                disable_mclk_switching = true;
3496                disable_sclk_switching = true;
3497        }
3498
3499        if (adev->pm.dpm.ac_power)
3500                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3501        else
3502                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3503
3504        for (i = ps->performance_level_count - 2; i >= 0; i--) {
3505                if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3506                        ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3507        }
3508        if (adev->pm.dpm.ac_power == false) {
3509                for (i = 0; i < ps->performance_level_count; i++) {
3510                        if (ps->performance_levels[i].mclk > max_limits->mclk)
3511                                ps->performance_levels[i].mclk = max_limits->mclk;
3512                        if (ps->performance_levels[i].sclk > max_limits->sclk)
3513                                ps->performance_levels[i].sclk = max_limits->sclk;
3514                        if (ps->performance_levels[i].vddc > max_limits->vddc)
3515                                ps->performance_levels[i].vddc = max_limits->vddc;
3516                        if (ps->performance_levels[i].vddci > max_limits->vddci)
3517                                ps->performance_levels[i].vddci = max_limits->vddci;
3518                }
3519        }
3520
3521        /* limit clocks to max supported clocks based on voltage dependency tables */
3522        btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3523                                                        &max_sclk_vddc);
3524        btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3525                                                        &max_mclk_vddci);
3526        btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3527                                                        &max_mclk_vddc);
3528
3529        for (i = 0; i < ps->performance_level_count; i++) {
3530                if (max_sclk_vddc) {
3531                        if (ps->performance_levels[i].sclk > max_sclk_vddc)
3532                                ps->performance_levels[i].sclk = max_sclk_vddc;
3533                }
3534                if (max_mclk_vddci) {
3535                        if (ps->performance_levels[i].mclk > max_mclk_vddci)
3536                                ps->performance_levels[i].mclk = max_mclk_vddci;
3537                }
3538                if (max_mclk_vddc) {
3539                        if (ps->performance_levels[i].mclk > max_mclk_vddc)
3540                                ps->performance_levels[i].mclk = max_mclk_vddc;
3541                }
3542                if (max_mclk) {
3543                        if (ps->performance_levels[i].mclk > max_mclk)
3544                                ps->performance_levels[i].mclk = max_mclk;
3545                }
3546                if (max_sclk) {
3547                        if (ps->performance_levels[i].sclk > max_sclk)
3548                                ps->performance_levels[i].sclk = max_sclk;
3549                }
3550        }
3551
3552        /* XXX validate the min clocks required for display */
3553
3554        if (disable_mclk_switching) {
3555                mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3556                vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3557        } else {
3558                mclk = ps->performance_levels[0].mclk;
3559                vddci = ps->performance_levels[0].vddci;
3560        }
3561
3562        if (disable_sclk_switching) {
3563                sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3564                vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3565        } else {
3566                sclk = ps->performance_levels[0].sclk;
3567                vddc = ps->performance_levels[0].vddc;
3568        }
3569
3570        if (rps->vce_active) {
3571                if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3572                        sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3573                if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3574                        mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3575        }
3576
3577        /* adjusted low state */
3578        ps->performance_levels[0].sclk = sclk;
3579        ps->performance_levels[0].mclk = mclk;
3580        ps->performance_levels[0].vddc = vddc;
3581        ps->performance_levels[0].vddci = vddci;
3582
3583        if (disable_sclk_switching) {
3584                sclk = ps->performance_levels[0].sclk;
3585                for (i = 1; i < ps->performance_level_count; i++) {
3586                        if (sclk < ps->performance_levels[i].sclk)
3587                                sclk = ps->performance_levels[i].sclk;
3588                }
3589                for (i = 0; i < ps->performance_level_count; i++) {
3590                        ps->performance_levels[i].sclk = sclk;
3591                        ps->performance_levels[i].vddc = vddc;
3592                }
3593        } else {
3594                for (i = 1; i < ps->performance_level_count; i++) {
3595                        if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3596                                ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3597                        if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3598                                ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3599                }
3600        }
3601
3602        if (disable_mclk_switching) {
3603                mclk = ps->performance_levels[0].mclk;
3604                for (i = 1; i < ps->performance_level_count; i++) {
3605                        if (mclk < ps->performance_levels[i].mclk)
3606                                mclk = ps->performance_levels[i].mclk;
3607                }
3608                for (i = 0; i < ps->performance_level_count; i++) {
3609                        ps->performance_levels[i].mclk = mclk;
3610                        ps->performance_levels[i].vddci = vddci;
3611                }
3612        } else {
3613                for (i = 1; i < ps->performance_level_count; i++) {
3614                        if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3615                                ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3616                        if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3617                                ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3618                }
3619        }
3620
3621        for (i = 0; i < ps->performance_level_count; i++)
3622                btc_adjust_clock_combinations(adev, max_limits,
3623                                              &ps->performance_levels[i]);
3624
3625        for (i = 0; i < ps->performance_level_count; i++) {
3626                if (ps->performance_levels[i].vddc < min_vce_voltage)
3627                        ps->performance_levels[i].vddc = min_vce_voltage;
3628                btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3629                                                   ps->performance_levels[i].sclk,
3630                                                   max_limits->vddc,  &ps->performance_levels[i].vddc);
3631                btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3632                                                   ps->performance_levels[i].mclk,
3633                                                   max_limits->vddci, &ps->performance_levels[i].vddci);
3634                btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3635                                                   ps->performance_levels[i].mclk,
3636                                                   max_limits->vddc,  &ps->performance_levels[i].vddc);
3637                btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3638                                                   adev->clock.current_dispclk,
3639                                                   max_limits->vddc,  &ps->performance_levels[i].vddc);
3640        }
3641
3642        for (i = 0; i < ps->performance_level_count; i++) {
3643                btc_apply_voltage_delta_rules(adev,
3644                                              max_limits->vddc, max_limits->vddci,
3645                                              &ps->performance_levels[i].vddc,
3646                                              &ps->performance_levels[i].vddci);
3647        }
3648
3649        ps->dc_compatible = true;
3650        for (i = 0; i < ps->performance_level_count; i++) {
3651                if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3652                        ps->dc_compatible = false;
3653        }
3654}
3655
3656#if 0
3657static int si_read_smc_soft_register(struct amdgpu_device *adev,
3658                                     u16 reg_offset, u32 *value)
3659{
3660        struct si_power_info *si_pi = si_get_pi(adev);
3661
3662        return amdgpu_si_read_smc_sram_dword(adev,
3663                                             si_pi->soft_regs_start + reg_offset, value,
3664                                             si_pi->sram_end);
3665}
3666#endif
3667
3668static int si_write_smc_soft_register(struct amdgpu_device *adev,
3669                                      u16 reg_offset, u32 value)
3670{
3671        struct si_power_info *si_pi = si_get_pi(adev);
3672
3673        return amdgpu_si_write_smc_sram_dword(adev,
3674                                              si_pi->soft_regs_start + reg_offset,
3675                                              value, si_pi->sram_end);
3676}
3677
3678static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3679{
3680        bool ret = false;
3681        u32 tmp, width, row, column, bank, density;
3682        bool is_memory_gddr5, is_special;
3683
3684        tmp = RREG32(MC_SEQ_MISC0);
3685        is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3686        is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3687                & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3688
3689        WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3690        width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3691
3692        tmp = RREG32(MC_ARB_RAMCFG);
3693        row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3694        column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3695        bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3696
3697        density = (1 << (row + column - 20 + bank)) * width;
3698
3699        if ((adev->pdev->device == 0x6819) &&
3700            is_memory_gddr5 && is_special && (density == 0x400))
3701                ret = true;
3702
3703        return ret;
3704}
3705
3706static void si_get_leakage_vddc(struct amdgpu_device *adev)
3707{
3708        struct si_power_info *si_pi = si_get_pi(adev);
3709        u16 vddc, count = 0;
3710        int i, ret;
3711
3712        for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3713                ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3714
3715                if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3716                        si_pi->leakage_voltage.entries[count].voltage = vddc;
3717                        si_pi->leakage_voltage.entries[count].leakage_index =
3718                                SISLANDS_LEAKAGE_INDEX0 + i;
3719                        count++;
3720                }
3721        }
3722        si_pi->leakage_voltage.count = count;
3723}
3724
3725static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3726                                                     u32 index, u16 *leakage_voltage)
3727{
3728        struct si_power_info *si_pi = si_get_pi(adev);
3729        int i;
3730
3731        if (leakage_voltage == NULL)
3732                return -EINVAL;
3733
3734        if ((index & 0xff00) != 0xff00)
3735                return -EINVAL;
3736
3737        if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3738                return -EINVAL;
3739
3740        if (index < SISLANDS_LEAKAGE_INDEX0)
3741                return -EINVAL;
3742
3743        for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3744                if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3745                        *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3746                        return 0;
3747                }
3748        }
3749        return -EAGAIN;
3750}
3751
3752static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3753{
3754        struct rv7xx_power_info *pi = rv770_get_pi(adev);
3755        bool want_thermal_protection;
3756        enum amdgpu_dpm_event_src dpm_event_src;
3757
3758        switch (sources) {
3759        case 0:
3760        default:
3761                want_thermal_protection = false;
3762                break;
3763        case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3764                want_thermal_protection = true;
3765                dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3766                break;
3767        case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3768                want_thermal_protection = true;
3769                dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3770                break;
3771        case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3772              (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3773                want_thermal_protection = true;
3774                dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3775                break;
3776        }
3777
3778        if (want_thermal_protection) {
3779                WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3780                if (pi->thermal_protection)
3781                        WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3782        } else {
3783                WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3784        }
3785}
3786
3787static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3788                                           enum amdgpu_dpm_auto_throttle_src source,
3789                                           bool enable)
3790{
3791        struct rv7xx_power_info *pi = rv770_get_pi(adev);
3792
3793        if (enable) {
3794                if (!(pi->active_auto_throttle_sources & (1 << source))) {
3795                        pi->active_auto_throttle_sources |= 1 << source;
3796                        si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3797                }
3798        } else {
3799                if (pi->active_auto_throttle_sources & (1 << source)) {
3800                        pi->active_auto_throttle_sources &= ~(1 << source);
3801                        si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3802                }
3803        }
3804}
3805
3806static void si_start_dpm(struct amdgpu_device *adev)
3807{
3808        WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3809}
3810
3811static void si_stop_dpm(struct amdgpu_device *adev)
3812{
3813        WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3814}
3815
3816static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3817{
3818        if (enable)
3819                WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3820        else
3821                WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3822
3823}
3824
3825#if 0
3826static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3827                                               u32 thermal_level)
3828{
3829        PPSMC_Result ret;
3830
3831        if (thermal_level == 0) {
3832                ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3833                if (ret == PPSMC_Result_OK)
3834                        return 0;
3835                else
3836                        return -EINVAL;
3837        }
3838        return 0;
3839}
3840
3841static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3842{
3843        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3844}
3845#endif
3846
3847#if 0
3848static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3849{
3850        if (ac_power)
3851                return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3852                        0 : -EINVAL;
3853
3854        return 0;
3855}
3856#endif
3857
3858static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3859                                                      PPSMC_Msg msg, u32 parameter)
3860{
3861        WREG32(SMC_SCRATCH0, parameter);
3862        return amdgpu_si_send_msg_to_smc(adev, msg);
3863}
3864
3865static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3866{
3867        if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3868                return -EINVAL;
3869
3870        return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3871                0 : -EINVAL;
3872}
3873
3874static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3875                                   enum amd_dpm_forced_level level)
3876{
3877        struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3878        struct  si_ps *ps = si_get_ps(rps);
3879        u32 levels = ps->performance_level_count;
3880
3881        if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3882                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3883                        return -EINVAL;
3884
3885                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3886                        return -EINVAL;
3887        } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3888                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3889                        return -EINVAL;
3890
3891                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3892                        return -EINVAL;
3893        } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3894                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3895                        return -EINVAL;
3896
3897                if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3898                        return -EINVAL;
3899        }
3900
3901        adev->pm.dpm.forced_level = level;
3902
3903        return 0;
3904}
3905
3906#if 0
3907static int si_set_boot_state(struct amdgpu_device *adev)
3908{
3909        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3910                0 : -EINVAL;
3911}
3912#endif
3913
3914static int si_set_sw_state(struct amdgpu_device *adev)
3915{
3916        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3917                0 : -EINVAL;
3918}
3919
3920static int si_halt_smc(struct amdgpu_device *adev)
3921{
3922        if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3923                return -EINVAL;
3924
3925        return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3926                0 : -EINVAL;
3927}
3928
3929static int si_resume_smc(struct amdgpu_device *adev)
3930{
3931        if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3932                return -EINVAL;
3933
3934        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3935                0 : -EINVAL;
3936}
3937
3938static void si_dpm_start_smc(struct amdgpu_device *adev)
3939{
3940        amdgpu_si_program_jump_on_start(adev);
3941        amdgpu_si_start_smc(adev);
3942        amdgpu_si_smc_clock(adev, true);
3943}
3944
3945static void si_dpm_stop_smc(struct amdgpu_device *adev)
3946{
3947        amdgpu_si_reset_smc(adev);
3948        amdgpu_si_smc_clock(adev, false);
3949}
3950
3951static int si_process_firmware_header(struct amdgpu_device *adev)
3952{
3953        struct si_power_info *si_pi = si_get_pi(adev);
3954        u32 tmp;
3955        int ret;
3956
3957        ret = amdgpu_si_read_smc_sram_dword(adev,
3958                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3959                                            SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3960                                            &tmp, si_pi->sram_end);
3961        if (ret)
3962                return ret;
3963
3964        si_pi->state_table_start = tmp;
3965
3966        ret = amdgpu_si_read_smc_sram_dword(adev,
3967                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3968                                            SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3969                                            &tmp, si_pi->sram_end);
3970        if (ret)
3971                return ret;
3972
3973        si_pi->soft_regs_start = tmp;
3974
3975        ret = amdgpu_si_read_smc_sram_dword(adev,
3976                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3977                                            SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3978                                            &tmp, si_pi->sram_end);
3979        if (ret)
3980                return ret;
3981
3982        si_pi->mc_reg_table_start = tmp;
3983
3984        ret = amdgpu_si_read_smc_sram_dword(adev,
3985                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3986                                            SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3987                                            &tmp, si_pi->sram_end);
3988        if (ret)
3989                return ret;
3990
3991        si_pi->fan_table_start = tmp;
3992
3993        ret = amdgpu_si_read_smc_sram_dword(adev,
3994                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3995                                            SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3996                                            &tmp, si_pi->sram_end);
3997        if (ret)
3998                return ret;
3999
4000        si_pi->arb_table_start = tmp;

4001
4002        ret = amdgpu_si_read_smc_sram_dword(adev,
4003                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4004                                            SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4005                                            &tmp, si_pi->sram_end);
4006        if (ret)
4007                return ret;
4008
4009        si_pi->cac_table_start = tmp;
4010
4011        ret = amdgpu_si_read_smc_sram_dword(adev,
4012                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4013                                            SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4014                                            &tmp, si_pi->sram_end);
4015        if (ret)
4016                return ret;
4017
4018        si_pi->dte_table_start = tmp;
4019
4020        ret = amdgpu_si_read_smc_sram_dword(adev,
4021                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4022                                            SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4023                                            &tmp, si_pi->sram_end);
4024        if (ret)
4025                return ret;
4026
4027        si_pi->spll_table_start = tmp;
4028
4029        ret = amdgpu_si_read_smc_sram_dword(adev,
4030                                            SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4031                                            SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4032                                            &tmp, si_pi->sram_end);
4033        if (ret)
4034                return ret;
4035
4036        si_pi->papm_cfg_table_start = tmp;
4037
4038        return ret;
4039}
4040
4041static void si_read_clock_registers(struct amdgpu_device *adev)
4042{
4043        struct si_power_info *si_pi = si_get_pi(adev);
4044
4045        si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4046        si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4047        si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4048        si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4049        si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4050        si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4051        si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4052        si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4053        si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4054        si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4055        si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4056        si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4057        si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4058        si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4059        si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4060}
4061
4062static void si_enable_thermal_protection(struct amdgpu_device *adev,
4063                                          bool enable)
4064{
4065        if (enable)
4066                WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4067        else
4068                WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4069}
4070
4071static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4072{
4073        WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4074}
4075
4076#if 0
4077static int si_enter_ulp_state(struct amdgpu_device *adev)
4078{
4079        WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4080
4081        udelay(25000);
4082
4083        return 0;
4084}
4085
4086static int si_exit_ulp_state(struct amdgpu_device *adev)
4087{
4088        int i;
4089
4090        WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4091
4092        udelay(7000);
4093
4094        for (i = 0; i < adev->usec_timeout; i++) {
4095                if (RREG32(SMC_RESP_0) == 1)
4096                        break;
4097                udelay(1000);
4098        }
4099
4100        return 0;
4101}
4102#endif
4103
4104static int si_notify_smc_display_change(struct amdgpu_device *adev,
4105                                     bool has_display)
4106{
4107        PPSMC_Msg msg = has_display ?
4108                PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4109
4110        return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4111                0 : -EINVAL;
4112}
4113
4114static void si_program_response_times(struct amdgpu_device *adev)
4115{
4116        u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4117        u32 vddc_dly, acpi_dly, vbi_dly;
4118        u32 reference_clock;
4119
4120        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4121
4122        voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4123        backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4124
4125        if (voltage_response_time == 0)
4126                voltage_response_time = 1000;
4127
4128        acpi_delay_time = 15000;
4129        vbi_time_out = 100000;
4130
4131        reference_clock = amdgpu_asic_get_xclk(adev);
4132
4133        vddc_dly = (voltage_response_time  * reference_clock) / 100;
4134        acpi_dly = (acpi_delay_time * reference_clock) / 100;
4135        vbi_dly  = (vbi_time_out * reference_clock) / 100;
4136
4137        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4138        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4139        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4140        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4141}
4142
4143static void si_program_ds_registers(struct amdgpu_device *adev)
4144{
4145        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4146        u32 tmp;
4147
4148        /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4149        if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4150                tmp = 0x10;
4151        else
4152                tmp = 0x1;
4153
4154        if (eg_pi->sclk_deep_sleep) {
4155                WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4156                WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4157                         ~AUTOSCALE_ON_SS_CLEAR);
4158        }
4159}
4160
4161static void si_program_display_gap(struct amdgpu_device *adev)
4162{
4163        u32 tmp, pipe;
4164        int i;
4165
4166        tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4167        if (adev->pm.dpm.new_active_crtc_count > 0)
4168                tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4169        else
4170                tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4171
4172        if (adev->pm.dpm.new_active_crtc_count > 1)
4173                tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4174        else
4175                tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4176
4177        WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4178
4179        tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4180        pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4181
4182        if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4183            (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4184                /* find the first active crtc */
4185                for (i = 0; i < adev->mode_info.num_crtc; i++) {
4186                        if (adev->pm.dpm.new_active_crtcs & (1 << i))
4187                                break;
4188                }
4189                if (i == adev->mode_info.num_crtc)
4190                        pipe = 0;
4191                else
4192                        pipe = i;
4193
4194                tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4195                tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4196                WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4197        }
4198
4199        /* Setting this to false forces the performance state to low if the crtcs are disabled.
4200         * This can be a problem on PowerXpress systems or if you want to use the card
4201         * for offscreen rendering or compute if there are no crtcs enabled.
4202         */
4203        si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4204}
4205
4206static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4207{
4208        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4209
4210        if (enable) {
4211                if (pi->sclk_ss)
4212                        WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4213        } else {
4214                WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4215                WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4216        }
4217}
4218
4219static void si_setup_bsp(struct amdgpu_device *adev)
4220{
4221        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4222        u32 xclk = amdgpu_asic_get_xclk(adev);
4223
4224        r600_calculate_u_and_p(pi->asi,
4225                               xclk,
4226                               16,
4227                               &pi->bsp,
4228                               &pi->bsu);
4229
4230        r600_calculate_u_and_p(pi->pasi,
4231                               xclk,
4232                               16,
4233                               &pi->pbsp,
4234                               &pi->pbsu);
4235
4236
4237        pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4238        pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4239
4240        WREG32(CG_BSP, pi->dsp);
4241}
4242
4243static void si_program_git(struct amdgpu_device *adev)
4244{
4245        WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4246}
4247
4248static void si_program_tp(struct amdgpu_device *adev)
4249{
4250        int i;
4251        enum r600_td td = R600_TD_DFLT;
4252
4253        for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4254                WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4255
4256        if (td == R600_TD_AUTO)
4257                WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4258        else
4259                WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4260
4261        if (td == R600_TD_UP)
4262                WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4263
4264        if (td == R600_TD_DOWN)
4265                WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4266}
4267
4268static void si_program_tpp(struct amdgpu_device *adev)
4269{
4270        WREG32(CG_TPC, R600_TPC_DFLT);
4271}
4272
4273static void si_program_sstp(struct amdgpu_device *adev)
4274{
4275        WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4276}
4277
4278static void si_enable_display_gap(struct amdgpu_device *adev)
4279{
4280        u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4281
4282        tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4283        tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4284                DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4285
4286        tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4287        tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4288                DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4289        WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4290}
4291
4292static void si_program_vc(struct amdgpu_device *adev)
4293{
4294        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4295
4296        WREG32(CG_FTV, pi->vrc);
4297}
4298
4299static void si_clear_vc(struct amdgpu_device *adev)
4300{
4301        WREG32(CG_FTV, 0);
4302}
4303
4304static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4305{
4306        u8 mc_para_index;
4307
4308        if (memory_clock < 10000)
4309                mc_para_index = 0;
4310        else if (memory_clock >= 80000)
4311                mc_para_index = 0x0f;
4312        else
4313                mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4314        return mc_para_index;
4315}
4316
4317static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4318{
4319        u8 mc_para_index;
4320
4321        if (strobe_mode) {
4322                if (memory_clock < 12500)
4323                        mc_para_index = 0x00;
4324                else if (memory_clock > 47500)
4325                        mc_para_index = 0x0f;
4326                else
4327                        mc_para_index = (u8)((memory_clock - 10000) / 2500);
4328        } else {
4329                if (memory_clock < 65000)
4330                        mc_para_index = 0x00;
4331                else if (memory_clock > 135000)
4332                        mc_para_index = 0x0f;
4333                else
4334                        mc_para_index = (u8)((memory_clock - 60000) / 5000);
4335        }
4336        return mc_para_index;
4337}
4338
4339static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4340{
4341        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4342        bool strobe_mode = false;
4343        u8 result = 0;
4344
4345        if (mclk <= pi->mclk_strobe_mode_threshold)
4346                strobe_mode = true;
4347
4348        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4349                result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4350        else
4351                result = si_get_ddr3_mclk_frequency_ratio(mclk);
4352
4353        if (strobe_mode)
4354                result |= SISLANDS_SMC_STROBE_ENABLE;
4355
4356        return result;
4357}
4358
4359static int si_upload_firmware(struct amdgpu_device *adev)
4360{
4361        struct si_power_info *si_pi = si_get_pi(adev);
4362
4363        amdgpu_si_reset_smc(adev);
4364        amdgpu_si_smc_clock(adev, false);
4365
4366        return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4367}
4368
4369static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4370                                              const struct atom_voltage_table *table,
4371                                              const struct amdgpu_phase_shedding_limits_table *limits)
4372{
4373        u32 data, num_bits, num_levels;
4374
4375        if ((table == NULL) || (limits == NULL))
4376                return false;
4377
4378        data = table->mask_low;
4379
4380        num_bits = hweight32(data);
4381
4382        if (num_bits == 0)
4383                return false;
4384
4385        num_levels = (1 << num_bits);
4386
4387        if (table->count != num_levels)
4388                return false;
4389
4390        if (limits->count != (num_levels - 1))
4391                return false;
4392
4393        return true;
4394}
4395
4396static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4397                                              u32 max_voltage_steps,
4398                                              struct atom_voltage_table *voltage_table)
4399{
4400        unsigned int i, diff;
4401
4402        if (voltage_table->count <= max_voltage_steps)
4403                return;
4404
4405        diff = voltage_table->count - max_voltage_steps;
4406
4407        for (i= 0; i < max_voltage_steps; i++)
4408                voltage_table->entries[i] = voltage_table->entries[i + diff];
4409
4410        voltage_table->count = max_voltage_steps;
4411}
4412
4413static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4414                                     struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4415                                     struct atom_voltage_table *voltage_table)
4416{
4417        u32 i;
4418
4419        if (voltage_dependency_table == NULL)
4420                return -EINVAL;
4421
4422        voltage_table->mask_low = 0;
4423        voltage_table->phase_delay = 0;
4424
4425        voltage_table->count = voltage_dependency_table->count;
4426        for (i = 0; i < voltage_table->count; i++) {
4427                voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4428                voltage_table->entries[i].smio_low = 0;
4429        }
4430
4431        return 0;
4432}
4433
4434static int si_construct_voltage_tables(struct amdgpu_device *adev)
4435{
4436        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4437        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4438        struct si_power_info *si_pi = si_get_pi(adev);
4439        int ret;
4440
4441        if (pi->voltage_control) {
4442                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4443                                                    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4444                if (ret)
4445                        return ret;
4446
4447                if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4448                        si_trim_voltage_table_to_fit_state_table(adev,
4449                                                                 SISLANDS_MAX_NO_VREG_STEPS,
4450                                                                 &eg_pi->vddc_voltage_table);
4451        } else if (si_pi->voltage_control_svi2) {
4452                ret = si_get_svi2_voltage_table(adev,
4453                                                &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4454                                                &eg_pi->vddc_voltage_table);
4455                if (ret)
4456                        return ret;
4457        } else {
4458                return -EINVAL;
4459        }
4460
4461        if (eg_pi->vddci_control) {
4462                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4463                                                    VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4464                if (ret)
4465                        return ret;
4466
4467                if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4468                        si_trim_voltage_table_to_fit_state_table(adev,
4469                                                                 SISLANDS_MAX_NO_VREG_STEPS,
4470                                                                 &eg_pi->vddci_voltage_table);
4471        }
4472        if (si_pi->vddci_control_svi2) {
4473                ret = si_get_svi2_voltage_table(adev,
4474                                                &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4475                                                &eg_pi->vddci_voltage_table);
4476                if (ret)
4477                        return ret;
4478        }
4479
4480        if (pi->mvdd_control) {
4481                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4482                                                    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4483
4484                if (ret) {
4485                        pi->mvdd_control = false;
4486                        return ret;
4487                }
4488
4489                if (si_pi->mvdd_voltage_table.count == 0) {
4490                        pi->mvdd_control = false;
4491                        return -EINVAL;
4492                }
4493
4494                if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4495                        si_trim_voltage_table_to_fit_state_table(adev,
4496                                                                 SISLANDS_MAX_NO_VREG_STEPS,
4497                                                                 &si_pi->mvdd_voltage_table);
4498        }
4499
4500        if (si_pi->vddc_phase_shed_control) {
4501                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4502                                                    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4503                if (ret)
4504                        si_pi->vddc_phase_shed_control = false;
4505
4506                if ((si_pi->vddc_phase_shed_table.count == 0) ||
4507                    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4508                        si_pi->vddc_phase_shed_control = false;
4509        }
4510
4511        return 0;
4512}
4513
4514static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4515                                          const struct atom_voltage_table *voltage_table,
4516                                          SISLANDS_SMC_STATETABLE *table)
4517{
4518        unsigned int i;
4519
4520        for (i = 0; i < voltage_table->count; i++)
4521                table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4522}
4523
4524static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4525                                          SISLANDS_SMC_STATETABLE *table)
4526{
4527        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4528        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4529        struct si_power_info *si_pi = si_get_pi(adev);
4530        u8 i;
4531
4532        if (si_pi->voltage_control_svi2) {
4533                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4534                        si_pi->svc_gpio_id);
4535                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4536                        si_pi->svd_gpio_id);
4537                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4538                                           2);
4539        } else {
4540                if (eg_pi->vddc_voltage_table.count) {
4541                        si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4542                        table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4543                                cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4544
4545                        for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4546                                if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4547                                        table->maxVDDCIndexInPPTable = i;
4548                                        break;
4549                                }
4550                        }
4551                }
4552
4553                if (eg_pi->vddci_voltage_table.count) {
4554                        si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4555
4556                        table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4557                                cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4558                }
4559
4560
4561                if (si_pi->mvdd_voltage_table.count) {
4562                        si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4563
4564                        table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4565                                cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4566                }
4567
4568                if (si_pi->vddc_phase_shed_control) {
4569                        if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4570                                                              &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4571                                si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4572
4573                                table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4574                                        cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4575
4576                                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4577                                                           (u32)si_pi->vddc_phase_shed_table.phase_delay);
4578                        } else {
4579                                si_pi->vddc_phase_shed_control = false;
4580                        }
4581                }
4582        }
4583
4584        return 0;
4585}
4586
4587static int si_populate_voltage_value(struct amdgpu_device *adev,
4588                                     const struct atom_voltage_table *table,
4589                                     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4590{
4591        unsigned int i;
4592
4593        for (i = 0; i < table->count; i++) {
4594                if (value <= table->entries[i].value) {
4595                        voltage->index = (u8)i;
4596                        voltage->value = cpu_to_be16(table->entries[i].value);
4597                        break;
4598                }
4599        }
4600
4601        if (i >= table->count)
4602                return -EINVAL;
4603
4604        return 0;
4605}
4606
4607static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4608                                  SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4609{
4610        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4611        struct si_power_info *si_pi = si_get_pi(adev);
4612
4613        if (pi->mvdd_control) {
4614                if (mclk <= pi->mvdd_split_frequency)
4615                        voltage->index = 0;
4616                else
4617                        voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4618
4619                voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4620        }
4621        return 0;
4622}
4623
4624static int si_get_std_voltage_value(struct amdgpu_device *adev,
4625                                    SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4626                                    u16 *std_voltage)
4627{
4628        u16 v_index;
4629        bool voltage_found = false;
4630        *std_voltage = be16_to_cpu(voltage->value);
4631
4632        if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4633                if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4634                        if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4635                                return -EINVAL;
4636
4637                        for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4638                                if (be16_to_cpu(voltage->value) ==
4639                                    (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4640                                        voltage_found = true;
4641                                        if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4642                                                *std_voltage =
4643                                                        adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4644                                        else
4645                                                *std_voltage =
4646                                                        adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4647                                        break;
4648                                }
4649                        }
4650
4651                        if (!voltage_found) {
4652                                for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4653                                        if (be16_to_cpu(voltage->value) <=
4654                                            (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4655                                                voltage_found = true;
4656                                                if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4657                                                        *std_voltage =
4658                                                                adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4659                                                else
4660                                                        *std_voltage =
4661                                                                adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4662                                                break;
4663                                        }
4664                                }
4665                        }
4666                } else {
4667                        if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4668                                *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4669                }
4670        }
4671
4672        return 0;
4673}
4674
4675static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4676                                         u16 value, u8 index,
4677                                         SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4678{
4679        voltage->index = index;
4680        voltage->value = cpu_to_be16(value);
4681
4682        return 0;
4683}
4684
4685static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4686                                            const struct amdgpu_phase_shedding_limits_table *limits,
4687                                            u16 voltage, u32 sclk, u32 mclk,
4688                                            SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4689{
4690        unsigned int i;
4691
4692        for (i = 0; i < limits->count; i++) {
4693                if ((voltage <= limits->entries[i].voltage) &&
4694                    (sclk <= limits->entries[i].sclk) &&
4695                    (mclk <= limits->entries[i].mclk))
4696                        break;
4697        }
4698
4699        smc_voltage->phase_settings = (u8)i;
4700
4701        return 0;
4702}
4703
4704static int si_init_arb_table_index(struct amdgpu_device *adev)
4705{
4706        struct si_power_info *si_pi = si_get_pi(adev);
4707        u32 tmp;
4708        int ret;
4709
4710        ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4711                                            &tmp, si_pi->sram_end);
4712        if (ret)
4713                return ret;
4714
4715        tmp &= 0x00FFFFFF;
4716        tmp |= MC_CG_ARB_FREQ_F1 << 24;
4717
4718        return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4719                                              tmp, si_pi->sram_end);
4720}
4721
4722static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4723{
4724        return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4725}
4726
4727static int si_reset_to_default(struct amdgpu_device *adev)
4728{
4729        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4730                0 : -EINVAL;
4731}
4732
4733static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4734{
4735        struct si_power_info *si_pi = si_get_pi(adev);
4736        u32 tmp;
4737        int ret;
4738
4739        ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4740                                            &tmp, si_pi->sram_end);
4741        if (ret)
4742                return ret;
4743
4744        tmp = (tmp >> 24) & 0xff;
4745
4746        if (tmp == MC_CG_ARB_FREQ_F0)
4747                return 0;
4748
4749        return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4750}
4751
4752static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4753                                            u32 engine_clock)
4754{
4755        u32 dram_rows;
4756        u32 dram_refresh_rate;
4757        u32 mc_arb_rfsh_rate;
4758        u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4759
4760        if (tmp >= 4)
4761                dram_rows = 16384;
4762        else
4763                dram_rows = 1 << (tmp + 10);
4764
4765        dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4766        mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4767
4768        return mc_arb_rfsh_rate;
4769}
4770
4771static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4772                                                struct rv7xx_pl *pl,
4773                                                SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4774{
4775        u32 dram_timing;
4776        u32 dram_timing2;
4777        u32 burst_time;
4778
4779        arb_regs->mc_arb_rfsh_rate =
4780                (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4781
4782        amdgpu_atombios_set_engine_dram_timings(adev,
4783                                            pl->sclk,
4784                                            pl->mclk);
4785
4786        dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4787        dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4788        burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4789
4790        arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4791        arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4792        arb_regs->mc_arb_burst_time = (u8)burst_time;
4793
4794        return 0;
4795}
4796
4797static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4798                                                  struct amdgpu_ps *amdgpu_state,
4799                                                  unsigned int first_arb_set)
4800{
4801        struct si_power_info *si_pi = si_get_pi(adev);
4802        struct  si_ps *state = si_get_ps(amdgpu_state);
4803        SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4804        int i, ret = 0;
4805
4806        for (i = 0; i < state->performance_level_count; i++) {
4807                ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4808                if (ret)
4809                        break;
4810                ret = amdgpu_si_copy_bytes_to_smc(adev,
4811                                                  si_pi->arb_table_start +
4812                                                  offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4813                                                  sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4814                                                  (u8 *)&arb_regs,
4815                                                  sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4816                                                  si_pi->sram_end);
4817                if (ret)
4818                        break;
4819        }
4820
4821        return ret;
4822}
4823
4824static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4825                                               struct amdgpu_ps *amdgpu_new_state)
4826{
4827        return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4828                                                      SISLANDS_DRIVER_STATE_ARB_INDEX);
4829}
4830
4831static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4832                                          struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4833{
4834        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4835        struct si_power_info *si_pi = si_get_pi(adev);
4836
4837        if (pi->mvdd_control)
4838                return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4839                                                 si_pi->mvdd_bootup_value, voltage);
4840
4841        return 0;
4842}
4843
4844static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4845                                         struct amdgpu_ps *amdgpu_initial_state,
4846                                         SISLANDS_SMC_STATETABLE *table)
4847{
4848        struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4849        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4850        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4851        struct si_power_info *si_pi = si_get_pi(adev);
4852        u32 reg;
4853        int ret;
4854
4855        table->initialState.levels[0].mclk.vDLL_CNTL =
4856                cpu_to_be32(si_pi->clock_registers.dll_cntl);
4857        table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4858                cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4859        table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4860                cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4861        table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4862                cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4863        table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4864                cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4865        table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4866                cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4867        table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4868                cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4869        table->initialState.levels[0].mclk.vMPLL_SS =
4870                cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4871        table->initialState.levels[0].mclk.vMPLL_SS2 =
4872                cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4873
4874        table->initialState.levels[0].mclk.mclk_value =
4875                cpu_to_be32(initial_state->performance_levels[0].mclk);
4876
4877        table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4878                cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4879        table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4880                cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4881        table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4882                cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4883        table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4884                cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4885        table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4886                cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4887        table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4888                cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4889
4890        table->initialState.levels[0].sclk.sclk_value =
4891                cpu_to_be32(initial_state->performance_levels[0].sclk);
4892
4893        table->initialState.levels[0].arbRefreshState =
4894                SISLANDS_INITIAL_STATE_ARB_INDEX;
4895
4896        table->initialState.levels[0].ACIndex = 0;
4897
4898        ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4899                                        initial_state->performance_levels[0].vddc,
4900                                        &table->initialState.levels[0].vddc);
4901
4902        if (!ret) {
4903                u16 std_vddc;
4904
4905                ret = si_get_std_voltage_value(adev,
4906                                               &table->initialState.levels[0].vddc,
4907                                               &std_vddc);
4908                if (!ret)
4909                        si_populate_std_voltage_value(adev, std_vddc,
4910                                                      table->initialState.levels[0].vddc.index,
4911                                                      &table->initialState.levels[0].std_vddc);
4912        }
4913
4914        if (eg_pi->vddci_control)
4915                si_populate_voltage_value(adev,
4916                                          &eg_pi->vddci_voltage_table,
4917                                          initial_state->performance_levels[0].vddci,
4918                                          &table->initialState.levels[0].vddci);
4919
4920        if (si_pi->vddc_phase_shed_control)
4921                si_populate_phase_shedding_value(adev,
4922                                                 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4923                                                 initial_state->performance_levels[0].vddc,
4924                                                 initial_state->performance_levels[0].sclk,
4925                                                 initial_state->performance_levels[0].mclk,
4926                                                 &table->initialState.levels[0].vddc);
4927
4928        si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4929
4930        reg = CG_R(0xffff) | CG_L(0);
4931        table->initialState.levels[0].aT = cpu_to_be32(reg);
4932        table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4933        table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4934
4935        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4936                table->initialState.levels[0].strobeMode =
4937                        si_get_strobe_mode_settings(adev,
4938                                                    initial_state->performance_levels[0].mclk);
4939
4940                if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4941                        table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4942                else
4943                        table->initialState.levels[0].mcFlags =  0;
4944        }
4945
4946        table->initialState.levelCount = 1;
4947
4948        table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4949
4950        table->initialState.levels[0].dpm2.MaxPS = 0;
4951        table->initialState.levels[0].dpm2.NearTDPDec = 0;
4952        table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4953        table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4954        table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4955
4956        reg = MIN_POWER_MASK | MAX_POWER_MASK;
4957        table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4958
4959        reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4960        table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4961
4962        return 0;
4963}
4964
4965static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4966                                      SISLANDS_SMC_STATETABLE *table)
4967{
4968        struct rv7xx_power_info *pi = rv770_get_pi(adev);
4969        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4970        struct si_power_info *si_pi = si_get_pi(adev);
4971        u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4972        u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4973        u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4974        u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4975        u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4976        u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4977        u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4978        u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4979        u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4980        u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4981        u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4982        u32 reg;
4983        int ret;
4984
4985        table->ACPIState = table->initialState;
4986
4987        table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4988
4989        if (pi->acpi_vddc) {
4990                ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4991                                                pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4992                if (!ret) {
4993                        u16 std_vddc;
4994
4995                        ret = si_get_std_voltage_value(adev,
4996                                                       &table->ACPIState.levels[0].vddc, &std_vddc);
4997                        if (!ret)
4998                                si_populate_std_voltage_value(adev, std_vddc,
4999                                                              table->ACPIState.levels[0].vddc.index,
5000                                                              &table->ACPIState.levels[0].std_vddc);

5001                }
5002                table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5003
5004                if (si_pi->vddc_phase_shed_control) {
5005                        si_populate_phase_shedding_value(adev,
5006                                                         &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5007                                                         pi->acpi_vddc,
5008                                                         0,
5009                                                         0,
5010                                                         &table->ACPIState.levels[0].vddc);
5011                }
5012        } else {
5013                ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5014                                                pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5015                if (!ret) {
5016                        u16 std_vddc;
5017
5018                        ret = si_get_std_voltage_value(adev,
5019                                                       &table->ACPIState.levels[0].vddc, &std_vddc);
5020
5021                        if (!ret)
5022                                si_populate_std_voltage_value(adev, std_vddc,
5023                                                              table->ACPIState.levels[0].vddc.index,
5024                                                              &table->ACPIState.levels[0].std_vddc);
5025                }
5026                table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5027                                                                                    si_pi->sys_pcie_mask,
5028                                                                                    si_pi->boot_pcie_gen,
5029                                                                                    AMDGPU_PCIE_GEN1);
5030
5031                if (si_pi->vddc_phase_shed_control)
5032                        si_populate_phase_shedding_value(adev,
5033                                                         &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5034                                                         pi->min_vddc_in_table,
5035                                                         0,
5036                                                         0,
5037                                                         &table->ACPIState.levels[0].vddc);
5038        }
5039
5040        if (pi->acpi_vddc) {
5041                if (eg_pi->acpi_vddci)
5042                        si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5043                                                  eg_pi->acpi_vddci,
5044                                                  &table->ACPIState.levels[0].vddci);
5045        }
5046
5047        mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5048        mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5049
5050        dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5051
5052        spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5053        spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5054
5055        table->ACPIState.levels[0].mclk.vDLL_CNTL =
5056                cpu_to_be32(dll_cntl);
5057        table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5058                cpu_to_be32(mclk_pwrmgt_cntl);
5059        table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5060                cpu_to_be32(mpll_ad_func_cntl);
5061        table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5062                cpu_to_be32(mpll_dq_func_cntl);
5063        table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5064                cpu_to_be32(mpll_func_cntl);
5065        table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5066                cpu_to_be32(mpll_func_cntl_1);
5067        table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5068                cpu_to_be32(mpll_func_cntl_2);
5069        table->ACPIState.levels[0].mclk.vMPLL_SS =
5070                cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5071        table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5072                cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5073
5074        table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5075                cpu_to_be32(spll_func_cntl);
5076        table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5077                cpu_to_be32(spll_func_cntl_2);
5078        table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5079                cpu_to_be32(spll_func_cntl_3);
5080        table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5081                cpu_to_be32(spll_func_cntl_4);
5082
5083        table->ACPIState.levels[0].mclk.mclk_value = 0;
5084        table->ACPIState.levels[0].sclk.sclk_value = 0;
5085
5086        si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5087
5088        if (eg_pi->dynamic_ac_timing)
5089                table->ACPIState.levels[0].ACIndex = 0;
5090
5091        table->ACPIState.levels[0].dpm2.MaxPS = 0;
5092        table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5093        table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5094        table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5095        table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5096
5097        reg = MIN_POWER_MASK | MAX_POWER_MASK;
5098        table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5099
5100        reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5101        table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5102
5103        return 0;
5104}
5105
5106static int si_populate_ulv_state(struct amdgpu_device *adev,
5107                                 SISLANDS_SMC_SWSTATE *state)
5108{
5109        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5110        struct si_power_info *si_pi = si_get_pi(adev);
5111        struct si_ulv_param *ulv = &si_pi->ulv;
5112        u32 sclk_in_sr = 1350; /* ??? */
5113        int ret;
5114
5115        ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5116                                            &state->levels[0]);
5117        if (!ret) {
5118                if (eg_pi->sclk_deep_sleep) {
5119                        if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5120                                state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5121                        else
5122                                state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5123                }
5124                if (ulv->one_pcie_lane_in_ulv)
5125                        state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5126                state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5127                state->levels[0].ACIndex = 1;
5128                state->levels[0].std_vddc = state->levels[0].vddc;
5129                state->levelCount = 1;
5130
5131                state->flags |= PPSMC_SWSTATE_FLAG_DC;
5132        }
5133
5134        return ret;
5135}
5136
5137static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5138{
5139        struct si_power_info *si_pi = si_get_pi(adev);
5140        struct si_ulv_param *ulv = &si_pi->ulv;
5141        SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5142        int ret;
5143
5144        ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5145                                                   &arb_regs);
5146        if (ret)
5147                return ret;
5148
5149        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5150                                   ulv->volt_change_delay);
5151
5152        ret = amdgpu_si_copy_bytes_to_smc(adev,
5153                                          si_pi->arb_table_start +
5154                                          offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5155                                          sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5156                                          (u8 *)&arb_regs,
5157                                          sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5158                                          si_pi->sram_end);
5159
5160        return ret;
5161}
5162
5163static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5164{
5165        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5166
5167        pi->mvdd_split_frequency = 30000;
5168}
5169
5170static int si_init_smc_table(struct amdgpu_device *adev)
5171{
5172        struct si_power_info *si_pi = si_get_pi(adev);
5173        struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5174        const struct si_ulv_param *ulv = &si_pi->ulv;
5175        SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5176        int ret;
5177        u32 lane_width;
5178        u32 vr_hot_gpio;
5179
5180        si_populate_smc_voltage_tables(adev, table);
5181
5182        switch (adev->pm.int_thermal_type) {
5183        case THERMAL_TYPE_SI:
5184        case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5185                table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5186                break;
5187        case THERMAL_TYPE_NONE:
5188                table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5189                break;
5190        default:
5191                table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5192                break;
5193        }
5194
5195        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5196                table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5197
5198        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5199                if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5200                        table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5201        }
5202
5203        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5204                table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5205
5206        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5207                table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5208
5209        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5210                table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5211
5212        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5213                table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5214                vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5215                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5216                                           vr_hot_gpio);
5217        }
5218
5219        ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5220        if (ret)
5221                return ret;
5222
5223        ret = si_populate_smc_acpi_state(adev, table);
5224        if (ret)
5225                return ret;
5226
5227        table->driverState = table->initialState;
5228
5229        ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5230                                                     SISLANDS_INITIAL_STATE_ARB_INDEX);
5231        if (ret)
5232                return ret;
5233
5234        if (ulv->supported && ulv->pl.vddc) {
5235                ret = si_populate_ulv_state(adev, &table->ULVState);
5236                if (ret)
5237                        return ret;
5238
5239                ret = si_program_ulv_memory_timing_parameters(adev);
5240                if (ret)
5241                        return ret;
5242
5243                WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5244                WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5245
5246                lane_width = amdgpu_get_pcie_lanes(adev);
5247                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5248        } else {
5249                table->ULVState = table->initialState;
5250        }
5251
5252        return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5253                                           (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5254                                           si_pi->sram_end);
5255}
5256
5257static int si_calculate_sclk_params(struct amdgpu_device *adev,
5258                                    u32 engine_clock,
5259                                    SISLANDS_SMC_SCLK_VALUE *sclk)
5260{
5261        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5262        struct si_power_info *si_pi = si_get_pi(adev);
5263        struct atom_clock_dividers dividers;
5264        u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5265        u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5266        u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5267        u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5268        u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5269        u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5270        u64 tmp;
5271        u32 reference_clock = adev->clock.spll.reference_freq;
5272        u32 reference_divider;
5273        u32 fbdiv;
5274        int ret;
5275
5276        ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5277                                             engine_clock, false, &dividers);
5278        if (ret)
5279                return ret;
5280
5281        reference_divider = 1 + dividers.ref_div;
5282
5283        tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5284        do_div(tmp, reference_clock);
5285        fbdiv = (u32) tmp;
5286
5287        spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5288        spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5289        spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5290
5291        spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5292        spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5293
5294        spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5295        spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5296        spll_func_cntl_3 |= SPLL_DITHEN;
5297
5298        if (pi->sclk_ss) {
5299                struct amdgpu_atom_ss ss;
5300                u32 vco_freq = engine_clock * dividers.post_div;
5301
5302                if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5303                                                     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5304                        u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5305                        u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5306
5307                        cg_spll_spread_spectrum &= ~CLK_S_MASK;
5308                        cg_spll_spread_spectrum |= CLK_S(clk_s);
5309                        cg_spll_spread_spectrum |= SSEN;
5310
5311                        cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5312                        cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5313                }
5314        }
5315
5316        sclk->sclk_value = engine_clock;
5317        sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5318        sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5319        sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5320        sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5321        sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5322        sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5323
5324        return 0;
5325}
5326
5327static int si_populate_sclk_value(struct amdgpu_device *adev,
5328                                  u32 engine_clock,
5329                                  SISLANDS_SMC_SCLK_VALUE *sclk)
5330{
5331        SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5332        int ret;
5333
5334        ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5335        if (!ret) {
5336                sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5337                sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5338                sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5339                sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5340                sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5341                sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5342                sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5343        }
5344
5345        return ret;
5346}
5347
5348static int si_populate_mclk_value(struct amdgpu_device *adev,
5349                                  u32 engine_clock,
5350                                  u32 memory_clock,
5351                                  SISLANDS_SMC_MCLK_VALUE *mclk,
5352                                  bool strobe_mode,
5353                                  bool dll_state_on)
5354{
5355        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5356        struct si_power_info *si_pi = si_get_pi(adev);
5357        u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5358        u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5359        u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5360        u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5361        u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5362        u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5363        u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5364        u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5365        u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5366        struct atom_mpll_param mpll_param;
5367        int ret;
5368
5369        ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5370        if (ret)
5371                return ret;
5372
5373        mpll_func_cntl &= ~BWCTRL_MASK;
5374        mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5375
5376        mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5377        mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5378                CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5379
5380        mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5381        mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5382
5383        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5384                mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5385                mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5386                        YCLK_POST_DIV(mpll_param.post_div);
5387        }
5388
5389        if (pi->mclk_ss) {
5390                struct amdgpu_atom_ss ss;
5391                u32 freq_nom;
5392                u32 tmp;
5393                u32 reference_clock = adev->clock.mpll.reference_freq;
5394
5395                if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5396                        freq_nom = memory_clock * 4;
5397                else
5398                        freq_nom = memory_clock * 2;
5399
5400                tmp = freq_nom / reference_clock;
5401                tmp = tmp * tmp;
5402                if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5403                                                     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5404                        u32 clks = reference_clock * 5 / ss.rate;
5405                        u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5406
5407                        mpll_ss1 &= ~CLKV_MASK;
5408                        mpll_ss1 |= CLKV(clkv);
5409
5410                        mpll_ss2 &= ~CLKS_MASK;
5411                        mpll_ss2 |= CLKS(clks);
5412                }
5413        }
5414
5415        mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5416        mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5417
5418        if (dll_state_on)
5419                mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5420        else
5421                mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5422
5423        mclk->mclk_value = cpu_to_be32(memory_clock);
5424        mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5425        mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5426        mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5427        mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5428        mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5429        mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5430        mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5431        mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5432        mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5433
5434        return 0;
5435}
5436
5437static void si_populate_smc_sp(struct amdgpu_device *adev,
5438                               struct amdgpu_ps *amdgpu_state,
5439                               SISLANDS_SMC_SWSTATE *smc_state)
5440{
5441        struct  si_ps *ps = si_get_ps(amdgpu_state);
5442        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5443        int i;
5444
5445        for (i = 0; i < ps->performance_level_count - 1; i++)
5446                smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5447
5448        smc_state->levels[ps->performance_level_count - 1].bSP =
5449                cpu_to_be32(pi->psp);
5450}
5451
5452static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5453                                         struct rv7xx_pl *pl,
5454                                         SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5455{
5456        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5457        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5458        struct si_power_info *si_pi = si_get_pi(adev);
5459        int ret;
5460        bool dll_state_on;
5461        u16 std_vddc;
5462        bool gmc_pg = false;
5463
5464        if (eg_pi->pcie_performance_request &&
5465            (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5466                level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5467        else
5468                level->gen2PCIE = (u8)pl->pcie_gen;
5469
5470        ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5471        if (ret)
5472                return ret;
5473
5474        level->mcFlags =  0;
5475
5476        if (pi->mclk_stutter_mode_threshold &&
5477            (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5478            !eg_pi->uvd_enabled &&
5479            (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5480            (adev->pm.dpm.new_active_crtc_count <= 2)) {
5481                level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5482
5483                if (gmc_pg)
5484                        level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5485        }
5486
5487        if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5488                if (pl->mclk > pi->mclk_edc_enable_threshold)
5489                        level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5490
5491                if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5492                        level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5493
5494                level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5495
5496                if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5497                        if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5498                            ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5499                                dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5500                        else
5501                                dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5502                } else {
5503                        dll_state_on = false;
5504                }
5505        } else {
5506                level->strobeMode = si_get_strobe_mode_settings(adev,
5507                                                                pl->mclk);
5508
5509                dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5510        }
5511
5512        ret = si_populate_mclk_value(adev,
5513                                     pl->sclk,
5514                                     pl->mclk,
5515                                     &level->mclk,
5516                                     (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5517        if (ret)
5518                return ret;
5519
5520        ret = si_populate_voltage_value(adev,
5521                                        &eg_pi->vddc_voltage_table,
5522                                        pl->vddc, &level->vddc);
5523        if (ret)
5524                return ret;
5525
5526
5527        ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5528        if (ret)
5529                return ret;
5530
5531        ret = si_populate_std_voltage_value(adev, std_vddc,
5532                                            level->vddc.index, &level->std_vddc);
5533        if (ret)
5534                return ret;
5535
5536        if (eg_pi->vddci_control) {
5537                ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5538                                                pl->vddci, &level->vddci);
5539                if (ret)
5540                        return ret;
5541        }
5542
5543        if (si_pi->vddc_phase_shed_control) {
5544                ret = si_populate_phase_shedding_value(adev,
5545                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5546                                                       pl->vddc,
5547                                                       pl->sclk,
5548                                                       pl->mclk,
5549                                                       &level->vddc);
5550                if (ret)
5551                        return ret;
5552        }
5553
5554        level->MaxPoweredUpCU = si_pi->max_cu;
5555
5556        ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5557
5558        return ret;
5559}
5560
5561static int si_populate_smc_t(struct amdgpu_device *adev,
5562                             struct amdgpu_ps *amdgpu_state,
5563                             SISLANDS_SMC_SWSTATE *smc_state)
5564{
5565        struct rv7xx_power_info *pi = rv770_get_pi(adev);
5566        struct  si_ps *state = si_get_ps(amdgpu_state);
5567        u32 a_t;
5568        u32 t_l, t_h;
5569        u32 high_bsp;
5570        int i, ret;
5571
5572        if (state->performance_level_count >= 9)
5573                return -EINVAL;
5574
5575        if (state->performance_level_count < 2) {
5576                a_t = CG_R(0xffff) | CG_L(0);
5577                smc_state->levels[0].aT = cpu_to_be32(a_t);
5578                return 0;
5579        }
5580
5581        smc_state->levels[0].aT = cpu_to_be32(0);
5582
5583        for (i = 0; i <= state->performance_level_count - 2; i++) {
5584                ret = r600_calculate_at(
5585                        (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5586                        100 * R600_AH_DFLT,
5587                        state->performance_levels[i + 1].sclk,
5588                        state->performance_levels[i].sclk,
5589                        &t_l,
5590                        &t_h);
5591
5592                if (ret) {
5593                        t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5594                        t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5595                }
5596
5597                a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5598                a_t |= CG_R(t_l * pi->bsp / 20000);
5599                smc_state->levels[i].aT = cpu_to_be32(a_t);
5600
5601                high_bsp = (i == state->performance_level_count - 2) ?
5602                        pi->pbsp : pi->bsp;
5603                a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5604                smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5605        }
5606
5607        return 0;
5608}
5609
5610static int si_disable_ulv(struct amdgpu_device *adev)
5611{
5612        struct si_power_info *si_pi = si_get_pi(adev);
5613        struct si_ulv_param *ulv = &si_pi->ulv;
5614
5615        if (ulv->supported)
5616                return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5617                        0 : -EINVAL;
5618
5619        return 0;
5620}
5621
5622static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5623                                       struct amdgpu_ps *amdgpu_state)
5624{
5625        const struct si_power_info *si_pi = si_get_pi(adev);
5626        const struct si_ulv_param *ulv = &si_pi->ulv;
5627        const struct  si_ps *state = si_get_ps(amdgpu_state);
5628        int i;
5629
5630        if (state->performance_levels[0].mclk != ulv->pl.mclk)
5631                return false;
5632
5633        /* XXX validate against display requirements! */
5634
5635        for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5636                if (adev->clock.current_dispclk <=
5637                    adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5638                        if (ulv->pl.vddc <
5639                            adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5640                                return false;
5641                }
5642        }
5643
5644        if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5645                return false;
5646
5647        return true;
5648}
5649
5650static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5651                                                       struct amdgpu_ps *amdgpu_new_state)
5652{
5653        const struct si_power_info *si_pi = si_get_pi(adev);
5654        const struct si_ulv_param *ulv = &si_pi->ulv;
5655
5656        if (ulv->supported) {
5657                if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5658                        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5659                                0 : -EINVAL;
5660        }
5661        return 0;
5662}
5663
5664static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5665                                         struct amdgpu_ps *amdgpu_state,
5666                                         SISLANDS_SMC_SWSTATE *smc_state)
5667{
5668        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5669        struct ni_power_info *ni_pi = ni_get_pi(adev);
5670        struct si_power_info *si_pi = si_get_pi(adev);
5671        struct  si_ps *state = si_get_ps(amdgpu_state);
5672        int i, ret;
5673        u32 threshold;
5674        u32 sclk_in_sr = 1350; /* ??? */
5675
5676        if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5677                return -EINVAL;
5678
5679        threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5680
5681        if (amdgpu_state->vclk && amdgpu_state->dclk) {
5682                eg_pi->uvd_enabled = true;
5683                if (eg_pi->smu_uvd_hs)
5684                        smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5685        } else {
5686                eg_pi->uvd_enabled = false;
5687        }
5688
5689        if (state->dc_compatible)
5690                smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5691
5692        smc_state->levelCount = 0;
5693        for (i = 0; i < state->performance_level_count; i++) {
5694                if (eg_pi->sclk_deep_sleep) {
5695                        if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5696                                if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5697                                        smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5698                                else
5699                                        smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5700                        }
5701                }
5702
5703                ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5704                                                    &smc_state->levels[i]);
5705                smc_state->levels[i].arbRefreshState =
5706                        (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5707
5708                if (ret)
5709                        return ret;
5710
5711                if (ni_pi->enable_power_containment)
5712                        smc_state->levels[i].displayWatermark =
5713                                (state->performance_levels[i].sclk < threshold) ?
5714                                PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5715                else
5716                        smc_state->levels[i].displayWatermark = (i < 2) ?
5717                                PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5718
5719                if (eg_pi->dynamic_ac_timing)
5720                        smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5721                else
5722                        smc_state->levels[i].ACIndex = 0;
5723
5724                smc_state->levelCount++;
5725        }
5726
5727        si_write_smc_soft_register(adev,
5728                                   SI_SMC_SOFT_REGISTER_watermark_threshold,
5729                                   threshold / 512);
5730
5731        si_populate_smc_sp(adev, amdgpu_state, smc_state);
5732
5733        ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5734        if (ret)
5735                ni_pi->enable_power_containment = false;
5736
5737        ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5738        if (ret)
5739                ni_pi->enable_sq_ramping = false;
5740
5741        return si_populate_smc_t(adev, amdgpu_state, smc_state);
5742}
5743
5744static int si_upload_sw_state(struct amdgpu_device *adev,
5745                              struct amdgpu_ps *amdgpu_new_state)
5746{
5747        struct si_power_info *si_pi = si_get_pi(adev);
5748        struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5749        int ret;
5750        u32 address = si_pi->state_table_start +
5751                offsetof(SISLANDS_SMC_STATETABLE, driverState);
5752        u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5753                ((new_state->performance_level_count - 1) *
5754                 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5755        SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5756
5757        memset(smc_state, 0, state_size);
5758
5759        ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5760        if (ret)
5761                return ret;
5762
5763        return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5764                                           state_size, si_pi->sram_end);
5765}
5766
5767static int si_upload_ulv_state(struct amdgpu_device *adev)
5768{
5769        struct si_power_info *si_pi = si_get_pi(adev);
5770        struct si_ulv_param *ulv = &si_pi->ulv;
5771        int ret = 0;
5772
5773        if (ulv->supported && ulv->pl.vddc) {
5774                u32 address = si_pi->state_table_start +
5775                        offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5776                SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5777                u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5778
5779                memset(smc_state, 0, state_size);
5780
5781                ret = si_populate_ulv_state(adev, smc_state);
5782                if (!ret)
5783                        ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5784                                                          state_size, si_pi->sram_end);
5785        }
5786
5787        return ret;
5788}
5789
5790static int si_upload_smc_data(struct amdgpu_device *adev)
5791{
5792        struct amdgpu_crtc *amdgpu_crtc = NULL;
5793        int i;
5794
5795        if (adev->pm.dpm.new_active_crtc_count == 0)
5796                return 0;
5797
5798        for (i = 0; i < adev->mode_info.num_crtc; i++) {
5799                if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5800                        amdgpu_crtc = adev->mode_info.crtcs[i];
5801                        break;
5802                }
5803        }
5804
5805        if (amdgpu_crtc == NULL)
5806                return 0;
5807
5808        if (amdgpu_crtc->line_time <= 0)
5809                return 0;
5810
5811        if (si_write_smc_soft_register(adev,
5812                                       SI_SMC_SOFT_REGISTER_crtc_index,
5813                                       amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5814                return 0;
5815
5816        if (si_write_smc_soft_register(adev,
5817                                       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5818                                       amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5819                return 0;
5820
5821        if (si_write_smc_soft_register(adev,
5822                                       SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5823                                       amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5824                return 0;
5825
5826        return 0;
5827}
5828
5829static int si_set_mc_special_registers(struct amdgpu_device *adev,
5830                                       struct si_mc_reg_table *table)
5831{
5832        u8 i, j, k;
5833        u32 temp_reg;
5834
5835        for (i = 0, j = table->last; i < table->last; i++) {
5836                if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5837                        return -EINVAL;
5838                switch (table->mc_reg_address[i].s1) {
5839                case MC_SEQ_MISC1:
5840                        temp_reg = RREG32(MC_PMG_CMD_EMRS);
5841                        table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5842                        table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5843                        for (k = 0; k < table->num_entries; k++)
5844                                table->mc_reg_table_entry[k].mc_data[j] =
5845                                        ((temp_reg & 0xffff0000)) |
5846                                        ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5847                        j++;
5848                        if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5849                                return -EINVAL;
5850
5851                        temp_reg = RREG32(MC_PMG_CMD_MRS);
5852                        table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5853                        table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5854                        for (k = 0; k < table->num_entries; k++) {
5855                                table->mc_reg_table_entry[k].mc_data[j] =
5856                                        (temp_reg & 0xffff0000) |
5857                                        (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5858                                if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5859                                        table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5860                        }
5861                        j++;
5862                        if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5863                                return -EINVAL;
5864
5865                        if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5866                                table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5867                                table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5868                                for (k = 0; k < table->num_entries; k++)
5869                                        table->mc_reg_table_entry[k].mc_data[j] =
5870                                                (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5871                                j++;
5872                                if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5873                                        return -EINVAL;
5874                        }
5875                        break;
5876                case MC_SEQ_RESERVE_M:
5877                        temp_reg = RREG32(MC_PMG_CMD_MRS1);
5878                        table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5879                        table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5880                        for(k = 0; k < table->num_entries; k++)
5881                                table->mc_reg_table_entry[k].mc_data[j] =
5882                                        (temp_reg & 0xffff0000) |
5883                                        (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5884                        j++;
5885                        if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5886                                return -EINVAL;
5887                        break;
5888                default:
5889                        break;
5890                }
5891        }
5892
5893        table->last = j;
5894
5895        return 0;
5896}
5897
5898static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5899{
5900        bool result = true;
5901        switch (in_reg) {
5902        case  MC_SEQ_RAS_TIMING:
5903                *out_reg = MC_SEQ_RAS_TIMING_LP;
5904                break;
5905        case MC_SEQ_CAS_TIMING:
5906                *out_reg = MC_SEQ_CAS_TIMING_LP;
5907                break;
5908        case MC_SEQ_MISC_TIMING:
5909                *out_reg = MC_SEQ_MISC_TIMING_LP;
5910                break;
5911        case MC_SEQ_MISC_TIMING2:
5912                *out_reg = MC_SEQ_MISC_TIMING2_LP;
5913                break;
5914        case MC_SEQ_RD_CTL_D0:
5915                *out_reg = MC_SEQ_RD_CTL_D0_LP;
5916                break;
5917        case MC_SEQ_RD_CTL_D1:
5918                *out_reg = MC_SEQ_RD_CTL_D1_LP;
5919                break;
5920        case MC_SEQ_WR_CTL_D0:
5921                *out_reg = MC_SEQ_WR_CTL_D0_LP;
5922                break;
5923        case MC_SEQ_WR_CTL_D1:
5924                *out_reg = MC_SEQ_WR_CTL_D1_LP;
5925                break;
5926        case MC_PMG_CMD_EMRS:
5927                *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5928                break;
5929        case MC_PMG_CMD_MRS:
5930                *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5931                break;
5932        case MC_PMG_CMD_MRS1:
5933                *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5934                break;
5935        case MC_SEQ_PMG_TIMING:
5936                *out_reg = MC_SEQ_PMG_TIMING_LP;
5937                break;
5938        case MC_PMG_CMD_MRS2:
5939                *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5940                break;
5941        case MC_SEQ_WR_CTL_2:
5942                *out_reg = MC_SEQ_WR_CTL_2_LP;
5943                break;
5944        default:
5945                result = false;
5946                break;
5947        }
5948
5949        return result;
5950}
5951
5952static void si_set_valid_flag(struct si_mc_reg_table *table)
5953{
5954        u8 i, j;
5955
5956        for (i = 0; i < table->last; i++) {
5957                for (j = 1; j < table->num_entries; j++) {
5958                        if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5959                                table->valid_flag |= 1 << i;
5960                                break;
5961                        }
5962                }
5963        }
5964}
5965
5966static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5967{
5968        u32 i;
5969        u16 address;
5970
5971        for (i = 0; i < table->last; i++)
5972                table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5973                        address : table->mc_reg_address[i].s1;
5974
5975}
5976
5977static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5978                                      struct si_mc_reg_table *si_table)
5979{
5980        u8 i, j;
5981
5982        if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5983                return -EINVAL;
5984        if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5985                return -EINVAL;
5986
5987        for (i = 0; i < table->last; i++)
5988                si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5989        si_table->last = table->last;
5990
5991        for (i = 0; i < table->num_entries; i++) {
5992                si_table->mc_reg_table_entry[i].mclk_max =
5993                        table->mc_reg_table_entry[i].mclk_max;
5994                for (j = 0; j < table->last; j++) {
5995                        si_table->mc_reg_table_entry[i].mc_data[j] =
5996                                table->mc_reg_table_entry[i].mc_data[j];
5997                }
5998        }
5999        si_table->num_entries = table->num_entries;
6000

6001        return 0;
6002}
6003
6004static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6005{
6006        struct si_power_info *si_pi = si_get_pi(adev);
6007        struct atom_mc_reg_table *table;
6008        struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6009        u8 module_index = rv770_get_memory_module_index(adev);
6010        int ret;
6011
6012        table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6013        if (!table)
6014                return -ENOMEM;
6015
6016        WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6017        WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6018        WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6019        WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6020        WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6021        WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6022        WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6023        WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6024        WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6025        WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6026        WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6027        WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6028        WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6029        WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6030
6031        ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6032        if (ret)
6033                goto init_mc_done;
6034
6035        ret = si_copy_vbios_mc_reg_table(table, si_table);
6036        if (ret)
6037                goto init_mc_done;
6038
6039        si_set_s0_mc_reg_index(si_table);
6040
6041        ret = si_set_mc_special_registers(adev, si_table);
6042        if (ret)
6043                goto init_mc_done;
6044
6045        si_set_valid_flag(si_table);
6046
6047init_mc_done:
6048        kfree(table);
6049
6050        return ret;
6051
6052}
6053
6054static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6055                                         SMC_SIslands_MCRegisters *mc_reg_table)
6056{
6057        struct si_power_info *si_pi = si_get_pi(adev);
6058        u32 i, j;
6059
6060        for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6061                if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6062                        if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6063                                break;
6064                        mc_reg_table->address[i].s0 =
6065                                cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6066                        mc_reg_table->address[i].s1 =
6067                                cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6068                        i++;
6069                }
6070        }
6071        mc_reg_table->last = (u8)i;
6072}
6073
6074static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6075                                    SMC_SIslands_MCRegisterSet *data,
6076                                    u32 num_entries, u32 valid_flag)
6077{
6078        u32 i, j;
6079
6080        for(i = 0, j = 0; j < num_entries; j++) {
6081                if (valid_flag & (1 << j)) {
6082                        data->value[i] = cpu_to_be32(entry->mc_data[j]);
6083                        i++;
6084                }
6085        }
6086}
6087
6088static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6089                                                 struct rv7xx_pl *pl,
6090                                                 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6091{
6092        struct si_power_info *si_pi = si_get_pi(adev);
6093        u32 i = 0;
6094
6095        for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6096                if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6097                        break;
6098        }
6099
6100        if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6101                --i;
6102
6103        si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6104                                mc_reg_table_data, si_pi->mc_reg_table.last,
6105                                si_pi->mc_reg_table.valid_flag);
6106}
6107
6108static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6109                                           struct amdgpu_ps *amdgpu_state,
6110                                           SMC_SIslands_MCRegisters *mc_reg_table)
6111{
6112        struct si_ps *state = si_get_ps(amdgpu_state);
6113        int i;
6114
6115        for (i = 0; i < state->performance_level_count; i++) {
6116                si_convert_mc_reg_table_entry_to_smc(adev,
6117                                                     &state->performance_levels[i],
6118                                                     &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6119        }
6120}
6121
6122static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6123                                    struct amdgpu_ps *amdgpu_boot_state)
6124{
6125        struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6126        struct si_power_info *si_pi = si_get_pi(adev);
6127        struct si_ulv_param *ulv = &si_pi->ulv;
6128        SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6129
6130        memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6131
6132        si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6133
6134        si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6135
6136        si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6137                                             &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6138
6139        si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6140                                &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6141                                si_pi->mc_reg_table.last,
6142                                si_pi->mc_reg_table.valid_flag);
6143
6144        if (ulv->supported && ulv->pl.vddc != 0)
6145                si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6146                                                     &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6147        else
6148                si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6149                                        &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6150                                        si_pi->mc_reg_table.last,
6151                                        si_pi->mc_reg_table.valid_flag);
6152
6153        si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6154
6155        return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6156                                           (u8 *)smc_mc_reg_table,
6157                                           sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6158}
6159
6160static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6161                                  struct amdgpu_ps *amdgpu_new_state)
6162{
6163        struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6164        struct si_power_info *si_pi = si_get_pi(adev);
6165        u32 address = si_pi->mc_reg_table_start +
6166                offsetof(SMC_SIslands_MCRegisters,
6167                         data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6168        SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6169
6170        memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6171
6172        si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6173
6174        return amdgpu_si_copy_bytes_to_smc(adev, address,
6175                                           (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6176                                           sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6177                                           si_pi->sram_end);
6178}
6179
6180static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6181{
6182        if (enable)
6183                WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6184        else
6185                WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6186}
6187
6188static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6189                                                      struct amdgpu_ps *amdgpu_state)
6190{
6191        struct si_ps *state = si_get_ps(amdgpu_state);
6192        int i;
6193        u16 pcie_speed, max_speed = 0;
6194
6195        for (i = 0; i < state->performance_level_count; i++) {
6196                pcie_speed = state->performance_levels[i].pcie_gen;
6197                if (max_speed < pcie_speed)
6198                        max_speed = pcie_speed;
6199        }
6200        return max_speed;
6201}
6202
6203static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6204{
6205        u32 speed_cntl;
6206
6207        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6208        speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6209
6210        return (u16)speed_cntl;
6211}
6212
6213static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6214                                                             struct amdgpu_ps *amdgpu_new_state,
6215                                                             struct amdgpu_ps *amdgpu_current_state)
6216{
6217        struct si_power_info *si_pi = si_get_pi(adev);
6218        enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6219        enum amdgpu_pcie_gen current_link_speed;
6220
6221        if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6222                current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6223        else
6224                current_link_speed = si_pi->force_pcie_gen;
6225
6226        si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6227        si_pi->pspp_notify_required = false;
6228        if (target_link_speed > current_link_speed) {
6229                switch (target_link_speed) {
6230#if defined(CONFIG_ACPI)
6231                case AMDGPU_PCIE_GEN3:
6232                        if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6233                                break;
6234                        si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6235                        if (current_link_speed == AMDGPU_PCIE_GEN2)
6236                                break;
6237                case AMDGPU_PCIE_GEN2:
6238                        if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6239                                break;
6240#endif
6241                default:
6242                        si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6243                        break;
6244                }
6245        } else {
6246                if (target_link_speed < current_link_speed)
6247                        si_pi->pspp_notify_required = true;
6248        }
6249}
6250
6251static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6252                                                           struct amdgpu_ps *amdgpu_new_state,
6253                                                           struct amdgpu_ps *amdgpu_current_state)
6254{
6255        struct si_power_info *si_pi = si_get_pi(adev);
6256        enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6257        u8 request;
6258
6259        if (si_pi->pspp_notify_required) {
6260                if (target_link_speed == AMDGPU_PCIE_GEN3)
6261                        request = PCIE_PERF_REQ_PECI_GEN3;
6262                else if (target_link_speed == AMDGPU_PCIE_GEN2)
6263                        request = PCIE_PERF_REQ_PECI_GEN2;
6264                else
6265                        request = PCIE_PERF_REQ_PECI_GEN1;
6266
6267                if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6268                    (si_get_current_pcie_speed(adev) > 0))
6269                        return;
6270
6271#if defined(CONFIG_ACPI)
6272                amdgpu_acpi_pcie_performance_request(adev, request, false);
6273#endif
6274        }
6275}
6276
6277#if 0
6278static int si_ds_request(struct amdgpu_device *adev,
6279                         bool ds_status_on, u32 count_write)
6280{
6281        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6282
6283        if (eg_pi->sclk_deep_sleep) {
6284                if (ds_status_on)
6285                        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6286                                PPSMC_Result_OK) ?
6287                                0 : -EINVAL;
6288                else
6289                        return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6290                                PPSMC_Result_OK) ? 0 : -EINVAL;
6291        }
6292        return 0;
6293}
6294#endif
6295
6296static void si_set_max_cu_value(struct amdgpu_device *adev)
6297{
6298        struct si_power_info *si_pi = si_get_pi(adev);
6299
6300        if (adev->asic_type == CHIP_VERDE) {
6301                switch (adev->pdev->device) {
6302                case 0x6820:
6303                case 0x6825:
6304                case 0x6821:
6305                case 0x6823:
6306                case 0x6827:
6307                        si_pi->max_cu = 10;
6308                        break;
6309                case 0x682D:
6310                case 0x6824:
6311                case 0x682F:
6312                case 0x6826:
6313                        si_pi->max_cu = 8;
6314                        break;
6315                case 0x6828:
6316                case 0x6830:
6317                case 0x6831:
6318                case 0x6838:
6319                case 0x6839:
6320                case 0x683D:
6321                        si_pi->max_cu = 10;
6322                        break;
6323                case 0x683B:
6324                case 0x683F:
6325                case 0x6829:
6326                        si_pi->max_cu = 8;
6327                        break;
6328                default:
6329                        si_pi->max_cu = 0;
6330                        break;
6331                }
6332        } else {
6333                si_pi->max_cu = 0;
6334        }
6335}
6336
6337static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6338                                                             struct amdgpu_clock_voltage_dependency_table *table)
6339{
6340        u32 i;
6341        int j;
6342        u16 leakage_voltage;
6343
6344        if (table) {
6345                for (i = 0; i < table->count; i++) {
6346                        switch (si_get_leakage_voltage_from_leakage_index(adev,
6347                                                                          table->entries[i].v,
6348                                                                          &leakage_voltage)) {
6349                        case 0:
6350                                table->entries[i].v = leakage_voltage;
6351                                break;
6352                        case -EAGAIN:
6353                                return -EINVAL;
6354                        case -EINVAL:
6355                        default:
6356                                break;
6357                        }
6358                }
6359
6360                for (j = (table->count - 2); j >= 0; j--) {
6361                        table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6362                                table->entries[j].v : table->entries[j + 1].v;
6363                }
6364        }
6365        return 0;
6366}
6367
6368static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6369{
6370        int ret = 0;
6371
6372        ret = si_patch_single_dependency_table_based_on_leakage(adev,
6373                                                                &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6374        if (ret)
6375                DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6376        ret = si_patch_single_dependency_table_based_on_leakage(adev,
6377                                                                &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6378        if (ret)
6379                DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6380        ret = si_patch_single_dependency_table_based_on_leakage(adev,
6381                                                                &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6382        if (ret)
6383                DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6384        return ret;
6385}
6386
6387static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6388                                          struct amdgpu_ps *amdgpu_new_state,
6389                                          struct amdgpu_ps *amdgpu_current_state)
6390{
6391        u32 lane_width;
6392        u32 new_lane_width =
6393                (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6394        u32 current_lane_width =
6395                (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6396
6397        if (new_lane_width != current_lane_width) {
6398                amdgpu_set_pcie_lanes(adev, new_lane_width);
6399                lane_width = amdgpu_get_pcie_lanes(adev);
6400                si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6401        }
6402}
6403
6404static void si_dpm_setup_asic(struct amdgpu_device *adev)
6405{
6406        si_read_clock_registers(adev);
6407        si_enable_acpi_power_management(adev);
6408}
6409
6410static int si_thermal_enable_alert(struct amdgpu_device *adev,
6411                                   bool enable)
6412{
6413        u32 thermal_int = RREG32(CG_THERMAL_INT);
6414
6415        if (enable) {
6416                PPSMC_Result result;
6417
6418                thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6419                WREG32(CG_THERMAL_INT, thermal_int);
6420                result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6421                if (result != PPSMC_Result_OK) {
6422                        DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6423                        return -EINVAL;
6424                }
6425        } else {
6426                thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6427                WREG32(CG_THERMAL_INT, thermal_int);
6428        }
6429
6430        return 0;
6431}
6432
6433static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6434                                            int min_temp, int max_temp)
6435{
6436        int low_temp = 0 * 1000;
6437        int high_temp = 255 * 1000;
6438
6439        if (low_temp < min_temp)
6440                low_temp = min_temp;
6441        if (high_temp > max_temp)
6442                high_temp = max_temp;
6443        if (high_temp < low_temp) {
6444                DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6445                return -EINVAL;
6446        }
6447
6448        WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6449        WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6450        WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6451
6452        adev->pm.dpm.thermal.min_temp = low_temp;
6453        adev->pm.dpm.thermal.max_temp = high_temp;
6454
6455        return 0;
6456}
6457
6458static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6459{
6460        struct si_power_info *si_pi = si_get_pi(adev);
6461        u32 tmp;
6462
6463        if (si_pi->fan_ctrl_is_in_default_mode) {
6464                tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6465                si_pi->fan_ctrl_default_mode = tmp;
6466                tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6467                si_pi->t_min = tmp;
6468                si_pi->fan_ctrl_is_in_default_mode = false;
6469        }
6470
6471        tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6472        tmp |= TMIN(0);
6473        WREG32(CG_FDO_CTRL2, tmp);
6474
6475        tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6476        tmp |= FDO_PWM_MODE(mode);
6477        WREG32(CG_FDO_CTRL2, tmp);
6478}
6479
6480static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6481{
6482        struct si_power_info *si_pi = si_get_pi(adev);
6483        PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6484        u32 duty100;
6485        u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6486        u16 fdo_min, slope1, slope2;
6487        u32 reference_clock, tmp;
6488        int ret;
6489        u64 tmp64;
6490
6491        if (!si_pi->fan_table_start) {
6492                adev->pm.dpm.fan.ucode_fan_control = false;
6493                return 0;
6494        }
6495
6496        duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6497
6498        if (duty100 == 0) {
6499                adev->pm.dpm.fan.ucode_fan_control = false;
6500                return 0;
6501        }
6502
6503        tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6504        do_div(tmp64, 10000);
6505        fdo_min = (u16)tmp64;
6506
6507        t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6508        t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6509
6510        pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6511        pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6512
6513        slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6514        slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6515
6516        fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6517        fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6518        fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6519        fan_table.slope1 = cpu_to_be16(slope1);
6520        fan_table.slope2 = cpu_to_be16(slope2);
6521        fan_table.fdo_min = cpu_to_be16(fdo_min);
6522        fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6523        fan_table.hys_up = cpu_to_be16(1);
6524        fan_table.hys_slope = cpu_to_be16(1);
6525        fan_table.temp_resp_lim = cpu_to_be16(5);
6526        reference_clock = amdgpu_asic_get_xclk(adev);
6527
6528        fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6529                                                reference_clock) / 1600);
6530        fan_table.fdo_max = cpu_to_be16((u16)duty100);
6531
6532        tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6533        fan_table.temp_src = (uint8_t)tmp;
6534
6535        ret = amdgpu_si_copy_bytes_to_smc(adev,
6536                                          si_pi->fan_table_start,
6537                                          (u8 *)(&fan_table),
6538                                          sizeof(fan_table),
6539                                          si_pi->sram_end);
6540
6541        if (ret) {
6542                DRM_ERROR("Failed to load fan table to the SMC.");
6543                adev->pm.dpm.fan.ucode_fan_control = false;
6544        }
6545
6546        return ret;
6547}
6548
6549static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6550{
6551        struct si_power_info *si_pi = si_get_pi(adev);
6552        PPSMC_Result ret;
6553
6554        ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6555        if (ret == PPSMC_Result_OK) {
6556                si_pi->fan_is_controlled_by_smc = true;
6557                return 0;
6558        } else {
6559                return -EINVAL;
6560        }
6561}
6562
6563static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6564{
6565        struct si_power_info *si_pi = si_get_pi(adev);
6566        PPSMC_Result ret;
6567
6568        ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6569
6570        if (ret == PPSMC_Result_OK) {
6571                si_pi->fan_is_controlled_by_smc = false;
6572                return 0;
6573        } else {
6574                return -EINVAL;
6575        }
6576}
6577
6578static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6579                                      u32 *speed)
6580{
6581        u32 duty, duty100;
6582        u64 tmp64;
6583
6584        if (adev->pm.no_fan)
6585                return -ENOENT;
6586
6587        duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6588        duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6589
6590        if (duty100 == 0)
6591                return -EINVAL;
6592
6593        tmp64 = (u64)duty * 100;
6594        do_div(tmp64, duty100);
6595        *speed = (u32)tmp64;
6596
6597        if (*speed > 100)
6598                *speed = 100;
6599
6600        return 0;
6601}
6602
6603static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6604                                      u32 speed)
6605{
6606        struct si_power_info *si_pi = si_get_pi(adev);
6607        u32 tmp;
6608        u32 duty, duty100;
6609        u64 tmp64;
6610
6611        if (adev->pm.no_fan)
6612                return -ENOENT;
6613
6614        if (si_pi->fan_is_controlled_by_smc)
6615                return -EINVAL;
6616
6617        if (speed > 100)
6618                return -EINVAL;
6619
6620        duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6621
6622        if (duty100 == 0)
6623                return -EINVAL;
6624
6625        tmp64 = (u64)speed * duty100;
6626        do_div(tmp64, 100);
6627        duty = (u32)tmp64;
6628
6629        tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6630        tmp |= FDO_STATIC_DUTY(duty);
6631        WREG32(CG_FDO_CTRL0, tmp);
6632
6633        return 0;
6634}
6635
6636static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6637{
6638        if (mode) {
6639                /* stop auto-manage */
6640                if (adev->pm.dpm.fan.ucode_fan_control)
6641                        si_fan_ctrl_stop_smc_fan_control(adev);
6642                si_fan_ctrl_set_static_mode(adev, mode);
6643        } else {
6644                /* restart auto-manage */
6645                if (adev->pm.dpm.fan.ucode_fan_control)
6646                        si_thermal_start_smc_fan_control(adev);
6647                else
6648                        si_fan_ctrl_set_default_mode(adev);
6649        }
6650}
6651
6652static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6653{
6654        struct si_power_info *si_pi = si_get_pi(adev);
6655        u32 tmp;
6656
6657        if (si_pi->fan_is_controlled_by_smc)
6658                return 0;
6659
6660        tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6661        return (tmp >> FDO_PWM_MODE_SHIFT);
6662}
6663
6664#if 0
6665static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6666                                         u32 *speed)
6667{
6668        u32 tach_period;
6669        u32 xclk = amdgpu_asic_get_xclk(adev);
6670
6671        if (adev->pm.no_fan)
6672                return -ENOENT;
6673
6674        if (adev->pm.fan_pulses_per_revolution == 0)
6675                return -ENOENT;
6676
6677        tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6678        if (tach_period == 0)
6679                return -ENOENT;
6680
6681        *speed = 60 * xclk * 10000 / tach_period;
6682
6683        return 0;
6684}
6685
6686static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6687                                         u32 speed)
6688{
6689        u32 tach_period, tmp;
6690        u32 xclk = amdgpu_asic_get_xclk(adev);
6691
6692        if (adev->pm.no_fan)
6693                return -ENOENT;
6694
6695        if (adev->pm.fan_pulses_per_revolution == 0)
6696                return -ENOENT;
6697
6698        if ((speed < adev->pm.fan_min_rpm) ||
6699            (speed > adev->pm.fan_max_rpm))
6700                return -EINVAL;
6701
6702        if (adev->pm.dpm.fan.ucode_fan_control)
6703                si_fan_ctrl_stop_smc_fan_control(adev);
6704
6705        tach_period = 60 * xclk * 10000 / (8 * speed);
6706        tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6707        tmp |= TARGET_PERIOD(tach_period);
6708        WREG32(CG_TACH_CTRL, tmp);
6709
6710        si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6711
6712        return 0;
6713}
6714#endif
6715
6716static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6717{
6718        struct si_power_info *si_pi = si_get_pi(adev);
6719        u32 tmp;
6720
6721        if (!si_pi->fan_ctrl_is_in_default_mode) {
6722                tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6723                tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6724                WREG32(CG_FDO_CTRL2, tmp);
6725
6726                tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6727                tmp |= TMIN(si_pi->t_min);
6728                WREG32(CG_FDO_CTRL2, tmp);
6729                si_pi->fan_ctrl_is_in_default_mode = true;
6730        }
6731}
6732
6733static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6734{
6735        if (adev->pm.dpm.fan.ucode_fan_control) {
6736                si_fan_ctrl_start_smc_fan_control(adev);
6737                si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6738        }
6739}
6740
6741static void si_thermal_initialize(struct amdgpu_device *adev)
6742{
6743        u32 tmp;
6744
6745        if (adev->pm.fan_pulses_per_revolution) {
6746                tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6747                tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6748                WREG32(CG_TACH_CTRL, tmp);
6749        }
6750
6751        tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6752        tmp |= TACH_PWM_RESP_RATE(0x28);
6753        WREG32(CG_FDO_CTRL2, tmp);
6754}
6755
6756static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6757{
6758        int ret;
6759
6760        si_thermal_initialize(adev);
6761        ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6762        if (ret)
6763                return ret;
6764        ret = si_thermal_enable_alert(adev, true);
6765        if (ret)
6766                return ret;
6767        if (adev->pm.dpm.fan.ucode_fan_control) {
6768                ret = si_halt_smc(adev);
6769                if (ret)
6770                        return ret;
6771                ret = si_thermal_setup_fan_table(adev);
6772                if (ret)
6773                        return ret;
6774                ret = si_resume_smc(adev);
6775                if (ret)
6776                        return ret;
6777                si_thermal_start_smc_fan_control(adev);
6778        }
6779
6780        return 0;
6781}
6782
6783static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6784{
6785        if (!adev->pm.no_fan) {
6786                si_fan_ctrl_set_default_mode(adev);
6787                si_fan_ctrl_stop_smc_fan_control(adev);
6788        }
6789}
6790
6791static int si_dpm_enable(struct amdgpu_device *adev)
6792{
6793        struct rv7xx_power_info *pi = rv770_get_pi(adev);
6794        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6795        struct si_power_info *si_pi = si_get_pi(adev);
6796        struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6797        int ret;
6798
6799        if (amdgpu_si_is_smc_running(adev))
6800                return -EINVAL;
6801        if (pi->voltage_control || si_pi->voltage_control_svi2)
6802                si_enable_voltage_control(adev, true);
6803        if (pi->mvdd_control)
6804                si_get_mvdd_configuration(adev);
6805        if (pi->voltage_control || si_pi->voltage_control_svi2) {
6806                ret = si_construct_voltage_tables(adev);
6807                if (ret) {
6808                        DRM_ERROR("si_construct_voltage_tables failed\n");
6809                        return ret;
6810                }
6811        }
6812        if (eg_pi->dynamic_ac_timing) {
6813                ret = si_initialize_mc_reg_table(adev);
6814                if (ret)
6815                        eg_pi->dynamic_ac_timing = false;
6816        }
6817        if (pi->dynamic_ss)
6818                si_enable_spread_spectrum(adev, true);
6819        if (pi->thermal_protection)
6820                si_enable_thermal_protection(adev, true);
6821        si_setup_bsp(adev);
6822        si_program_git(adev);
6823        si_program_tp(adev);
6824        si_program_tpp(adev);
6825        si_program_sstp(adev);
6826        si_enable_display_gap(adev);
6827        si_program_vc(adev);
6828        ret = si_upload_firmware(adev);
6829        if (ret) {
6830                DRM_ERROR("si_upload_firmware failed\n");
6831                return ret;
6832        }
6833        ret = si_process_firmware_header(adev);
6834        if (ret) {
6835                DRM_ERROR("si_process_firmware_header failed\n");
6836                return ret;
6837        }
6838        ret = si_initial_switch_from_arb_f0_to_f1(adev);
6839        if (ret) {
6840                DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6841                return ret;
6842        }
6843        ret = si_init_smc_table(adev);
6844        if (ret) {
6845                DRM_ERROR("si_init_smc_table failed\n");
6846                return ret;
6847        }
6848        ret = si_init_smc_spll_table(adev);
6849        if (ret) {
6850                DRM_ERROR("si_init_smc_spll_table failed\n");
6851                return ret;
6852        }
6853        ret = si_init_arb_table_index(adev);
6854        if (ret) {
6855                DRM_ERROR("si_init_arb_table_index failed\n");
6856                return ret;
6857        }
6858        if (eg_pi->dynamic_ac_timing) {
6859                ret = si_populate_mc_reg_table(adev, boot_ps);
6860                if (ret) {
6861                        DRM_ERROR("si_populate_mc_reg_table failed\n");
6862                        return ret;
6863                }
6864        }
6865        ret = si_initialize_smc_cac_tables(adev);
6866        if (ret) {
6867                DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6868                return ret;
6869        }
6870        ret = si_initialize_hardware_cac_manager(adev);
6871        if (ret) {
6872                DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6873                return ret;
6874        }
6875        ret = si_initialize_smc_dte_tables(adev);
6876        if (ret) {
6877                DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6878                return ret;
6879        }
6880        ret = si_populate_smc_tdp_limits(adev, boot_ps);
6881        if (ret) {
6882                DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6883                return ret;
6884        }
6885        ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6886        if (ret) {
6887                DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6888                return ret;
6889        }
6890        si_program_response_times(adev);
6891        si_program_ds_registers(adev);
6892        si_dpm_start_smc(adev);
6893        ret = si_notify_smc_display_change(adev, false);
6894        if (ret) {
6895                DRM_ERROR("si_notify_smc_display_change failed\n");
6896                return ret;
6897        }
6898        si_enable_sclk_control(adev, true);
6899        si_start_dpm(adev);
6900
6901        si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6902        si_thermal_start_thermal_controller(adev);
6903        ni_update_current_ps(adev, boot_ps);
6904
6905        return 0;
6906}
6907
6908static int si_set_temperature_range(struct amdgpu_device *adev)
6909{
6910        int ret;
6911
6912        ret = si_thermal_enable_alert(adev, false);
6913        if (ret)
6914                return ret;
6915        ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6916        if (ret)
6917                return ret;
6918        ret = si_thermal_enable_alert(adev, true);
6919        if (ret)
6920                return ret;
6921
6922        return ret;
6923}
6924
6925static void si_dpm_disable(struct amdgpu_device *adev)
6926{
6927        struct rv7xx_power_info *pi = rv770_get_pi(adev);
6928        struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6929
6930        if (!amdgpu_si_is_smc_running(adev))
6931                return;
6932        si_thermal_stop_thermal_controller(adev);
6933        si_disable_ulv(adev);
6934        si_clear_vc(adev);
6935        if (pi->thermal_protection)
6936                si_enable_thermal_protection(adev, false);
6937        si_enable_power_containment(adev, boot_ps, false);
6938        si_enable_smc_cac(adev, boot_ps, false);
6939        si_enable_spread_spectrum(adev, false);
6940        si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6941        si_stop_dpm(adev);
6942        si_reset_to_default(adev);
6943        si_dpm_stop_smc(adev);
6944        si_force_switch_to_arb_f0(adev);
6945
6946        ni_update_current_ps(adev, boot_ps);
6947}
6948
6949static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6950{
6951        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6952        struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6953        struct amdgpu_ps *new_ps = &requested_ps;
6954
6955        ni_update_requested_ps(adev, new_ps);
6956        si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6957
6958        return 0;
6959}
6960
6961static int si_power_control_set_level(struct amdgpu_device *adev)
6962{
6963        struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6964        int ret;
6965
6966        ret = si_restrict_performance_levels_before_switch(adev);
6967        if (ret)
6968                return ret;
6969        ret = si_halt_smc(adev);
6970        if (ret)
6971                return ret;
6972        ret = si_populate_smc_tdp_limits(adev, new_ps);
6973        if (ret)
6974                return ret;
6975        ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6976        if (ret)
6977                return ret;
6978        ret = si_resume_smc(adev);
6979        if (ret)
6980                return ret;
6981        ret = si_set_sw_state(adev);
6982        if (ret)
6983                return ret;
6984        return 0;
6985}
6986
6987static int si_dpm_set_power_state(struct amdgpu_device *adev)
6988{
6989        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6990        struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6991        struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6992        int ret;
6993
6994        ret = si_disable_ulv(adev);
6995        if (ret) {
6996                DRM_ERROR("si_disable_ulv failed\n");
6997                return ret;
6998        }
6999        ret = si_restrict_performance_levels_before_switch(adev);
7000        if (ret) {

7001                DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7002                return ret;
7003        }
7004        if (eg_pi->pcie_performance_request)
7005                si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7006        ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7007        ret = si_enable_power_containment(adev, new_ps, false);
7008        if (ret) {
7009                DRM_ERROR("si_enable_power_containment failed\n");
7010                return ret;
7011        }
7012        ret = si_enable_smc_cac(adev, new_ps, false);
7013        if (ret) {
7014                DRM_ERROR("si_enable_smc_cac failed\n");
7015                return ret;
7016        }
7017        ret = si_halt_smc(adev);
7018        if (ret) {
7019                DRM_ERROR("si_halt_smc failed\n");
7020                return ret;
7021        }
7022        ret = si_upload_sw_state(adev, new_ps);
7023        if (ret) {
7024                DRM_ERROR("si_upload_sw_state failed\n");
7025                return ret;
7026        }
7027        ret = si_upload_smc_data(adev);
7028        if (ret) {
7029                DRM_ERROR("si_upload_smc_data failed\n");
7030                return ret;
7031        }
7032        ret = si_upload_ulv_state(adev);
7033        if (ret) {
7034                DRM_ERROR("si_upload_ulv_state failed\n");
7035                return ret;
7036        }
7037        if (eg_pi->dynamic_ac_timing) {
7038                ret = si_upload_mc_reg_table(adev, new_ps);
7039                if (ret) {
7040                        DRM_ERROR("si_upload_mc_reg_table failed\n");
7041                        return ret;
7042                }
7043        }
7044        ret = si_program_memory_timing_parameters(adev, new_ps);
7045        if (ret) {
7046                DRM_ERROR("si_program_memory_timing_parameters failed\n");
7047                return ret;
7048        }
7049        si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7050
7051        ret = si_resume_smc(adev);
7052        if (ret) {
7053                DRM_ERROR("si_resume_smc failed\n");
7054                return ret;
7055        }
7056        ret = si_set_sw_state(adev);
7057        if (ret) {
7058                DRM_ERROR("si_set_sw_state failed\n");
7059                return ret;
7060        }
7061        ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7062        if (eg_pi->pcie_performance_request)
7063                si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7064        ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7065        if (ret) {
7066                DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7067                return ret;
7068        }
7069        ret = si_enable_smc_cac(adev, new_ps, true);
7070        if (ret) {
7071                DRM_ERROR("si_enable_smc_cac failed\n");
7072                return ret;
7073        }
7074        ret = si_enable_power_containment(adev, new_ps, true);
7075        if (ret) {
7076                DRM_ERROR("si_enable_power_containment failed\n");
7077                return ret;
7078        }
7079
7080        ret = si_power_control_set_level(adev);
7081        if (ret) {
7082                DRM_ERROR("si_power_control_set_level failed\n");
7083                return ret;
7084        }
7085
7086        return 0;
7087}
7088
7089static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7090{
7091        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7092        struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7093
7094        ni_update_current_ps(adev, new_ps);
7095}
7096
7097#if 0
7098void si_dpm_reset_asic(struct amdgpu_device *adev)
7099{
7100        si_restrict_performance_levels_before_switch(adev);
7101        si_disable_ulv(adev);
7102        si_set_boot_state(adev);
7103}
7104#endif
7105
7106static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7107{
7108        si_program_display_gap(adev);
7109}
7110
7111
7112static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7113                                          struct amdgpu_ps *rps,
7114                                          struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7115                                          u8 table_rev)
7116{
7117        rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7118        rps->class = le16_to_cpu(non_clock_info->usClassification);
7119        rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7120
7121        if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7122                rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7123                rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7124        } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7125                rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7126                rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7127        } else {
7128                rps->vclk = 0;
7129                rps->dclk = 0;
7130        }
7131
7132        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7133                adev->pm.dpm.boot_ps = rps;
7134        if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7135                adev->pm.dpm.uvd_ps = rps;
7136}
7137
7138static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7139                                      struct amdgpu_ps *rps, int index,
7140                                      union pplib_clock_info *clock_info)
7141{
7142        struct rv7xx_power_info *pi = rv770_get_pi(adev);
7143        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7144        struct si_power_info *si_pi = si_get_pi(adev);
7145        struct  si_ps *ps = si_get_ps(rps);
7146        u16 leakage_voltage;
7147        struct rv7xx_pl *pl = &ps->performance_levels[index];
7148        int ret;
7149
7150        ps->performance_level_count = index + 1;
7151
7152        pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7153        pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7154        pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7155        pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7156
7157        pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7158        pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7159        pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7160        pl->pcie_gen = r600_get_pcie_gen_support(adev,
7161                                                 si_pi->sys_pcie_mask,
7162                                                 si_pi->boot_pcie_gen,
7163                                                 clock_info->si.ucPCIEGen);
7164
7165        /* patch up vddc if necessary */
7166        ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7167                                                        &leakage_voltage);
7168        if (ret == 0)
7169                pl->vddc = leakage_voltage;
7170
7171        if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7172                pi->acpi_vddc = pl->vddc;
7173                eg_pi->acpi_vddci = pl->vddci;
7174                si_pi->acpi_pcie_gen = pl->pcie_gen;
7175        }
7176
7177        if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7178            index == 0) {
7179                /* XXX disable for A0 tahiti */
7180                si_pi->ulv.supported = false;
7181                si_pi->ulv.pl = *pl;
7182                si_pi->ulv.one_pcie_lane_in_ulv = false;
7183                si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7184                si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7185                si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7186        }
7187
7188        if (pi->min_vddc_in_table > pl->vddc)
7189                pi->min_vddc_in_table = pl->vddc;
7190
7191        if (pi->max_vddc_in_table < pl->vddc)
7192                pi->max_vddc_in_table = pl->vddc;
7193
7194        /* patch up boot state */
7195        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7196                u16 vddc, vddci, mvdd;
7197                amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7198                pl->mclk = adev->clock.default_mclk;
7199                pl->sclk = adev->clock.default_sclk;
7200                pl->vddc = vddc;
7201                pl->vddci = vddci;
7202                si_pi->mvdd_bootup_value = mvdd;
7203        }
7204
7205        if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7206            ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7207                adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7208                adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7209                adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7210                adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7211        }
7212}
7213
7214union pplib_power_state {
7215        struct _ATOM_PPLIB_STATE v1;
7216        struct _ATOM_PPLIB_STATE_V2 v2;
7217};
7218
7219static int si_parse_power_table(struct amdgpu_device *adev)
7220{
7221        struct amdgpu_mode_info *mode_info = &adev->mode_info;
7222        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7223        union pplib_power_state *power_state;
7224        int i, j, k, non_clock_array_index, clock_array_index;
7225        union pplib_clock_info *clock_info;
7226        struct _StateArray *state_array;
7227        struct _ClockInfoArray *clock_info_array;
7228        struct _NonClockInfoArray *non_clock_info_array;
7229        union power_info *power_info;
7230        int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7231        u16 data_offset;
7232        u8 frev, crev;
7233        u8 *power_state_offset;
7234        struct  si_ps *ps;
7235
7236        if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7237                                   &frev, &crev, &data_offset))
7238                return -EINVAL;
7239        power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7240
7241        amdgpu_add_thermal_controller(adev);
7242
7243        state_array = (struct _StateArray *)
7244                (mode_info->atom_context->bios + data_offset +
7245                 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7246        clock_info_array = (struct _ClockInfoArray *)
7247                (mode_info->atom_context->bios + data_offset +
7248                 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7249        non_clock_info_array = (struct _NonClockInfoArray *)
7250                (mode_info->atom_context->bios + data_offset +
7251                 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7252
7253        adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7254                                  state_array->ucNumEntries, GFP_KERNEL);
7255        if (!adev->pm.dpm.ps)
7256                return -ENOMEM;
7257        power_state_offset = (u8 *)state_array->states;
7258        for (i = 0; i < state_array->ucNumEntries; i++) {
7259                u8 *idx;
7260                power_state = (union pplib_power_state *)power_state_offset;
7261                non_clock_array_index = power_state->v2.nonClockInfoIndex;
7262                non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7263                        &non_clock_info_array->nonClockInfo[non_clock_array_index];
7264                ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7265                if (ps == NULL) {
7266                        kfree(adev->pm.dpm.ps);
7267                        return -ENOMEM;
7268                }
7269                adev->pm.dpm.ps[i].ps_priv = ps;
7270                si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7271                                              non_clock_info,
7272                                              non_clock_info_array->ucEntrySize);
7273                k = 0;
7274                idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7275                for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7276                        clock_array_index = idx[j];
7277                        if (clock_array_index >= clock_info_array->ucNumEntries)
7278                                continue;
7279                        if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7280                                break;
7281                        clock_info = (union pplib_clock_info *)
7282                                ((u8 *)&clock_info_array->clockInfo[0] +
7283                                 (clock_array_index * clock_info_array->ucEntrySize));
7284                        si_parse_pplib_clock_info(adev,
7285                                                  &adev->pm.dpm.ps[i], k,
7286                                                  clock_info);
7287                        k++;
7288                }
7289                power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7290        }
7291        adev->pm.dpm.num_ps = state_array->ucNumEntries;
7292
7293        /* fill in the vce power states */
7294        for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7295                u32 sclk, mclk;
7296                clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7297                clock_info = (union pplib_clock_info *)
7298                        &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7299                sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7300                sclk |= clock_info->si.ucEngineClockHigh << 16;
7301                mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7302                mclk |= clock_info->si.ucMemoryClockHigh << 16;
7303                adev->pm.dpm.vce_states[i].sclk = sclk;
7304                adev->pm.dpm.vce_states[i].mclk = mclk;
7305        }
7306
7307        return 0;
7308}
7309
7310static int si_dpm_init(struct amdgpu_device *adev)
7311{
7312        struct rv7xx_power_info *pi;
7313        struct evergreen_power_info *eg_pi;
7314        struct ni_power_info *ni_pi;
7315        struct si_power_info *si_pi;
7316        struct atom_clock_dividers dividers;
7317        int ret;
7318        u32 mask;
7319
7320        si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7321        if (si_pi == NULL)
7322                return -ENOMEM;
7323        adev->pm.dpm.priv = si_pi;
7324        ni_pi = &si_pi->ni;
7325        eg_pi = &ni_pi->eg;
7326        pi = &eg_pi->rv7xx;
7327
7328        ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7329        if (ret)
7330                si_pi->sys_pcie_mask = 0;
7331        else
7332                si_pi->sys_pcie_mask = mask;
7333        si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7334        si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7335
7336        si_set_max_cu_value(adev);
7337
7338        rv770_get_max_vddc(adev);
7339        si_get_leakage_vddc(adev);
7340        si_patch_dependency_tables_based_on_leakage(adev);
7341
7342        pi->acpi_vddc = 0;
7343        eg_pi->acpi_vddci = 0;
7344        pi->min_vddc_in_table = 0;
7345        pi->max_vddc_in_table = 0;
7346
7347        ret = amdgpu_get_platform_caps(adev);
7348        if (ret)
7349                return ret;
7350
7351        ret = amdgpu_parse_extended_power_table(adev);
7352        if (ret)
7353                return ret;
7354
7355        ret = si_parse_power_table(adev);
7356        if (ret)
7357                return ret;
7358
7359        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7360                kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7361        if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7362                amdgpu_free_extended_power_table(adev);
7363                return -ENOMEM;
7364        }
7365        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7366        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7367        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7368        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7369        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7370        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7371        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7372        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7373        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7374
7375        if (adev->pm.dpm.voltage_response_time == 0)
7376                adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7377        if (adev->pm.dpm.backbias_response_time == 0)
7378                adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7379
7380        ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7381                                             0, false, &dividers);
7382        if (ret)
7383                pi->ref_div = dividers.ref_div + 1;
7384        else
7385                pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7386
7387        eg_pi->smu_uvd_hs = false;
7388
7389        pi->mclk_strobe_mode_threshold = 40000;
7390        if (si_is_special_1gb_platform(adev))
7391                pi->mclk_stutter_mode_threshold = 0;
7392        else
7393                pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7394        pi->mclk_edc_enable_threshold = 40000;
7395        eg_pi->mclk_edc_wr_enable_threshold = 40000;
7396
7397        ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7398
7399        pi->voltage_control =
7400                amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7401                                            VOLTAGE_OBJ_GPIO_LUT);
7402        if (!pi->voltage_control) {
7403                si_pi->voltage_control_svi2 =
7404                        amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7405                                                    VOLTAGE_OBJ_SVID2);
7406                if (si_pi->voltage_control_svi2)
7407                        amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7408                                                  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7409        }
7410
7411        pi->mvdd_control =
7412                amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7413                                            VOLTAGE_OBJ_GPIO_LUT);
7414
7415        eg_pi->vddci_control =
7416                amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7417                                            VOLTAGE_OBJ_GPIO_LUT);
7418        if (!eg_pi->vddci_control)
7419                si_pi->vddci_control_svi2 =
7420                        amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7421                                                    VOLTAGE_OBJ_SVID2);
7422
7423        si_pi->vddc_phase_shed_control =
7424                amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7425                                            VOLTAGE_OBJ_PHASE_LUT);
7426
7427        rv770_get_engine_memory_ss(adev);
7428
7429        pi->asi = RV770_ASI_DFLT;
7430        pi->pasi = CYPRESS_HASI_DFLT;
7431        pi->vrc = SISLANDS_VRC_DFLT;
7432
7433        pi->gfx_clock_gating = true;
7434
7435        eg_pi->sclk_deep_sleep = true;
7436        si_pi->sclk_deep_sleep_above_low = false;
7437
7438        if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7439                pi->thermal_protection = true;
7440        else
7441                pi->thermal_protection = false;
7442
7443        eg_pi->dynamic_ac_timing = true;
7444
7445        eg_pi->light_sleep = true;
7446#if defined(CONFIG_ACPI)
7447        eg_pi->pcie_performance_request =
7448                amdgpu_acpi_is_pcie_performance_request_supported(adev);
7449#else
7450        eg_pi->pcie_performance_request = false;
7451#endif
7452
7453        si_pi->sram_end = SMC_RAM_END;
7454
7455        adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7456        adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7457        adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7458        adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7459        adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7460        adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7461        adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7462
7463        si_initialize_powertune_defaults(adev);
7464
7465        /* make sure dc limits are valid */
7466        if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7467            (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7468                adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7469                        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7470
7471        si_pi->fan_ctrl_is_in_default_mode = true;
7472
7473        return 0;
7474}
7475
7476static void si_dpm_fini(struct amdgpu_device *adev)
7477{
7478        int i;
7479
7480        if (adev->pm.dpm.ps)
7481                for (i = 0; i < adev->pm.dpm.num_ps; i++)
7482                        kfree(adev->pm.dpm.ps[i].ps_priv);
7483        kfree(adev->pm.dpm.ps);
7484        kfree(adev->pm.dpm.priv);
7485        kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7486        amdgpu_free_extended_power_table(adev);
7487}
7488
7489static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7490                                                    struct seq_file *m)
7491{
7492        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7493        struct amdgpu_ps *rps = &eg_pi->current_rps;
7494        struct  si_ps *ps = si_get_ps(rps);
7495        struct rv7xx_pl *pl;
7496        u32 current_index =
7497                (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7498                CURRENT_STATE_INDEX_SHIFT;
7499
7500        if (current_index >= ps->performance_level_count) {
7501                seq_printf(m, "invalid dpm profile %d\n", current_index);
7502        } else {
7503                pl = &ps->performance_levels[current_index];
7504                seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7505                seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7506                           current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7507        }
7508}
7509
7510static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7511                                      struct amdgpu_irq_src *source,
7512                                      unsigned type,
7513                                      enum amdgpu_interrupt_state state)
7514{
7515        u32 cg_thermal_int;
7516
7517        switch (type) {
7518        case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7519                switch (state) {
7520                case AMDGPU_IRQ_STATE_DISABLE:
7521                        cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7522                        cg_thermal_int |= THERM_INT_MASK_HIGH;
7523                        WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7524                        break;
7525                case AMDGPU_IRQ_STATE_ENABLE:
7526                        cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7527                        cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7528                        WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7529                        break;
7530                default:
7531                        break;
7532                }
7533                break;
7534
7535        case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7536                switch (state) {
7537                case AMDGPU_IRQ_STATE_DISABLE:
7538                        cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7539                        cg_thermal_int |= THERM_INT_MASK_LOW;
7540                        WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7541                        break;
7542                case AMDGPU_IRQ_STATE_ENABLE:
7543                        cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7544                        cg_thermal_int &= ~THERM_INT_MASK_LOW;
7545                        WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7546                        break;
7547                default:
7548                        break;
7549                }
7550                break;
7551
7552        default:
7553                break;
7554        }
7555        return 0;
7556}
7557
7558static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7559                                    struct amdgpu_irq_src *source,
7560                                    struct amdgpu_iv_entry *entry)
7561{
7562        bool queue_thermal = false;
7563
7564        if (entry == NULL)
7565                return -EINVAL;
7566
7567        switch (entry->src_id) {
7568        case 230: /* thermal low to high */
7569                DRM_DEBUG("IH: thermal low to high\n");
7570                adev->pm.dpm.thermal.high_to_low = false;
7571                queue_thermal = true;
7572                break;
7573        case 231: /* thermal high to low */
7574                DRM_DEBUG("IH: thermal high to low\n");
7575                adev->pm.dpm.thermal.high_to_low = true;
7576                queue_thermal = true;
7577                break;
7578        default:
7579                break;
7580        }
7581
7582        if (queue_thermal)
7583                schedule_work(&adev->pm.dpm.thermal.work);
7584
7585        return 0;
7586}
7587
7588static int si_dpm_late_init(void *handle)
7589{
7590        int ret;
7591        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7592
7593        if (!amdgpu_dpm)
7594                return 0;
7595
7596        /* init the sysfs and debugfs files late */
7597        ret = amdgpu_pm_sysfs_init(adev);
7598        if (ret)
7599                return ret;
7600
7601        ret = si_set_temperature_range(adev);
7602        if (ret)
7603                return ret;
7604#if 0 //TODO ?
7605        si_dpm_powergate_uvd(adev, true);
7606#endif
7607        return 0;
7608}
7609
7610/**
7611 * si_dpm_init_microcode - load ucode images from disk
7612 *
7613 * @adev: amdgpu_device pointer
7614 *
7615 * Use the firmware interface to load the ucode images into
7616 * the driver (not loaded into hw).
7617 * Returns 0 on success, error on failure.
7618 */
7619static int si_dpm_init_microcode(struct amdgpu_device *adev)
7620{
7621        const char *chip_name;
7622        char fw_name[30];
7623        int err;
7624
7625        DRM_DEBUG("\n");
7626        switch (adev->asic_type) {
7627        case CHIP_TAHITI:
7628                chip_name = "tahiti";
7629                break;
7630        case CHIP_PITCAIRN:
7631                if ((adev->pdev->revision == 0x81) &&
7632                    ((adev->pdev->device == 0x6810) ||
7633                    (adev->pdev->device == 0x6811)))
7634                        chip_name = "pitcairn_k";
7635                else
7636                        chip_name = "pitcairn";
7637                break;
7638        case CHIP_VERDE:
7639                if (((adev->pdev->device == 0x6820) &&
7640                        ((adev->pdev->revision == 0x81) ||
7641                        (adev->pdev->revision == 0x83))) ||
7642                    ((adev->pdev->device == 0x6821) &&
7643                        ((adev->pdev->revision == 0x83) ||
7644                        (adev->pdev->revision == 0x87))) ||
7645                    ((adev->pdev->revision == 0x87) &&
7646                        ((adev->pdev->device == 0x6823) ||
7647                        (adev->pdev->device == 0x682b))))
7648                        chip_name = "verde_k";
7649                else
7650                        chip_name = "verde";
7651                break;
7652        case CHIP_OLAND:
7653                if (((adev->pdev->revision == 0x81) &&
7654                        ((adev->pdev->device == 0x6600) ||
7655                        (adev->pdev->device == 0x6604) ||
7656                        (adev->pdev->device == 0x6605) ||
7657                        (adev->pdev->device == 0x6610))) ||
7658                    ((adev->pdev->revision == 0x83) &&
7659                        (adev->pdev->device == 0x6610)))
7660                        chip_name = "oland_k";
7661                else
7662                        chip_name = "oland";
7663                break;
7664        case CHIP_HAINAN:
7665                if (((adev->pdev->revision == 0x81) &&
7666                        (adev->pdev->device == 0x6660)) ||
7667                    ((adev->pdev->revision == 0x83) &&
7668                        ((adev->pdev->device == 0x6660) ||
7669                        (adev->pdev->device == 0x6663) ||
7670                        (adev->pdev->device == 0x6665) ||
7671                         (adev->pdev->device == 0x6667))))
7672                        chip_name = "hainan_k";
7673                else if ((adev->pdev->revision == 0xc3) &&
7674                         (adev->pdev->device == 0x6665))
7675                        chip_name = "banks_k_2";
7676                else
7677                        chip_name = "hainan";
7678                break;
7679        default: BUG();
7680        }
7681
7682        snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7683        err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7684        if (err)
7685                goto out;
7686        err = amdgpu_ucode_validate(adev->pm.fw);
7687
7688out:
7689        if (err) {
7690                DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7691                          err, fw_name);
7692                release_firmware(adev->pm.fw);
7693                adev->pm.fw = NULL;
7694        }
7695        return err;
7696
7697}
7698
7699static int si_dpm_sw_init(void *handle)
7700{
7701        int ret;
7702        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7703
7704        ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7705        if (ret)
7706                return ret;
7707
7708        ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7709        if (ret)
7710                return ret;
7711
7712        /* default to balanced state */
7713        adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7714        adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7715        adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7716        adev->pm.default_sclk = adev->clock.default_sclk;
7717        adev->pm.default_mclk = adev->clock.default_mclk;
7718        adev->pm.current_sclk = adev->clock.default_sclk;
7719        adev->pm.current_mclk = adev->clock.default_mclk;
7720        adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7721
7722        if (amdgpu_dpm == 0)
7723                return 0;
7724
7725        ret = si_dpm_init_microcode(adev);
7726        if (ret)
7727                return ret;
7728
7729        INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7730        mutex_lock(&adev->pm.mutex);
7731        ret = si_dpm_init(adev);
7732        if (ret)
7733                goto dpm_failed;
7734        adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7735        if (amdgpu_dpm == 1)
7736                amdgpu_pm_print_power_states(adev);
7737        mutex_unlock(&adev->pm.mutex);
7738        DRM_INFO("amdgpu: dpm initialized\n");
7739
7740        return 0;
7741
7742dpm_failed:
7743        si_dpm_fini(adev);
7744        mutex_unlock(&adev->pm.mutex);
7745        DRM_ERROR("amdgpu: dpm initialization failed\n");
7746        return ret;
7747}
7748
7749static int si_dpm_sw_fini(void *handle)
7750{
7751        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7752
7753        flush_work(&adev->pm.dpm.thermal.work);
7754
7755        mutex_lock(&adev->pm.mutex);
7756        amdgpu_pm_sysfs_fini(adev);
7757        si_dpm_fini(adev);
7758        mutex_unlock(&adev->pm.mutex);
7759
7760        return 0;
7761}
7762
7763static int si_dpm_hw_init(void *handle)
7764{
7765        int ret;
7766
7767        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7768
7769        if (!amdgpu_dpm)
7770                return 0;
7771
7772        mutex_lock(&adev->pm.mutex);
7773        si_dpm_setup_asic(adev);
7774        ret = si_dpm_enable(adev);
7775        if (ret)
7776                adev->pm.dpm_enabled = false;
7777        else
7778                adev->pm.dpm_enabled = true;
7779        mutex_unlock(&adev->pm.mutex);
7780
7781        return ret;
7782}
7783
7784static int si_dpm_hw_fini(void *handle)
7785{
7786        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7787
7788        if (adev->pm.dpm_enabled) {
7789                mutex_lock(&adev->pm.mutex);
7790                si_dpm_disable(adev);
7791                mutex_unlock(&adev->pm.mutex);
7792        }
7793
7794        return 0;
7795}
7796
7797static int si_dpm_suspend(void *handle)
7798{
7799        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7800
7801        if (adev->pm.dpm_enabled) {
7802                mutex_lock(&adev->pm.mutex);
7803                /* disable dpm */
7804                si_dpm_disable(adev);
7805                /* reset the power state */
7806                adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7807                mutex_unlock(&adev->pm.mutex);
7808        }
7809        return 0;
7810}
7811
7812static int si_dpm_resume(void *handle)
7813{
7814        int ret;
7815        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7816
7817        if (adev->pm.dpm_enabled) {
7818                /* asic init will reset to the boot state */
7819                mutex_lock(&adev->pm.mutex);
7820                si_dpm_setup_asic(adev);
7821                ret = si_dpm_enable(adev);
7822                if (ret)
7823                        adev->pm.dpm_enabled = false;
7824                else
7825                        adev->pm.dpm_enabled = true;
7826                mutex_unlock(&adev->pm.mutex);
7827                if (adev->pm.dpm_enabled)
7828                        amdgpu_pm_compute_clocks(adev);
7829        }
7830        return 0;
7831}
7832
7833static bool si_dpm_is_idle(void *handle)
7834{
7835        /* XXX */
7836        return true;
7837}
7838
7839static int si_dpm_wait_for_idle(void *handle)
7840{
7841        /* XXX */
7842        return 0;
7843}
7844
7845static int si_dpm_soft_reset(void *handle)
7846{
7847        return 0;
7848}
7849
7850static int si_dpm_set_clockgating_state(void *handle,
7851                                        enum amd_clockgating_state state)
7852{
7853        return 0;
7854}
7855
7856static int si_dpm_set_powergating_state(void *handle,
7857                                        enum amd_powergating_state state)
7858{
7859        return 0;
7860}
7861
7862/* get temperature in millidegrees */
7863static int si_dpm_get_temp(struct amdgpu_device *adev)
7864{
7865        u32 temp;
7866        int actual_temp = 0;
7867
7868        temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7869                CTF_TEMP_SHIFT;
7870
7871        if (temp & 0x200)
7872                actual_temp = 255;
7873        else
7874                actual_temp = temp & 0x1ff;
7875
7876        actual_temp = (actual_temp * 1000);
7877
7878        return actual_temp;
7879}
7880
7881static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7882{
7883        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7884        struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7885
7886        if (low)
7887                return requested_state->performance_levels[0].sclk;
7888        else
7889                return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7890}
7891
7892static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7893{
7894        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7895        struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7896
7897        if (low)
7898                return requested_state->performance_levels[0].mclk;
7899        else
7900                return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7901}
7902
7903static void si_dpm_print_power_state(struct amdgpu_device *adev,
7904                                     struct amdgpu_ps *rps)
7905{
7906        struct  si_ps *ps = si_get_ps(rps);
7907        struct rv7xx_pl *pl;
7908        int i;
7909
7910        amdgpu_dpm_print_class_info(rps->class, rps->class2);
7911        amdgpu_dpm_print_cap_info(rps->caps);
7912        DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7913        for (i = 0; i < ps->performance_level_count; i++) {
7914                pl = &ps->performance_levels[i];
7915                if (adev->asic_type >= CHIP_TAHITI)
7916                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7917                                 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7918                else
7919                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7920                                 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7921        }
7922        amdgpu_dpm_print_ps_status(adev, rps);
7923}
7924
7925static int si_dpm_early_init(void *handle)
7926{
7927
7928        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7929
7930        si_dpm_set_dpm_funcs(adev);
7931        si_dpm_set_irq_funcs(adev);
7932        return 0;
7933}
7934
7935static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7936                                                const struct rv7xx_pl *si_cpl2)
7937{
7938        return ((si_cpl1->mclk == si_cpl2->mclk) &&
7939                  (si_cpl1->sclk == si_cpl2->sclk) &&
7940                  (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7941                  (si_cpl1->vddc == si_cpl2->vddc) &&
7942                  (si_cpl1->vddci == si_cpl2->vddci));
7943}
7944
7945static int si_check_state_equal(struct amdgpu_device *adev,
7946                                struct amdgpu_ps *cps,
7947                                struct amdgpu_ps *rps,
7948                                bool *equal)
7949{
7950        struct si_ps *si_cps;
7951        struct si_ps *si_rps;
7952        int i;
7953
7954        if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7955                return -EINVAL;
7956
7957        si_cps = si_get_ps(cps);
7958        si_rps = si_get_ps(rps);
7959
7960        if (si_cps == NULL) {
7961                printk("si_cps is NULL\n");
7962                *equal = false;
7963                return 0;
7964        }
7965
7966        if (si_cps->performance_level_count != si_rps->performance_level_count) {
7967                *equal = false;
7968                return 0;
7969        }
7970
7971        for (i = 0; i < si_cps->performance_level_count; i++) {
7972                if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7973                                        &(si_rps->performance_levels[i]))) {
7974                        *equal = false;
7975                        return 0;
7976                }
7977        }
7978
7979        /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7980        *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7981        *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7982
7983        return 0;
7984}
7985
7986static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
7987                              void *value, int *size)
7988{
7989        struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7990        struct amdgpu_ps *rps = &eg_pi->current_rps;
7991        struct  si_ps *ps = si_get_ps(rps);
7992        uint32_t sclk, mclk;
7993        u32 pl_index =
7994                (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7995                CURRENT_STATE_INDEX_SHIFT;
7996
7997        /* size must be at least 4 bytes for all sensors */
7998        if (*size < 4)
7999                return -EINVAL;
8000

8001        switch (idx) {
8002        case AMDGPU_PP_SENSOR_GFX_SCLK:
8003                if (pl_index < ps->performance_level_count) {
8004                        sclk = ps->performance_levels[pl_index].sclk;
8005                        *((uint32_t *)value) = sclk;
8006                        *size = 4;
8007                        return 0;
8008                }
8009                return -EINVAL;
8010        case AMDGPU_PP_SENSOR_GFX_MCLK:
8011                if (pl_index < ps->performance_level_count) {
8012                        mclk = ps->performance_levels[pl_index].mclk;
8013                        *((uint32_t *)value) = mclk;
8014                        *size = 4;
8015                        return 0;
8016                }
8017                return -EINVAL;
8018        case AMDGPU_PP_SENSOR_GPU_TEMP:
8019                *((uint32_t *)value) = si_dpm_get_temp(adev);
8020                *size = 4;
8021                return 0;
8022        default:
8023                return -EINVAL;
8024        }
8025}
8026
8027const struct amd_ip_funcs si_dpm_ip_funcs = {
8028        .name = "si_dpm",
8029        .early_init = si_dpm_early_init,
8030        .late_init = si_dpm_late_init,
8031        .sw_init = si_dpm_sw_init,
8032        .sw_fini = si_dpm_sw_fini,
8033        .hw_init = si_dpm_hw_init,
8034        .hw_fini = si_dpm_hw_fini,
8035        .suspend = si_dpm_suspend,
8036        .resume = si_dpm_resume,
8037        .is_idle = si_dpm_is_idle,
8038        .wait_for_idle = si_dpm_wait_for_idle,
8039        .soft_reset = si_dpm_soft_reset,
8040        .set_clockgating_state = si_dpm_set_clockgating_state,
8041        .set_powergating_state = si_dpm_set_powergating_state,
8042};
8043
8044static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8045        .get_temperature = &si_dpm_get_temp,
8046        .pre_set_power_state = &si_dpm_pre_set_power_state,
8047        .set_power_state = &si_dpm_set_power_state,
8048        .post_set_power_state = &si_dpm_post_set_power_state,
8049        .display_configuration_changed = &si_dpm_display_configuration_changed,
8050        .get_sclk = &si_dpm_get_sclk,
8051        .get_mclk = &si_dpm_get_mclk,
8052        .print_power_state = &si_dpm_print_power_state,
8053        .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8054        .force_performance_level = &si_dpm_force_performance_level,
8055        .vblank_too_short = &si_dpm_vblank_too_short,
8056        .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8057        .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8058        .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8059        .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8060        .check_state_equal = &si_check_state_equal,
8061        .get_vce_clock_state = amdgpu_get_vce_clock_state,
8062        .read_sensor = &si_dpm_read_sensor,
8063};
8064
8065static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8066{
8067        if (adev->pm.funcs == NULL)
8068                adev->pm.funcs = &si_dpm_funcs;
8069}
8070
8071static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8072        .set = si_dpm_set_interrupt_state,
8073        .process = si_dpm_process_interrupt,
8074};
8075
8076static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8077{
8078        adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8079        adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8080}
8081
8082
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