linux/drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h
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   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef SMU71_DISCRETE_H
  24#define SMU71_DISCRETE_H
  25
  26#include "smu71.h"
  27
  28#if !defined(SMC_MICROCODE)
  29#pragma pack(push, 1)
  30#endif
  31
  32#define VDDC_ON_SVI2  0x1
  33#define VDDCI_ON_SVI2 0x2
  34#define MVDD_ON_SVI2  0x4
  35
  36struct SMU71_Discrete_VoltageLevel
  37{
  38    uint16_t    Voltage;
  39    uint16_t    StdVoltageHiSidd;
  40    uint16_t    StdVoltageLoSidd;
  41    uint8_t     Smio;
  42    uint8_t     padding;
  43};
  44
  45typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
  46
  47struct SMU71_Discrete_GraphicsLevel
  48{
  49    uint32_t    MinVddc;
  50    uint32_t    MinVddcPhases;
  51
  52    uint32_t    SclkFrequency;
  53
  54    uint8_t     pcieDpmLevel;
  55    uint8_t     DeepSleepDivId;
  56    uint16_t    ActivityLevel;
  57
  58    uint32_t    CgSpllFuncCntl3;
  59    uint32_t    CgSpllFuncCntl4;
  60    uint32_t    SpllSpreadSpectrum;
  61    uint32_t    SpllSpreadSpectrum2;
  62    uint32_t    CcPwrDynRm;
  63    uint32_t    CcPwrDynRm1;
  64    uint8_t     SclkDid;
  65    uint8_t     DisplayWatermark;
  66    uint8_t     EnabledForActivity;
  67    uint8_t     EnabledForThrottle;
  68    uint8_t     UpHyst;
  69    uint8_t     DownHyst;
  70    uint8_t     VoltageDownHyst;
  71    uint8_t     PowerThrottle;
  72};
  73
  74typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
  75
  76struct SMU71_Discrete_ACPILevel
  77{
  78    uint32_t    Flags;
  79    uint32_t    MinVddc;
  80    uint32_t    MinVddcPhases;
  81    uint32_t    SclkFrequency;
  82    uint8_t     SclkDid;
  83    uint8_t     DisplayWatermark;
  84    uint8_t     DeepSleepDivId;
  85    uint8_t     padding;
  86    uint32_t    CgSpllFuncCntl;
  87    uint32_t    CgSpllFuncCntl2;
  88    uint32_t    CgSpllFuncCntl3;
  89    uint32_t    CgSpllFuncCntl4;
  90    uint32_t    SpllSpreadSpectrum;
  91    uint32_t    SpllSpreadSpectrum2;
  92    uint32_t    CcPwrDynRm;
  93    uint32_t    CcPwrDynRm1;
  94};
  95
  96typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
  97
  98struct SMU71_Discrete_Ulv
  99{
 100    uint32_t    CcPwrDynRm;
 101    uint32_t    CcPwrDynRm1;
 102    uint16_t    VddcOffset;
 103    uint8_t     VddcOffsetVid;
 104    uint8_t     VddcPhase;
 105    uint32_t    Reserved;
 106};
 107
 108typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
 109
 110struct SMU71_Discrete_MemoryLevel
 111{
 112    uint32_t    MinVddc;
 113    uint32_t    MinVddcPhases;
 114    uint32_t    MinVddci;
 115    uint32_t    MinMvdd;
 116
 117    uint32_t    MclkFrequency;
 118
 119    uint8_t     EdcReadEnable;
 120    uint8_t     EdcWriteEnable;
 121    uint8_t     RttEnable;
 122    uint8_t     StutterEnable;
 123
 124    uint8_t     StrobeEnable;
 125    uint8_t     StrobeRatio;
 126    uint8_t     EnabledForThrottle;
 127    uint8_t     EnabledForActivity;
 128
 129    uint8_t     UpHyst;
 130    uint8_t     DownHyst;
 131    uint8_t     VoltageDownHyst;
 132    uint8_t     padding;
 133
 134    uint16_t    ActivityLevel;
 135    uint8_t     DisplayWatermark;
 136    uint8_t     padding1;
 137
 138    uint32_t    MpllFuncCntl;
 139    uint32_t    MpllFuncCntl_1;
 140    uint32_t    MpllFuncCntl_2;
 141    uint32_t    MpllAdFuncCntl;
 142    uint32_t    MpllDqFuncCntl;
 143    uint32_t    MclkPwrmgtCntl;
 144    uint32_t    DllCntl;
 145    uint32_t    MpllSs1;
 146    uint32_t    MpllSs2;
 147};
 148
 149typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
 150
 151struct SMU71_Discrete_LinkLevel
 152{
 153    uint8_t     PcieGenSpeed;           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
 154    uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
 155    uint8_t     EnabledForActivity;
 156    uint8_t     SPC;
 157    uint32_t    DownThreshold;
 158    uint32_t    UpThreshold;
 159    uint32_t    Reserved;
 160};
 161
 162typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
 163
 164
 165#ifdef SMU__DYNAMIC_MCARB_SETTINGS
 166// MC ARB DRAM Timing registers.
 167struct SMU71_Discrete_MCArbDramTimingTableEntry
 168{
 169    uint32_t McArbDramTiming;
 170    uint32_t McArbDramTiming2;
 171    uint8_t  McArbBurstTime;
 172    uint8_t  padding[3];
 173};
 174
 175typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
 176
 177struct SMU71_Discrete_MCArbDramTimingTable
 178{
 179    SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
 180};
 181
 182typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
 183#endif
 184
 185// UVD VCLK/DCLK state (level) definition.
 186struct SMU71_Discrete_UvdLevel
 187{
 188    uint32_t VclkFrequency;
 189    uint32_t DclkFrequency;
 190    uint16_t MinVddc;
 191    uint8_t  MinVddcPhases;
 192    uint8_t  VclkDivider;
 193    uint8_t  DclkDivider;
 194    uint8_t  padding[3];
 195};
 196
 197typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
 198
 199// Clocks for other external blocks (VCE, ACP, SAMU).
 200struct SMU71_Discrete_ExtClkLevel
 201{
 202    uint32_t Frequency;
 203    uint16_t MinVoltage;
 204    uint8_t  MinPhases;
 205    uint8_t  Divider;
 206};
 207
 208typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
 209
 210// Everything that we need to keep track of about the current state.
 211// Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
 212// that need to be checked later.
 213// We don't need to cache everything about a state, just a few parameters.
 214struct SMU71_Discrete_StateInfo
 215{
 216    uint32_t SclkFrequency;
 217    uint32_t MclkFrequency;
 218    uint32_t VclkFrequency;
 219    uint32_t DclkFrequency;
 220    uint32_t SamclkFrequency;
 221    uint32_t AclkFrequency;
 222    uint32_t EclkFrequency;
 223    uint16_t MvddVoltage;
 224    uint16_t padding16;
 225    uint8_t  DisplayWatermark;
 226    uint8_t  McArbIndex;
 227    uint8_t  McRegIndex;
 228    uint8_t  SeqIndex;
 229    uint8_t  SclkDid;
 230    int8_t   SclkIndex;
 231    int8_t   MclkIndex;
 232    uint8_t  PCIeGen;
 233
 234};
 235
 236typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
 237
 238
 239struct SMU71_Discrete_DpmTable
 240{
 241    // Multi-DPM controller settings
 242    SMU71_PIDController                  GraphicsPIDController;
 243    SMU71_PIDController                  MemoryPIDController;
 244    SMU71_PIDController                  LinkPIDController;
 245
 246    uint32_t                            SystemFlags;
 247
 248    // SMIO masks for voltage and phase controls
 249    uint32_t                            SmioMaskVddcVid;
 250    uint32_t                            SmioMaskVddcPhase;
 251    uint32_t                            SmioMaskVddciVid;
 252    uint32_t                            SmioMaskMvddVid;
 253
 254    uint32_t                            VddcLevelCount;
 255    uint32_t                            VddciLevelCount;
 256    uint32_t                            MvddLevelCount;
 257
 258    SMU71_Discrete_VoltageLevel          VddcLevel               [SMU71_MAX_LEVELS_VDDC];
 259    SMU71_Discrete_VoltageLevel          VddciLevel              [SMU71_MAX_LEVELS_VDDCI];
 260    SMU71_Discrete_VoltageLevel          MvddLevel               [SMU71_MAX_LEVELS_MVDD];
 261
 262    uint8_t                             GraphicsDpmLevelCount;
 263    uint8_t                             MemoryDpmLevelCount;
 264    uint8_t                             LinkLevelCount;
 265    uint8_t                             MasterDeepSleepControl;
 266
 267    uint32_t                            Reserved[5];
 268
 269    // State table entries for each DPM state
 270    SMU71_Discrete_GraphicsLevel         GraphicsLevel           [SMU71_MAX_LEVELS_GRAPHICS];
 271    SMU71_Discrete_MemoryLevel           MemoryACPILevel;
 272    SMU71_Discrete_MemoryLevel           MemoryLevel             [SMU71_MAX_LEVELS_MEMORY];
 273    SMU71_Discrete_LinkLevel             LinkLevel               [SMU71_MAX_LEVELS_LINK];
 274    SMU71_Discrete_ACPILevel             ACPILevel;
 275
 276    uint32_t                            SclkStepSize;
 277    uint32_t                            Smio                    [SMU71_MAX_ENTRIES_SMIO];
 278
 279    uint8_t                             GraphicsBootLevel;
 280    uint8_t                             GraphicsVoltageChangeEnable;
 281    uint8_t                             GraphicsThermThrottleEnable;
 282    uint8_t                             GraphicsInterval;
 283
 284    uint8_t                             VoltageInterval;
 285    uint8_t                             ThermalInterval;
 286    uint16_t                            TemperatureLimitHigh;
 287
 288    uint16_t                            TemperatureLimitLow;
 289    uint8_t                             MemoryBootLevel;
 290    uint8_t                             MemoryVoltageChangeEnable;
 291
 292    uint8_t                             MemoryInterval;
 293    uint8_t                             MemoryThermThrottleEnable;
 294    uint8_t                             MergedVddci;
 295    uint8_t                             padding2;
 296
 297    uint16_t                            VoltageResponseTime;
 298    uint16_t                            PhaseResponseTime;
 299
 300    uint8_t                             PCIeBootLinkLevel;
 301    uint8_t                             PCIeGenInterval;
 302    uint8_t                             DTEInterval;
 303    uint8_t                             DTEMode;
 304
 305    uint8_t                             SVI2Enable;
 306    uint8_t                             VRHotGpio;
 307    uint8_t                             AcDcGpio;
 308    uint8_t                             ThermGpio;
 309
 310    uint32_t                            DisplayCac;
 311
 312    uint16_t                            MaxPwr;
 313    uint16_t                            NomPwr;
 314
 315    uint16_t                            FpsHighThreshold;
 316    uint16_t                            FpsLowThreshold;
 317
 318    uint16_t                            BAPMTI_R  [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
 319    uint16_t                            BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
 320
 321    uint8_t                             DTEAmbientTempBase;
 322    uint8_t                             DTETjOffset;
 323    uint8_t                             GpuTjMax;
 324    uint8_t                             GpuTjHyst;
 325
 326    uint16_t                            BootVddc;
 327    uint16_t                            BootVddci;
 328
 329    uint16_t                            BootMVdd;
 330    uint16_t                            padding;
 331
 332    uint32_t                            BAPM_TEMP_GRADIENT;
 333
 334    uint32_t                            LowSclkInterruptThreshold;
 335    uint32_t                            VddGfxReChkWait;
 336
 337    uint16_t                            PPM_PkgPwrLimit;
 338    uint16_t                            PPM_TemperatureLimit;
 339
 340    uint16_t                            DefaultTdp;
 341    uint16_t                            TargetTdp;
 342};
 343
 344typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
 345
 346// --------------------------------------------------- AC Timing Parameters ------------------------------------------------
 347#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
 348#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
 349
 350struct SMU71_Discrete_MCRegisterAddress
 351{
 352    uint16_t s0;
 353    uint16_t s1;
 354};
 355
 356typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
 357
 358struct SMU71_Discrete_MCRegisterSet
 359{
 360    uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 361};
 362
 363typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
 364
 365struct SMU71_Discrete_MCRegisters
 366{
 367    uint8_t                             last;
 368    uint8_t                             reserved[3];
 369    SMU71_Discrete_MCRegisterAddress     address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 370    SMU71_Discrete_MCRegisterSet         data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
 371};
 372
 373typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
 374
 375
 376// --------------------------------------------------- Fan Table -----------------------------------------------------------
 377struct SMU71_Discrete_FanTable
 378{
 379    uint16_t FdoMode;
 380    int16_t  TempMin;
 381    int16_t  TempMed;
 382    int16_t  TempMax;
 383    int16_t  Slope1;
 384    int16_t  Slope2;
 385    int16_t  FdoMin;
 386    int16_t  HystUp;
 387    int16_t  HystDown;
 388    int16_t  HystSlope;
 389    int16_t  TempRespLim;
 390    int16_t  TempCurr;
 391    int16_t  SlopeCurr;
 392    int16_t  PwmCurr;
 393    uint32_t RefreshPeriod;
 394    int16_t  FdoMax;
 395    uint8_t  TempSrc;
 396    int8_t   Padding;
 397};
 398
 399typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
 400
 401#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
 402#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
 403
 404struct SMU71_MclkDpmScoreboard
 405{
 406
 407    uint32_t PercentageBusy;
 408
 409    int32_t  PIDError;
 410    int32_t  PIDIntegral;
 411    int32_t  PIDOutput;
 412
 413    uint32_t SigmaDeltaAccum;
 414    uint32_t SigmaDeltaOutput;
 415    uint32_t SigmaDeltaLevel;
 416
 417    uint32_t UtilizationSetpoint;
 418
 419    uint8_t  TdpClampMode;
 420    uint8_t  TdcClampMode;
 421    uint8_t  ThermClampMode;
 422    uint8_t  VoltageBusy;
 423
 424    int8_t   CurrLevel;
 425    int8_t   TargLevel;
 426    uint8_t  LevelChangeInProgress;
 427    uint8_t  UpHyst;
 428
 429    uint8_t  DownHyst;
 430    uint8_t  VoltageDownHyst;
 431    uint8_t  DpmEnable;
 432    uint8_t  DpmRunning;
 433
 434    uint8_t  DpmForce;
 435    uint8_t  DpmForceLevel;
 436    uint8_t  DisplayWatermark;
 437    uint8_t  McArbIndex;
 438
 439    uint32_t MinimumPerfMclk;
 440
 441    uint8_t  AcpiReq;
 442    uint8_t  AcpiAck;
 443    uint8_t  MclkSwitchInProgress;
 444    uint8_t  MclkSwitchCritical;
 445
 446    uint8_t  TargetMclkIndex;
 447    uint8_t  TargetMvddIndex;
 448    uint8_t  MclkSwitchResult;
 449
 450    uint8_t  EnabledLevelsChange;
 451
 452    uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
 453    uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
 454
 455    void     (*TargetStateCalculator)(uint8_t);
 456    void     (*SavedTargetStateCalculator)(uint8_t);
 457
 458    uint16_t AutoDpmInterval;
 459    uint16_t AutoDpmRange;
 460
 461    uint16_t  MclkSwitchingTime;
 462    uint8_t padding[2];
 463};
 464
 465typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
 466
 467struct SMU71_UlvScoreboard
 468{
 469    uint8_t     EnterUlv;
 470    uint8_t     ExitUlv;
 471    uint8_t     UlvActive;
 472    uint8_t     WaitingForUlv;
 473    uint8_t     UlvEnable;
 474    uint8_t     UlvRunning;
 475    uint8_t     UlvMasterEnable;
 476    uint8_t     padding;
 477    uint32_t    UlvAbortedCount;
 478    uint32_t    UlvTimeStamp;
 479};
 480
 481typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
 482
 483struct SMU71_VddGfxScoreboard
 484{
 485    uint8_t     VddGfxEnable;
 486    uint8_t     VddGfxActive;
 487    uint8_t     padding[2];
 488
 489    uint32_t    VddGfxEnteredCount;
 490    uint32_t    VddGfxAbortedCount;
 491};
 492
 493typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
 494
 495struct SMU71_AcpiScoreboard {
 496  uint32_t SavedInterruptMask[2];
 497  uint8_t LastACPIRequest;
 498  uint8_t CgBifResp;
 499  uint8_t RequestType;
 500  uint8_t Padding;
 501  SMU71_Discrete_ACPILevel D0Level;
 502};
 503
 504typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
 505
 506
 507struct SMU71_Discrete_PmFuses {
 508  // dw0-dw1
 509  uint8_t BapmVddCVidHiSidd[8];
 510
 511  // dw2-dw3
 512  uint8_t BapmVddCVidLoSidd[8];
 513
 514  // dw4-dw5
 515  uint8_t VddCVid[8];
 516
 517  // dw6
 518  uint8_t SviLoadLineEn;
 519  uint8_t SviLoadLineVddC;
 520  uint8_t SviLoadLineTrimVddC;
 521  uint8_t SviLoadLineOffsetVddC;
 522
 523  // dw7
 524  uint16_t TDC_VDDC_PkgLimit;
 525  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
 526  uint8_t TDC_MAWt;
 527
 528  // dw8
 529  uint8_t TdcWaterfallCtl;
 530  uint8_t LPMLTemperatureMin;
 531  uint8_t LPMLTemperatureMax;
 532  uint8_t Reserved;
 533
 534  // dw9-dw12
 535  uint8_t LPMLTemperatureScaler[16];
 536
 537  // dw13-dw14
 538  int16_t FuzzyFan_ErrorSetDelta;
 539  int16_t FuzzyFan_ErrorRateSetDelta;
 540  int16_t FuzzyFan_PwmSetDelta;
 541  uint16_t Reserved6;
 542
 543  // dw15
 544  uint8_t GnbLPML[16];
 545
 546  // dw15
 547  uint8_t GnbLPMLMaxVid;
 548  uint8_t GnbLPMLMinVid;
 549  uint8_t Reserved1[2];
 550
 551  // dw16
 552  uint16_t BapmVddCBaseLeakageHiSidd;
 553  uint16_t BapmVddCBaseLeakageLoSidd;
 554};
 555
 556typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
 557
 558struct SMU71_Discrete_Log_Header_Table {
 559  uint32_t    version;
 560  uint32_t    asic_id;
 561  uint16_t    flags;
 562  uint16_t    entry_size;
 563  uint32_t    total_size;
 564  uint32_t    num_of_entries;
 565  uint8_t     type;
 566  uint8_t     mode;
 567  uint8_t     filler_0[2];
 568  uint32_t    filler_1[2];
 569};
 570
 571typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
 572
 573struct SMU71_Discrete_Log_Cntl {
 574    uint8_t             Enabled;
 575    uint8_t             Type;
 576    uint8_t             padding[2];
 577    uint32_t            BufferSize;
 578    uint32_t            SamplesLogged;
 579    uint32_t            SampleSize;
 580    uint32_t            AddrL;
 581    uint32_t            AddrH;
 582};
 583
 584typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
 585
 586#if defined SMU__DGPU_ONLY
 587  #define CAC_ACC_NW_NUM_OF_SIGNALS 83
 588#endif
 589
 590
 591struct SMU71_Discrete_Cac_Collection_Table {
 592  uint32_t temperature;
 593  uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
 594  uint32_t filler[4];
 595};
 596
 597typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
 598
 599struct SMU71_Discrete_Cac_Verification_Table {
 600  uint32_t VddcTotalPower;
 601  uint32_t VddcLeakagePower;
 602  uint32_t VddcConstantPower;
 603  uint32_t VddcGfxDynamicPower;
 604  uint32_t VddcUvdDynamicPower;
 605  uint32_t VddcVceDynamicPower;
 606  uint32_t VddcAcpDynamicPower;
 607  uint32_t VddcPcieDynamicPower;
 608  uint32_t VddcDceDynamicPower;
 609  uint32_t VddcCurrent;
 610  uint32_t VddcVoltage;
 611  uint32_t VddciTotalPower;
 612  uint32_t VddciLeakagePower;
 613  uint32_t VddciConstantPower;
 614  uint32_t VddciDynamicPower;
 615  uint32_t Vddr1TotalPower;
 616  uint32_t Vddr1LeakagePower;
 617  uint32_t Vddr1ConstantPower;
 618  uint32_t Vddr1DynamicPower;
 619  uint32_t spare[8];
 620  uint32_t temperature;
 621};
 622
 623typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
 624
 625#if !defined(SMC_MICROCODE)
 626#pragma pack(pop)
 627#endif
 628
 629
 630#endif
 631
 632