LXR linux/drivers/i2c/busses/i2c-designware-core.h

   1/*
   2 * Synopsys DesignWare I2C adapter driver.
   3 *
   4 * Based on the TI DAVINCI I2C adapter driver.
   5 *
   6 * Copyright (C) 2006 Texas Instruments.
   7 * Copyright (C) 2007 MontaVista Software Inc.
   8 * Copyright (C) 2009 Provigent Ltd.
   9 *
  10 * ----------------------------------------------------------------------------
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License as published by
  14 * the Free Software Foundation; either version 2 of the License, or
  15 * (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 * ----------------------------------------------------------------------------
  22 *
  23 */
  24
  25#include <linux/i2c.h>
  26#include <linux/pm_qos.h>
  27
  28#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |                     \
  29                                        I2C_FUNC_SMBUS_BYTE |           \
  30                                        I2C_FUNC_SMBUS_BYTE_DATA |      \
  31                                        I2C_FUNC_SMBUS_WORD_DATA |      \
  32                                        I2C_FUNC_SMBUS_BLOCK_DATA |     \
  33                                        I2C_FUNC_SMBUS_I2C_BLOCK)
  34
  35#define DW_IC_CON_MASTER                0x1
  36#define DW_IC_CON_SPEED_STD             0x2
  37#define DW_IC_CON_SPEED_FAST            0x4
  38#define DW_IC_CON_SPEED_HIGH            0x6
  39#define DW_IC_CON_SPEED_MASK            0x6
  40#define DW_IC_CON_10BITADDR_SLAVE               0x8
  41#define DW_IC_CON_10BITADDR_MASTER      0x10
  42#define DW_IC_CON_RESTART_EN            0x20
  43#define DW_IC_CON_SLAVE_DISABLE         0x40
  44#define DW_IC_CON_STOP_DET_IFADDRESSED          0x80
  45#define DW_IC_CON_TX_EMPTY_CTRL         0x100
  46#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL         0x200
  47
  48/*
  49 * Registers offset
  50 */
  51#define DW_IC_CON               0x0
  52#define DW_IC_TAR               0x4
  53#define DW_IC_SAR               0x8
  54#define DW_IC_DATA_CMD          0x10
  55#define DW_IC_SS_SCL_HCNT       0x14
  56#define DW_IC_SS_SCL_LCNT       0x18
  57#define DW_IC_FS_SCL_HCNT       0x1c
  58#define DW_IC_FS_SCL_LCNT       0x20
  59#define DW_IC_HS_SCL_HCNT       0x24
  60#define DW_IC_HS_SCL_LCNT       0x28
  61#define DW_IC_INTR_STAT         0x2c
  62#define DW_IC_INTR_MASK         0x30
  63#define DW_IC_RAW_INTR_STAT     0x34
  64#define DW_IC_RX_TL             0x38
  65#define DW_IC_TX_TL             0x3c
  66#define DW_IC_CLR_INTR          0x40
  67#define DW_IC_CLR_RX_UNDER      0x44
  68#define DW_IC_CLR_RX_OVER       0x48
  69#define DW_IC_CLR_TX_OVER       0x4c
  70#define DW_IC_CLR_RD_REQ        0x50
  71#define DW_IC_CLR_TX_ABRT       0x54
  72#define DW_IC_CLR_RX_DONE       0x58
  73#define DW_IC_CLR_ACTIVITY      0x5c
  74#define DW_IC_CLR_STOP_DET      0x60
  75#define DW_IC_CLR_START_DET     0x64
  76#define DW_IC_CLR_GEN_CALL      0x68
  77#define DW_IC_ENABLE            0x6c
  78#define DW_IC_STATUS            0x70
  79#define DW_IC_TXFLR             0x74
  80#define DW_IC_RXFLR             0x78
  81#define DW_IC_SDA_HOLD          0x7c
  82#define DW_IC_TX_ABRT_SOURCE    0x80
  83#define DW_IC_ENABLE_STATUS     0x9c
  84#define DW_IC_CLR_RESTART_DET   0xa8
  85#define DW_IC_COMP_PARAM_1      0xf4
  86#define DW_IC_COMP_VERSION      0xf8
  87#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  88#define DW_IC_COMP_TYPE         0xfc
  89#define DW_IC_COMP_TYPE_VALUE   0x44570140
  90
  91#define DW_IC_INTR_RX_UNDER     0x001
  92#define DW_IC_INTR_RX_OVER      0x002
  93#define DW_IC_INTR_RX_FULL      0x004
  94#define DW_IC_INTR_TX_OVER      0x008
  95#define DW_IC_INTR_TX_EMPTY     0x010
  96#define DW_IC_INTR_RD_REQ       0x020
  97#define DW_IC_INTR_TX_ABRT      0x040
  98#define DW_IC_INTR_RX_DONE      0x080
  99#define DW_IC_INTR_ACTIVITY     0x100
 100#define DW_IC_INTR_STOP_DET     0x200
 101#define DW_IC_INTR_START_DET    0x400
 102#define DW_IC_INTR_GEN_CALL     0x800
 103#define DW_IC_INTR_RESTART_DET  0x1000
 104
 105#define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
 106                                         DW_IC_INTR_TX_ABRT | \
 107                                         DW_IC_INTR_STOP_DET)
 108#define DW_IC_INTR_MASTER_MASK          (DW_IC_INTR_DEFAULT_MASK | \
 109                                         DW_IC_INTR_TX_EMPTY)
 110#define DW_IC_INTR_SLAVE_MASK           (DW_IC_INTR_DEFAULT_MASK | \
 111                                         DW_IC_INTR_RX_DONE | \
 112                                         DW_IC_INTR_RX_UNDER | \
 113                                         DW_IC_INTR_RD_REQ)
 114
 115#define DW_IC_STATUS_ACTIVITY           0x1
 116#define DW_IC_STATUS_TFE                BIT(2)
 117#define DW_IC_STATUS_MASTER_ACTIVITY    BIT(5)
 118#define DW_IC_STATUS_SLAVE_ACTIVITY     BIT(6)
 119
 120#define DW_IC_SDA_HOLD_RX_SHIFT         16
 121#define DW_IC_SDA_HOLD_RX_MASK          GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
 122
 123#define DW_IC_ERR_TX_ABRT       0x1
 124
 125#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 126
 127#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
 128#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      GENMASK(3, 2)
 129
 130/*
 131 * status codes
 132 */
 133#define STATUS_IDLE                     0x0
 134#define STATUS_WRITE_IN_PROGRESS        0x1
 135#define STATUS_READ_IN_PROGRESS         0x2
 136
 137#define TIMEOUT                 20 /* ms */
 138
 139/*
 140 * operation modes
 141 */
 142#define DW_IC_MASTER            0
 143#define DW_IC_SLAVE             1
 144
 145/*
 146 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 147 *
 148 * Only expected abort codes are listed here
 149 * refer to the datasheet for the full list
 150 */
 151#define ABRT_7B_ADDR_NOACK      0
 152#define ABRT_10ADDR1_NOACK      1
 153#define ABRT_10ADDR2_NOACK      2
 154#define ABRT_TXDATA_NOACK       3
 155#define ABRT_GCALL_NOACK        4
 156#define ABRT_GCALL_READ         5
 157#define ABRT_SBYTE_ACKDET       7
 158#define ABRT_SBYTE_NORSTRT      9
 159#define ABRT_10B_RD_NORSTRT     10
 160#define ABRT_MASTER_DIS         11
 161#define ARB_LOST                12
 162#define ABRT_SLAVE_FLUSH_TXFIFO 13
 163#define ABRT_SLAVE_ARBLOST      14
 164#define ABRT_SLAVE_RD_INTX      15
 165
 166#define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 167#define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 168#define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 169#define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 170#define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 171#define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 172#define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 173#define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 174#define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 175#define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 176#define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 177#define DW_IC_RX_ABRT_SLAVE_RD_INTX     (1UL << ABRT_SLAVE_RD_INTX)
 178#define DW_IC_RX_ABRT_SLAVE_ARBLOST     (1UL << ABRT_SLAVE_ARBLOST)
 179#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO        (1UL << ABRT_SLAVE_FLUSH_TXFIFO)
 180
 181#define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 182                                         DW_IC_TX_ABRT_10ADDR1_NOACK | \
 183                                         DW_IC_TX_ABRT_10ADDR2_NOACK | \
 184                                         DW_IC_TX_ABRT_TXDATA_NOACK | \
 185                                         DW_IC_TX_ABRT_GCALL_NOACK)
 186
 187
 188/**
 189 * struct dw_i2c_dev - private i2c-designware data
 190 * @dev: driver model device node
 191 * @base: IO registers pointer
 192 * @cmd_complete: tx completion indicator
 193 * @clk: input reference clock
 194 * @slave: represent an I2C slave device
 195 * @cmd_err: run time hadware error code
 196 * @msgs: points to an array of messages currently being transferred
 197 * @msgs_num: the number of elements in msgs
 198 * @msg_write_idx: the element index of the current tx message in the msgs
 199 *      array
 200 * @tx_buf_len: the length of the current tx buffer
 201 * @tx_buf: the current tx buffer
 202 * @msg_read_idx: the element index of the current rx message in the msgs
 203 *      array
 204 * @rx_buf_len: the length of the current rx buffer
 205 * @rx_buf: the current rx buffer
 206 * @msg_err: error status of the current transfer
 207 * @status: i2c master status, one of STATUS_*
 208 * @abort_source: copy of the TX_ABRT_SOURCE register
 209 * @irq: interrupt number for the i2c master
 210 * @adapter: i2c subsystem adapter node
 211 * @slave_cfg: configuration for the slave device
 212 * @tx_fifo_depth: depth of the hardware tx fifo
 213 * @rx_fifo_depth: depth of the hardware rx fifo
 214 * @rx_outstanding: current master-rx elements in tx fifo
 215 * @clk_freq: bus clock frequency
 216 * @ss_hcnt: standard speed HCNT value
 217 * @ss_lcnt: standard speed LCNT value
 218 * @fs_hcnt: fast speed HCNT value
 219 * @fs_lcnt: fast speed LCNT value
 220 * @fp_hcnt: fast plus HCNT value
 221 * @fp_lcnt: fast plus LCNT value
 222 * @hs_hcnt: high speed HCNT value
 223 * @hs_lcnt: high speed LCNT value
 224 * @pm_qos: pm_qos_request used while holding a hardware lock on the bus
 225 * @acquire_lock: function to acquire a hardware lock on the bus
 226 * @release_lock: function to release a hardware lock on the bus
 227 * @pm_disabled: true if power-management should be disabled for this i2c-bus
 228 * @disable: function to disable the controller
 229 * @disable_int: function to disable all interrupts
 230 * @init: function to initialize the I2C hardware
 231 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
 232 *
 233 * HCNT and LCNT parameters can be used if the platform knows more accurate
 234 * values than the one computed based only on the input clock frequency.
 235 * Leave them to be %0 if not used.
 236 */
 237struct dw_i2c_dev {
 238        struct device           *dev;
 239        void __iomem            *base;
 240        struct completion       cmd_complete;
 241        struct clk              *clk;
 242        struct reset_control    *rst;
 243        struct i2c_client               *slave;
 244        u32                     (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
 245        struct dw_pci_controller *controller;
 246        int                     cmd_err;
 247        struct i2c_msg          *msgs;
 248        int                     msgs_num;
 249        int                     msg_write_idx;
 250        u32                     tx_buf_len;
 251        u8                      *tx_buf;
 252        int                     msg_read_idx;
 253        u32                     rx_buf_len;
 254        u8                      *rx_buf;
 255        int                     msg_err;
 256        unsigned int            status;
 257        u32                     abort_source;
 258        int                     irq;
 259        u32                     flags;
 260        struct i2c_adapter      adapter;
 261        u32                     functionality;
 262        u32                     master_cfg;
 263        u32                     slave_cfg;
 264        unsigned int            tx_fifo_depth;
 265        unsigned int            rx_fifo_depth;
 266        int                     rx_outstanding;
 267        u32                     clk_freq;
 268        u32                     sda_hold_time;
 269        u32                     sda_falling_time;
 270        u32                     scl_falling_time;
 271        u16                     ss_hcnt;
 272        u16                     ss_lcnt;
 273        u16                     fs_hcnt;
 274        u16                     fs_lcnt;
 275        u16                     fp_hcnt;
 276        u16                     fp_lcnt;
 277        u16                     hs_hcnt;
 278        u16                     hs_lcnt;
 279        struct pm_qos_request   pm_qos;
 280        int                     (*acquire_lock)(struct dw_i2c_dev *dev);
 281        void                    (*release_lock)(struct dw_i2c_dev *dev);
 282        bool                    pm_disabled;
 283        void                    (*disable)(struct dw_i2c_dev *dev);
 284        void                    (*disable_int)(struct dw_i2c_dev *dev);
 285        int                     (*init)(struct dw_i2c_dev *dev);
 286        int                     mode;
 287};
 288
 289#define ACCESS_SWAP             0x00000001
 290#define ACCESS_16BIT            0x00000002
 291#define ACCESS_INTR_MASK        0x00000004
 292
 293#define MODEL_CHERRYTRAIL       0x00000100
 294
 295u32 dw_readl(struct dw_i2c_dev *dev, int offset);
 296void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
 297u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
 298u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
 299void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable);
 300void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable);
 301unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev);
 302int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
 303void i2c_dw_release_lock(struct dw_i2c_dev *dev);
 304int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
 305int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
 306u32 i2c_dw_func(struct i2c_adapter *adap);
 307void i2c_dw_disable(struct dw_i2c_dev *dev);
 308void i2c_dw_disable_int(struct dw_i2c_dev *dev);
 309
 310extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
 311extern int i2c_dw_probe(struct dw_i2c_dev *dev);
 312#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
 313extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
 314#else
 315static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
 316#endif
 317
 318#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
 319extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev);
 320extern void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev);
 321#else
 322static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; }
 323static inline void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev) {}
 324#endif
 325