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24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/errno.h>
27#include <linux/export.h>
28#include <linux/i2c.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/pm_runtime.h>
33
34#include "i2c-designware-core.h"
35
36static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
37{
38
39 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
40 dw_writel(dev, 0, DW_IC_RX_TL);
41
42
43 dw_writel(dev, dev->master_cfg, DW_IC_CON);
44}
45
46
47
48
49
50
51
52
53
54static int i2c_dw_init_master(struct dw_i2c_dev *dev)
55{
56 u32 hcnt, lcnt;
57 u32 reg, comp_param1;
58 u32 sda_falling_time, scl_falling_time;
59 int ret;
60
61 ret = i2c_dw_acquire_lock(dev);
62 if (ret)
63 return ret;
64
65 reg = dw_readl(dev, DW_IC_COMP_TYPE);
66 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
67
68 dev->flags |= ACCESS_SWAP;
69 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
70
71 dev->flags |= ACCESS_16BIT;
72 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
73 dev_err(dev->dev,
74 "Unknown Synopsys component type: 0x%08x\n", reg);
75 i2c_dw_release_lock(dev);
76 return -ENODEV;
77 }
78
79 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
80
81
82 __i2c_dw_enable_and_wait(dev, false);
83
84
85
86 sda_falling_time = dev->sda_falling_time ?: 300;
87 scl_falling_time = dev->scl_falling_time ?: 300;
88
89
90 if (dev->ss_hcnt && dev->ss_lcnt) {
91 hcnt = dev->ss_hcnt;
92 lcnt = dev->ss_lcnt;
93 } else {
94 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
95 4000,
96 sda_falling_time,
97 0,
98 0);
99 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
100 4700,
101 scl_falling_time,
102 0);
103 }
104 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
105 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
106 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
107
108
109 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
110 hcnt = dev->fp_hcnt;
111 lcnt = dev->fp_lcnt;
112 } else if (dev->fs_hcnt && dev->fs_lcnt) {
113 hcnt = dev->fs_hcnt;
114 lcnt = dev->fs_lcnt;
115 } else {
116 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
117 600,
118 sda_falling_time,
119 0,
120 0);
121 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
122 1300,
123 scl_falling_time,
124 0);
125 }
126 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
127 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
128 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
129
130 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
131 DW_IC_CON_SPEED_HIGH) {
132 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
133 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
134 dev_err(dev->dev, "High Speed not supported!\n");
135 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
136 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
137 } else if (dev->hs_hcnt && dev->hs_lcnt) {
138 hcnt = dev->hs_hcnt;
139 lcnt = dev->hs_lcnt;
140 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
141 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
142 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
143 hcnt, lcnt);
144 }
145 }
146
147
148 reg = dw_readl(dev, DW_IC_COMP_VERSION);
149 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
150 if (!dev->sda_hold_time) {
151
152 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
153 }
154
155
156
157
158
159
160
161 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
162 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
163 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
164 } else {
165 dev_warn(dev->dev,
166 "Hardware too old to adjust SDA hold time.\n");
167 }
168
169 i2c_dw_configure_fifo_master(dev);
170 i2c_dw_release_lock(dev);
171
172 return 0;
173}
174
175static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
176{
177 struct i2c_msg *msgs = dev->msgs;
178 u32 ic_con, ic_tar = 0;
179
180
181 __i2c_dw_enable_and_wait(dev, false);
182
183
184 ic_con = dw_readl(dev, DW_IC_CON);
185 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
186 ic_con |= DW_IC_CON_10BITADDR_MASTER;
187
188
189
190
191
192
193 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
194 } else {
195 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
196 }
197
198 dw_writel(dev, ic_con, DW_IC_CON);
199
200
201
202
203
204 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
205
206
207 i2c_dw_disable_int(dev);
208
209
210 __i2c_dw_enable(dev, true);
211
212
213 dw_readl(dev, DW_IC_CLR_INTR);
214 dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
215}
216
217
218
219
220
221
222
223static void
224i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
225{
226 struct i2c_msg *msgs = dev->msgs;
227 u32 intr_mask;
228 int tx_limit, rx_limit;
229 u32 addr = msgs[dev->msg_write_idx].addr;
230 u32 buf_len = dev->tx_buf_len;
231 u8 *buf = dev->tx_buf;
232 bool need_restart = false;
233
234 intr_mask = DW_IC_INTR_MASTER_MASK;
235
236 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
237 u32 flags = msgs[dev->msg_write_idx].flags;
238
239
240
241
242
243
244 if (msgs[dev->msg_write_idx].addr != addr) {
245 dev_err(dev->dev,
246 "%s: invalid target address\n", __func__);
247 dev->msg_err = -EINVAL;
248 break;
249 }
250
251 if (msgs[dev->msg_write_idx].len == 0) {
252 dev_err(dev->dev,
253 "%s: invalid message length\n", __func__);
254 dev->msg_err = -EINVAL;
255 break;
256 }
257
258 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
259
260 buf = msgs[dev->msg_write_idx].buf;
261 buf_len = msgs[dev->msg_write_idx].len;
262
263
264
265
266
267 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
268 (dev->msg_write_idx > 0))
269 need_restart = true;
270 }
271
272 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
273 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
274
275 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
276 u32 cmd = 0;
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291 if (dev->msg_write_idx == dev->msgs_num - 1 &&
292 buf_len == 1 && !(flags & I2C_M_RECV_LEN))
293 cmd |= BIT(9);
294
295 if (need_restart) {
296 cmd |= BIT(10);
297 need_restart = false;
298 }
299
300 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
301
302
303 if (dev->rx_outstanding >= dev->rx_fifo_depth)
304 break;
305
306 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
307 rx_limit--;
308 dev->rx_outstanding++;
309 } else
310 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
311 tx_limit--; buf_len--;
312 }
313
314 dev->tx_buf = buf;
315 dev->tx_buf_len = buf_len;
316
317
318
319
320
321
322 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
323
324 dev->status |= STATUS_WRITE_IN_PROGRESS;
325 break;
326 } else
327 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
328 }
329
330
331
332
333
334 if (dev->msg_write_idx == dev->msgs_num)
335 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
336
337 if (dev->msg_err)
338 intr_mask = 0;
339
340 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
341}
342
343static u8
344i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
345{
346 struct i2c_msg *msgs = dev->msgs;
347 u32 flags = msgs[dev->msg_read_idx].flags;
348
349
350
351
352
353 len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
354 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
355 msgs[dev->msg_read_idx].len = len;
356 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
357
358 return len;
359}
360
361static void
362i2c_dw_read(struct dw_i2c_dev *dev)
363{
364 struct i2c_msg *msgs = dev->msgs;
365 int rx_valid;
366
367 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
368 u32 len;
369 u8 *buf;
370
371 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
372 continue;
373
374 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
375 len = msgs[dev->msg_read_idx].len;
376 buf = msgs[dev->msg_read_idx].buf;
377 } else {
378 len = dev->rx_buf_len;
379 buf = dev->rx_buf;
380 }
381
382 rx_valid = dw_readl(dev, DW_IC_RXFLR);
383
384 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
385 u32 flags = msgs[dev->msg_read_idx].flags;
386
387 *buf = dw_readl(dev, DW_IC_DATA_CMD);
388
389 if (flags & I2C_M_RECV_LEN &&
390 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
391 len = i2c_dw_recv_len(dev, *buf);
392 }
393 buf++;
394 dev->rx_outstanding--;
395 }
396
397 if (len > 0) {
398 dev->status |= STATUS_READ_IN_PROGRESS;
399 dev->rx_buf_len = len;
400 dev->rx_buf = buf;
401 return;
402 } else
403 dev->status &= ~STATUS_READ_IN_PROGRESS;
404 }
405}
406
407
408
409
410static int
411i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
412{
413 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
414 int ret;
415
416 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
417
418 pm_runtime_get_sync(dev->dev);
419
420 reinit_completion(&dev->cmd_complete);
421 dev->msgs = msgs;
422 dev->msgs_num = num;
423 dev->cmd_err = 0;
424 dev->msg_write_idx = 0;
425 dev->msg_read_idx = 0;
426 dev->msg_err = 0;
427 dev->status = STATUS_IDLE;
428 dev->abort_source = 0;
429 dev->rx_outstanding = 0;
430
431 ret = i2c_dw_acquire_lock(dev);
432 if (ret)
433 goto done_nolock;
434
435 ret = i2c_dw_wait_bus_not_busy(dev);
436 if (ret < 0)
437 goto done;
438
439
440 i2c_dw_xfer_init(dev);
441
442
443 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
444 dev_err(dev->dev, "controller timed out\n");
445
446 i2c_dw_init_master(dev);
447 ret = -ETIMEDOUT;
448 goto done;
449 }
450
451
452
453
454
455
456
457
458
459 __i2c_dw_enable(dev, false);
460
461 if (dev->msg_err) {
462 ret = dev->msg_err;
463 goto done;
464 }
465
466
467 if (likely(!dev->cmd_err && !dev->status)) {
468 ret = num;
469 goto done;
470 }
471
472
473 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
474 ret = i2c_dw_handle_tx_abort(dev);
475 goto done;
476 }
477
478 if (dev->status)
479 dev_err(dev->dev,
480 "transfer terminated early - interrupt latency too high?\n");
481
482 ret = -EIO;
483
484done:
485 i2c_dw_release_lock(dev);
486
487done_nolock:
488 pm_runtime_mark_last_busy(dev->dev);
489 pm_runtime_put_autosuspend(dev->dev);
490
491 return ret;
492}
493
494static const struct i2c_algorithm i2c_dw_algo = {
495 .master_xfer = i2c_dw_xfer,
496 .functionality = i2c_dw_func,
497};
498
499static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
500{
501 u32 stat;
502
503
504
505
506
507
508
509
510
511
512
513
514
515 stat = dw_readl(dev, DW_IC_INTR_STAT);
516
517
518
519
520
521
522
523
524 if (stat & DW_IC_INTR_RX_UNDER)
525 dw_readl(dev, DW_IC_CLR_RX_UNDER);
526 if (stat & DW_IC_INTR_RX_OVER)
527 dw_readl(dev, DW_IC_CLR_RX_OVER);
528 if (stat & DW_IC_INTR_TX_OVER)
529 dw_readl(dev, DW_IC_CLR_TX_OVER);
530 if (stat & DW_IC_INTR_RD_REQ)
531 dw_readl(dev, DW_IC_CLR_RD_REQ);
532 if (stat & DW_IC_INTR_TX_ABRT) {
533
534
535
536
537 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
538 dw_readl(dev, DW_IC_CLR_TX_ABRT);
539 }
540 if (stat & DW_IC_INTR_RX_DONE)
541 dw_readl(dev, DW_IC_CLR_RX_DONE);
542 if (stat & DW_IC_INTR_ACTIVITY)
543 dw_readl(dev, DW_IC_CLR_ACTIVITY);
544 if (stat & DW_IC_INTR_STOP_DET)
545 dw_readl(dev, DW_IC_CLR_STOP_DET);
546 if (stat & DW_IC_INTR_START_DET)
547 dw_readl(dev, DW_IC_CLR_START_DET);
548 if (stat & DW_IC_INTR_GEN_CALL)
549 dw_readl(dev, DW_IC_CLR_GEN_CALL);
550
551 return stat;
552}
553
554
555
556
557
558static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
559{
560 u32 stat;
561
562 stat = i2c_dw_read_clear_intrbits(dev);
563 if (stat & DW_IC_INTR_TX_ABRT) {
564 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
565 dev->status = STATUS_IDLE;
566
567
568
569
570
571 dw_writel(dev, 0, DW_IC_INTR_MASK);
572 goto tx_aborted;
573 }
574
575 if (stat & DW_IC_INTR_RX_FULL)
576 i2c_dw_read(dev);
577
578 if (stat & DW_IC_INTR_TX_EMPTY)
579 i2c_dw_xfer_msg(dev);
580
581
582
583
584
585
586
587tx_aborted:
588 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
589 complete(&dev->cmd_complete);
590 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
591
592 stat = dw_readl(dev, DW_IC_INTR_MASK);
593 i2c_dw_disable_int(dev);
594 dw_writel(dev, stat, DW_IC_INTR_MASK);
595 }
596
597 return 0;
598}
599
600static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
601{
602 struct dw_i2c_dev *dev = dev_id;
603 u32 stat, enabled;
604
605 enabled = dw_readl(dev, DW_IC_ENABLE);
606 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
607 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
608 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
609 return IRQ_NONE;
610
611 i2c_dw_irq_handler_master(dev);
612
613 return IRQ_HANDLED;
614}
615
616int i2c_dw_probe(struct dw_i2c_dev *dev)
617{
618 struct i2c_adapter *adap = &dev->adapter;
619 unsigned long irq_flags;
620 int ret;
621
622 init_completion(&dev->cmd_complete);
623
624 dev->init = i2c_dw_init_master;
625 dev->disable = i2c_dw_disable;
626 dev->disable_int = i2c_dw_disable_int;
627
628 ret = dev->init(dev);
629 if (ret)
630 return ret;
631
632 snprintf(adap->name, sizeof(adap->name),
633 "Synopsys DesignWare I2C adapter");
634 adap->retries = 3;
635 adap->algo = &i2c_dw_algo;
636 adap->dev.parent = dev->dev;
637 i2c_set_adapdata(adap, dev);
638
639 if (dev->pm_disabled) {
640 dev_pm_syscore_device(dev->dev, true);
641 irq_flags = IRQF_NO_SUSPEND;
642 } else {
643 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
644 }
645
646 i2c_dw_disable_int(dev);
647 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
648 dev_name(dev->dev), dev);
649 if (ret) {
650 dev_err(dev->dev, "failure requesting irq %i: %d\n",
651 dev->irq, ret);
652 return ret;
653 }
654
655
656
657
658
659
660
661 pm_runtime_get_noresume(dev->dev);
662 ret = i2c_add_numbered_adapter(adap);
663 if (ret)
664 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
665 pm_runtime_put_noidle(dev->dev);
666
667 return ret;
668}
669EXPORT_SYMBOL_GPL(i2c_dw_probe);
670
671MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
672MODULE_LICENSE("GPL");
673