linux/drivers/i2c/busses/i2c-nomadik.c
<<
>>
Prefs
   1/*
   2 * Copyright (C) 2009 ST-Ericsson SA
   3 * Copyright (C) 2009 STMicroelectronics
   4 *
   5 * I2C master mode controller driver, used in Nomadik 8815
   6 * and Ux500 platforms.
   7 *
   8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   9 * Author: Sachin Verma <sachin.verma@st.com>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License version 2, as
  13 * published by the Free Software Foundation.
  14 */
  15#include <linux/init.h>
  16#include <linux/module.h>
  17#include <linux/amba/bus.h>
  18#include <linux/slab.h>
  19#include <linux/interrupt.h>
  20#include <linux/i2c.h>
  21#include <linux/err.h>
  22#include <linux/clk.h>
  23#include <linux/io.h>
  24#include <linux/pm_runtime.h>
  25#include <linux/of.h>
  26#include <linux/pinctrl/consumer.h>
  27
  28#define DRIVER_NAME "nmk-i2c"
  29
  30/* I2C Controller register offsets */
  31#define I2C_CR          (0x000)
  32#define I2C_SCR         (0x004)
  33#define I2C_HSMCR       (0x008)
  34#define I2C_MCR         (0x00C)
  35#define I2C_TFR         (0x010)
  36#define I2C_SR          (0x014)
  37#define I2C_RFR         (0x018)
  38#define I2C_TFTR        (0x01C)
  39#define I2C_RFTR        (0x020)
  40#define I2C_DMAR        (0x024)
  41#define I2C_BRCR        (0x028)
  42#define I2C_IMSCR       (0x02C)
  43#define I2C_RISR        (0x030)
  44#define I2C_MISR        (0x034)
  45#define I2C_ICR         (0x038)
  46
  47/* Control registers */
  48#define I2C_CR_PE               (0x1 << 0)      /* Peripheral Enable */
  49#define I2C_CR_OM               (0x3 << 1)      /* Operating mode */
  50#define I2C_CR_SAM              (0x1 << 3)      /* Slave addressing mode */
  51#define I2C_CR_SM               (0x3 << 4)      /* Speed mode */
  52#define I2C_CR_SGCM             (0x1 << 6)      /* Slave general call mode */
  53#define I2C_CR_FTX              (0x1 << 7)      /* Flush Transmit */
  54#define I2C_CR_FRX              (0x1 << 8)      /* Flush Receive */
  55#define I2C_CR_DMA_TX_EN        (0x1 << 9)      /* DMA Tx enable */
  56#define I2C_CR_DMA_RX_EN        (0x1 << 10)     /* DMA Rx Enable */
  57#define I2C_CR_DMA_SLE          (0x1 << 11)     /* DMA sync. logic enable */
  58#define I2C_CR_LM               (0x1 << 12)     /* Loopback mode */
  59#define I2C_CR_FON              (0x3 << 13)     /* Filtering on */
  60#define I2C_CR_FS               (0x3 << 15)     /* Force stop enable */
  61
  62/* Master controller (MCR) register */
  63#define I2C_MCR_OP              (0x1 << 0)      /* Operation */
  64#define I2C_MCR_A7              (0x7f << 1)     /* 7-bit address */
  65#define I2C_MCR_EA10            (0x7 << 8)      /* 10-bit Extended address */
  66#define I2C_MCR_SB              (0x1 << 11)     /* Extended address */
  67#define I2C_MCR_AM              (0x3 << 12)     /* Address type */
  68#define I2C_MCR_STOP            (0x1 << 14)     /* Stop condition */
  69#define I2C_MCR_LENGTH          (0x7ff << 15)   /* Transaction length */
  70
  71/* Status register (SR) */
  72#define I2C_SR_OP               (0x3 << 0)      /* Operation */
  73#define I2C_SR_STATUS           (0x3 << 2)      /* controller status */
  74#define I2C_SR_CAUSE            (0x7 << 4)      /* Abort cause */
  75#define I2C_SR_TYPE             (0x3 << 7)      /* Receive type */
  76#define I2C_SR_LENGTH           (0x7ff << 9)    /* Transfer length */
  77
  78/* Interrupt mask set/clear (IMSCR) bits */
  79#define I2C_IT_TXFE             (0x1 << 0)
  80#define I2C_IT_TXFNE            (0x1 << 1)
  81#define I2C_IT_TXFF             (0x1 << 2)
  82#define I2C_IT_TXFOVR           (0x1 << 3)
  83#define I2C_IT_RXFE             (0x1 << 4)
  84#define I2C_IT_RXFNF            (0x1 << 5)
  85#define I2C_IT_RXFF             (0x1 << 6)
  86#define I2C_IT_RFSR             (0x1 << 16)
  87#define I2C_IT_RFSE             (0x1 << 17)
  88#define I2C_IT_WTSR             (0x1 << 18)
  89#define I2C_IT_MTD              (0x1 << 19)
  90#define I2C_IT_STD              (0x1 << 20)
  91#define I2C_IT_MAL              (0x1 << 24)
  92#define I2C_IT_BERR             (0x1 << 25)
  93#define I2C_IT_MTDWS            (0x1 << 28)
  94
  95#define GEN_MASK(val, mask, sb)  (((val) << (sb)) & (mask))
  96
  97/* some bits in ICR are reserved */
  98#define I2C_CLEAR_ALL_INTS      0x131f007f
  99
 100/* first three msb bits are reserved */
 101#define IRQ_MASK(mask)          (mask & 0x1fffffff)
 102
 103/* maximum threshold value */
 104#define MAX_I2C_FIFO_THRESHOLD  15
 105
 106enum i2c_freq_mode {
 107        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
 108        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
 109        I2C_FREQ_MODE_HIGH_SPEED,       /* up to 3.4 Mb/s */
 110        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
 111};
 112
 113/**
 114 * struct i2c_vendor_data - per-vendor variations
 115 * @has_mtdws: variant has the MTDWS bit
 116 * @fifodepth: variant FIFO depth
 117 */
 118struct i2c_vendor_data {
 119        bool has_mtdws;
 120        u32 fifodepth;
 121};
 122
 123enum i2c_status {
 124        I2C_NOP,
 125        I2C_ON_GOING,
 126        I2C_OK,
 127        I2C_ABORT
 128};
 129
 130/* operation */
 131enum i2c_operation {
 132        I2C_NO_OPERATION = 0xff,
 133        I2C_WRITE = 0x00,
 134        I2C_READ = 0x01
 135};
 136
 137/**
 138 * struct i2c_nmk_client - client specific data
 139 * @slave_adr: 7-bit slave address
 140 * @count: no. bytes to be transferred
 141 * @buffer: client data buffer
 142 * @xfer_bytes: bytes transferred till now
 143 * @operation: current I2C operation
 144 */
 145struct i2c_nmk_client {
 146        unsigned short          slave_adr;
 147        unsigned long           count;
 148        unsigned char           *buffer;
 149        unsigned long           xfer_bytes;
 150        enum i2c_operation      operation;
 151};
 152
 153/**
 154 * struct nmk_i2c_dev - private data structure of the controller.
 155 * @vendor: vendor data for this variant.
 156 * @adev: parent amba device.
 157 * @adap: corresponding I2C adapter.
 158 * @irq: interrupt line for the controller.
 159 * @virtbase: virtual io memory area.
 160 * @clk: hardware i2c block clock.
 161 * @cli: holder of client specific data.
 162 * @clk_freq: clock frequency for the operation mode
 163 * @tft: Tx FIFO Threshold in bytes
 164 * @rft: Rx FIFO Threshold in bytes
 165 * @timeout Slave response timeout (ms)
 166 * @sm: speed mode
 167 * @stop: stop condition.
 168 * @xfer_complete: acknowledge completion for a I2C message.
 169 * @result: controller propogated result.
 170 */
 171struct nmk_i2c_dev {
 172        struct i2c_vendor_data          *vendor;
 173        struct amba_device              *adev;
 174        struct i2c_adapter              adap;
 175        int                             irq;
 176        void __iomem                    *virtbase;
 177        struct clk                      *clk;
 178        struct i2c_nmk_client           cli;
 179        u32                             clk_freq;
 180        unsigned char                   tft;
 181        unsigned char                   rft;
 182        int                             timeout;
 183        enum i2c_freq_mode              sm;
 184        int                             stop;
 185        struct completion               xfer_complete;
 186        int                             result;
 187};
 188
 189/* controller's abort causes */
 190static const char *abort_causes[] = {
 191        "no ack received after address transmission",
 192        "no ack received during data phase",
 193        "ack received after xmission of master code",
 194        "master lost arbitration",
 195        "slave restarts",
 196        "slave reset",
 197        "overflow, maxsize is 2047 bytes",
 198};
 199
 200static inline void i2c_set_bit(void __iomem *reg, u32 mask)
 201{
 202        writel(readl(reg) | mask, reg);
 203}
 204
 205static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
 206{
 207        writel(readl(reg) & ~mask, reg);
 208}
 209
 210/**
 211 * flush_i2c_fifo() - This function flushes the I2C FIFO
 212 * @dev: private data of I2C Driver
 213 *
 214 * This function flushes the I2C Tx and Rx FIFOs. It returns
 215 * 0 on successful flushing of FIFO
 216 */
 217static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
 218{
 219#define LOOP_ATTEMPTS 10
 220        int i;
 221        unsigned long timeout;
 222
 223        /*
 224         * flush the transmit and receive FIFO. The flushing
 225         * operation takes several cycles before to be completed.
 226         * On the completion, the I2C internal logic clears these
 227         * bits, until then no one must access Tx, Rx FIFO and
 228         * should poll on these bits waiting for the completion.
 229         */
 230        writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
 231
 232        for (i = 0; i < LOOP_ATTEMPTS; i++) {
 233                timeout = jiffies + dev->adap.timeout;
 234
 235                while (!time_after(jiffies, timeout)) {
 236                        if ((readl(dev->virtbase + I2C_CR) &
 237                                (I2C_CR_FTX | I2C_CR_FRX)) == 0)
 238                                        return 0;
 239                }
 240        }
 241
 242        dev_err(&dev->adev->dev,
 243                "flushing operation timed out giving up after %d attempts",
 244                LOOP_ATTEMPTS);
 245
 246        return -ETIMEDOUT;
 247}
 248
 249/**
 250 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
 251 * @dev: private data of I2C Driver
 252 */
 253static void disable_all_interrupts(struct nmk_i2c_dev *dev)
 254{
 255        u32 mask = IRQ_MASK(0);
 256        writel(mask, dev->virtbase + I2C_IMSCR);
 257}
 258
 259/**
 260 * clear_all_interrupts() - Clear all interrupts of I2C Controller
 261 * @dev: private data of I2C Driver
 262 */
 263static void clear_all_interrupts(struct nmk_i2c_dev *dev)
 264{
 265        u32 mask;
 266        mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
 267        writel(mask, dev->virtbase + I2C_ICR);
 268}
 269
 270/**
 271 * init_hw() - initialize the I2C hardware
 272 * @dev: private data of I2C Driver
 273 */
 274static int init_hw(struct nmk_i2c_dev *dev)
 275{
 276        int stat;
 277
 278        stat = flush_i2c_fifo(dev);
 279        if (stat)
 280                goto exit;
 281
 282        /* disable the controller */
 283        i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
 284
 285        disable_all_interrupts(dev);
 286
 287        clear_all_interrupts(dev);
 288
 289        dev->cli.operation = I2C_NO_OPERATION;
 290
 291exit:
 292        return stat;
 293}
 294
 295/* enable peripheral, master mode operation */
 296#define DEFAULT_I2C_REG_CR      ((1 << 1) | I2C_CR_PE)
 297
 298/**
 299 * load_i2c_mcr_reg() - load the MCR register
 300 * @dev: private data of controller
 301 * @flags: message flags
 302 */
 303static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
 304{
 305        u32 mcr = 0;
 306        unsigned short slave_adr_3msb_bits;
 307
 308        mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
 309
 310        if (unlikely(flags & I2C_M_TEN)) {
 311                /* 10-bit address transaction */
 312                mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
 313                /*
 314                 * Get the top 3 bits.
 315                 * EA10 represents extended address in MCR. This includes
 316                 * the extension (MSB bits) of the 7 bit address loaded
 317                 * in A7
 318                 */
 319                slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
 320
 321                mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
 322        } else {
 323                /* 7-bit address transaction */
 324                mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
 325        }
 326
 327        /* start byte procedure not applied */
 328        mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
 329
 330        /* check the operation, master read/write? */
 331        if (dev->cli.operation == I2C_WRITE)
 332                mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
 333        else
 334                mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
 335
 336        /* stop or repeated start? */
 337        if (dev->stop)
 338                mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
 339        else
 340                mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
 341
 342        mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
 343
 344        return mcr;
 345}
 346
 347/**
 348 * setup_i2c_controller() - setup the controller
 349 * @dev: private data of controller
 350 */
 351static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 352{
 353        u32 brcr1, brcr2;
 354        u32 i2c_clk, div;
 355        u32 ns;
 356        u16 slsu;
 357
 358        writel(0x0, dev->virtbase + I2C_CR);
 359        writel(0x0, dev->virtbase + I2C_HSMCR);
 360        writel(0x0, dev->virtbase + I2C_TFTR);
 361        writel(0x0, dev->virtbase + I2C_RFTR);
 362        writel(0x0, dev->virtbase + I2C_DMAR);
 363
 364        i2c_clk = clk_get_rate(dev->clk);
 365
 366        /*
 367         * set the slsu:
 368         *
 369         * slsu defines the data setup time after SCL clock
 370         * stretching in terms of i2c clk cycles + 1 (zero means
 371         * "wait one cycle"), the needed setup time for the three
 372         * modes are 250ns, 100ns, 10ns respectively.
 373         *
 374         * As the time for one cycle T in nanoseconds is
 375         * T = (1/f) * 1000000000 =>
 376         * slsu = cycles / (1000000000 / f) + 1
 377         */
 378        ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
 379        switch (dev->sm) {
 380        case I2C_FREQ_MODE_FAST:
 381        case I2C_FREQ_MODE_FAST_PLUS:
 382                slsu = DIV_ROUND_UP(100, ns); /* Fast */
 383                break;
 384        case I2C_FREQ_MODE_HIGH_SPEED:
 385                slsu = DIV_ROUND_UP(10, ns); /* High */
 386                break;
 387        case I2C_FREQ_MODE_STANDARD:
 388        default:
 389                slsu = DIV_ROUND_UP(250, ns); /* Standard */
 390                break;
 391        }
 392        slsu += 1;
 393
 394        dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
 395        writel(slsu << 16, dev->virtbase + I2C_SCR);
 396
 397        /*
 398         * The spec says, in case of std. mode the divider is
 399         * 2 whereas it is 3 for fast and fastplus mode of
 400         * operation. TODO - high speed support.
 401         */
 402        div = (dev->clk_freq > 100000) ? 3 : 2;
 403
 404        /*
 405         * generate the mask for baud rate counters. The controller
 406         * has two baud rate counters. One is used for High speed
 407         * operation, and the other is for std, fast mode, fast mode
 408         * plus operation. Currently we do not supprt high speed mode
 409         * so set brcr1 to 0.
 410         */
 411        brcr1 = 0 << 16;
 412        brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
 413
 414        /* set the baud rate counter register */
 415        writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
 416
 417        /*
 418         * set the speed mode. Currently we support
 419         * only standard and fast mode of operation
 420         * TODO - support for fast mode plus (up to 1Mb/s)
 421         * and high speed (up to 3.4 Mb/s)
 422         */
 423        if (dev->sm > I2C_FREQ_MODE_FAST) {
 424                dev_err(&dev->adev->dev,
 425                        "do not support this mode defaulting to std. mode\n");
 426                brcr2 = i2c_clk/(100000 * 2) & 0xffff;
 427                writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
 428                writel(I2C_FREQ_MODE_STANDARD << 4,
 429                                dev->virtbase + I2C_CR);
 430        }
 431        writel(dev->sm << 4, dev->virtbase + I2C_CR);
 432
 433        /* set the Tx and Rx FIFO threshold */
 434        writel(dev->tft, dev->virtbase + I2C_TFTR);
 435        writel(dev->rft, dev->virtbase + I2C_RFTR);
 436}
 437
 438/**
 439 * read_i2c() - Read from I2C client device
 440 * @dev: private data of I2C Driver
 441 * @flags: message flags
 442 *
 443 * This function reads from i2c client device when controller is in
 444 * master mode. There is a completion timeout. If there is no transfer
 445 * before timeout error is returned.
 446 */
 447static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
 448{
 449        int status = 0;
 450        u32 mcr, irq_mask;
 451        unsigned long timeout;
 452
 453        mcr = load_i2c_mcr_reg(dev, flags);
 454        writel(mcr, dev->virtbase + I2C_MCR);
 455
 456        /* load the current CR value */
 457        writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 458                        dev->virtbase + I2C_CR);
 459
 460        /* enable the controller */
 461        i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
 462
 463        init_completion(&dev->xfer_complete);
 464
 465        /* enable interrupts by setting the mask */
 466        irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
 467                        I2C_IT_MAL | I2C_IT_BERR);
 468
 469        if (dev->stop || !dev->vendor->has_mtdws)
 470                irq_mask |= I2C_IT_MTD;
 471        else
 472                irq_mask |= I2C_IT_MTDWS;
 473
 474        irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
 475
 476        writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
 477                        dev->virtbase + I2C_IMSCR);
 478
 479        timeout = wait_for_completion_timeout(
 480                &dev->xfer_complete, dev->adap.timeout);
 481
 482        if (timeout == 0) {
 483                /* Controller timed out */
 484                dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
 485                                dev->cli.slave_adr);
 486                status = -ETIMEDOUT;
 487        }
 488        return status;
 489}
 490
 491static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
 492{
 493        int count;
 494
 495        for (count = (no_bytes - 2);
 496                        (count > 0) &&
 497                        (dev->cli.count != 0);
 498                        count--) {
 499                /* write to the Tx FIFO */
 500                writeb(*dev->cli.buffer,
 501                        dev->virtbase + I2C_TFR);
 502                dev->cli.buffer++;
 503                dev->cli.count--;
 504                dev->cli.xfer_bytes++;
 505        }
 506
 507}
 508
 509/**
 510 * write_i2c() - Write data to I2C client.
 511 * @dev: private data of I2C Driver
 512 * @flags: message flags
 513 *
 514 * This function writes data to I2C client
 515 */
 516static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
 517{
 518        u32 status = 0;
 519        u32 mcr, irq_mask;
 520        unsigned long timeout;
 521
 522        mcr = load_i2c_mcr_reg(dev, flags);
 523
 524        writel(mcr, dev->virtbase + I2C_MCR);
 525
 526        /* load the current CR value */
 527        writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 528                        dev->virtbase + I2C_CR);
 529
 530        /* enable the controller */
 531        i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
 532
 533        init_completion(&dev->xfer_complete);
 534
 535        /* enable interrupts by settings the masks */
 536        irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
 537
 538        /* Fill the TX FIFO with transmit data */
 539        fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
 540
 541        if (dev->cli.count != 0)
 542                irq_mask |= I2C_IT_TXFNE;
 543
 544        /*
 545         * check if we want to transfer a single or multiple bytes, if so
 546         * set the MTDWS bit (Master Transaction Done Without Stop)
 547         * to start repeated start operation
 548         */
 549        if (dev->stop || !dev->vendor->has_mtdws)
 550                irq_mask |= I2C_IT_MTD;
 551        else
 552                irq_mask |= I2C_IT_MTDWS;
 553
 554        irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
 555
 556        writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
 557                        dev->virtbase + I2C_IMSCR);
 558
 559        timeout = wait_for_completion_timeout(
 560                &dev->xfer_complete, dev->adap.timeout);
 561
 562        if (timeout == 0) {
 563                /* Controller timed out */
 564                dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
 565                                dev->cli.slave_adr);
 566                status = -ETIMEDOUT;
 567        }
 568
 569        return status;
 570}
 571
 572/**
 573 * nmk_i2c_xfer_one() - transmit a single I2C message
 574 * @dev: device with a message encoded into it
 575 * @flags: message flags
 576 */
 577static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
 578{
 579        int status;
 580
 581        if (flags & I2C_M_RD) {
 582                /* read operation */
 583                dev->cli.operation = I2C_READ;
 584                status = read_i2c(dev, flags);
 585        } else {
 586                /* write operation */
 587                dev->cli.operation = I2C_WRITE;
 588                status = write_i2c(dev, flags);
 589        }
 590
 591        if (status || (dev->result)) {
 592                u32 i2c_sr;
 593                u32 cause;
 594
 595                i2c_sr = readl(dev->virtbase + I2C_SR);
 596                /*
 597                 * Check if the controller I2C operation status
 598                 * is set to ABORT(11b).
 599                 */
 600                if (((i2c_sr >> 2) & 0x3) == 0x3) {
 601                        /* get the abort cause */
 602                        cause = (i2c_sr >> 4) & 0x7;
 603                        dev_err(&dev->adev->dev, "%s\n",
 604                                cause >= ARRAY_SIZE(abort_causes) ?
 605                                "unknown reason" :
 606                                abort_causes[cause]);
 607                }
 608
 609                (void) init_hw(dev);
 610
 611                status = status ? status : dev->result;
 612        }
 613
 614        return status;
 615}
 616
 617/**
 618 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
 619 * @i2c_adap: Adapter pointer to the controller
 620 * @msgs: Pointer to data to be written.
 621 * @num_msgs: Number of messages to be executed
 622 *
 623 * This is the function called by the generic kernel i2c_transfer()
 624 * or i2c_smbus...() API calls. Note that this code is protected by the
 625 * semaphore set in the kernel i2c_transfer() function.
 626 *
 627 * NOTE:
 628 * READ TRANSFER : We impose a restriction of the first message to be the
 629 *              index message for any read transaction.
 630 *              - a no index is coded as '0',
 631 *              - 2byte big endian index is coded as '3'
 632 *              !!! msg[0].buf holds the actual index.
 633 *              This is compatible with generic messages of smbus emulator
 634 *              that send a one byte index.
 635 *              eg. a I2C transation to read 2 bytes from index 0
 636 *                      idx = 0;
 637 *                      msg[0].addr = client->addr;
 638 *                      msg[0].flags = 0x0;
 639 *                      msg[0].len = 1;
 640 *                      msg[0].buf = &idx;
 641 *
 642 *                      msg[1].addr = client->addr;
 643 *                      msg[1].flags = I2C_M_RD;
 644 *                      msg[1].len = 2;
 645 *                      msg[1].buf = rd_buff
 646 *                      i2c_transfer(adap, msg, 2);
 647 *
 648 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
 649 *              If you want to emulate an SMBUS write transaction put the
 650 *              index as first byte(or first and second) in the payload.
 651 *              eg. a I2C transation to write 2 bytes from index 1
 652 *                      wr_buff[0] = 0x1;
 653 *                      wr_buff[1] = 0x23;
 654 *                      wr_buff[2] = 0x46;
 655 *                      msg[0].flags = 0x0;
 656 *                      msg[0].len = 3;
 657 *                      msg[0].buf = wr_buff;
 658 *                      i2c_transfer(adap, msg, 1);
 659 *
 660 * To read or write a block of data (multiple bytes) using SMBUS emulation
 661 * please use the i2c_smbus_read_i2c_block_data()
 662 * or i2c_smbus_write_i2c_block_data() API
 663 */
 664static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
 665                struct i2c_msg msgs[], int num_msgs)
 666{
 667        int status = 0;
 668        int i;
 669        struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
 670        int j;
 671
 672        pm_runtime_get_sync(&dev->adev->dev);
 673
 674        /* Attempt three times to send the message queue */
 675        for (j = 0; j < 3; j++) {
 676                /* setup the i2c controller */
 677                setup_i2c_controller(dev);
 678
 679                for (i = 0; i < num_msgs; i++) {
 680                        dev->cli.slave_adr      = msgs[i].addr;
 681                        dev->cli.buffer         = msgs[i].buf;
 682                        dev->cli.count          = msgs[i].len;
 683                        dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
 684                        dev->result = 0;
 685
 686                        status = nmk_i2c_xfer_one(dev, msgs[i].flags);
 687                        if (status != 0)
 688                                break;
 689                }
 690                if (status == 0)
 691                        break;
 692        }
 693
 694        pm_runtime_put_sync(&dev->adev->dev);
 695
 696        /* return the no. messages processed */
 697        if (status)
 698                return status;
 699        else
 700                return num_msgs;
 701}
 702
 703/**
 704 * disable_interrupts() - disable the interrupts
 705 * @dev: private data of controller
 706 * @irq: interrupt number
 707 */
 708static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
 709{
 710        irq = IRQ_MASK(irq);
 711        writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
 712                        dev->virtbase + I2C_IMSCR);
 713        return 0;
 714}
 715
 716/**
 717 * i2c_irq_handler() - interrupt routine
 718 * @irq: interrupt number
 719 * @arg: data passed to the handler
 720 *
 721 * This is the interrupt handler for the i2c driver. Currently
 722 * it handles the major interrupts like Rx & Tx FIFO management
 723 * interrupts, master transaction interrupts, arbitration and
 724 * bus error interrupts. The rest of the interrupts are treated as
 725 * unhandled.
 726 */
 727static irqreturn_t i2c_irq_handler(int irq, void *arg)
 728{
 729        struct nmk_i2c_dev *dev = arg;
 730        u32 tft, rft;
 731        u32 count;
 732        u32 misr, src;
 733
 734        /* load Tx FIFO and Rx FIFO threshold values */
 735        tft = readl(dev->virtbase + I2C_TFTR);
 736        rft = readl(dev->virtbase + I2C_RFTR);
 737
 738        /* read interrupt status register */
 739        misr = readl(dev->virtbase + I2C_MISR);
 740
 741        src = __ffs(misr);
 742        switch ((1 << src)) {
 743
 744        /* Transmit FIFO nearly empty interrupt */
 745        case I2C_IT_TXFNE:
 746        {
 747                if (dev->cli.operation == I2C_READ) {
 748                        /*
 749                         * in read operation why do we care for writing?
 750                         * so disable the Transmit FIFO interrupt
 751                         */
 752                        disable_interrupts(dev, I2C_IT_TXFNE);
 753                } else {
 754                        fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
 755                        /*
 756                         * if done, close the transfer by disabling the
 757                         * corresponding TXFNE interrupt
 758                         */
 759                        if (dev->cli.count == 0)
 760                                disable_interrupts(dev, I2C_IT_TXFNE);
 761                }
 762        }
 763        break;
 764
 765        /*
 766         * Rx FIFO nearly full interrupt.
 767         * This is set when the numer of entries in Rx FIFO is
 768         * greater or equal than the threshold value programmed
 769         * in RFT
 770         */
 771        case I2C_IT_RXFNF:
 772                for (count = rft; count > 0; count--) {
 773                        /* Read the Rx FIFO */
 774                        *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
 775                        dev->cli.buffer++;
 776                }
 777                dev->cli.count -= rft;
 778                dev->cli.xfer_bytes += rft;
 779                break;
 780
 781        /* Rx FIFO full */
 782        case I2C_IT_RXFF:
 783                for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
 784                        *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
 785                        dev->cli.buffer++;
 786                }
 787                dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
 788                dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
 789                break;
 790
 791        /* Master Transaction Done with/without stop */
 792        case I2C_IT_MTD:
 793        case I2C_IT_MTDWS:
 794                if (dev->cli.operation == I2C_READ) {
 795                        while (!(readl(dev->virtbase + I2C_RISR)
 796                                 & I2C_IT_RXFE)) {
 797                                if (dev->cli.count == 0)
 798                                        break;
 799                                *dev->cli.buffer =
 800                                        readb(dev->virtbase + I2C_RFR);
 801                                dev->cli.buffer++;
 802                                dev->cli.count--;
 803                                dev->cli.xfer_bytes++;
 804                        }
 805                }
 806
 807                disable_all_interrupts(dev);
 808                clear_all_interrupts(dev);
 809
 810                if (dev->cli.count) {
 811                        dev->result = -EIO;
 812                        dev_err(&dev->adev->dev,
 813                                "%lu bytes still remain to be xfered\n",
 814                                dev->cli.count);
 815                        (void) init_hw(dev);
 816                }
 817                complete(&dev->xfer_complete);
 818
 819                break;
 820
 821        /* Master Arbitration lost interrupt */
 822        case I2C_IT_MAL:
 823                dev->result = -EIO;
 824                (void) init_hw(dev);
 825
 826                i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
 827                complete(&dev->xfer_complete);
 828
 829                break;
 830
 831        /*
 832         * Bus Error interrupt.
 833         * This happens when an unexpected start/stop condition occurs
 834         * during the transaction.
 835         */
 836        case I2C_IT_BERR:
 837                dev->result = -EIO;
 838                /* get the status */
 839                if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
 840                        (void) init_hw(dev);
 841
 842                i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
 843                complete(&dev->xfer_complete);
 844
 845                break;
 846
 847        /*
 848         * Tx FIFO overrun interrupt.
 849         * This is set when a write operation in Tx FIFO is performed and
 850         * the Tx FIFO is full.
 851         */
 852        case I2C_IT_TXFOVR:
 853                dev->result = -EIO;
 854                (void) init_hw(dev);
 855
 856                dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
 857                complete(&dev->xfer_complete);
 858
 859                break;
 860
 861        /* unhandled interrupts by this driver - TODO*/
 862        case I2C_IT_TXFE:
 863        case I2C_IT_TXFF:
 864        case I2C_IT_RXFE:
 865        case I2C_IT_RFSR:
 866        case I2C_IT_RFSE:
 867        case I2C_IT_WTSR:
 868        case I2C_IT_STD:
 869                dev_err(&dev->adev->dev, "unhandled Interrupt\n");
 870                break;
 871        default:
 872                dev_err(&dev->adev->dev, "spurious Interrupt..\n");
 873                break;
 874        }
 875
 876        return IRQ_HANDLED;
 877}
 878
 879#ifdef CONFIG_PM_SLEEP
 880static int nmk_i2c_suspend_late(struct device *dev)
 881{
 882        int ret;
 883
 884        ret = pm_runtime_force_suspend(dev);
 885        if (ret)
 886                return ret;
 887
 888        pinctrl_pm_select_sleep_state(dev);
 889        return 0;
 890}
 891
 892static int nmk_i2c_resume_early(struct device *dev)
 893{
 894        return pm_runtime_force_resume(dev);
 895}
 896#endif
 897
 898#ifdef CONFIG_PM
 899static int nmk_i2c_runtime_suspend(struct device *dev)
 900{
 901        struct amba_device *adev = to_amba_device(dev);
 902        struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
 903
 904        clk_disable_unprepare(nmk_i2c->clk);
 905        pinctrl_pm_select_idle_state(dev);
 906        return 0;
 907}
 908
 909static int nmk_i2c_runtime_resume(struct device *dev)
 910{
 911        struct amba_device *adev = to_amba_device(dev);
 912        struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
 913        int ret;
 914
 915        ret = clk_prepare_enable(nmk_i2c->clk);
 916        if (ret) {
 917                dev_err(dev, "can't prepare_enable clock\n");
 918                return ret;
 919        }
 920
 921        pinctrl_pm_select_default_state(dev);
 922
 923        ret = init_hw(nmk_i2c);
 924        if (ret) {
 925                clk_disable_unprepare(nmk_i2c->clk);
 926                pinctrl_pm_select_idle_state(dev);
 927        }
 928
 929        return ret;
 930}
 931#endif
 932
 933static const struct dev_pm_ops nmk_i2c_pm = {
 934        SET_LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
 935        SET_RUNTIME_PM_OPS(nmk_i2c_runtime_suspend,
 936                        nmk_i2c_runtime_resume,
 937                        NULL)
 938};
 939
 940static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
 941{
 942        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 943}
 944
 945static const struct i2c_algorithm nmk_i2c_algo = {
 946        .master_xfer    = nmk_i2c_xfer,
 947        .functionality  = nmk_i2c_functionality
 948};
 949
 950static void nmk_i2c_of_probe(struct device_node *np,
 951                             struct nmk_i2c_dev *nmk)
 952{
 953        /* Default to 100 kHz if no frequency is given in the node */
 954        if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
 955                nmk->clk_freq = 100000;
 956
 957        /* This driver only supports 'standard' and 'fast' modes of operation. */
 958        if (nmk->clk_freq <= 100000)
 959                nmk->sm = I2C_FREQ_MODE_STANDARD;
 960        else
 961                nmk->sm = I2C_FREQ_MODE_FAST;
 962        nmk->tft = 1; /* Tx FIFO threshold */
 963        nmk->rft = 8; /* Rx FIFO threshold */
 964        nmk->timeout = 200; /* Slave response timeout(ms) */
 965}
 966
 967static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 968{
 969        int ret = 0;
 970        struct device_node *np = adev->dev.of_node;
 971        struct nmk_i2c_dev      *dev;
 972        struct i2c_adapter *adap;
 973        struct i2c_vendor_data *vendor = id->data;
 974        u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
 975
 976        dev = devm_kzalloc(&adev->dev, sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 977        if (!dev) {
 978                dev_err(&adev->dev, "cannot allocate memory\n");
 979                ret = -ENOMEM;
 980                goto err_no_mem;
 981        }
 982        dev->vendor = vendor;
 983        dev->adev = adev;
 984        nmk_i2c_of_probe(np, dev);
 985
 986        if (dev->tft > max_fifo_threshold) {
 987                dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
 988                         dev->tft, max_fifo_threshold);
 989                dev->tft = max_fifo_threshold;
 990        }
 991
 992        if (dev->rft > max_fifo_threshold) {
 993                dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
 994                        dev->rft, max_fifo_threshold);
 995                dev->rft = max_fifo_threshold;
 996        }
 997
 998        amba_set_drvdata(adev, dev);
 999
1000        dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
1001                                resource_size(&adev->res));
1002        if (!dev->virtbase) {
1003                ret = -ENOMEM;
1004                goto err_no_mem;
1005        }
1006
1007        dev->irq = adev->irq[0];
1008        ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
1009                                DRIVER_NAME, dev);
1010        if (ret) {
1011                dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
1012                goto err_no_mem;
1013        }
1014
1015        pm_suspend_ignore_children(&adev->dev, true);
1016
1017        dev->clk = devm_clk_get(&adev->dev, NULL);
1018        if (IS_ERR(dev->clk)) {
1019                dev_err(&adev->dev, "could not get i2c clock\n");
1020                ret = PTR_ERR(dev->clk);
1021                goto err_no_mem;
1022        }
1023
1024        ret = clk_prepare_enable(dev->clk);
1025        if (ret) {
1026                dev_err(&adev->dev, "can't prepare_enable clock\n");
1027                goto err_no_mem;
1028        }
1029
1030        init_hw(dev);
1031
1032        adap = &dev->adap;
1033        adap->dev.of_node = np;
1034        adap->dev.parent = &adev->dev;
1035        adap->owner = THIS_MODULE;
1036        adap->class = I2C_CLASS_DEPRECATED;
1037        adap->algo = &nmk_i2c_algo;
1038        adap->timeout = msecs_to_jiffies(dev->timeout);
1039        snprintf(adap->name, sizeof(adap->name),
1040                 "Nomadik I2C at %pR", &adev->res);
1041
1042        i2c_set_adapdata(adap, dev);
1043
1044        dev_info(&adev->dev,
1045                 "initialize %s on virtual base %p\n",
1046                 adap->name, dev->virtbase);
1047
1048        ret = i2c_add_adapter(adap);
1049        if (ret)
1050                goto err_no_adap;
1051
1052        pm_runtime_put(&adev->dev);
1053
1054        return 0;
1055
1056 err_no_adap:
1057        clk_disable_unprepare(dev->clk);
1058 err_no_mem:
1059
1060        return ret;
1061}
1062
1063static int nmk_i2c_remove(struct amba_device *adev)
1064{
1065        struct resource *res = &adev->res;
1066        struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1067
1068        i2c_del_adapter(&dev->adap);
1069        flush_i2c_fifo(dev);
1070        disable_all_interrupts(dev);
1071        clear_all_interrupts(dev);
1072        /* disable the controller */
1073        i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1074        clk_disable_unprepare(dev->clk);
1075        if (res)
1076                release_mem_region(res->start, resource_size(res));
1077
1078        return 0;
1079}
1080
1081static struct i2c_vendor_data vendor_stn8815 = {
1082        .has_mtdws = false,
1083        .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1084};
1085
1086static struct i2c_vendor_data vendor_db8500 = {
1087        .has_mtdws = true,
1088        .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1089};
1090
1091static const struct amba_id nmk_i2c_ids[] = {
1092        {
1093                .id     = 0x00180024,
1094                .mask   = 0x00ffffff,
1095                .data   = &vendor_stn8815,
1096        },
1097        {
1098                .id     = 0x00380024,
1099                .mask   = 0x00ffffff,
1100                .data   = &vendor_db8500,
1101        },
1102        {},
1103};
1104
1105MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1106
1107static struct amba_driver nmk_i2c_driver = {
1108        .drv = {
1109                .owner = THIS_MODULE,
1110                .name = DRIVER_NAME,
1111                .pm = &nmk_i2c_pm,
1112        },
1113        .id_table = nmk_i2c_ids,
1114        .probe = nmk_i2c_probe,
1115        .remove = nmk_i2c_remove,
1116};
1117
1118static int __init nmk_i2c_init(void)
1119{
1120        return amba_driver_register(&nmk_i2c_driver);
1121}
1122
1123static void __exit nmk_i2c_exit(void)
1124{
1125        amba_driver_unregister(&nmk_i2c_driver);
1126}
1127
1128subsys_initcall(nmk_i2c_init);
1129module_exit(nmk_i2c_exit);
1130
1131MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1132MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1133MODULE_LICENSE("GPL");
1134