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16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/reset.h>
29
30#include "i2c-stm32.h"
31
32
33#define STM32F4_I2C_CR1 0x00
34#define STM32F4_I2C_CR2 0x04
35#define STM32F4_I2C_DR 0x10
36#define STM32F4_I2C_SR1 0x14
37#define STM32F4_I2C_SR2 0x18
38#define STM32F4_I2C_CCR 0x1C
39#define STM32F4_I2C_TRISE 0x20
40#define STM32F4_I2C_FLTR 0x24
41
42
43#define STM32F4_I2C_CR1_POS BIT(11)
44#define STM32F4_I2C_CR1_ACK BIT(10)
45#define STM32F4_I2C_CR1_STOP BIT(9)
46#define STM32F4_I2C_CR1_START BIT(8)
47#define STM32F4_I2C_CR1_PE BIT(0)
48
49
50#define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0)
51#define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK)
52#define STM32F4_I2C_CR2_ITBUFEN BIT(10)
53#define STM32F4_I2C_CR2_ITEVTEN BIT(9)
54#define STM32F4_I2C_CR2_ITERREN BIT(8)
55#define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \
56 STM32F4_I2C_CR2_ITEVTEN | \
57 STM32F4_I2C_CR2_ITERREN)
58
59
60#define STM32F4_I2C_SR1_AF BIT(10)
61#define STM32F4_I2C_SR1_ARLO BIT(9)
62#define STM32F4_I2C_SR1_BERR BIT(8)
63#define STM32F4_I2C_SR1_TXE BIT(7)
64#define STM32F4_I2C_SR1_RXNE BIT(6)
65#define STM32F4_I2C_SR1_BTF BIT(2)
66#define STM32F4_I2C_SR1_ADDR BIT(1)
67#define STM32F4_I2C_SR1_SB BIT(0)
68#define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \
69 STM32F4_I2C_SR1_ADDR | \
70 STM32F4_I2C_SR1_SB)
71#define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \
72 STM32F4_I2C_SR1_RXNE)
73#define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \
74 STM32F4_I2C_SR1_ARLO | \
75 STM32F4_I2C_SR1_BERR)
76
77
78#define STM32F4_I2C_SR2_BUSY BIT(1)
79
80
81#define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0)
82#define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK)
83#define STM32F4_I2C_CCR_FS BIT(15)
84#define STM32F4_I2C_CCR_DUTY BIT(14)
85
86
87#define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0)
88#define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK)
89
90#define STM32F4_I2C_MIN_STANDARD_FREQ 2U
91#define STM32F4_I2C_MIN_FAST_FREQ 6U
92#define STM32F4_I2C_MAX_FREQ 46U
93#define HZ_TO_MHZ 1000000
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102
103struct stm32f4_i2c_msg {
104 u8 addr;
105 u32 count;
106 u8 *buf;
107 int result;
108 bool stop;
109};
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121
122struct stm32f4_i2c_dev {
123 struct i2c_adapter adap;
124 struct device *dev;
125 void __iomem *base;
126 struct completion complete;
127 struct clk *clk;
128 int speed;
129 int parent_rate;
130 struct stm32f4_i2c_msg msg;
131};
132
133static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask)
134{
135 writel_relaxed(readl_relaxed(reg) | mask, reg);
136}
137
138static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask)
139{
140 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
141}
142
143static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev)
144{
145 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
146
147 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK);
148}
149
150static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
151{
152 u32 freq;
153 u32 cr2 = 0;
154
155 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
156 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
157
158 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
159
160
161
162
163
164 if (freq < STM32F4_I2C_MIN_STANDARD_FREQ ||
165 freq > STM32F4_I2C_MAX_FREQ) {
166 dev_err(i2c_dev->dev,
167 "bad parent clk freq for standard mode\n");
168 return -EINVAL;
169 }
170 } else {
171
172
173
174
175
176 if (freq < STM32F4_I2C_MIN_FAST_FREQ ||
177 freq > STM32F4_I2C_MAX_FREQ) {
178 dev_err(i2c_dev->dev,
179 "bad parent clk freq for fast mode\n");
180 return -EINVAL;
181 }
182 }
183
184 cr2 |= STM32F4_I2C_CR2_FREQ(freq);
185 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
186
187 return 0;
188}
189
190static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
191{
192 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
193 u32 trise;
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215 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
216 trise = freq + 1;
217 else
218 trise = freq * 3 / 10 + 1;
219
220 writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise),
221 i2c_dev->base + STM32F4_I2C_TRISE);
222}
223
224static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
225{
226 u32 val;
227 u32 ccr = 0;
228
229 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
230
231
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245 val = i2c_dev->parent_rate / (100000 << 1);
246 } else {
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265 val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3);
266
267
268 ccr |= STM32F4_I2C_CCR_FS;
269 }
270
271 ccr |= STM32F4_I2C_CCR_CCR(val);
272 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
273}
274
275
276
277
278
279static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev)
280{
281 int ret;
282
283 ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev);
284 if (ret)
285 return ret;
286
287 stm32f4_i2c_set_rise_time(i2c_dev);
288
289 stm32f4_i2c_set_speed_mode(i2c_dev);
290
291
292 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
293
294 return 0;
295}
296
297static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev)
298{
299 u32 status;
300 int ret;
301
302 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
303 status,
304 !(status & STM32F4_I2C_SR2_BUSY),
305 10, 1000);
306 if (ret) {
307 dev_dbg(i2c_dev->dev, "bus not free\n");
308 ret = -EBUSY;
309 }
310
311 return ret;
312}
313
314
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317
318
319static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte)
320{
321 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
322}
323
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327
328
329
330static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev)
331{
332 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
333
334 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++);
335 msg->count--;
336}
337
338static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev)
339{
340 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
341 u32 rbuf;
342
343 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR);
344 *msg->buf++ = rbuf;
345 msg->count--;
346}
347
348static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev)
349{
350 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
351 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
352
353 stm32f4_i2c_disable_irq(i2c_dev);
354
355 reg = i2c_dev->base + STM32F4_I2C_CR1;
356 if (msg->stop)
357 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
358 else
359 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
360
361 complete(&i2c_dev->complete);
362}
363
364
365
366
367
368static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev)
369{
370 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
371 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
372
373 if (msg->count) {
374 stm32f4_i2c_write_msg(i2c_dev);
375 if (!msg->count) {
376
377
378
379
380 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
381 }
382 } else {
383 stm32f4_i2c_terminate_xfer(i2c_dev);
384 }
385}
386
387
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390
391
392
393static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev)
394{
395 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
396 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
397
398 switch (msg->count) {
399 case 1:
400 stm32f4_i2c_disable_irq(i2c_dev);
401 stm32f4_i2c_read_msg(i2c_dev);
402 complete(&i2c_dev->complete);
403 break;
404
405
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407
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409
410
411
412 case 2:
413 case 3:
414 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
415 break;
416
417
418
419
420 default:
421 stm32f4_i2c_read_msg(i2c_dev);
422 }
423}
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431
432
433static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
434{
435 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
436 void __iomem *reg;
437 u32 mask;
438 int i;
439
440 switch (msg->count) {
441 case 2:
442
443
444
445
446
447
448
449
450 reg = i2c_dev->base + STM32F4_I2C_CR1;
451 if (msg->stop)
452 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
453 else
454 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
455
456 for (i = 2; i > 0; i--)
457 stm32f4_i2c_read_msg(i2c_dev);
458
459 reg = i2c_dev->base + STM32F4_I2C_CR2;
460 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
461 stm32f4_i2c_clr_bits(reg, mask);
462
463 complete(&i2c_dev->complete);
464 break;
465 case 3:
466
467
468
469
470
471 reg = i2c_dev->base + STM32F4_I2C_CR1;
472 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK);
473 stm32f4_i2c_read_msg(i2c_dev);
474 break;
475 default:
476 stm32f4_i2c_read_msg(i2c_dev);
477 }
478}
479
480
481
482
483
484
485static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev)
486{
487 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
488 u32 cr1;
489
490 switch (msg->count) {
491 case 0:
492 stm32f4_i2c_terminate_xfer(i2c_dev);
493
494
495 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
496 break;
497 case 1:
498
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501
502
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504
505 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
506 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS);
507 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
508
509 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
510
511 if (msg->stop)
512 cr1 |= STM32F4_I2C_CR1_STOP;
513 else
514 cr1 |= STM32F4_I2C_CR1_START;
515 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
516 break;
517 case 2:
518
519
520
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525 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
526 cr1 &= ~STM32F4_I2C_CR1_ACK;
527 cr1 |= STM32F4_I2C_CR1_POS;
528 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
529
530 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
531 break;
532
533 default:
534
535
536
537
538
539
540 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
541 cr1 |= STM32F4_I2C_CR1_ACK;
542 cr1 &= ~STM32F4_I2C_CR1_POS;
543 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
544
545 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
546 break;
547 }
548}
549
550
551
552
553
554
555static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data)
556{
557 struct stm32f4_i2c_dev *i2c_dev = data;
558 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
559 u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK;
560 u32 status, ien, event, cr2;
561
562 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2);
563 ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK;
564
565
566 if (ien & STM32F4_I2C_CR2_ITBUFEN)
567 possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK;
568
569 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
570 event = status & possible_status;
571 if (!event) {
572 dev_dbg(i2c_dev->dev,
573 "spurious evt irq (status=0x%08x, ien=0x%08x)\n",
574 status, ien);
575 return IRQ_NONE;
576 }
577
578
579 if (event & STM32F4_I2C_SR1_SB)
580 stm32f4_i2c_write_byte(i2c_dev, msg->addr);
581
582
583 if (event & STM32F4_I2C_SR1_ADDR) {
584 if (msg->addr & I2C_M_RD)
585 stm32f4_i2c_handle_rx_addr(i2c_dev);
586 else
587 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
588
589
590
591
592
593 cr2 |= STM32F4_I2C_CR2_ITBUFEN;
594 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
595 }
596
597
598 if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD))
599 stm32f4_i2c_handle_write(i2c_dev);
600
601
602 if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD))
603 stm32f4_i2c_handle_read(i2c_dev);
604
605
606
607
608
609
610
611
612 if (event & STM32F4_I2C_SR1_BTF) {
613 if (msg->addr & I2C_M_RD)
614 stm32f4_i2c_handle_rx_done(i2c_dev);
615 else
616 stm32f4_i2c_handle_write(i2c_dev);
617 }
618
619 return IRQ_HANDLED;
620}
621
622
623
624
625
626
627static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data)
628{
629 struct stm32f4_i2c_dev *i2c_dev = data;
630 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
631 void __iomem *reg;
632 u32 status;
633
634 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
635
636
637 if (status & STM32F4_I2C_SR1_ARLO) {
638 status &= ~STM32F4_I2C_SR1_ARLO;
639 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
640 msg->result = -EAGAIN;
641 }
642
643
644
645
646
647 if (status & STM32F4_I2C_SR1_AF) {
648 if (!(msg->addr & I2C_M_RD)) {
649 reg = i2c_dev->base + STM32F4_I2C_CR1;
650 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
651 }
652 status &= ~STM32F4_I2C_SR1_AF;
653 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
654 msg->result = -EIO;
655 }
656
657
658 if (status & STM32F4_I2C_SR1_BERR) {
659 status &= ~STM32F4_I2C_SR1_BERR;
660 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
661 msg->result = -EIO;
662 }
663
664 stm32f4_i2c_disable_irq(i2c_dev);
665 complete(&i2c_dev->complete);
666
667 return IRQ_HANDLED;
668}
669
670
671
672
673
674
675
676
677static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev,
678 struct i2c_msg *msg, bool is_first,
679 bool is_last)
680{
681 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg;
682 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1;
683 unsigned long timeout;
684 u32 mask;
685 int ret;
686
687 f4_msg->addr = i2c_8bit_addr_from_msg(msg);
688 f4_msg->buf = msg->buf;
689 f4_msg->count = msg->len;
690 f4_msg->result = 0;
691 f4_msg->stop = is_last;
692
693 reinit_completion(&i2c_dev->complete);
694
695
696 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
697 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask);
698
699 if (is_first) {
700 ret = stm32f4_i2c_wait_free_bus(i2c_dev);
701 if (ret)
702 return ret;
703
704
705 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
706 }
707
708 timeout = wait_for_completion_timeout(&i2c_dev->complete,
709 i2c_dev->adap.timeout);
710 ret = f4_msg->result;
711
712 if (!timeout)
713 ret = -ETIMEDOUT;
714
715 return ret;
716}
717
718
719
720
721
722
723
724static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
725 int num)
726{
727 struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
728 int ret, i;
729
730 ret = clk_enable(i2c_dev->clk);
731 if (ret) {
732 dev_err(i2c_dev->dev, "Failed to enable clock\n");
733 return ret;
734 }
735
736 for (i = 0; i < num && !ret; i++)
737 ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0,
738 i == num - 1);
739
740 clk_disable(i2c_dev->clk);
741
742 return (ret < 0) ? ret : num;
743}
744
745static u32 stm32f4_i2c_func(struct i2c_adapter *adap)
746{
747 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
748}
749
750static const struct i2c_algorithm stm32f4_i2c_algo = {
751 .master_xfer = stm32f4_i2c_xfer,
752 .functionality = stm32f4_i2c_func,
753};
754
755static int stm32f4_i2c_probe(struct platform_device *pdev)
756{
757 struct device_node *np = pdev->dev.of_node;
758 struct stm32f4_i2c_dev *i2c_dev;
759 struct resource *res;
760 u32 irq_event, irq_error, clk_rate;
761 struct i2c_adapter *adap;
762 struct reset_control *rst;
763 int ret;
764
765 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
766 if (!i2c_dev)
767 return -ENOMEM;
768
769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
771 if (IS_ERR(i2c_dev->base))
772 return PTR_ERR(i2c_dev->base);
773
774 irq_event = irq_of_parse_and_map(np, 0);
775 if (!irq_event) {
776 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
777 return -EINVAL;
778 }
779
780 irq_error = irq_of_parse_and_map(np, 1);
781 if (!irq_error) {
782 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
783 return -EINVAL;
784 }
785
786 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
787 if (IS_ERR(i2c_dev->clk)) {
788 dev_err(&pdev->dev, "Error: Missing controller clock\n");
789 return PTR_ERR(i2c_dev->clk);
790 }
791 ret = clk_prepare_enable(i2c_dev->clk);
792 if (ret) {
793 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
794 return ret;
795 }
796
797 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
798 if (IS_ERR(rst)) {
799 dev_err(&pdev->dev, "Error: Missing controller reset\n");
800 ret = PTR_ERR(rst);
801 goto clk_free;
802 }
803 reset_control_assert(rst);
804 udelay(2);
805 reset_control_deassert(rst);
806
807 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
808 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
809 if (!ret && clk_rate >= 400000)
810 i2c_dev->speed = STM32_I2C_SPEED_FAST;
811
812 i2c_dev->dev = &pdev->dev;
813
814 ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0,
815 pdev->name, i2c_dev);
816 if (ret) {
817 dev_err(&pdev->dev, "Failed to request irq event %i\n",
818 irq_event);
819 goto clk_free;
820 }
821
822 ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0,
823 pdev->name, i2c_dev);
824 if (ret) {
825 dev_err(&pdev->dev, "Failed to request irq error %i\n",
826 irq_error);
827 goto clk_free;
828 }
829
830 ret = stm32f4_i2c_hw_config(i2c_dev);
831 if (ret)
832 goto clk_free;
833
834 adap = &i2c_dev->adap;
835 i2c_set_adapdata(adap, i2c_dev);
836 snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start);
837 adap->owner = THIS_MODULE;
838 adap->timeout = 2 * HZ;
839 adap->retries = 0;
840 adap->algo = &stm32f4_i2c_algo;
841 adap->dev.parent = &pdev->dev;
842 adap->dev.of_node = pdev->dev.of_node;
843
844 init_completion(&i2c_dev->complete);
845
846 ret = i2c_add_adapter(adap);
847 if (ret)
848 goto clk_free;
849
850 platform_set_drvdata(pdev, i2c_dev);
851
852 clk_disable(i2c_dev->clk);
853
854 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n");
855
856 return 0;
857
858clk_free:
859 clk_disable_unprepare(i2c_dev->clk);
860 return ret;
861}
862
863static int stm32f4_i2c_remove(struct platform_device *pdev)
864{
865 struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
866
867 i2c_del_adapter(&i2c_dev->adap);
868
869 clk_unprepare(i2c_dev->clk);
870
871 return 0;
872}
873
874static const struct of_device_id stm32f4_i2c_match[] = {
875 { .compatible = "st,stm32f4-i2c", },
876 {},
877};
878MODULE_DEVICE_TABLE(of, stm32f4_i2c_match);
879
880static struct platform_driver stm32f4_i2c_driver = {
881 .driver = {
882 .name = "stm32f4-i2c",
883 .of_match_table = stm32f4_i2c_match,
884 },
885 .probe = stm32f4_i2c_probe,
886 .remove = stm32f4_i2c_remove,
887};
888
889module_platform_driver(stm32f4_i2c_driver);
890
891MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
892MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver");
893MODULE_LICENSE("GPL v2");
894