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24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
38#define MAX_WRITE_REGSIZE 16
39#define LOG2_E_100X 144
40
41#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
42
43
44enum sony_dvbc_constellation_t {
45 SONY_DVBC_CONSTELLATION_16QAM,
46 SONY_DVBC_CONSTELLATION_32QAM,
47 SONY_DVBC_CONSTELLATION_64QAM,
48 SONY_DVBC_CONSTELLATION_128QAM,
49 SONY_DVBC_CONSTELLATION_256QAM
50};
51
52enum cxd2841er_state {
53 STATE_SHUTDOWN = 0,
54 STATE_SLEEP_S,
55 STATE_ACTIVE_S,
56 STATE_SLEEP_TC,
57 STATE_ACTIVE_TC
58};
59
60struct cxd2841er_priv {
61 struct dvb_frontend frontend;
62 struct i2c_adapter *i2c;
63 u8 i2c_addr_slvx;
64 u8 i2c_addr_slvt;
65 const struct cxd2841er_config *config;
66 enum cxd2841er_state state;
67 u8 system;
68 enum cxd2841er_xtal xtal;
69 enum fe_caps caps;
70 u32 flags;
71};
72
73static const struct cxd2841er_cnr_data s_cn_data[] = {
74 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
75 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
76 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
77 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
78 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
79 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
80 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
81 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
82 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
83 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
84 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
85 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
86 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
87 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
88 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
89 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
90 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
91 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
92 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
93 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
94 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
95 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
96 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
97 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
98 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
99 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
100 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
101 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
102 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
103 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
104 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
105 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
106 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
107 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
108 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
109 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
110 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
111 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
112 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
113 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
114 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
115 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
116 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
117 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
118 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
119 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
120 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
121 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
122 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
123 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
124 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
125 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
126 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
127 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
128 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
129 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
130 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
131 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
132 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
133 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
134 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
135 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
136 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
137 { 0x0015, 19900 }, { 0x0014, 20000 },
138};
139
140static const struct cxd2841er_cnr_data s2_cn_data[] = {
141 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
142 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
143 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
144 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
145 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
146 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
147 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
148 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
149 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
150 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
151 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
152 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
153 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
154 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
155 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
156 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
157 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
158 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
159 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
160 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
161 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
162 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
163 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
164 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
165 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
166 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
167 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
168 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
169 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
170 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
171 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
172 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
173 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
174 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
175 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
176 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
177 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
178 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
179 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
180 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
181 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
182 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
183 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
184 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
185 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
186 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
187 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
188 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
189 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
190 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
191 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
192 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
193 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
194 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
195 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
196 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
197 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
198 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
199 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
200 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
201 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
202 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
203 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
204 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
205};
206
207static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
208static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
209
210static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, u8 write,
212 const u8 *data, u32 len)
213{
214 dev_dbg(&priv->i2c->dev,
215 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
216 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
217}
218
219static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
220 u8 addr, u8 reg, const u8 *data, u32 len)
221{
222 int ret;
223 u8 buf[MAX_WRITE_REGSIZE + 1];
224 u8 i2c_addr = (addr == I2C_SLVX ?
225 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
226 struct i2c_msg msg[1] = {
227 {
228 .addr = i2c_addr,
229 .flags = 0,
230 .len = len + 1,
231 .buf = buf,
232 }
233 };
234
235 if (len + 1 >= sizeof(buf)) {
236 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
237 reg, len + 1);
238 return -E2BIG;
239 }
240
241 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
242 buf[0] = reg;
243 memcpy(&buf[1], data, len);
244
245 ret = i2c_transfer(priv->i2c, msg, 1);
246 if (ret >= 0 && ret != 1)
247 ret = -EIO;
248 if (ret < 0) {
249 dev_warn(&priv->i2c->dev,
250 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
251 KBUILD_MODNAME, ret, i2c_addr, reg, len);
252 return ret;
253 }
254 return 0;
255}
256
257static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
258 u8 addr, u8 reg, u8 val)
259{
260 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
261}
262
263static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
264 u8 addr, u8 reg, u8 *val, u32 len)
265{
266 int ret;
267 u8 i2c_addr = (addr == I2C_SLVX ?
268 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
269 struct i2c_msg msg[2] = {
270 {
271 .addr = i2c_addr,
272 .flags = 0,
273 .len = 1,
274 .buf = ®,
275 }, {
276 .addr = i2c_addr,
277 .flags = I2C_M_RD,
278 .len = len,
279 .buf = val,
280 }
281 };
282
283 ret = i2c_transfer(priv->i2c, msg, 2);
284 if (ret >= 0 && ret != 2)
285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
293 return 0;
294}
295
296static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298{
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300}
301
302static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304{
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315}
316
317static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
318{
319 u64 tmp;
320
321 tmp = (u64) ifhz * 16777216;
322 do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
323
324 return (u32) tmp;
325}
326
327static u32 cxd2841er_calc_iffreq(u32 ifhz)
328{
329 return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
330}
331
332static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
333{
334 u32 hz;
335
336 if (priv->frontend.ops.tuner_ops.get_if_frequency
337 && (priv->flags & CXD2841ER_AUTO_IFHZ))
338 priv->frontend.ops.tuner_ops.get_if_frequency(
339 &priv->frontend, &hz);
340 else
341 hz = def_hz;
342
343 return hz;
344}
345
346static int cxd2841er_tuner_set(struct dvb_frontend *fe)
347{
348 struct cxd2841er_priv *priv = fe->demodulator_priv;
349
350 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
351 fe->ops.i2c_gate_ctrl(fe, 1);
352 if (fe->ops.tuner_ops.set_params)
353 fe->ops.tuner_ops.set_params(fe);
354 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
355 fe->ops.i2c_gate_ctrl(fe, 0);
356
357 return 0;
358}
359
360static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
361 u32 symbol_rate)
362{
363 u32 reg_value = 0;
364 u8 data[3] = {0, 0, 0};
365
366 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
367
368
369
370
371
372 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
373 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
374 dev_err(&priv->i2c->dev,
375 "%s(): reg_value is out of range\n", __func__);
376 return -EINVAL;
377 }
378 data[0] = (u8)((reg_value >> 16) & 0x0F);
379 data[1] = (u8)((reg_value >> 8) & 0xFF);
380 data[2] = (u8)(reg_value & 0xFF);
381
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
383 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
384 return 0;
385}
386
387static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
388 u8 system);
389
390static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
391 u8 system, u32 symbol_rate)
392{
393 int ret;
394 u8 data[4] = { 0, 0, 0, 0 };
395
396 if (priv->state != STATE_SLEEP_S) {
397 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
398 __func__, (int)priv->state);
399 return -EINVAL;
400 }
401 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
402 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
403
404 if (system == SYS_DVBS) {
405 data[0] = 0x0A;
406 } else if (system == SYS_DVBS2) {
407 data[0] = 0x0B;
408 } else {
409 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
410 __func__, system);
411 return -EINVAL;
412 }
413
414 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
415 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
416
417 data[0] = 0x00;
418
419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
420
421 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
422
423 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
424
425 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
426
427 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
428
429 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
430
431 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
432
433 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
434
435 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
436
437 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
438
439 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
440
441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
442 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
443 data[0] = 0x07;
444 data[1] = 0x3B;
445 data[2] = 0x08;
446 data[3] = 0xC5;
447
448 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
449 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
450 data[0] = 0x05;
451 data[1] = 0x80;
452 data[2] = 0x0A;
453 data[3] = 0x80;
454 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
455 data[0] = 0x0C;
456 data[1] = 0xCC;
457 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
458
459 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
460 if (ret != 0)
461 return ret;
462
463 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
464
465 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
466
467 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
468 priv->state = STATE_ACTIVE_S;
469 return 0;
470}
471
472static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
473 u32 bandwidth);
474
475static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
476 u32 bandwidth);
477
478static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
479 u32 bandwidth);
480
481static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
482 u32 bandwidth);
483
484static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
485
486static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
487
488static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
489
490static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
491
492static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
493 struct dtv_frontend_properties *p)
494{
495 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
496 if (priv->state != STATE_ACTIVE_S &&
497 priv->state != STATE_ACTIVE_TC) {
498 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
499 __func__, priv->state);
500 return -EINVAL;
501 }
502
503 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
504
505 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
506 if (priv->state == STATE_ACTIVE_S)
507 return cxd2841er_dvbs2_set_symbol_rate(
508 priv, p->symbol_rate / 1000);
509 else if (priv->state == STATE_ACTIVE_TC) {
510 switch (priv->system) {
511 case SYS_DVBT:
512 return cxd2841er_sleep_tc_to_active_t_band(
513 priv, p->bandwidth_hz);
514 case SYS_DVBT2:
515 return cxd2841er_sleep_tc_to_active_t2_band(
516 priv, p->bandwidth_hz);
517 case SYS_DVBC_ANNEX_A:
518 return cxd2841er_sleep_tc_to_active_c_band(
519 priv, p->bandwidth_hz);
520 case SYS_ISDBT:
521 cxd2841er_active_i_to_sleep_tc(priv);
522 cxd2841er_sleep_tc_to_shutdown(priv);
523 cxd2841er_shutdown_to_sleep_tc(priv);
524 return cxd2841er_sleep_tc_to_active_i(
525 priv, p->bandwidth_hz);
526 }
527 }
528 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
529 __func__, priv->system);
530 return -EINVAL;
531}
532
533static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
534{
535 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
536 if (priv->state != STATE_ACTIVE_S) {
537 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
538 __func__, priv->state);
539 return -EINVAL;
540 }
541
542 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
543
544 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
545
546 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
547
548 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
549
550 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
551
552 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
553
554 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
555
556 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
557
558 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
559
560 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
561
562 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
563
564 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
565
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
567
568 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
569
570 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
571
572 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
573 priv->state = STATE_SLEEP_S;
574 return 0;
575}
576
577static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
578{
579 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
580 if (priv->state != STATE_SLEEP_S) {
581 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
582 __func__, priv->state);
583 return -EINVAL;
584 }
585
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
587
588 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
589
590 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
591
592 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
593
594 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
595
596 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
597 priv->state = STATE_SHUTDOWN;
598 return 0;
599}
600
601static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
602{
603 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
604 if (priv->state != STATE_SLEEP_TC) {
605 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
606 __func__, priv->state);
607 return -EINVAL;
608 }
609
610 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
611
612 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
613
614 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
615 priv->state = STATE_SHUTDOWN;
616 return 0;
617}
618
619static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
620{
621 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
622 if (priv->state != STATE_ACTIVE_TC) {
623 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
624 __func__, priv->state);
625 return -EINVAL;
626 }
627
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
629
630 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
631
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
633
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
635
636 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
637
638 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
639
640 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
641
642 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
643
644 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
645
646 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
647
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
649
650 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
651 priv->state = STATE_SLEEP_TC;
652 return 0;
653}
654
655static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
656{
657 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
658 if (priv->state != STATE_ACTIVE_TC) {
659 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
660 __func__, priv->state);
661 return -EINVAL;
662 }
663
664 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
665
666 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
667
668 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
669
670 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
671
672 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
674 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
675 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
676 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
677 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
678 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
679 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
680 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
681
682 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
683
684 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
685
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
687
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
689
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
691
692 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
693
694 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
695
696 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
697 priv->state = STATE_SLEEP_TC;
698 return 0;
699}
700
701static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
702{
703 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
704 if (priv->state != STATE_ACTIVE_TC) {
705 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
706 __func__, priv->state);
707 return -EINVAL;
708 }
709
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
711
712 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
713
714 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
715
716 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
717
718 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
719 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
720
721 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
722
723 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
724
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
726
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
728
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
730
731 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
732
733 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
734
735 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
736 priv->state = STATE_SLEEP_TC;
737 return 0;
738}
739
740static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
741{
742 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
743 if (priv->state != STATE_ACTIVE_TC) {
744 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
745 __func__, priv->state);
746 return -EINVAL;
747 }
748
749 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
750
751 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
752
753 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
754
755 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
756
757
758
759
760 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
761
762 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
763
764 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
765
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
767
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
769
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
771
772 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
773
774 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
775 priv->state = STATE_SLEEP_TC;
776 return 0;
777}
778
779static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
780{
781 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
782 if (priv->state != STATE_SHUTDOWN) {
783 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
784 __func__, priv->state);
785 return -EINVAL;
786 }
787
788 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
789
790 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
791 usleep_range(3000, 5000);
792
793 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
794
795 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
796
797 switch (priv->xtal) {
798 case SONY_XTAL_20500:
799 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
800 break;
801 case SONY_XTAL_24000:
802
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
804 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
805 break;
806 case SONY_XTAL_41000:
807 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
808 break;
809 default:
810 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
811 __func__, priv->xtal);
812 return -EINVAL;
813 }
814
815
816 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
817
818 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
819 usleep_range(1000, 2000);
820
821 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
822
823 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
824
825 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
826
827 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
828 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
829
830 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
831 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
832 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
833 priv->state = STATE_SLEEP_S;
834 return 0;
835}
836
837static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
838{
839 u8 data = 0;
840
841 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
842 if (priv->state != STATE_SHUTDOWN) {
843 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
844 __func__, priv->state);
845 return -EINVAL;
846 }
847
848 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
849
850 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
851 usleep_range(3000, 5000);
852
853 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
854
855 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
856
857 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
858
859 switch (priv->xtal) {
860 case SONY_XTAL_20500:
861 data = 0x0;
862 break;
863 case SONY_XTAL_24000:
864
865 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
866 data = 0x3;
867 break;
868 case SONY_XTAL_41000:
869 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
870 data = 0x1;
871 break;
872 }
873 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
874
875 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
876 usleep_range(1000, 2000);
877
878 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
879
880 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
881 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
882
883 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
884 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
885 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
886 priv->state = STATE_SLEEP_TC;
887 return 0;
888}
889
890static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
891{
892 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
893
894 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
895
896 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
897
898 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
899 return 0;
900}
901
902
903static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
904 u8 system)
905{
906 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
907
908 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
909
910 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
911 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
912 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
913 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
914 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
915 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
916
917
918
919
920
921 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
922 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
923
924
925
926
927 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
928 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
929
930
931
932
933 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
934
935
936
937
938
939 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
940
941
942
943
944 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
945 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
946
947
948
949
950
951 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
952
953 if (system == SYS_DVBT) {
954
955 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
956 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
957 } else if (system == SYS_DVBC_ANNEX_A) {
958
959 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
960 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
961 }
962}
963
964static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
965{
966 u8 chip_id = 0;
967
968 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
969 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
970 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
971 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
972 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
973
974 return chip_id;
975}
976
977static int cxd2841er_read_status_s(struct dvb_frontend *fe,
978 enum fe_status *status)
979{
980 u8 reg = 0;
981 struct cxd2841er_priv *priv = fe->demodulator_priv;
982
983 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
984 *status = 0;
985 if (priv->state != STATE_ACTIVE_S) {
986 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
987 __func__, priv->state);
988 return -EINVAL;
989 }
990
991 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
992
993
994
995
996 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
997 if (reg & 0x04) {
998 *status = FE_HAS_SIGNAL
999 | FE_HAS_CARRIER
1000 | FE_HAS_VITERBI
1001 | FE_HAS_SYNC
1002 | FE_HAS_LOCK;
1003 }
1004 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1005 return 0;
1006}
1007
1008static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1009 u8 *sync, u8 *tslock, u8 *unlock)
1010{
1011 u8 data = 0;
1012
1013 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1014 if (priv->state != STATE_ACTIVE_TC)
1015 return -EINVAL;
1016 if (priv->system == SYS_DVBT) {
1017
1018 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1019 } else {
1020
1021 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1022 }
1023 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1024 if ((data & 0x07) == 0x07) {
1025 dev_dbg(&priv->i2c->dev,
1026 "%s(): invalid hardware state detected\n", __func__);
1027 *sync = 0;
1028 *tslock = 0;
1029 *unlock = 0;
1030 } else {
1031 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1032 *tslock = ((data & 0x20) ? 1 : 0);
1033 *unlock = ((data & 0x10) ? 1 : 0);
1034 }
1035 return 0;
1036}
1037
1038static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1039{
1040 u8 data;
1041
1042 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1043 if (priv->state != STATE_ACTIVE_TC)
1044 return -EINVAL;
1045 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1046 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1047 if ((data & 0x01) == 0) {
1048 *tslock = 0;
1049 } else {
1050 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1051 *tslock = ((data & 0x20) ? 1 : 0);
1052 }
1053 return 0;
1054}
1055
1056static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1057 u8 *sync, u8 *tslock, u8 *unlock)
1058{
1059 u8 data = 0;
1060
1061 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1062 if (priv->state != STATE_ACTIVE_TC)
1063 return -EINVAL;
1064
1065 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1066 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1067 dev_dbg(&priv->i2c->dev,
1068 "%s(): lock=0x%x\n", __func__, data);
1069 *sync = ((data & 0x02) ? 1 : 0);
1070 *tslock = ((data & 0x01) ? 1 : 0);
1071 *unlock = ((data & 0x10) ? 1 : 0);
1072 return 0;
1073}
1074
1075static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1076 enum fe_status *status)
1077{
1078 int ret = 0;
1079 u8 sync = 0;
1080 u8 tslock = 0;
1081 u8 unlock = 0;
1082 struct cxd2841er_priv *priv = fe->demodulator_priv;
1083
1084 *status = 0;
1085 if (priv->state == STATE_ACTIVE_TC) {
1086 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1087 ret = cxd2841er_read_status_t_t2(
1088 priv, &sync, &tslock, &unlock);
1089 if (ret)
1090 goto done;
1091 if (unlock)
1092 goto done;
1093 if (sync)
1094 *status = FE_HAS_SIGNAL |
1095 FE_HAS_CARRIER |
1096 FE_HAS_VITERBI |
1097 FE_HAS_SYNC;
1098 if (tslock)
1099 *status |= FE_HAS_LOCK;
1100 } else if (priv->system == SYS_ISDBT) {
1101 ret = cxd2841er_read_status_i(
1102 priv, &sync, &tslock, &unlock);
1103 if (ret)
1104 goto done;
1105 if (unlock)
1106 goto done;
1107 if (sync)
1108 *status = FE_HAS_SIGNAL |
1109 FE_HAS_CARRIER |
1110 FE_HAS_VITERBI |
1111 FE_HAS_SYNC;
1112 if (tslock)
1113 *status |= FE_HAS_LOCK;
1114 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1115 ret = cxd2841er_read_status_c(priv, &tslock);
1116 if (ret)
1117 goto done;
1118 if (tslock)
1119 *status = FE_HAS_SIGNAL |
1120 FE_HAS_CARRIER |
1121 FE_HAS_VITERBI |
1122 FE_HAS_SYNC |
1123 FE_HAS_LOCK;
1124 }
1125 }
1126done:
1127 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1128 return ret;
1129}
1130
1131static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1132 int *offset)
1133{
1134 u8 data[3];
1135 u8 is_hs_mode;
1136 s32 cfrl_ctrlval;
1137 s32 temp_div, temp_q, temp_r;
1138
1139 if (priv->state != STATE_ACTIVE_S) {
1140 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1141 __func__, priv->state);
1142 return -EINVAL;
1143 }
1144
1145
1146
1147
1148
1149 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1150 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1151 if (data[0] & 0x01) {
1152
1153
1154
1155
1156 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1157 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1158 } else {
1159 dev_dbg(&priv->i2c->dev,
1160 "%s(): unable to detect sampling rate mode\n",
1161 __func__);
1162 return -EINVAL;
1163 }
1164
1165
1166
1167
1168
1169
1170 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1171 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1172 (((u32)data[1] & 0xFF) << 8) |
1173 ((u32)data[2] & 0xFF), 20);
1174 temp_div = (is_hs_mode ? 1048576 : 1572864);
1175 if (cfrl_ctrlval > 0) {
1176 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1177 temp_div, &temp_r);
1178 } else {
1179 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1180 temp_div, &temp_r);
1181 }
1182 if (temp_r >= temp_div / 2)
1183 temp_q++;
1184 if (cfrl_ctrlval > 0)
1185 temp_q *= -1;
1186 *offset = temp_q;
1187 return 0;
1188}
1189
1190static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1191 u32 bandwidth, int *offset)
1192{
1193 u8 data[4];
1194
1195 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1196 if (priv->state != STATE_ACTIVE_TC) {
1197 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1198 __func__, priv->state);
1199 return -EINVAL;
1200 }
1201 if (priv->system != SYS_ISDBT) {
1202 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1203 __func__, priv->system);
1204 return -EINVAL;
1205 }
1206 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1207 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1208 *offset = -1 * sign_extend32(
1209 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1210 ((u32)data[2] << 8) | (u32)data[3], 29);
1211
1212 switch (bandwidth) {
1213 case 6000000:
1214 *offset = -1 * ((*offset) * 8/264);
1215 break;
1216 case 7000000:
1217 *offset = -1 * ((*offset) * 8/231);
1218 break;
1219 case 8000000:
1220 *offset = -1 * ((*offset) * 8/198);
1221 break;
1222 default:
1223 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1224 __func__, bandwidth);
1225 return -EINVAL;
1226 }
1227
1228 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1229 __func__, bandwidth, *offset);
1230
1231 return 0;
1232}
1233
1234static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1235 u32 bandwidth, int *offset)
1236{
1237 u8 data[4];
1238
1239 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1240 if (priv->state != STATE_ACTIVE_TC) {
1241 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1242 __func__, priv->state);
1243 return -EINVAL;
1244 }
1245 if (priv->system != SYS_DVBT) {
1246 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1247 __func__, priv->system);
1248 return -EINVAL;
1249 }
1250 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1251 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1252 *offset = -1 * sign_extend32(
1253 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1254 ((u32)data[2] << 8) | (u32)data[3], 29);
1255 *offset *= (bandwidth / 1000000);
1256 *offset /= 235;
1257 return 0;
1258}
1259
1260static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1261 u32 bandwidth, int *offset)
1262{
1263 u8 data[4];
1264
1265 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1266 if (priv->state != STATE_ACTIVE_TC) {
1267 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1268 __func__, priv->state);
1269 return -EINVAL;
1270 }
1271 if (priv->system != SYS_DVBT2) {
1272 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1273 __func__, priv->system);
1274 return -EINVAL;
1275 }
1276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1277 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1278 *offset = -1 * sign_extend32(
1279 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1280 ((u32)data[2] << 8) | (u32)data[3], 27);
1281 switch (bandwidth) {
1282 case 1712000:
1283 *offset /= 582;
1284 break;
1285 case 5000000:
1286 case 6000000:
1287 case 7000000:
1288 case 8000000:
1289 *offset *= (bandwidth / 1000000);
1290 *offset /= 940;
1291 break;
1292 default:
1293 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1294 __func__, bandwidth);
1295 return -EINVAL;
1296 }
1297 return 0;
1298}
1299
1300static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1301 int *offset)
1302{
1303 u8 data[2];
1304
1305 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1306 if (priv->state != STATE_ACTIVE_TC) {
1307 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1308 __func__, priv->state);
1309 return -EINVAL;
1310 }
1311 if (priv->system != SYS_DVBC_ANNEX_A) {
1312 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1313 __func__, priv->system);
1314 return -EINVAL;
1315 }
1316 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1317 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1318 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1319 | (u32)data[1], 13), 16384);
1320 return 0;
1321}
1322
1323static int cxd2841er_read_packet_errors_c(
1324 struct cxd2841er_priv *priv, u32 *penum)
1325{
1326 u8 data[3];
1327
1328 *penum = 0;
1329 if (priv->state != STATE_ACTIVE_TC) {
1330 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1331 __func__, priv->state);
1332 return -EINVAL;
1333 }
1334 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1335 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1336 if (data[2] & 0x01)
1337 *penum = ((u32)data[0] << 8) | (u32)data[1];
1338 return 0;
1339}
1340
1341static int cxd2841er_read_packet_errors_t(
1342 struct cxd2841er_priv *priv, u32 *penum)
1343{
1344 u8 data[3];
1345
1346 *penum = 0;
1347 if (priv->state != STATE_ACTIVE_TC) {
1348 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1349 __func__, priv->state);
1350 return -EINVAL;
1351 }
1352 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1353 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1354 if (data[2] & 0x01)
1355 *penum = ((u32)data[0] << 8) | (u32)data[1];
1356 return 0;
1357}
1358
1359static int cxd2841er_read_packet_errors_t2(
1360 struct cxd2841er_priv *priv, u32 *penum)
1361{
1362 u8 data[3];
1363
1364 *penum = 0;
1365 if (priv->state != STATE_ACTIVE_TC) {
1366 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1367 __func__, priv->state);
1368 return -EINVAL;
1369 }
1370 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1371 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1372 if (data[0] & 0x01)
1373 *penum = ((u32)data[1] << 8) | (u32)data[2];
1374 return 0;
1375}
1376
1377static int cxd2841er_read_packet_errors_i(
1378 struct cxd2841er_priv *priv, u32 *penum)
1379{
1380 u8 data[2];
1381
1382 *penum = 0;
1383 if (priv->state != STATE_ACTIVE_TC) {
1384 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1385 __func__, priv->state);
1386 return -EINVAL;
1387 }
1388 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1389 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1390
1391 if (!(data[0] & 0x01))
1392 return 0;
1393
1394
1395 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1396 *penum = ((u32)data[0] << 8) | (u32)data[1];
1397
1398
1399 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1400 *penum += ((u32)data[0] << 8) | (u32)data[1];
1401
1402
1403 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1404 *penum += ((u32)data[0] << 8) | (u32)data[1];
1405
1406 return 0;
1407}
1408
1409static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1410 u32 *bit_error, u32 *bit_count)
1411{
1412 u8 data[3];
1413 u32 bit_err, period_exp;
1414
1415 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1416 if (priv->state != STATE_ACTIVE_TC) {
1417 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1418 __func__, priv->state);
1419 return -EINVAL;
1420 }
1421 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1422 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1423 if (!(data[0] & 0x80)) {
1424 dev_dbg(&priv->i2c->dev,
1425 "%s(): no valid BER data\n", __func__);
1426 return -EINVAL;
1427 }
1428 bit_err = ((u32)(data[0] & 0x3f) << 16) |
1429 ((u32)data[1] << 8) |
1430 (u32)data[2];
1431 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1432 period_exp = data[0] & 0x1f;
1433
1434 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1435 dev_dbg(&priv->i2c->dev,
1436 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1437 __func__, period_exp, bit_err);
1438 return -EINVAL;
1439 }
1440
1441 dev_dbg(&priv->i2c->dev,
1442 "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1443 __func__, period_exp, bit_err,
1444 ((1 << period_exp) * 204 * 8));
1445
1446 *bit_error = bit_err;
1447 *bit_count = ((1 << period_exp) * 204 * 8);
1448
1449 return 0;
1450}
1451
1452static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1453 u32 *bit_error, u32 *bit_count)
1454{
1455 u8 data[3];
1456 u8 pktnum[2];
1457
1458 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1459 if (priv->state != STATE_ACTIVE_TC) {
1460 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1461 __func__, priv->state);
1462 return -EINVAL;
1463 }
1464
1465 cxd2841er_freeze_regs(priv);
1466 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1467 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1468 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1469 cxd2841er_unfreeze_regs(priv);
1470
1471 if (!pktnum[0] && !pktnum[1]) {
1472 dev_dbg(&priv->i2c->dev,
1473 "%s(): no valid BER data\n", __func__);
1474 return -EINVAL;
1475 }
1476
1477 *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1478 ((u32)data[1] << 8) | data[2];
1479 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1480 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1481 __func__, *bit_error, *bit_count);
1482
1483 return 0;
1484}
1485
1486static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1487 u32 *bit_error, u32 *bit_count)
1488{
1489 u8 data[11];
1490
1491
1492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1504 if (data[0] & 0x01) {
1505 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1506 ((u32)(data[2] & 0xFF) << 8) |
1507 (u32)(data[3] & 0xFF);
1508 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1509 ((u32)(data[9] & 0xFF) << 8) |
1510 (u32)(data[10] & 0xFF);
1511 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1512 dev_dbg(&priv->i2c->dev,
1513 "%s(): invalid bit_error %d, bit_count %d\n",
1514 __func__, *bit_error, *bit_count);
1515 return -EINVAL;
1516 }
1517 return 0;
1518 }
1519 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1520 return -EINVAL;
1521}
1522
1523
1524static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1525 u32 *bit_error, u32 *bit_count)
1526{
1527 u8 data[5];
1528 u32 period;
1529
1530
1531 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1532
1533
1534
1535
1536
1537
1538
1539
1540 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1541 if (data[0] & 0x01) {
1542
1543 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1544 ((u32)(data[2] & 0xFF) << 16) |
1545 ((u32)(data[3] & 0xFF) << 8) |
1546 (u32)(data[4] & 0xFF);
1547
1548
1549 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1550 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1551
1552 period = (u32)(1 << (data[0] & 0x0F));
1553 if (period == 0) {
1554 dev_dbg(&priv->i2c->dev,
1555 "%s(): period is 0\n", __func__);
1556 return -EINVAL;
1557 }
1558 if (*bit_error > (period * 64800)) {
1559 dev_dbg(&priv->i2c->dev,
1560 "%s(): invalid bit_err 0x%x period 0x%x\n",
1561 __func__, *bit_error, period);
1562 return -EINVAL;
1563 }
1564 *bit_count = period * 64800;
1565
1566 return 0;
1567 } else {
1568 dev_dbg(&priv->i2c->dev,
1569 "%s(): no data available\n", __func__);
1570 }
1571 return -EINVAL;
1572}
1573
1574static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1575 u32 *bit_error, u32 *bit_count)
1576{
1577 u8 data[4];
1578 u32 period_exp, n_ldpc;
1579
1580 if (priv->state != STATE_ACTIVE_TC) {
1581 dev_dbg(&priv->i2c->dev,
1582 "%s(): invalid state %d\n", __func__, priv->state);
1583 return -EINVAL;
1584 }
1585 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1586 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1587 if (!(data[0] & 0x10)) {
1588 dev_dbg(&priv->i2c->dev,
1589 "%s(): no valid BER data\n", __func__);
1590 return -EINVAL;
1591 }
1592 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1593 ((u32)data[1] << 16) |
1594 ((u32)data[2] << 8) |
1595 (u32)data[3];
1596 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1597 period_exp = data[0] & 0x0f;
1598 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1599 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1600 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1601 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1602 dev_dbg(&priv->i2c->dev,
1603 "%s(): invalid BER value\n", __func__);
1604 return -EINVAL;
1605 }
1606
1607
1608
1609
1610
1611
1612 if (period_exp >= 4) {
1613 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1614 *bit_error *= 3125ULL;
1615 } else {
1616 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1617 *bit_error *= 50000ULL;
1618 }
1619 return 0;
1620}
1621
1622static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1623 u32 *bit_error, u32 *bit_count)
1624{
1625 u8 data[2];
1626 u32 period;
1627
1628 if (priv->state != STATE_ACTIVE_TC) {
1629 dev_dbg(&priv->i2c->dev,
1630 "%s(): invalid state %d\n", __func__, priv->state);
1631 return -EINVAL;
1632 }
1633 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1634 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1635 if (!(data[0] & 0x01)) {
1636 dev_dbg(&priv->i2c->dev,
1637 "%s(): no valid BER data\n", __func__);
1638 return 0;
1639 }
1640 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1641 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1642 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1643 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1644
1645
1646
1647
1648
1649
1650 *bit_count = period / 128;
1651 *bit_error *= 78125ULL;
1652 return 0;
1653}
1654
1655static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1656{
1657
1658
1659
1660
1661 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1662 return 0;
1663}
1664
1665static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1666{
1667
1668
1669
1670 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1671 return 0;
1672}
1673
1674static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1675 u8 delsys, u32 *snr)
1676{
1677 u8 data[3];
1678 u32 res = 0, value;
1679 int min_index, max_index, index;
1680 static const struct cxd2841er_cnr_data *cn_data;
1681
1682 cxd2841er_freeze_regs(priv);
1683
1684 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1685
1686
1687
1688
1689
1690
1691 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1692 cxd2841er_unfreeze_regs(priv);
1693
1694 if (data[0] & 0x01) {
1695 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1696 min_index = 0;
1697 if (delsys == SYS_DVBS) {
1698 cn_data = s_cn_data;
1699 max_index = sizeof(s_cn_data) /
1700 sizeof(s_cn_data[0]) - 1;
1701 } else {
1702 cn_data = s2_cn_data;
1703 max_index = sizeof(s2_cn_data) /
1704 sizeof(s2_cn_data[0]) - 1;
1705 }
1706 if (value >= cn_data[min_index].value) {
1707 res = cn_data[min_index].cnr_x1000;
1708 goto done;
1709 }
1710 if (value <= cn_data[max_index].value) {
1711 res = cn_data[max_index].cnr_x1000;
1712 goto done;
1713 }
1714 while ((max_index - min_index) > 1) {
1715 index = (max_index + min_index) / 2;
1716 if (value == cn_data[index].value) {
1717 res = cn_data[index].cnr_x1000;
1718 goto done;
1719 } else if (value > cn_data[index].value)
1720 max_index = index;
1721 else
1722 min_index = index;
1723 if ((max_index - min_index) <= 1) {
1724 if (value == cn_data[max_index].value) {
1725 res = cn_data[max_index].cnr_x1000;
1726 goto done;
1727 } else {
1728 res = cn_data[min_index].cnr_x1000;
1729 goto done;
1730 }
1731 }
1732 }
1733 } else {
1734 dev_dbg(&priv->i2c->dev,
1735 "%s(): no data available\n", __func__);
1736 return -EINVAL;
1737 }
1738done:
1739 *snr = res;
1740 return 0;
1741}
1742
1743static uint32_t sony_log(uint32_t x)
1744{
1745 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1746}
1747
1748static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1749{
1750 u32 reg;
1751 u8 data[2];
1752 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1753
1754 *snr = 0;
1755 if (priv->state != STATE_ACTIVE_TC) {
1756 dev_dbg(&priv->i2c->dev,
1757 "%s(): invalid state %d\n",
1758 __func__, priv->state);
1759 return -EINVAL;
1760 }
1761
1762 cxd2841er_freeze_regs(priv);
1763 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1764 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1765 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1766 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1767 cxd2841er_unfreeze_regs(priv);
1768
1769 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1770 if (reg == 0) {
1771 dev_dbg(&priv->i2c->dev,
1772 "%s(): reg value out of range\n", __func__);
1773 return 0;
1774 }
1775
1776 switch (qam) {
1777 case SONY_DVBC_CONSTELLATION_16QAM:
1778 case SONY_DVBC_CONSTELLATION_64QAM:
1779 case SONY_DVBC_CONSTELLATION_256QAM:
1780
1781 if (reg < 126)
1782 reg = 126;
1783 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1784 break;
1785 case SONY_DVBC_CONSTELLATION_32QAM:
1786 case SONY_DVBC_CONSTELLATION_128QAM:
1787
1788 if (reg < 69)
1789 reg = 69;
1790 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1791 break;
1792 default:
1793 return -EINVAL;
1794 }
1795
1796 return 0;
1797}
1798
1799static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1800{
1801 u32 reg;
1802 u8 data[2];
1803
1804 *snr = 0;
1805 if (priv->state != STATE_ACTIVE_TC) {
1806 dev_dbg(&priv->i2c->dev,
1807 "%s(): invalid state %d\n", __func__, priv->state);
1808 return -EINVAL;
1809 }
1810
1811 cxd2841er_freeze_regs(priv);
1812 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1813 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1814 cxd2841er_unfreeze_regs(priv);
1815
1816 reg = ((u32)data[0] << 8) | (u32)data[1];
1817 if (reg == 0) {
1818 dev_dbg(&priv->i2c->dev,
1819 "%s(): reg value out of range\n", __func__);
1820 return 0;
1821 }
1822 if (reg > 4996)
1823 reg = 4996;
1824 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1825 return 0;
1826}
1827
1828static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1829{
1830 u32 reg;
1831 u8 data[2];
1832
1833 *snr = 0;
1834 if (priv->state != STATE_ACTIVE_TC) {
1835 dev_dbg(&priv->i2c->dev,
1836 "%s(): invalid state %d\n", __func__, priv->state);
1837 return -EINVAL;
1838 }
1839
1840 cxd2841er_freeze_regs(priv);
1841 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1842 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1843 cxd2841er_unfreeze_regs(priv);
1844
1845 reg = ((u32)data[0] << 8) | (u32)data[1];
1846 if (reg == 0) {
1847 dev_dbg(&priv->i2c->dev,
1848 "%s(): reg value out of range\n", __func__);
1849 return 0;
1850 }
1851 if (reg > 10876)
1852 reg = 10876;
1853 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1854 return 0;
1855}
1856
1857static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1858{
1859 u32 reg;
1860 u8 data[2];
1861
1862 *snr = 0;
1863 if (priv->state != STATE_ACTIVE_TC) {
1864 dev_dbg(&priv->i2c->dev,
1865 "%s(): invalid state %d\n", __func__,
1866 priv->state);
1867 return -EINVAL;
1868 }
1869
1870 cxd2841er_freeze_regs(priv);
1871 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1872 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1873 cxd2841er_unfreeze_regs(priv);
1874
1875 reg = ((u32)data[0] << 8) | (u32)data[1];
1876 if (reg == 0) {
1877 dev_dbg(&priv->i2c->dev,
1878 "%s(): reg value out of range\n", __func__);
1879 return 0;
1880 }
1881 *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1882 return 0;
1883}
1884
1885static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1886 u8 delsys)
1887{
1888 u8 data[2];
1889
1890 cxd2841er_write_reg(
1891 priv, I2C_SLVT, 0x00, 0x40);
1892 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1893 dev_dbg(&priv->i2c->dev,
1894 "%s(): AGC value=%u\n",
1895 __func__, (((u16)data[0] & 0x0F) << 8) |
1896 (u16)(data[1] & 0xFF));
1897 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1898}
1899
1900static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1901 u8 delsys)
1902{
1903 u8 data[2];
1904
1905 cxd2841er_write_reg(
1906 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1907 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1908 dev_dbg(&priv->i2c->dev,
1909 "%s(): AGC value=%u\n",
1910 __func__, (((u16)data[0] & 0x0F) << 8) |
1911 (u16)(data[1] & 0xFF));
1912 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1913}
1914
1915static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1916 u8 delsys)
1917{
1918 u8 data[2];
1919
1920 cxd2841er_write_reg(
1921 priv, I2C_SLVT, 0x00, 0x60);
1922 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1923
1924 dev_dbg(&priv->i2c->dev,
1925 "%s(): AGC value=%u\n",
1926 __func__, (((u16)data[0] & 0x0F) << 8) |
1927 (u16)(data[1] & 0xFF));
1928 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1929}
1930
1931static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1932{
1933 u8 data[2];
1934
1935
1936 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1937
1938
1939
1940
1941
1942 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1943 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1944}
1945
1946static void cxd2841er_read_ber(struct dvb_frontend *fe)
1947{
1948 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1949 struct cxd2841er_priv *priv = fe->demodulator_priv;
1950 u32 ret, bit_error = 0, bit_count = 0;
1951
1952 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1953 switch (p->delivery_system) {
1954 case SYS_DVBC_ANNEX_A:
1955 case SYS_DVBC_ANNEX_B:
1956 case SYS_DVBC_ANNEX_C:
1957 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1958 break;
1959 case SYS_ISDBT:
1960 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1961 break;
1962 case SYS_DVBS:
1963 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1964 break;
1965 case SYS_DVBS2:
1966 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1967 break;
1968 case SYS_DVBT:
1969 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1970 break;
1971 case SYS_DVBT2:
1972 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1973 break;
1974 default:
1975 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1976 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1977 return;
1978 }
1979
1980 if (!ret) {
1981 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1982 p->post_bit_error.stat[0].uvalue += bit_error;
1983 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1984 p->post_bit_count.stat[0].uvalue += bit_count;
1985 } else {
1986 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1987 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1988 }
1989}
1990
1991static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1992{
1993 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1994 struct cxd2841er_priv *priv = fe->demodulator_priv;
1995 s32 strength;
1996
1997 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1998 switch (p->delivery_system) {
1999 case SYS_DVBT:
2000 case SYS_DVBT2:
2001 strength = cxd2841er_read_agc_gain_t_t2(priv,
2002 p->delivery_system);
2003 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2004
2005 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
2006 break;
2007 case SYS_DVBC_ANNEX_A:
2008 case SYS_DVBC_ANNEX_B:
2009 case SYS_DVBC_ANNEX_C:
2010 strength = cxd2841er_read_agc_gain_c(priv,
2011 p->delivery_system);
2012 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2013
2014
2015
2016
2017
2018 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2019 break;
2020 case SYS_ISDBT:
2021 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2022 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2023
2024
2025
2026
2027 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2028 break;
2029 case SYS_DVBS:
2030 case SYS_DVBS2:
2031 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2032 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2033 p->strength.stat[0].uvalue = strength;
2034 break;
2035 default:
2036 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2037 break;
2038 }
2039}
2040
2041static void cxd2841er_read_snr(struct dvb_frontend *fe)
2042{
2043 u32 tmp = 0;
2044 int ret = 0;
2045 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2046 struct cxd2841er_priv *priv = fe->demodulator_priv;
2047
2048 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2049 switch (p->delivery_system) {
2050 case SYS_DVBC_ANNEX_A:
2051 case SYS_DVBC_ANNEX_B:
2052 case SYS_DVBC_ANNEX_C:
2053 ret = cxd2841er_read_snr_c(priv, &tmp);
2054 break;
2055 case SYS_DVBT:
2056 ret = cxd2841er_read_snr_t(priv, &tmp);
2057 break;
2058 case SYS_DVBT2:
2059 ret = cxd2841er_read_snr_t2(priv, &tmp);
2060 break;
2061 case SYS_ISDBT:
2062 ret = cxd2841er_read_snr_i(priv, &tmp);
2063 break;
2064 case SYS_DVBS:
2065 case SYS_DVBS2:
2066 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2067 break;
2068 default:
2069 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2070 __func__, p->delivery_system);
2071 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2072 return;
2073 }
2074
2075 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2076 __func__, (int32_t)tmp);
2077
2078 if (!ret) {
2079 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2080 p->cnr.stat[0].svalue = tmp;
2081 } else {
2082 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2083 }
2084}
2085
2086static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2087{
2088 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2089 struct cxd2841er_priv *priv = fe->demodulator_priv;
2090 u32 ucblocks = 0;
2091
2092 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2093 switch (p->delivery_system) {
2094 case SYS_DVBC_ANNEX_A:
2095 case SYS_DVBC_ANNEX_B:
2096 case SYS_DVBC_ANNEX_C:
2097 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2098 break;
2099 case SYS_DVBT:
2100 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2101 break;
2102 case SYS_DVBT2:
2103 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2104 break;
2105 case SYS_ISDBT:
2106 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2107 break;
2108 default:
2109 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2110 return;
2111 }
2112 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2113
2114 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2115 p->block_error.stat[0].uvalue = ucblocks;
2116}
2117
2118static int cxd2841er_dvbt2_set_profile(
2119 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2120{
2121 u8 tune_mode;
2122 u8 seq_not2d_time;
2123
2124 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2125 switch (profile) {
2126 case DVBT2_PROFILE_BASE:
2127 tune_mode = 0x01;
2128
2129 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2130 break;
2131 case DVBT2_PROFILE_LITE:
2132 tune_mode = 0x05;
2133
2134 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2135 break;
2136 case DVBT2_PROFILE_ANY:
2137 tune_mode = 0x00;
2138
2139 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2140 break;
2141 default:
2142 return -EINVAL;
2143 }
2144
2145 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2146
2147 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2148
2149 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2150
2151 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2152 return 0;
2153}
2154
2155static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2156 u8 is_auto, u8 plp_id)
2157{
2158 if (is_auto) {
2159 dev_dbg(&priv->i2c->dev,
2160 "%s() using auto PLP selection\n", __func__);
2161 } else {
2162 dev_dbg(&priv->i2c->dev,
2163 "%s() using manual PLP selection, ID %d\n",
2164 __func__, plp_id);
2165 }
2166
2167 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2168 if (!is_auto) {
2169
2170 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2171 }
2172
2173 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2174 return 0;
2175}
2176
2177static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2178 u32 bandwidth)
2179{
2180 u32 iffreq, ifhz;
2181 u8 data[MAX_WRITE_REGSIZE];
2182
2183 static const uint8_t nominalRate8bw[3][5] = {
2184
2185 {0x11, 0xF0, 0x00, 0x00, 0x00},
2186 {0x15, 0x00, 0x00, 0x00, 0x00},
2187 {0x11, 0xF0, 0x00, 0x00, 0x00}
2188 };
2189
2190 static const uint8_t nominalRate7bw[3][5] = {
2191
2192 {0x14, 0x80, 0x00, 0x00, 0x00},
2193 {0x18, 0x00, 0x00, 0x00, 0x00},
2194 {0x14, 0x80, 0x00, 0x00, 0x00}
2195 };
2196
2197 static const uint8_t nominalRate6bw[3][5] = {
2198
2199 {0x17, 0xEA, 0xAA, 0xAA, 0xAA},
2200 {0x1C, 0x00, 0x00, 0x00, 0x00},
2201 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}
2202 };
2203
2204 static const uint8_t nominalRate5bw[3][5] = {
2205
2206 {0x1C, 0xB3, 0x33, 0x33, 0x33},
2207 {0x21, 0x99, 0x99, 0x99, 0x99},
2208 {0x1C, 0xB3, 0x33, 0x33, 0x33}
2209 };
2210
2211 static const uint8_t nominalRate17bw[3][5] = {
2212
2213 {0x58, 0xE2, 0xAF, 0xE0, 0xBC},
2214 {0x68, 0x0F, 0xA2, 0x32, 0xD0},
2215 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}
2216 };
2217
2218 static const uint8_t itbCoef8bw[3][14] = {
2219 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2220 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8},
2221 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2222 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5},
2223 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2224 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}
2225 };
2226
2227 static const uint8_t itbCoef7bw[3][14] = {
2228 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2229 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5},
2230 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2231 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD},
2232 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2233 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}
2234 };
2235
2236 static const uint8_t itbCoef6bw[3][14] = {
2237 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2238 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4},
2239 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2240 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8},
2241 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2242 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}
2243 };
2244
2245 static const uint8_t itbCoef5bw[3][14] = {
2246 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2247 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4},
2248 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2249 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8},
2250 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2251 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}
2252 };
2253
2254 static const uint8_t itbCoef17bw[3][14] = {
2255 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2256 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99},
2257 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2258 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4},
2259 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2260 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}
2261 };
2262
2263
2264 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2265
2266 switch (bandwidth) {
2267 case 8000000:
2268
2269 cxd2841er_write_regs(priv, I2C_SLVT,
2270 0x9F, nominalRate8bw[priv->xtal], 5);
2271
2272
2273 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2274 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2275 0x7a, 0x00, 0x0f);
2276
2277
2278 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2279
2280
2281
2282
2283 if (priv->flags & CXD2841ER_ASCOT)
2284 cxd2841er_write_regs(priv, I2C_SLVT,
2285 0xA6, itbCoef8bw[priv->xtal], 14);
2286
2287 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2288 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2289 data[0] = (u8) ((iffreq >> 16) & 0xff);
2290 data[1] = (u8)((iffreq >> 8) & 0xff);
2291 data[2] = (u8)(iffreq & 0xff);
2292 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2293
2294 cxd2841er_set_reg_bits(
2295 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2296 break;
2297 case 7000000:
2298
2299 cxd2841er_write_regs(priv, I2C_SLVT,
2300 0x9F, nominalRate7bw[priv->xtal], 5);
2301
2302
2303 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2304 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2305 0x7a, 0x00, 0x0f);
2306
2307
2308 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2309
2310
2311
2312
2313 if (priv->flags & CXD2841ER_ASCOT)
2314 cxd2841er_write_regs(priv, I2C_SLVT,
2315 0xA6, itbCoef7bw[priv->xtal], 14);
2316
2317 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2318 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2319 data[0] = (u8) ((iffreq >> 16) & 0xff);
2320 data[1] = (u8)((iffreq >> 8) & 0xff);
2321 data[2] = (u8)(iffreq & 0xff);
2322 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2323
2324 cxd2841er_set_reg_bits(
2325 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2326 break;
2327 case 6000000:
2328
2329 cxd2841er_write_regs(priv, I2C_SLVT,
2330 0x9F, nominalRate6bw[priv->xtal], 5);
2331
2332
2333 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2334 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2335 0x7a, 0x00, 0x0f);
2336
2337
2338 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2339
2340
2341
2342
2343 if (priv->flags & CXD2841ER_ASCOT)
2344 cxd2841er_write_regs(priv, I2C_SLVT,
2345 0xA6, itbCoef6bw[priv->xtal], 14);
2346
2347 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2348 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2349 data[0] = (u8) ((iffreq >> 16) & 0xff);
2350 data[1] = (u8)((iffreq >> 8) & 0xff);
2351 data[2] = (u8)(iffreq & 0xff);
2352 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2353
2354 cxd2841er_set_reg_bits(
2355 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2356 break;
2357 case 5000000:
2358
2359 cxd2841er_write_regs(priv, I2C_SLVT,
2360 0x9F, nominalRate5bw[priv->xtal], 5);
2361
2362
2363 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2364 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2365 0x7a, 0x00, 0x0f);
2366
2367
2368 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2369
2370
2371
2372
2373 if (priv->flags & CXD2841ER_ASCOT)
2374 cxd2841er_write_regs(priv, I2C_SLVT,
2375 0xA6, itbCoef5bw[priv->xtal], 14);
2376
2377 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2378 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2379 data[0] = (u8) ((iffreq >> 16) & 0xff);
2380 data[1] = (u8)((iffreq >> 8) & 0xff);
2381 data[2] = (u8)(iffreq & 0xff);
2382 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2383
2384 cxd2841er_set_reg_bits(
2385 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2386 break;
2387 case 1712000:
2388
2389 cxd2841er_write_regs(priv, I2C_SLVT,
2390 0x9F, nominalRate17bw[priv->xtal], 5);
2391
2392
2393 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2394 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2395 0x7a, 0x03, 0x0f);
2396
2397
2398 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2399
2400
2401
2402
2403 if (priv->flags & CXD2841ER_ASCOT)
2404 cxd2841er_write_regs(priv, I2C_SLVT,
2405 0xA6, itbCoef17bw[priv->xtal], 14);
2406
2407 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2408 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2409 data[0] = (u8) ((iffreq >> 16) & 0xff);
2410 data[1] = (u8)((iffreq >> 8) & 0xff);
2411 data[2] = (u8)(iffreq & 0xff);
2412 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2413
2414 cxd2841er_set_reg_bits(
2415 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2416 break;
2417 default:
2418 return -EINVAL;
2419 }
2420 return 0;
2421}
2422
2423static int cxd2841er_sleep_tc_to_active_t_band(
2424 struct cxd2841er_priv *priv, u32 bandwidth)
2425{
2426 u8 data[MAX_WRITE_REGSIZE];
2427 u32 iffreq, ifhz;
2428 static const u8 nominalRate8bw[3][5] = {
2429
2430 {0x11, 0xF0, 0x00, 0x00, 0x00},
2431 {0x15, 0x00, 0x00, 0x00, 0x00},
2432 {0x11, 0xF0, 0x00, 0x00, 0x00}
2433 };
2434 static const u8 nominalRate7bw[3][5] = {
2435
2436 {0x14, 0x80, 0x00, 0x00, 0x00},
2437 {0x18, 0x00, 0x00, 0x00, 0x00},
2438 {0x14, 0x80, 0x00, 0x00, 0x00}
2439 };
2440 static const u8 nominalRate6bw[3][5] = {
2441
2442 {0x17, 0xEA, 0xAA, 0xAA, 0xAA},
2443 {0x1C, 0x00, 0x00, 0x00, 0x00},
2444 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}
2445 };
2446 static const u8 nominalRate5bw[3][5] = {
2447
2448 {0x1C, 0xB3, 0x33, 0x33, 0x33},
2449 {0x21, 0x99, 0x99, 0x99, 0x99},
2450 {0x1C, 0xB3, 0x33, 0x33, 0x33}
2451 };
2452
2453 static const u8 itbCoef8bw[3][14] = {
2454 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2455 0x1F, 0xA8, 0x2C, 0xC8},
2456 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2457 0x2A, 0xAC, 0x29, 0xB5},
2458 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2459 0x1F, 0xA8, 0x2C, 0xC8}
2460 };
2461 static const u8 itbCoef7bw[3][14] = {
2462 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2463 0x26, 0xA9, 0x21, 0xA5},
2464 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2465 0x2B, 0xA6, 0x2B, 0xAD},
2466 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2467 0x26, 0xA9, 0x21, 0xA5}
2468 };
2469 static const u8 itbCoef6bw[3][14] = {
2470 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2471 0x00, 0xE6, 0x23, 0xA4},
2472 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2473 0x29, 0xA2, 0x29, 0xA8},
2474 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2475 0x00, 0xE6, 0x23, 0xA4}
2476 };
2477 static const u8 itbCoef5bw[3][14] = {
2478 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2479 0x00, 0xE6, 0x23, 0xA4},
2480 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2481 0x29, 0xA2, 0x29, 0xA8},
2482 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2483 0x00, 0xE6, 0x23, 0xA4}
2484 };
2485
2486
2487 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2488
2489 data[0] = 0x01;
2490 data[1] = 0x14;
2491 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2492
2493
2494 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2495
2496 switch (bandwidth) {
2497 case 8000000:
2498
2499 cxd2841er_write_regs(priv, I2C_SLVT,
2500 0x9F, nominalRate8bw[priv->xtal], 5);
2501
2502
2503
2504 if (priv->flags & CXD2841ER_ASCOT)
2505 cxd2841er_write_regs(priv, I2C_SLVT,
2506 0xA6, itbCoef8bw[priv->xtal], 14);
2507
2508 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2509 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2510 data[0] = (u8) ((iffreq >> 16) & 0xff);
2511 data[1] = (u8)((iffreq >> 8) & 0xff);
2512 data[2] = (u8)(iffreq & 0xff);
2513 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2514
2515 cxd2841er_set_reg_bits(
2516 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2517
2518
2519 if (priv->xtal == SONY_XTAL_24000) {
2520 data[0] = 0x15;
2521 data[1] = 0x28;
2522 } else {
2523 data[0] = 0x01;
2524 data[1] = 0xE0;
2525 }
2526 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2527
2528
2529 data[0] = 0x01;
2530 data[1] = 0x02;
2531 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2532 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2533 break;
2534 case 7000000:
2535
2536 cxd2841er_write_regs(priv, I2C_SLVT,
2537 0x9F, nominalRate7bw[priv->xtal], 5);
2538
2539
2540
2541 if (priv->flags & CXD2841ER_ASCOT)
2542 cxd2841er_write_regs(priv, I2C_SLVT,
2543 0xA6, itbCoef7bw[priv->xtal], 14);
2544
2545 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2546 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2547 data[0] = (u8) ((iffreq >> 16) & 0xff);
2548 data[1] = (u8)((iffreq >> 8) & 0xff);
2549 data[2] = (u8)(iffreq & 0xff);
2550 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2551
2552 cxd2841er_set_reg_bits(
2553 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2554
2555
2556 if (priv->xtal == SONY_XTAL_24000) {
2557 data[0] = 0x1F;
2558 data[1] = 0xF8;
2559 } else {
2560 data[0] = 0x12;
2561 data[1] = 0xF8;
2562 }
2563 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2564
2565
2566 data[0] = 0x00;
2567 data[1] = 0x03;
2568 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2569 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2570 break;
2571 case 6000000:
2572
2573 cxd2841er_write_regs(priv, I2C_SLVT,
2574 0x9F, nominalRate6bw[priv->xtal], 5);
2575
2576
2577
2578 if (priv->flags & CXD2841ER_ASCOT)
2579 cxd2841er_write_regs(priv, I2C_SLVT,
2580 0xA6, itbCoef6bw[priv->xtal], 14);
2581
2582 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2583 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2584 data[0] = (u8) ((iffreq >> 16) & 0xff);
2585 data[1] = (u8)((iffreq >> 8) & 0xff);
2586 data[2] = (u8)(iffreq & 0xff);
2587 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2588
2589 cxd2841er_set_reg_bits(
2590 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2591
2592
2593 if (priv->xtal == SONY_XTAL_24000) {
2594 data[0] = 0x25;
2595 data[1] = 0x4C;
2596 } else {
2597 data[0] = 0x1F;
2598 data[1] = 0xDC;
2599 }
2600 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2601
2602
2603 data[0] = 0x00;
2604 data[1] = 0x03;
2605 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2606 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2607 break;
2608 case 5000000:
2609
2610 cxd2841er_write_regs(priv, I2C_SLVT,
2611 0x9F, nominalRate5bw[priv->xtal], 5);
2612
2613
2614
2615 if (priv->flags & CXD2841ER_ASCOT)
2616 cxd2841er_write_regs(priv, I2C_SLVT,
2617 0xA6, itbCoef5bw[priv->xtal], 14);
2618
2619 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2620 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2621 data[0] = (u8) ((iffreq >> 16) & 0xff);
2622 data[1] = (u8)((iffreq >> 8) & 0xff);
2623 data[2] = (u8)(iffreq & 0xff);
2624 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2625
2626 cxd2841er_set_reg_bits(
2627 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2628
2629
2630 if (priv->xtal == SONY_XTAL_24000) {
2631 data[0] = 0x2C;
2632 data[1] = 0xC2;
2633 } else {
2634 data[0] = 0x26;
2635 data[1] = 0x3C;
2636 }
2637 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2638
2639
2640 data[0] = 0x00;
2641 data[1] = 0x03;
2642 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2643 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2644 break;
2645 }
2646
2647 return 0;
2648}
2649
2650static int cxd2841er_sleep_tc_to_active_i_band(
2651 struct cxd2841er_priv *priv, u32 bandwidth)
2652{
2653 u32 iffreq, ifhz;
2654 u8 data[3];
2655
2656
2657 static const u8 nominalRate8bw[3][5] = {
2658 {0x00, 0x00, 0x00, 0x00, 0x00},
2659 {0x11, 0xB8, 0x00, 0x00, 0x00},
2660 {0x00, 0x00, 0x00, 0x00, 0x00}
2661 };
2662
2663 static const u8 nominalRate7bw[3][5] = {
2664 {0x00, 0x00, 0x00, 0x00, 0x00},
2665 {0x14, 0x40, 0x00, 0x00, 0x00},
2666 {0x00, 0x00, 0x00, 0x00, 0x00}
2667 };
2668
2669 static const u8 nominalRate6bw[3][5] = {
2670 {0x14, 0x2E, 0x00, 0x00, 0x00},
2671 {0x17, 0xA0, 0x00, 0x00, 0x00},
2672 {0x14, 0x2E, 0x00, 0x00, 0x00}
2673 };
2674
2675 static const u8 itbCoef8bw[3][14] = {
2676 {0x00},
2677 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2678 0xA5, 0x2A, 0xAC, 0x29, 0xB5},
2679 {0x0},
2680 };
2681
2682 static const u8 itbCoef7bw[3][14] = {
2683 {0x00},
2684 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2685 0xA2, 0x2B, 0xA6, 0x2B, 0xAD},
2686 {0x00},
2687 };
2688
2689 static const u8 itbCoef6bw[3][14] = {
2690 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2691 0xCF, 0x00, 0xE6, 0x23, 0xA4},
2692 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2693 0xA4, 0x29, 0xA2, 0x29, 0xA8},
2694 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2695 0xCF, 0x00, 0xE6, 0x23, 0xA4},
2696 };
2697
2698 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2699
2700 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2701
2702
2703
2704
2705 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2706 dev_err(&priv->i2c->dev,
2707 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2708 __func__, bandwidth);
2709 return -EINVAL;
2710 }
2711
2712 switch (bandwidth) {
2713 case 8000000:
2714
2715 cxd2841er_write_regs(priv, I2C_SLVT,
2716 0x9F, nominalRate8bw[priv->xtal], 5);
2717
2718 if (priv->flags & CXD2841ER_ASCOT)
2719 cxd2841er_write_regs(priv, I2C_SLVT,
2720 0xA6, itbCoef8bw[priv->xtal], 14);
2721
2722
2723 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2724 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2725 data[0] = (u8) ((iffreq >> 16) & 0xff);
2726 data[1] = (u8)((iffreq >> 8) & 0xff);
2727 data[2] = (u8)(iffreq & 0xff);
2728 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2729
2730
2731 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2732
2733
2734 data[0] = 0x13;
2735 data[1] = 0xFC;
2736 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2737
2738
2739 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2740 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2741 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2742 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2743 break;
2744 case 7000000:
2745
2746 cxd2841er_write_regs(priv, I2C_SLVT,
2747 0x9F, nominalRate7bw[priv->xtal], 5);
2748
2749 if (priv->flags & CXD2841ER_ASCOT)
2750 cxd2841er_write_regs(priv, I2C_SLVT,
2751 0xA6, itbCoef7bw[priv->xtal], 14);
2752
2753
2754 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2755 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2756 data[0] = (u8) ((iffreq >> 16) & 0xff);
2757 data[1] = (u8)((iffreq >> 8) & 0xff);
2758 data[2] = (u8)(iffreq & 0xff);
2759 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2760
2761
2762 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2763
2764
2765 data[0] = 0x1A;
2766 data[1] = 0xFA;
2767 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2768
2769
2770 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2771 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2772 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2773 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2774 break;
2775 case 6000000:
2776
2777 cxd2841er_write_regs(priv, I2C_SLVT,
2778 0x9F, nominalRate6bw[priv->xtal], 5);
2779
2780 if (priv->flags & CXD2841ER_ASCOT)
2781 cxd2841er_write_regs(priv, I2C_SLVT,
2782 0xA6, itbCoef6bw[priv->xtal], 14);
2783
2784
2785 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2786 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2787 data[0] = (u8) ((iffreq >> 16) & 0xff);
2788 data[1] = (u8)((iffreq >> 8) & 0xff);
2789 data[2] = (u8)(iffreq & 0xff);
2790 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2791
2792
2793 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2794
2795
2796 if (priv->xtal == SONY_XTAL_24000) {
2797 data[0] = 0x1F;
2798 data[1] = 0x79;
2799 } else {
2800 data[0] = 0x1A;
2801 data[1] = 0xE2;
2802 }
2803 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2804
2805
2806 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2807 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2808 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2809 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2810 break;
2811 default:
2812 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2813 __func__, bandwidth);
2814 return -EINVAL;
2815 }
2816 return 0;
2817}
2818
2819static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2820 u32 bandwidth)
2821{
2822 u8 bw7_8mhz_b10_a6[] = {
2823 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2824 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2825 u8 bw6mhz_b10_a6[] = {
2826 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2827 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2828 u8 b10_b6[3];
2829 u32 iffreq, ifhz;
2830
2831 if (bandwidth != 6000000 &&
2832 bandwidth != 7000000 &&
2833 bandwidth != 8000000) {
2834 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2835 __func__, bandwidth);
2836 bandwidth = 8000000;
2837 }
2838
2839 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2840 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2841 switch (bandwidth) {
2842 case 8000000:
2843 case 7000000:
2844 if (priv->flags & CXD2841ER_ASCOT)
2845 cxd2841er_write_regs(
2846 priv, I2C_SLVT, 0xa6,
2847 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2848 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2849 iffreq = cxd2841er_calc_iffreq(ifhz);
2850 break;
2851 case 6000000:
2852 if (priv->flags & CXD2841ER_ASCOT)
2853 cxd2841er_write_regs(
2854 priv, I2C_SLVT, 0xa6,
2855 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2856 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2857 iffreq = cxd2841er_calc_iffreq(ifhz);
2858 break;
2859 default:
2860 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2861 __func__, bandwidth);
2862 return -EINVAL;
2863 }
2864
2865 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2866 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2867 b10_b6[2] = (u8)(iffreq & 0xff);
2868 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2869
2870 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2871 switch (bandwidth) {
2872 case 8000000:
2873 case 7000000:
2874 cxd2841er_set_reg_bits(
2875 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2876 break;
2877 case 6000000:
2878 cxd2841er_set_reg_bits(
2879 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2880 break;
2881 }
2882
2883 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2884 switch (bandwidth) {
2885 case 8000000:
2886 cxd2841er_set_reg_bits(
2887 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2888 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2889 break;
2890 case 7000000:
2891 cxd2841er_set_reg_bits(
2892 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2893 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2894 break;
2895 case 6000000:
2896 cxd2841er_set_reg_bits(
2897 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2898 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2899 break;
2900 }
2901 return 0;
2902}
2903
2904static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2905 u32 bandwidth)
2906{
2907 u8 data[2] = { 0x09, 0x54 };
2908 u8 data24m[3] = {0xDC, 0x6C, 0x00};
2909
2910 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2911 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2912
2913 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2914
2915 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2916
2917 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2918
2919 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2920
2921 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2922
2923 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2924
2925 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2926
2927 if (priv->xtal == SONY_XTAL_41000) {
2928 data[0] = 0x0A;
2929 data[1] = 0xD4;
2930 }
2931 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2932
2933 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2934
2935 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2936
2937 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2938
2939 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2940
2941 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2942
2943 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2944
2945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2946 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2947
2948 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2949
2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2951
2952 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2953 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2954
2955 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2956
2957 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2958 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2959
2960 if (priv->xtal == SONY_XTAL_24000) {
2961
2962 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2963 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2964 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2965 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2966 }
2967
2968 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2969
2970 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2971
2972 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2973
2974 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2975 priv->state = STATE_ACTIVE_TC;
2976 return 0;
2977}
2978
2979static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2980 u32 bandwidth)
2981{
2982 u8 data[MAX_WRITE_REGSIZE];
2983
2984 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2985 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2986
2987 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2988
2989 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2990
2991 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2992
2993 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2994
2995 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2996 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2997
2998 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2999
3000 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3001
3002 if (priv->xtal == SONY_XTAL_41000) {
3003 data[0] = 0x0A;
3004 data[1] = 0xD4;
3005 } else {
3006 data[0] = 0x09;
3007 data[1] = 0x54;
3008 }
3009
3010 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3011
3012 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3013
3014 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3015
3016 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3017
3018 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3019
3020 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3021
3022 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3023
3024 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3025 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3026
3027 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3028
3029 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3030
3031 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3032 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3033
3034 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3035
3036 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3037
3038 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3039
3040 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3041 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3042
3043 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3044 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3045 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3046 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3047 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3048
3049 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3050 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3051
3052 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3053 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3054
3055
3056 if (priv->xtal == SONY_XTAL_24000) {
3057
3058 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3059 data[0] = 0xEB;
3060 data[1] = 0x03;
3061 data[2] = 0x3B;
3062 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3063
3064
3065 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3066 data[0] = 0x5E;
3067 data[1] = 0x5E;
3068 data[2] = 0x47;
3069 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3070
3071 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3072
3073 data[0] = 0x3F;
3074 data[1] = 0xFF;
3075 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3076
3077
3078 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3079 data[0] = 0x0B;
3080 data[1] = 0x72;
3081 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3082
3083 data[0] = 0x93;
3084 data[1] = 0xF3;
3085 data[2] = 0x00;
3086 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3087
3088 data[0] = 0x05;
3089 data[1] = 0xB8;
3090 data[2] = 0xD8;
3091 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3092
3093 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3094
3095
3096 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3097 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3098
3099
3100 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3101 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3102
3103
3104 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3105 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3106 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3107
3108
3109 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3110 data[0] = 0x89;
3111 data[1] = 0x89;
3112 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3113
3114
3115 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3116 data[0] = 0x24;
3117 data[1] = 0x95;
3118 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3119 }
3120
3121 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3122
3123
3124 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3125
3126 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3127
3128 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3129 priv->state = STATE_ACTIVE_TC;
3130 return 0;
3131}
3132
3133
3134static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3135 u32 bandwidth)
3136{
3137 u8 data[2] = { 0x09, 0x54 };
3138 u8 data24m[2] = {0x60, 0x00};
3139 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3140
3141 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3142 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3143
3144 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3145
3146 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3147
3148 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3149
3150 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3151
3152 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3153 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3154
3155 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3156
3157 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3158
3159 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3160
3161 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3162
3163 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3164 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3165
3166 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3167 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3168
3169
3170 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3171 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3172 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3173
3174 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3175 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3176 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3177 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3178 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3179 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3180 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3181 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3182 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3183
3184 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3185 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3186
3187 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3188 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3189
3190 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3191 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3192
3193
3194
3195 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3196 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3197
3198 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3199 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3200
3201 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3202
3203 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3204
3205 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3206
3207 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3208 priv->state = STATE_ACTIVE_TC;
3209 return 0;
3210}
3211
3212static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3213 u32 bandwidth)
3214{
3215 u8 data[2] = { 0x09, 0x54 };
3216
3217 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3218 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3219
3220 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3221
3222 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3223
3224 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3225
3226 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3227
3228 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3229 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3230
3231 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3232
3233 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3234
3235 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3236
3237 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3238
3239 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3240
3241 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3242
3243 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3244
3245 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3246
3247 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3248
3249 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3250 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3251
3252 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3253
3254 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3255
3256 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3257
3258 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3259 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3260
3261 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3262
3263 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3264
3265 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3266
3267 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3268 priv->state = STATE_ACTIVE_TC;
3269 return 0;
3270}
3271
3272static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3273 struct dtv_frontend_properties *p)
3274{
3275 enum fe_status status = 0;
3276 struct cxd2841er_priv *priv = fe->demodulator_priv;
3277
3278 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3279 if (priv->state == STATE_ACTIVE_S)
3280 cxd2841er_read_status_s(fe, &status);
3281 else if (priv->state == STATE_ACTIVE_TC)
3282 cxd2841er_read_status_tc(fe, &status);
3283
3284 if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3285 cxd2841er_read_signal_strength(fe);
3286 else
3287 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3288
3289 if (status & FE_HAS_LOCK) {
3290 cxd2841er_read_snr(fe);
3291 cxd2841er_read_ucblocks(fe);
3292
3293 cxd2841er_read_ber(fe);
3294 } else {
3295 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3296 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3297 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3298 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3299 }
3300 return 0;
3301}
3302
3303static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3304{
3305 int ret = 0, i, timeout, carr_offset;
3306 enum fe_status status;
3307 struct cxd2841er_priv *priv = fe->demodulator_priv;
3308 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3309 u32 symbol_rate = p->symbol_rate/1000;
3310
3311 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3312 __func__,
3313 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3314 p->frequency, symbol_rate, priv->xtal);
3315
3316 if (priv->flags & CXD2841ER_EARLY_TUNE)
3317 cxd2841er_tuner_set(fe);
3318
3319 switch (priv->state) {
3320 case STATE_SLEEP_S:
3321 ret = cxd2841er_sleep_s_to_active_s(
3322 priv, p->delivery_system, symbol_rate);
3323 break;
3324 case STATE_ACTIVE_S:
3325 ret = cxd2841er_retune_active(priv, p);
3326 break;
3327 default:
3328 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3329 __func__, priv->state);
3330 ret = -EINVAL;
3331 goto done;
3332 }
3333 if (ret) {
3334 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3335 goto done;
3336 }
3337
3338 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3339 cxd2841er_tuner_set(fe);
3340
3341 cxd2841er_tune_done(priv);
3342 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3343 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3344 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3345 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3346 cxd2841er_read_status_s(fe, &status);
3347 if (status & FE_HAS_LOCK)
3348 break;
3349 }
3350 if (status & FE_HAS_LOCK) {
3351 if (cxd2841er_get_carrier_offset_s_s2(
3352 priv, &carr_offset)) {
3353 ret = -EINVAL;
3354 goto done;
3355 }
3356 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3357 __func__, carr_offset);
3358 }
3359done:
3360
3361 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3362 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3363 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3364 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3365 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3366
3367 return ret;
3368}
3369
3370static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3371{
3372 int ret = 0, timeout;
3373 enum fe_status status;
3374 struct cxd2841er_priv *priv = fe->demodulator_priv;
3375 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3376
3377 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3378 __func__, p->delivery_system, p->bandwidth_hz);
3379
3380 if (priv->flags & CXD2841ER_EARLY_TUNE)
3381 cxd2841er_tuner_set(fe);
3382
3383
3384 if (priv->state == STATE_ACTIVE_TC &&
3385 priv->system != p->delivery_system) {
3386 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3387 __func__, priv->system, p->delivery_system);
3388 cxd2841er_sleep_tc(fe);
3389 }
3390
3391 if (p->delivery_system == SYS_DVBT) {
3392 priv->system = SYS_DVBT;
3393 switch (priv->state) {
3394 case STATE_SLEEP_TC:
3395 ret = cxd2841er_sleep_tc_to_active_t(
3396 priv, p->bandwidth_hz);
3397 break;
3398 case STATE_ACTIVE_TC:
3399 ret = cxd2841er_retune_active(priv, p);
3400 break;
3401 default:
3402 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3403 __func__, priv->state);
3404 ret = -EINVAL;
3405 }
3406 } else if (p->delivery_system == SYS_DVBT2) {
3407 priv->system = SYS_DVBT2;
3408 cxd2841er_dvbt2_set_plp_config(priv,
3409 (int)(p->stream_id > 255), p->stream_id);
3410 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3411 switch (priv->state) {
3412 case STATE_SLEEP_TC:
3413 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3414 p->bandwidth_hz);
3415 break;
3416 case STATE_ACTIVE_TC:
3417 ret = cxd2841er_retune_active(priv, p);
3418 break;
3419 default:
3420 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3421 __func__, priv->state);
3422 ret = -EINVAL;
3423 }
3424 } else if (p->delivery_system == SYS_ISDBT) {
3425 priv->system = SYS_ISDBT;
3426 switch (priv->state) {
3427 case STATE_SLEEP_TC:
3428 ret = cxd2841er_sleep_tc_to_active_i(
3429 priv, p->bandwidth_hz);
3430 break;
3431 case STATE_ACTIVE_TC:
3432 ret = cxd2841er_retune_active(priv, p);
3433 break;
3434 default:
3435 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3436 __func__, priv->state);
3437 ret = -EINVAL;
3438 }
3439 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3440 p->delivery_system == SYS_DVBC_ANNEX_C) {
3441 priv->system = SYS_DVBC_ANNEX_A;
3442
3443 if (p->bandwidth_hz != 6000000 &&
3444 p->bandwidth_hz != 7000000 &&
3445 p->bandwidth_hz != 8000000) {
3446 p->bandwidth_hz = 8000000;
3447 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3448 __func__, p->bandwidth_hz);
3449 }
3450
3451 switch (priv->state) {
3452 case STATE_SLEEP_TC:
3453 ret = cxd2841er_sleep_tc_to_active_c(
3454 priv, p->bandwidth_hz);
3455 break;
3456 case STATE_ACTIVE_TC:
3457 ret = cxd2841er_retune_active(priv, p);
3458 break;
3459 default:
3460 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3461 __func__, priv->state);
3462 ret = -EINVAL;
3463 }
3464 } else {
3465 dev_dbg(&priv->i2c->dev,
3466 "%s(): invalid delivery system %d\n",
3467 __func__, p->delivery_system);
3468 ret = -EINVAL;
3469 }
3470 if (ret)
3471 goto done;
3472
3473 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3474 cxd2841er_tuner_set(fe);
3475
3476 cxd2841er_tune_done(priv);
3477
3478 if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3479 goto done;
3480
3481 timeout = 2500;
3482 while (timeout > 0) {
3483 ret = cxd2841er_read_status_tc(fe, &status);
3484 if (ret)
3485 goto done;
3486 if (status & FE_HAS_LOCK)
3487 break;
3488 msleep(20);
3489 timeout -= 20;
3490 }
3491 if (timeout < 0)
3492 dev_dbg(&priv->i2c->dev,
3493 "%s(): LOCK wait timeout\n", __func__);
3494done:
3495 return ret;
3496}
3497
3498static int cxd2841er_tune_s(struct dvb_frontend *fe,
3499 bool re_tune,
3500 unsigned int mode_flags,
3501 unsigned int *delay,
3502 enum fe_status *status)
3503{
3504 int ret, carrier_offset;
3505 struct cxd2841er_priv *priv = fe->demodulator_priv;
3506 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3507
3508 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3509 if (re_tune) {
3510 ret = cxd2841er_set_frontend_s(fe);
3511 if (ret)
3512 return ret;
3513 cxd2841er_read_status_s(fe, status);
3514 if (*status & FE_HAS_LOCK) {
3515 if (cxd2841er_get_carrier_offset_s_s2(
3516 priv, &carrier_offset))
3517 return -EINVAL;
3518 p->frequency += carrier_offset;
3519 ret = cxd2841er_set_frontend_s(fe);
3520 if (ret)
3521 return ret;
3522 }
3523 }
3524 *delay = HZ / 5;
3525 return cxd2841er_read_status_s(fe, status);
3526}
3527
3528static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3529 bool re_tune,
3530 unsigned int mode_flags,
3531 unsigned int *delay,
3532 enum fe_status *status)
3533{
3534 int ret, carrier_offset;
3535 struct cxd2841er_priv *priv = fe->demodulator_priv;
3536 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3537
3538 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3539 re_tune, p->bandwidth_hz);
3540 if (re_tune) {
3541 ret = cxd2841er_set_frontend_tc(fe);
3542 if (ret)
3543 return ret;
3544 cxd2841er_read_status_tc(fe, status);
3545 if (*status & FE_HAS_LOCK) {
3546 switch (priv->system) {
3547 case SYS_ISDBT:
3548 ret = cxd2841er_get_carrier_offset_i(
3549 priv, p->bandwidth_hz,
3550 &carrier_offset);
3551 if (ret)
3552 return ret;
3553 break;
3554 case SYS_DVBT:
3555 ret = cxd2841er_get_carrier_offset_t(
3556 priv, p->bandwidth_hz,
3557 &carrier_offset);
3558 if (ret)
3559 return ret;
3560 break;
3561 case SYS_DVBT2:
3562 ret = cxd2841er_get_carrier_offset_t2(
3563 priv, p->bandwidth_hz,
3564 &carrier_offset);
3565 if (ret)
3566 return ret;
3567 break;
3568 case SYS_DVBC_ANNEX_A:
3569 ret = cxd2841er_get_carrier_offset_c(
3570 priv, &carrier_offset);
3571 if (ret)
3572 return ret;
3573 break;
3574 default:
3575 dev_dbg(&priv->i2c->dev,
3576 "%s(): invalid delivery system %d\n",
3577 __func__, priv->system);
3578 return -EINVAL;
3579 }
3580 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3581 __func__, carrier_offset);
3582 p->frequency += carrier_offset;
3583 ret = cxd2841er_set_frontend_tc(fe);
3584 if (ret)
3585 return ret;
3586 }
3587 }
3588 *delay = HZ / 5;
3589 return cxd2841er_read_status_tc(fe, status);
3590}
3591
3592static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3593{
3594 struct cxd2841er_priv *priv = fe->demodulator_priv;
3595
3596 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3597 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3598 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3599 return 0;
3600}
3601
3602static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3603{
3604 struct cxd2841er_priv *priv = fe->demodulator_priv;
3605
3606 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3607
3608 if (priv->state == STATE_ACTIVE_TC) {
3609 switch (priv->system) {
3610 case SYS_DVBT:
3611 cxd2841er_active_t_to_sleep_tc(priv);
3612 break;
3613 case SYS_DVBT2:
3614 cxd2841er_active_t2_to_sleep_tc(priv);
3615 break;
3616 case SYS_ISDBT:
3617 cxd2841er_active_i_to_sleep_tc(priv);
3618 break;
3619 case SYS_DVBC_ANNEX_A:
3620 cxd2841er_active_c_to_sleep_tc(priv);
3621 break;
3622 default:
3623 dev_warn(&priv->i2c->dev,
3624 "%s(): unknown delivery system %d\n",
3625 __func__, priv->system);
3626 }
3627 }
3628 if (priv->state != STATE_SLEEP_TC) {
3629 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3630 __func__, priv->state);
3631 return -EINVAL;
3632 }
3633 return 0;
3634}
3635
3636static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3637{
3638 struct cxd2841er_priv *priv = fe->demodulator_priv;
3639
3640 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3641
3642 if (!cxd2841er_sleep_tc(fe))
3643 cxd2841er_sleep_tc_to_shutdown(priv);
3644 return 0;
3645}
3646
3647static int cxd2841er_send_burst(struct dvb_frontend *fe,
3648 enum fe_sec_mini_cmd burst)
3649{
3650 u8 data;
3651 struct cxd2841er_priv *priv = fe->demodulator_priv;
3652
3653 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3654 (burst == SEC_MINI_A ? "A" : "B"));
3655 if (priv->state != STATE_SLEEP_S &&
3656 priv->state != STATE_ACTIVE_S) {
3657 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3658 __func__, priv->state);
3659 return -EINVAL;
3660 }
3661 data = (burst == SEC_MINI_A ? 0 : 1);
3662 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3663 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3664 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3665 return 0;
3666}
3667
3668static int cxd2841er_set_tone(struct dvb_frontend *fe,
3669 enum fe_sec_tone_mode tone)
3670{
3671 u8 data;
3672 struct cxd2841er_priv *priv = fe->demodulator_priv;
3673
3674 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3675 (tone == SEC_TONE_ON ? "On" : "Off"));
3676 if (priv->state != STATE_SLEEP_S &&
3677 priv->state != STATE_ACTIVE_S) {
3678 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3679 __func__, priv->state);
3680 return -EINVAL;
3681 }
3682 data = (tone == SEC_TONE_ON ? 1 : 0);
3683 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3684 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3685 return 0;
3686}
3687
3688static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3689 struct dvb_diseqc_master_cmd *cmd)
3690{
3691 int i;
3692 u8 data[12];
3693 struct cxd2841er_priv *priv = fe->demodulator_priv;
3694
3695 if (priv->state != STATE_SLEEP_S &&
3696 priv->state != STATE_ACTIVE_S) {
3697 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3698 __func__, priv->state);
3699 return -EINVAL;
3700 }
3701 dev_dbg(&priv->i2c->dev,
3702 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3703 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3704
3705 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3706
3707 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3708 memset(data, 0, sizeof(data));
3709 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3710 data[i] = cmd->msg[i];
3711 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3712
3713 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3714
3715 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3716
3717 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3718
3719 for (i = 0; i < 50; i++) {
3720 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3721 if (!data[0]) {
3722 dev_dbg(&priv->i2c->dev,
3723 "%s(): DiSEqC cmd has been sent\n", __func__);
3724 return 0;
3725 }
3726 msleep(20);
3727 }
3728 dev_dbg(&priv->i2c->dev,
3729 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3730 return -ETIMEDOUT;
3731}
3732
3733static void cxd2841er_release(struct dvb_frontend *fe)
3734{
3735 struct cxd2841er_priv *priv = fe->demodulator_priv;
3736
3737 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3738 kfree(priv);
3739}
3740
3741static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3742{
3743 struct cxd2841er_priv *priv = fe->demodulator_priv;
3744
3745 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3746 cxd2841er_set_reg_bits(
3747 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3748 return 0;
3749}
3750
3751static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3752{
3753 struct cxd2841er_priv *priv = fe->demodulator_priv;
3754
3755 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3756 return DVBFE_ALGO_HW;
3757}
3758
3759static void cxd2841er_init_stats(struct dvb_frontend *fe)
3760{
3761 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3762
3763 p->strength.len = 1;
3764 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3765 p->cnr.len = 1;
3766 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3767 p->block_error.len = 1;
3768 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3769 p->post_bit_error.len = 1;
3770 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3771 p->post_bit_count.len = 1;
3772 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3773}
3774
3775
3776static int cxd2841er_init_s(struct dvb_frontend *fe)
3777{
3778 struct cxd2841er_priv *priv = fe->demodulator_priv;
3779
3780
3781 if (priv->state == STATE_SLEEP_S) {
3782 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3783 __func__);
3784 cxd2841er_sleep_s_to_shutdown(priv);
3785 } else if (priv->state == STATE_ACTIVE_S) {
3786 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3787 __func__);
3788 cxd2841er_active_s_to_sleep_s(priv);
3789 cxd2841er_sleep_s_to_shutdown(priv);
3790 }
3791
3792 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3793 cxd2841er_shutdown_to_sleep_s(priv);
3794
3795 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3796 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3797
3798 cxd2841er_init_stats(fe);
3799
3800 return 0;
3801}
3802
3803static int cxd2841er_init_tc(struct dvb_frontend *fe)
3804{
3805 struct cxd2841er_priv *priv = fe->demodulator_priv;
3806 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3807
3808 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3809 __func__, p->bandwidth_hz);
3810 cxd2841er_shutdown_to_sleep_tc(priv);
3811
3812 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3813 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3814 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3815
3816 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3817
3818 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3819 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3820 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3821
3822
3823 if (priv->flags & CXD2841ER_TSBITS)
3824 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3825
3826 cxd2841er_init_stats(fe);
3827
3828 return 0;
3829}
3830
3831static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3832static struct dvb_frontend_ops cxd2841er_t_c_ops;
3833
3834static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3835 struct i2c_adapter *i2c,
3836 u8 system)
3837{
3838 u8 chip_id = 0;
3839 const char *type;
3840 const char *name;
3841 struct cxd2841er_priv *priv = NULL;
3842
3843
3844 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3845 if (!priv)
3846 return NULL;
3847 priv->i2c = i2c;
3848 priv->config = cfg;
3849 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3850 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3851 priv->xtal = cfg->xtal;
3852 priv->flags = cfg->flags;
3853 priv->frontend.demodulator_priv = priv;
3854 dev_info(&priv->i2c->dev,
3855 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3856 __func__, priv->i2c,
3857 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3858 chip_id = cxd2841er_chip_id(priv);
3859 switch (chip_id) {
3860 case CXD2837ER_CHIP_ID:
3861 snprintf(cxd2841er_t_c_ops.info.name, 128,
3862 "Sony CXD2837ER DVB-T/T2/C demodulator");
3863 name = "CXD2837ER";
3864 type = "C/T/T2";
3865 break;
3866 case CXD2838ER_CHIP_ID:
3867 snprintf(cxd2841er_t_c_ops.info.name, 128,
3868 "Sony CXD2838ER ISDB-T demodulator");
3869 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3870 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3871 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3872 name = "CXD2838ER";
3873 type = "ISDB-T";
3874 break;
3875 case CXD2841ER_CHIP_ID:
3876 snprintf(cxd2841er_t_c_ops.info.name, 128,
3877 "Sony CXD2841ER DVB-T/T2/C demodulator");
3878 name = "CXD2841ER";
3879 type = "T/T2/C/ISDB-T";
3880 break;
3881 case CXD2843ER_CHIP_ID:
3882 snprintf(cxd2841er_t_c_ops.info.name, 128,
3883 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3884 name = "CXD2843ER";
3885 type = "C/C2/T/T2";
3886 break;
3887 case CXD2854ER_CHIP_ID:
3888 snprintf(cxd2841er_t_c_ops.info.name, 128,
3889 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3890 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3891 name = "CXD2854ER";
3892 type = "C/C2/T/T2/ISDB-T";
3893 break;
3894 default:
3895 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3896 __func__, chip_id);
3897 priv->frontend.demodulator_priv = NULL;
3898 kfree(priv);
3899 return NULL;
3900 }
3901
3902
3903 if (system == SYS_DVBS) {
3904 memcpy(&priv->frontend.ops,
3905 &cxd2841er_dvbs_s2_ops,
3906 sizeof(struct dvb_frontend_ops));
3907 type = "S/S2";
3908 } else {
3909 memcpy(&priv->frontend.ops,
3910 &cxd2841er_t_c_ops,
3911 sizeof(struct dvb_frontend_ops));
3912 }
3913
3914 dev_info(&priv->i2c->dev,
3915 "%s(): attaching %s DVB-%s frontend\n",
3916 __func__, name, type);
3917 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3918 __func__, chip_id);
3919 return &priv->frontend;
3920}
3921
3922struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3923 struct i2c_adapter *i2c)
3924{
3925 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3926}
3927EXPORT_SYMBOL(cxd2841er_attach_s);
3928
3929struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3930 struct i2c_adapter *i2c)
3931{
3932 return cxd2841er_attach(cfg, i2c, 0);
3933}
3934EXPORT_SYMBOL(cxd2841er_attach_t_c);
3935
3936static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3937 .delsys = { SYS_DVBS, SYS_DVBS2 },
3938 .info = {
3939 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3940 .frequency_min = 500000,
3941 .frequency_max = 2500000,
3942 .frequency_stepsize = 0,
3943 .symbol_rate_min = 1000000,
3944 .symbol_rate_max = 45000000,
3945 .symbol_rate_tolerance = 500,
3946 .caps = FE_CAN_INVERSION_AUTO |
3947 FE_CAN_FEC_AUTO |
3948 FE_CAN_QPSK,
3949 },
3950 .init = cxd2841er_init_s,
3951 .sleep = cxd2841er_sleep_s,
3952 .release = cxd2841er_release,
3953 .set_frontend = cxd2841er_set_frontend_s,
3954 .get_frontend = cxd2841er_get_frontend,
3955 .read_status = cxd2841er_read_status_s,
3956 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3957 .get_frontend_algo = cxd2841er_get_algo,
3958 .set_tone = cxd2841er_set_tone,
3959 .diseqc_send_burst = cxd2841er_send_burst,
3960 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3961 .tune = cxd2841er_tune_s
3962};
3963
3964static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3965 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3966 .info = {
3967 .name = "",
3968 .caps = FE_CAN_FEC_1_2 |
3969 FE_CAN_FEC_2_3 |
3970 FE_CAN_FEC_3_4 |
3971 FE_CAN_FEC_5_6 |
3972 FE_CAN_FEC_7_8 |
3973 FE_CAN_FEC_AUTO |
3974 FE_CAN_QPSK |
3975 FE_CAN_QAM_16 |
3976 FE_CAN_QAM_32 |
3977 FE_CAN_QAM_64 |
3978 FE_CAN_QAM_128 |
3979 FE_CAN_QAM_256 |
3980 FE_CAN_QAM_AUTO |
3981 FE_CAN_TRANSMISSION_MODE_AUTO |
3982 FE_CAN_GUARD_INTERVAL_AUTO |
3983 FE_CAN_HIERARCHY_AUTO |
3984 FE_CAN_MUTE_TS |
3985 FE_CAN_2G_MODULATION,
3986 .frequency_min = 42000000,
3987 .frequency_max = 1002000000,
3988 .symbol_rate_min = 870000,
3989 .symbol_rate_max = 11700000
3990 },
3991 .init = cxd2841er_init_tc,
3992 .sleep = cxd2841er_shutdown_tc,
3993 .release = cxd2841er_release,
3994 .set_frontend = cxd2841er_set_frontend_tc,
3995 .get_frontend = cxd2841er_get_frontend,
3996 .read_status = cxd2841er_read_status_tc,
3997 .tune = cxd2841er_tune_tc,
3998 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3999 .get_frontend_algo = cxd2841er_get_algo
4000};
4001
4002MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4003MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4004MODULE_LICENSE("GPL");
4005
