LXR linux/drivers/media/i2c/adv748x/adv748x.h

   1/*
   2 * Driver for Analog Devices ADV748X video decoder and HDMI receiver
   3 *
   4 * Copyright (C) 2017 Renesas Electronics Corp.
   5 *
   6 * This program is free software; you can redistribute  it and/or modify it
   7 * under  the terms of  the GNU General  Public License as published by the
   8 * Free Software Foundation;  either version 2 of the  License, or (at your
   9 * option) any later version.
  10 *
  11 * Authors:
  12 *      Koji Matsuoka <koji.matsuoka.xm@renesas.com>
  13 *      Niklas Söderlund <niklas.soderlund@ragnatech.se>
  14 *      Kieran Bingham <kieran.bingham@ideasonboard.com>
  15 *
  16 * The ADV748x range of receivers have the following configurations:
  17 *
  18 *                  Analog   HDMI  MHL  4-Lane  1-Lane
  19 *                    In      In         CSI     CSI
  20 *       ADV7480               X    X     X
  21 *       ADV7481      X        X    X     X       X
  22 *       ADV7482      X        X          X       X
  23 */
  24
  25#include <linux/i2c.h>
  26
  27#ifndef _ADV748X_H_
  28#define _ADV748X_H_
  29
  30/* I2C slave addresses */
  31#define ADV748X_I2C_IO                  0x70    /* IO Map */
  32#define ADV748X_I2C_DPLL                0x26    /* DPLL Map */
  33#define ADV748X_I2C_CP                  0x22    /* CP Map */
  34#define ADV748X_I2C_HDMI                0x34    /* HDMI Map */
  35#define ADV748X_I2C_EDID                0x36    /* EDID Map */
  36#define ADV748X_I2C_REPEATER            0x32    /* HDMI RX Repeater Map */
  37#define ADV748X_I2C_INFOFRAME           0x31    /* HDMI RX InfoFrame Map */
  38#define ADV748X_I2C_CEC                 0x41    /* CEC Map */
  39#define ADV748X_I2C_SDP                 0x79    /* SDP Map */
  40#define ADV748X_I2C_TXB                 0x48    /* CSI-TXB Map */
  41#define ADV748X_I2C_TXA                 0x4a    /* CSI-TXA Map */
  42
  43enum adv748x_page {
  44        ADV748X_PAGE_IO,
  45        ADV748X_PAGE_DPLL,
  46        ADV748X_PAGE_CP,
  47        ADV748X_PAGE_HDMI,
  48        ADV748X_PAGE_EDID,
  49        ADV748X_PAGE_REPEATER,
  50        ADV748X_PAGE_INFOFRAME,
  51        ADV748X_PAGE_CEC,
  52        ADV748X_PAGE_SDP,
  53        ADV748X_PAGE_TXB,
  54        ADV748X_PAGE_TXA,
  55        ADV748X_PAGE_MAX,
  56
  57        /* Fake pages for register sequences */
  58        ADV748X_PAGE_WAIT,              /* Wait x msec */
  59        ADV748X_PAGE_EOR,               /* End Mark */
  60};
  61
  62/**
  63 * enum adv748x_ports - Device tree port number definitions
  64 *
  65 * The ADV748X ports define the mapping between subdevices
  66 * and the device tree specification
  67 */
  68enum adv748x_ports {
  69        ADV748X_PORT_AIN0 = 0,
  70        ADV748X_PORT_AIN1 = 1,
  71        ADV748X_PORT_AIN2 = 2,
  72        ADV748X_PORT_AIN3 = 3,
  73        ADV748X_PORT_AIN4 = 4,
  74        ADV748X_PORT_AIN5 = 5,
  75        ADV748X_PORT_AIN6 = 6,
  76        ADV748X_PORT_AIN7 = 7,
  77        ADV748X_PORT_HDMI = 8,
  78        ADV748X_PORT_TTL = 9,
  79        ADV748X_PORT_TXA = 10,
  80        ADV748X_PORT_TXB = 11,
  81        ADV748X_PORT_MAX = 12,
  82};
  83
  84enum adv748x_csi2_pads {
  85        ADV748X_CSI2_SINK,
  86        ADV748X_CSI2_SOURCE,
  87        ADV748X_CSI2_NR_PADS,
  88};
  89
  90/* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
  91#define ADV748X_CSI2_MAX_SUBDEVS 2
  92
  93struct adv748x_csi2 {
  94        struct adv748x_state *state;
  95        struct v4l2_mbus_framefmt format;
  96        unsigned int page;
  97
  98        struct media_pad pads[ADV748X_CSI2_NR_PADS];
  99        struct v4l2_ctrl_handler ctrl_hdl;
 100        struct v4l2_subdev sd;
 101};
 102
 103#define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
 104#define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
 105
 106enum adv748x_hdmi_pads {
 107        ADV748X_HDMI_SINK,
 108        ADV748X_HDMI_SOURCE,
 109        ADV748X_HDMI_NR_PADS,
 110};
 111
 112struct adv748x_hdmi {
 113        struct media_pad pads[ADV748X_HDMI_NR_PADS];
 114        struct v4l2_ctrl_handler ctrl_hdl;
 115        struct v4l2_subdev sd;
 116        struct v4l2_mbus_framefmt format;
 117
 118        struct v4l2_dv_timings timings;
 119        struct v4l2_fract aspect_ratio;
 120
 121        struct {
 122                u8 edid[512];
 123                u32 present;
 124                unsigned int blocks;
 125        } edid;
 126};
 127
 128#define adv748x_ctrl_to_hdmi(ctrl) \
 129        container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
 130#define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
 131
 132enum adv748x_afe_pads {
 133        ADV748X_AFE_SINK_AIN0,
 134        ADV748X_AFE_SINK_AIN1,
 135        ADV748X_AFE_SINK_AIN2,
 136        ADV748X_AFE_SINK_AIN3,
 137        ADV748X_AFE_SINK_AIN4,
 138        ADV748X_AFE_SINK_AIN5,
 139        ADV748X_AFE_SINK_AIN6,
 140        ADV748X_AFE_SINK_AIN7,
 141        ADV748X_AFE_SOURCE,
 142        ADV748X_AFE_NR_PADS,
 143};
 144
 145struct adv748x_afe {
 146        struct media_pad pads[ADV748X_AFE_NR_PADS];
 147        struct v4l2_ctrl_handler ctrl_hdl;
 148        struct v4l2_subdev sd;
 149        struct v4l2_mbus_framefmt format;
 150
 151        bool streaming;
 152        v4l2_std_id curr_norm;
 153        unsigned int input;
 154};
 155
 156#define adv748x_ctrl_to_afe(ctrl) \
 157        container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
 158#define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
 159
 160/**
 161 * struct adv748x_state - State of ADV748X
 162 * @dev:                (OF) device
 163 * @client:             I2C client
 164 * @mutex:              protect global state
 165 *
 166 * @endpoints:          parsed device node endpoints for each port
 167 *
 168 * @i2c_addresses       I2C Page addresses
 169 * @i2c_clients         I2C clients for the page accesses
 170 * @regmap              regmap configuration pages.
 171 *
 172 * @hdmi:               state of HDMI receiver context
 173 * @afe:                state of AFE receiver context
 174 * @txa:                state of TXA transmitter context
 175 * @txb:                state of TXB transmitter context
 176 */
 177struct adv748x_state {
 178        struct device *dev;
 179        struct i2c_client *client;
 180        struct mutex mutex;
 181
 182        struct device_node *endpoints[ADV748X_PORT_MAX];
 183
 184        struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
 185        struct regmap *regmap[ADV748X_PAGE_MAX];
 186
 187        struct adv748x_hdmi hdmi;
 188        struct adv748x_afe afe;
 189        struct adv748x_csi2 txa;
 190        struct adv748x_csi2 txb;
 191};
 192
 193#define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
 194#define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
 195
 196#define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
 197#define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
 198#define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
 199
 200/* Register Mappings */
 201
 202/* IO Map */
 203#define ADV748X_IO_PD                   0x00    /* power down controls */
 204#define ADV748X_IO_PD_RX_EN             BIT(6)
 205
 206#define ADV748X_IO_REG_04               0x04
 207#define ADV748X_IO_REG_04_FORCE_FR      BIT(0)  /* Force CP free-run */
 208
 209#define ADV748X_IO_DATAPATH             0x03    /* datapath cntrl */
 210#define ADV748X_IO_DATAPATH_VFREQ_M     0x70
 211#define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
 212
 213#define ADV748X_IO_VID_STD              0x05
 214
 215#define ADV748X_IO_10                   0x10    /* io_reg_10 */
 216#define ADV748X_IO_10_CSI4_EN           BIT(7)
 217#define ADV748X_IO_10_CSI1_EN           BIT(6)
 218#define ADV748X_IO_10_PIX_OUT_EN        BIT(5)
 219
 220#define ADV748X_IO_CHIP_REV_ID_1        0xdf
 221#define ADV748X_IO_CHIP_REV_ID_2        0xe0
 222
 223#define ADV748X_IO_SLAVE_ADDR_BASE      0xf2
 224
 225/* HDMI RX Map */
 226#define ADV748X_HDMI_LW1                0x07    /* line width_1 */
 227#define ADV748X_HDMI_LW1_VERT_FILTER    BIT(7)
 228#define ADV748X_HDMI_LW1_DE_REGEN       BIT(5)
 229#define ADV748X_HDMI_LW1_WIDTH_MASK     0x1fff
 230
 231#define ADV748X_HDMI_F0H1               0x09    /* field0 height_1 */
 232#define ADV748X_HDMI_F0H1_HEIGHT_MASK   0x1fff
 233
 234#define ADV748X_HDMI_F1H1               0x0b    /* field1 height_1 */
 235#define ADV748X_HDMI_F1H1_INTERLACED    BIT(5)
 236
 237#define ADV748X_HDMI_HFRONT_PORCH       0x20    /* hsync_front_porch_1 */
 238#define ADV748X_HDMI_HFRONT_PORCH_MASK  0x1fff
 239
 240#define ADV748X_HDMI_HSYNC_WIDTH        0x22    /* hsync_pulse_width_1 */
 241#define ADV748X_HDMI_HSYNC_WIDTH_MASK   0x1fff
 242
 243#define ADV748X_HDMI_HBACK_PORCH        0x24    /* hsync_back_porch_1 */
 244#define ADV748X_HDMI_HBACK_PORCH_MASK   0x1fff
 245
 246#define ADV748X_HDMI_VFRONT_PORCH       0x2a    /* field0_vs_front_porch_1 */
 247#define ADV748X_HDMI_VFRONT_PORCH_MASK  0x3fff
 248
 249#define ADV748X_HDMI_VSYNC_WIDTH        0x2e    /* field0_vs_pulse_width_1 */
 250#define ADV748X_HDMI_VSYNC_WIDTH_MASK   0x3fff
 251
 252#define ADV748X_HDMI_VBACK_PORCH        0x32    /* field0_vs_back_porch_1 */
 253#define ADV748X_HDMI_VBACK_PORCH_MASK   0x3fff
 254
 255#define ADV748X_HDMI_TMDS_1             0x51    /* hdmi_reg_51 */
 256#define ADV748X_HDMI_TMDS_2             0x52    /* hdmi_reg_52 */
 257
 258/* HDMI RX Repeater Map */
 259#define ADV748X_REPEATER_EDID_SZ        0x70    /* primary_edid_size */
 260#define ADV748X_REPEATER_EDID_SZ_SHIFT  4
 261
 262#define ADV748X_REPEATER_EDID_CTL       0x74    /* hdcp edid controls */
 263#define ADV748X_REPEATER_EDID_CTL_EN    BIT(0)  /* man_edid_a_enable */
 264
 265/* SDP Main Map */
 266#define ADV748X_SDP_INSEL               0x00    /* user_map_rw_reg_00 */
 267
 268#define ADV748X_SDP_VID_SEL             0x02    /* user_map_rw_reg_02 */
 269#define ADV748X_SDP_VID_SEL_MASK        0xf0
 270#define ADV748X_SDP_VID_SEL_SHIFT       4
 271
 272/* Contrast - Unsigned*/
 273#define ADV748X_SDP_CON                 0x08    /* user_map_rw_reg_08 */
 274#define ADV748X_SDP_CON_MIN             0
 275#define ADV748X_SDP_CON_DEF             128
 276#define ADV748X_SDP_CON_MAX             255
 277
 278/* Brightness - Signed */
 279#define ADV748X_SDP_BRI                 0x0a    /* user_map_rw_reg_0a */
 280#define ADV748X_SDP_BRI_MIN             -128
 281#define ADV748X_SDP_BRI_DEF             0
 282#define ADV748X_SDP_BRI_MAX             127
 283
 284/* Hue - Signed, inverted*/
 285#define ADV748X_SDP_HUE                 0x0b    /* user_map_rw_reg_0b */
 286#define ADV748X_SDP_HUE_MIN             -127
 287#define ADV748X_SDP_HUE_DEF             0
 288#define ADV748X_SDP_HUE_MAX             128
 289
 290/* Test Patterns / Default Values */
 291#define ADV748X_SDP_DEF                 0x0c    /* user_map_rw_reg_0c */
 292#define ADV748X_SDP_DEF_VAL_EN          BIT(0)  /* Force free run mode */
 293#define ADV748X_SDP_DEF_VAL_AUTO_EN     BIT(1)  /* Free run when no signal */
 294
 295#define ADV748X_SDP_MAP_SEL             0x0e    /* user_map_rw_reg_0e */
 296#define ADV748X_SDP_MAP_SEL_RO_MAIN     1
 297
 298/* Free run pattern select */
 299#define ADV748X_SDP_FRP                 0x14
 300#define ADV748X_SDP_FRP_MASK            GENMASK(3, 1)
 301
 302/* Saturation */
 303#define ADV748X_SDP_SD_SAT_U            0xe3    /* user_map_rw_reg_e3 */
 304#define ADV748X_SDP_SD_SAT_V            0xe4    /* user_map_rw_reg_e4 */
 305#define ADV748X_SDP_SAT_MIN             0
 306#define ADV748X_SDP_SAT_DEF             128
 307#define ADV748X_SDP_SAT_MAX             255
 308
 309/* SDP RO Main Map */
 310#define ADV748X_SDP_RO_10               0x10
 311#define ADV748X_SDP_RO_10_IN_LOCK       BIT(0)
 312
 313/* CP Map */
 314#define ADV748X_CP_PAT_GEN              0x37    /* int_pat_gen_1 */
 315#define ADV748X_CP_PAT_GEN_EN           BIT(7)
 316
 317/* Contrast Control - Unsigned */
 318#define ADV748X_CP_CON                  0x3a    /* contrast_cntrl */
 319#define ADV748X_CP_CON_MIN              0       /* Minimum contrast */
 320#define ADV748X_CP_CON_DEF              128     /* Default */
 321#define ADV748X_CP_CON_MAX              255     /* Maximum contrast */
 322
 323/* Saturation Control - Unsigned */
 324#define ADV748X_CP_SAT                  0x3b    /* saturation_cntrl */
 325#define ADV748X_CP_SAT_MIN              0       /* Minimum saturation */
 326#define ADV748X_CP_SAT_DEF              128     /* Default */
 327#define ADV748X_CP_SAT_MAX              255     /* Maximum saturation */
 328
 329/* Brightness Control - Signed */
 330#define ADV748X_CP_BRI                  0x3c    /* brightness_cntrl */
 331#define ADV748X_CP_BRI_MIN              -128    /* Luma is -512d */
 332#define ADV748X_CP_BRI_DEF              0       /* Luma is 0 */
 333#define ADV748X_CP_BRI_MAX              127     /* Luma is 508d */
 334
 335/* Hue Control */
 336#define ADV748X_CP_HUE                  0x3d    /* hue_cntrl */
 337#define ADV748X_CP_HUE_MIN              0       /* -90 degree */
 338#define ADV748X_CP_HUE_DEF              0       /* -90 degree */
 339#define ADV748X_CP_HUE_MAX              255     /* +90 degree */
 340
 341#define ADV748X_CP_VID_ADJ              0x3e    /* vid_adj_0 */
 342#define ADV748X_CP_VID_ADJ_ENABLE       BIT(7)  /* Enable colour controls */
 343
 344#define ADV748X_CP_DE_POS_HIGH          0x8b    /* de_pos_adj_6 */
 345#define ADV748X_CP_DE_POS_HIGH_SET      BIT(6)
 346#define ADV748X_CP_DE_POS_END_LOW       0x8c    /* de_pos_adj_7 */
 347#define ADV748X_CP_DE_POS_START_LOW     0x8d    /* de_pos_adj_8 */
 348
 349#define ADV748X_CP_VID_ADJ_2                    0x91
 350#define ADV748X_CP_VID_ADJ_2_INTERLACED         BIT(6)
 351#define ADV748X_CP_VID_ADJ_2_INTERLACED_3D      BIT(4)
 352
 353#define ADV748X_CP_CLMP_POS             0xc9    /* clmp_pos_cntrl_4 */
 354#define ADV748X_CP_CLMP_POS_DIS_AUTO    BIT(0)  /* dis_auto_param_buff */
 355
 356/* CSI : TXA/TXB Maps */
 357#define ADV748X_CSI_VC_REF              0x0d    /* csi_tx_top_reg_0d */
 358#define ADV748X_CSI_VC_REF_SHIFT        6
 359
 360#define ADV748X_CSI_FS_AS_LS            0x1e    /* csi_tx_top_reg_1e */
 361#define ADV748X_CSI_FS_AS_LS_UNKNOWN    BIT(6)  /* Undocumented bit */
 362
 363/* Register handling */
 364
 365int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
 366int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
 367int adv748x_write_block(struct adv748x_state *state, int client_page,
 368                        unsigned int init_reg, const void *val,
 369                        size_t val_len);
 370
 371#define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
 372#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
 373#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~m) | v)
 374
 375#define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
 376#define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, r+1)) & m)
 377#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
 378
 379#define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
 380#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
 381
 382#define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
 383#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
 384#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~m) | v)
 385
 386#define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
 387#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
 388#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~m) | v)
 389
 390#define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
 391#define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)
 392
 393#define tx_read(t, r) adv748x_read(t->state, t->page, r)
 394#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
 395
 396static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
 397{
 398        pad = media_entity_remote_pad(pad);
 399        if (!pad)
 400                return NULL;
 401
 402        return media_entity_to_v4l2_subdev(pad->entity);
 403}
 404
 405void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
 406                         const struct v4l2_subdev_ops *ops, u32 function,
 407                         const char *ident);
 408
 409int adv748x_register_subdevs(struct adv748x_state *state,
 410                             struct v4l2_device *v4l2_dev);
 411
 412int adv748x_txa_power(struct adv748x_state *state, bool on);
 413int adv748x_txb_power(struct adv748x_state *state, bool on);
 414
 415int adv748x_afe_init(struct adv748x_afe *afe);
 416void adv748x_afe_cleanup(struct adv748x_afe *afe);
 417
 418int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
 419void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
 420int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
 421
 422int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
 423void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
 424
 425#endif /* _ADV748X_H_ */
 426