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14#define pr_fmt(fmt) "%s: " fmt, __func__
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/ssbi.h>
26#include <linux/regmap.h>
27#include <linux/of_platform.h>
28#include <linux/mfd/core.h>
29
30#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
31
32#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
33#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
34#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
35#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
36#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
37#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
38#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
39#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
40#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
41
42#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
43#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
44#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
45#define PM8821_SSBI_REG(m, b, offset) \
46 ((m == 0) ? \
47 (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
48 (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
49#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
50#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
51#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
52#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
53
54#define PM8821_BLOCKS_PER_MASTER 7
55
56#define PM_IRQF_LVL_SEL 0x01
57#define PM_IRQF_MASK_FE 0x02
58#define PM_IRQF_MASK_RE 0x04
59#define PM_IRQF_CLR 0x08
60#define PM_IRQF_BITS_MASK 0x70
61#define PM_IRQF_BITS_SHIFT 4
62#define PM_IRQF_WRITE 0x80
63
64#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
65 PM_IRQF_MASK_RE)
66
67#define REG_HWREV 0x002
68#define REG_HWREV_2 0x0E8
69
70#define PM8XXX_NR_IRQS 256
71#define PM8821_NR_IRQS 112
72
73struct pm_irq_chip {
74 struct regmap *regmap;
75 spinlock_t pm_irq_lock;
76 struct irq_domain *irqdomain;
77 unsigned int num_irqs;
78 unsigned int num_blocks;
79 unsigned int num_masters;
80 u8 config[0];
81};
82
83struct pm_irq_data {
84 int num_irqs;
85 const struct irq_domain_ops *irq_domain_ops;
86 void (*irq_handler)(struct irq_desc *desc);
87};
88
89static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
90 unsigned int *ip)
91{
92 int rc;
93
94 spin_lock(&chip->pm_irq_lock);
95 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
96 if (rc) {
97 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
98 goto bail;
99 }
100
101 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
102 if (rc)
103 pr_err("Failed Reading Status rc=%d\n", rc);
104bail:
105 spin_unlock(&chip->pm_irq_lock);
106 return rc;
107}
108
109static int
110pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
111{
112 int rc;
113
114 spin_lock(&chip->pm_irq_lock);
115 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
116 if (rc) {
117 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
118 goto bail;
119 }
120
121 cp |= PM_IRQF_WRITE;
122 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
123 if (rc)
124 pr_err("Failed Configuring IRQ rc=%d\n", rc);
125bail:
126 spin_unlock(&chip->pm_irq_lock);
127 return rc;
128}
129
130static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
131{
132 int pmirq, irq, i, ret = 0;
133 unsigned int bits;
134
135 ret = pm8xxx_read_block_irq(chip, block, &bits);
136 if (ret) {
137 pr_err("Failed reading %d block ret=%d", block, ret);
138 return ret;
139 }
140 if (!bits) {
141 pr_err("block bit set in master but no irqs: %d", block);
142 return 0;
143 }
144
145
146 for (i = 0; i < 8; i++) {
147 if (bits & (1 << i)) {
148 pmirq = block * 8 + i;
149 irq = irq_find_mapping(chip->irqdomain, pmirq);
150 generic_handle_irq(irq);
151 }
152 }
153 return 0;
154}
155
156static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
157{
158 unsigned int blockbits;
159 int block_number, i, ret = 0;
160
161 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
162 &blockbits);
163 if (ret) {
164 pr_err("Failed to read master %d ret=%d\n", master, ret);
165 return ret;
166 }
167 if (!blockbits) {
168 pr_err("master bit set in root but no blocks: %d", master);
169 return 0;
170 }
171
172 for (i = 0; i < 8; i++)
173 if (blockbits & (1 << i)) {
174 block_number = master * 8 + i;
175 ret |= pm8xxx_irq_block_handler(chip, block_number);
176 }
177 return ret;
178}
179
180static void pm8xxx_irq_handler(struct irq_desc *desc)
181{
182 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
183 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
184 unsigned int root;
185 int i, ret, masters = 0;
186
187 chained_irq_enter(irq_chip, desc);
188
189 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
190 if (ret) {
191 pr_err("Can't read root status ret=%d\n", ret);
192 return;
193 }
194
195
196 masters = root >> 1;
197
198
199 for (i = 0; i < chip->num_masters; i++)
200 if (masters & (1 << i))
201 pm8xxx_irq_master_handler(chip, i);
202
203 chained_irq_exit(irq_chip, desc);
204}
205
206static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
207 int master, int block)
208{
209 int pmirq, irq, i, ret;
210 unsigned int bits;
211
212 ret = regmap_read(chip->regmap,
213 PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
214 if (ret) {
215 pr_err("Reading block %d failed ret=%d", block, ret);
216 return;
217 }
218
219
220 block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
221
222
223 for (i = 0; i < 8; i++) {
224 if (bits & BIT(i)) {
225 pmirq = block * 8 + i;
226 irq = irq_find_mapping(chip->irqdomain, pmirq);
227 generic_handle_irq(irq);
228 }
229 }
230}
231
232static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
233 int master, u8 master_val)
234{
235 int block;
236
237 for (block = 1; block < 8; block++)
238 if (master_val & BIT(block))
239 pm8821_irq_block_handler(chip, master, block);
240}
241
242static void pm8821_irq_handler(struct irq_desc *desc)
243{
244 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
245 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
246 unsigned int master;
247 int ret;
248
249 chained_irq_enter(irq_chip, desc);
250 ret = regmap_read(chip->regmap,
251 PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
252 if (ret) {
253 pr_err("Failed to read master 0 ret=%d\n", ret);
254 goto done;
255 }
256
257
258 if (master & GENMASK(7, 1))
259 pm8821_irq_master_handler(chip, 0, master);
260
261
262 if (!(master & BIT(0)))
263 goto done;
264
265 ret = regmap_read(chip->regmap,
266 PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
267 if (ret) {
268 pr_err("Failed to read master 1 ret=%d\n", ret);
269 goto done;
270 }
271
272 pm8821_irq_master_handler(chip, 1, master);
273
274done:
275 chained_irq_exit(irq_chip, desc);
276}
277
278static void pm8xxx_irq_mask_ack(struct irq_data *d)
279{
280 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
281 unsigned int pmirq = irqd_to_hwirq(d);
282 u8 block, config;
283
284 block = pmirq / 8;
285
286 config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
287 pm8xxx_config_irq(chip, block, config);
288}
289
290static void pm8xxx_irq_unmask(struct irq_data *d)
291{
292 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
293 unsigned int pmirq = irqd_to_hwirq(d);
294 u8 block, config;
295
296 block = pmirq / 8;
297
298 config = chip->config[pmirq];
299 pm8xxx_config_irq(chip, block, config);
300}
301
302static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
303{
304 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
305 unsigned int pmirq = irqd_to_hwirq(d);
306 int irq_bit;
307 u8 block, config;
308
309 block = pmirq / 8;
310 irq_bit = pmirq % 8;
311
312 chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
313 | PM_IRQF_MASK_ALL;
314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315 if (flow_type & IRQF_TRIGGER_RISING)
316 chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
317 if (flow_type & IRQF_TRIGGER_FALLING)
318 chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
319 } else {
320 chip->config[pmirq] |= PM_IRQF_LVL_SEL;
321
322 if (flow_type & IRQF_TRIGGER_HIGH)
323 chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
324 else
325 chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
326 }
327
328 config = chip->config[pmirq] | PM_IRQF_CLR;
329 return pm8xxx_config_irq(chip, block, config);
330}
331
332static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
333 enum irqchip_irq_state which,
334 bool *state)
335{
336 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
337 unsigned int pmirq = irqd_to_hwirq(d);
338 unsigned int bits;
339 int irq_bit;
340 u8 block;
341 int rc;
342
343 if (which != IRQCHIP_STATE_LINE_LEVEL)
344 return -EINVAL;
345
346 block = pmirq / 8;
347 irq_bit = pmirq % 8;
348
349 spin_lock(&chip->pm_irq_lock);
350 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
351 if (rc) {
352 pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
353 goto bail;
354 }
355
356 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
357 if (rc) {
358 pr_err("Failed Reading Status rc=%d\n", rc);
359 goto bail;
360 }
361
362 *state = !!(bits & BIT(irq_bit));
363bail:
364 spin_unlock(&chip->pm_irq_lock);
365
366 return rc;
367}
368
369static struct irq_chip pm8xxx_irq_chip = {
370 .name = "pm8xxx",
371 .irq_mask_ack = pm8xxx_irq_mask_ack,
372 .irq_unmask = pm8xxx_irq_unmask,
373 .irq_set_type = pm8xxx_irq_set_type,
374 .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
375 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
376};
377
378static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
379 irq_hw_number_t hwirq)
380{
381 struct pm_irq_chip *chip = d->host_data;
382
383 irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
384 irq_set_chip_data(irq, chip);
385 irq_set_noprobe(irq);
386
387 return 0;
388}
389
390static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
391 .xlate = irq_domain_xlate_twocell,
392 .map = pm8xxx_irq_domain_map,
393};
394
395static void pm8821_irq_mask_ack(struct irq_data *d)
396{
397 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
398 unsigned int pmirq = irqd_to_hwirq(d);
399 u8 block, master;
400 int irq_bit, rc;
401
402 block = pmirq / 8;
403 master = block / PM8821_BLOCKS_PER_MASTER;
404 irq_bit = pmirq % 8;
405 block %= PM8821_BLOCKS_PER_MASTER;
406
407 rc = regmap_update_bits(chip->regmap,
408 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
409 BIT(irq_bit), BIT(irq_bit));
410 if (rc) {
411 pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
412 return;
413 }
414
415 rc = regmap_update_bits(chip->regmap,
416 PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
417 BIT(irq_bit), BIT(irq_bit));
418 if (rc)
419 pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
420}
421
422static void pm8821_irq_unmask(struct irq_data *d)
423{
424 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
425 unsigned int pmirq = irqd_to_hwirq(d);
426 int irq_bit, rc;
427 u8 block, master;
428
429 block = pmirq / 8;
430 master = block / PM8821_BLOCKS_PER_MASTER;
431 irq_bit = pmirq % 8;
432 block %= PM8821_BLOCKS_PER_MASTER;
433
434 rc = regmap_update_bits(chip->regmap,
435 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
436 BIT(irq_bit), ~BIT(irq_bit));
437 if (rc)
438 pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
439
440}
441
442static int pm8821_irq_get_irqchip_state(struct irq_data *d,
443 enum irqchip_irq_state which,
444 bool *state)
445{
446 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
447 int rc, pmirq = irqd_to_hwirq(d);
448 u8 block, irq_bit, master;
449 unsigned int bits;
450
451 block = pmirq / 8;
452 master = block / PM8821_BLOCKS_PER_MASTER;
453 irq_bit = pmirq % 8;
454 block %= PM8821_BLOCKS_PER_MASTER;
455
456 rc = regmap_read(chip->regmap,
457 PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
458 if (rc) {
459 pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
460 return rc;
461 }
462
463 *state = !!(bits & BIT(irq_bit));
464
465 return rc;
466}
467
468static struct irq_chip pm8821_irq_chip = {
469 .name = "pm8821",
470 .irq_mask_ack = pm8821_irq_mask_ack,
471 .irq_unmask = pm8821_irq_unmask,
472 .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
473 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
474};
475
476static int pm8821_irq_domain_map(struct irq_domain *d, unsigned int irq,
477 irq_hw_number_t hwirq)
478{
479 struct pm_irq_chip *chip = d->host_data;
480
481 irq_set_chip_and_handler(irq, &pm8821_irq_chip, handle_level_irq);
482 irq_set_chip_data(irq, chip);
483 irq_set_noprobe(irq);
484
485 return 0;
486}
487
488static const struct irq_domain_ops pm8821_irq_domain_ops = {
489 .xlate = irq_domain_xlate_twocell,
490 .map = pm8821_irq_domain_map,
491};
492
493static const struct regmap_config ssbi_regmap_config = {
494 .reg_bits = 16,
495 .val_bits = 8,
496 .max_register = 0x3ff,
497 .fast_io = true,
498 .reg_read = ssbi_reg_read,
499 .reg_write = ssbi_reg_write
500};
501
502static const struct pm_irq_data pm8xxx_data = {
503 .num_irqs = PM8XXX_NR_IRQS,
504 .irq_domain_ops = &pm8xxx_irq_domain_ops,
505 .irq_handler = pm8xxx_irq_handler,
506};
507
508static const struct pm_irq_data pm8821_data = {
509 .num_irqs = PM8821_NR_IRQS,
510 .irq_domain_ops = &pm8821_irq_domain_ops,
511 .irq_handler = pm8821_irq_handler,
512};
513
514static const struct of_device_id pm8xxx_id_table[] = {
515 { .compatible = "qcom,pm8018", .data = &pm8xxx_data},
516 { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
517 { .compatible = "qcom,pm8821", .data = &pm8821_data},
518 { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
519 { }
520};
521MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
522
523static int pm8xxx_probe(struct platform_device *pdev)
524{
525 const struct pm_irq_data *data;
526 struct regmap *regmap;
527 int irq, rc;
528 unsigned int val;
529 u32 rev;
530 struct pm_irq_chip *chip;
531
532 data = of_device_get_match_data(&pdev->dev);
533 if (!data) {
534 dev_err(&pdev->dev, "No matching driver data found\n");
535 return -EINVAL;
536 }
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq < 0)
540 return irq;
541
542 regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
543 &ssbi_regmap_config);
544 if (IS_ERR(regmap))
545 return PTR_ERR(regmap);
546
547
548 rc = regmap_read(regmap, REG_HWREV, &val);
549 if (rc) {
550 pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
551 return rc;
552 }
553 pr_info("PMIC revision 1: %02X\n", val);
554 rev = val;
555
556
557 rc = regmap_read(regmap, REG_HWREV_2, &val);
558 if (rc) {
559 pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
560 REG_HWREV_2, rc);
561 return rc;
562 }
563 pr_info("PMIC revision 2: %02X\n", val);
564 rev |= val << BITS_PER_BYTE;
565
566 chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
567 sizeof(chip->config[0]) * data->num_irqs,
568 GFP_KERNEL);
569 if (!chip)
570 return -ENOMEM;
571
572 platform_set_drvdata(pdev, chip);
573 chip->regmap = regmap;
574 chip->num_irqs = data->num_irqs;
575 chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
576 chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
577 spin_lock_init(&chip->pm_irq_lock);
578
579 chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
580 data->num_irqs,
581 data->irq_domain_ops,
582 chip);
583 if (!chip->irqdomain)
584 return -ENODEV;
585
586 irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
587 irq_set_irq_wake(irq, 1);
588
589 rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
590 if (rc) {
591 irq_set_chained_handler_and_data(irq, NULL, NULL);
592 irq_domain_remove(chip->irqdomain);
593 }
594
595 return rc;
596}
597
598static int pm8xxx_remove_child(struct device *dev, void *unused)
599{
600 platform_device_unregister(to_platform_device(dev));
601 return 0;
602}
603
604static int pm8xxx_remove(struct platform_device *pdev)
605{
606 int irq = platform_get_irq(pdev, 0);
607 struct pm_irq_chip *chip = platform_get_drvdata(pdev);
608
609 device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
610 irq_set_chained_handler_and_data(irq, NULL, NULL);
611 irq_domain_remove(chip->irqdomain);
612
613 return 0;
614}
615
616static struct platform_driver pm8xxx_driver = {
617 .probe = pm8xxx_probe,
618 .remove = pm8xxx_remove,
619 .driver = {
620 .name = "pm8xxx-core",
621 .of_match_table = pm8xxx_id_table,
622 },
623};
624
625static int __init pm8xxx_init(void)
626{
627 return platform_driver_register(&pm8xxx_driver);
628}
629subsys_initcall(pm8xxx_init);
630
631static void __exit pm8xxx_exit(void)
632{
633 platform_driver_unregister(&pm8xxx_driver);
634}
635module_exit(pm8xxx_exit);
636
637MODULE_LICENSE("GPL v2");
638MODULE_DESCRIPTION("PMIC 8xxx core driver");
639MODULE_VERSION("1.0");
640MODULE_ALIAS("platform:pm8xxx-core");
641
