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11#ifndef _T3_H
12#define _T3_H
13
14#define TG3_64BIT_REG_HIGH 0x00UL
15#define TG3_64BIT_REG_LOW 0x04UL
16
17
18#define TG3_BDINFO_HOST_ADDR 0x0UL
19#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL
20#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001
21#define BDINFO_FLAGS_DISABLED 0x00000002
22#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
23#define BDINFO_FLAGS_MAXLEN_SHIFT 16
24#define TG3_BDINFO_NIC_ADDR 0xcUL
25#define TG3_BDINFO_SIZE 0x10UL
26
27#define TG3_RX_STD_MAX_SIZE_5700 512
28#define TG3_RX_STD_MAX_SIZE_5717 2048
29#define TG3_RX_JMB_MAX_SIZE_5700 256
30#define TG3_RX_JMB_MAX_SIZE_5717 1024
31#define TG3_RX_RET_MAX_SIZE_5700 1024
32#define TG3_RX_RET_MAX_SIZE_5705 512
33#define TG3_RX_RET_MAX_SIZE_5717 4096
34
35#define TG3_RSS_INDIR_TBL_SIZE 128
36
37
38#define TG3PCI_VENDOR 0x00000000
39#define TG3PCI_VENDOR_BROADCOM 0x14e4
40#define TG3PCI_DEVICE 0x00000002
41#define TG3PCI_DEVICE_TIGON3_1 0x1644
42#define TG3PCI_DEVICE_TIGON3_2 0x1645
43#define TG3PCI_DEVICE_TIGON3_3 0x1646
44#define TG3PCI_DEVICE_TIGON3_4 0x1647
45#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
46#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
47#define TG3PCI_DEVICE_TIGON3_57780 0x1692
48#define TG3PCI_DEVICE_TIGON3_5787M 0x1693
49#define TG3PCI_DEVICE_TIGON3_57760 0x1690
50#define TG3PCI_DEVICE_TIGON3_57790 0x1694
51#define TG3PCI_DEVICE_TIGON3_57788 0x1691
52#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699
53#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0
54#define TG3PCI_DEVICE_TIGON3_5717 0x1655
55#define TG3PCI_DEVICE_TIGON3_5717_C 0x1665
56#define TG3PCI_DEVICE_TIGON3_5718 0x1656
57#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
58#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
59#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
60#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
61#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
62#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
63#define TG3PCI_DEVICE_TIGON3_5719 0x1657
64#define TG3PCI_DEVICE_TIGON3_5720 0x165f
65#define TG3PCI_DEVICE_TIGON3_57762 0x1682
66#define TG3PCI_DEVICE_TIGON3_57766 0x1686
67#define TG3PCI_DEVICE_TIGON3_57786 0x16b3
68#define TG3PCI_DEVICE_TIGON3_57782 0x16b7
69#define TG3PCI_DEVICE_TIGON3_5762 0x1687
70#define TG3PCI_DEVICE_TIGON3_5725 0x1643
71#define TG3PCI_DEVICE_TIGON3_5727 0x16f3
72#define TG3PCI_DEVICE_TIGON3_57764 0x1642
73#define TG3PCI_DEVICE_TIGON3_57767 0x1683
74#define TG3PCI_DEVICE_TIGON3_57787 0x1641
75
76#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
77#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
78#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
79#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
80#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
81#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
82#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
83#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
84#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
85#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
86#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
87#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
88#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
89#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
90#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
91#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
92#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
93#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
94#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
95#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
96#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
97#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
98#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
99#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
100#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
101#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
102#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
103#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
104#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
105#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
106#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
107#define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601
108#define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612
109#define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056
110
111
112#define TG3PCI_MSI_DATA 0x00000064
113
114#define TG3PCI_MISC_HOST_CTRL 0x00000068
115#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
116#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
117#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
118#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
119#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
120#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
121#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
122#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
123#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
124#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
125#define MISC_HOST_CTRL_CHIPREV 0xffff0000
126#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
127
128#define CHIPREV_ID_5700_A0 0x7000
129#define CHIPREV_ID_5700_A1 0x7001
130#define CHIPREV_ID_5700_B0 0x7100
131#define CHIPREV_ID_5700_B1 0x7101
132#define CHIPREV_ID_5700_B3 0x7102
133#define CHIPREV_ID_5700_ALTIMA 0x7104
134#define CHIPREV_ID_5700_C0 0x7200
135#define CHIPREV_ID_5701_A0 0x0000
136#define CHIPREV_ID_5701_B0 0x0100
137#define CHIPREV_ID_5701_B2 0x0102
138#define CHIPREV_ID_5701_B5 0x0105
139#define CHIPREV_ID_5703_A0 0x1000
140#define CHIPREV_ID_5703_A1 0x1001
141#define CHIPREV_ID_5703_A2 0x1002
142#define CHIPREV_ID_5703_A3 0x1003
143#define CHIPREV_ID_5704_A0 0x2000
144#define CHIPREV_ID_5704_A1 0x2001
145#define CHIPREV_ID_5704_A2 0x2002
146#define CHIPREV_ID_5704_A3 0x2003
147#define CHIPREV_ID_5705_A0 0x3000
148#define CHIPREV_ID_5705_A1 0x3001
149#define CHIPREV_ID_5705_A2 0x3002
150#define CHIPREV_ID_5705_A3 0x3003
151#define CHIPREV_ID_5750_A0 0x4000
152#define CHIPREV_ID_5750_A1 0x4001
153#define CHIPREV_ID_5750_A3 0x4003
154#define CHIPREV_ID_5750_C2 0x4202
155#define CHIPREV_ID_5752_A0_HW 0x5000
156#define CHIPREV_ID_5752_A0 0x6000
157#define CHIPREV_ID_5752_A1 0x6001
158#define CHIPREV_ID_5714_A2 0x9002
159#define CHIPREV_ID_5906_A1 0xc001
160#define CHIPREV_ID_57780_A0 0x57780000
161#define CHIPREV_ID_57780_A1 0x57780001
162#define CHIPREV_ID_5717_A0 0x05717000
163#define CHIPREV_ID_5717_C0 0x05717200
164#define CHIPREV_ID_57765_A0 0x57785000
165#define CHIPREV_ID_5719_A0 0x05719000
166#define CHIPREV_ID_5720_A0 0x05720000
167#define CHIPREV_ID_5762_A0 0x05762000
168
169#define ASIC_REV_5700 0x07
170#define ASIC_REV_5701 0x00
171#define ASIC_REV_5703 0x01
172#define ASIC_REV_5704 0x02
173#define ASIC_REV_5705 0x03
174#define ASIC_REV_5750 0x04
175#define ASIC_REV_5752 0x06
176#define ASIC_REV_5780 0x08
177#define ASIC_REV_5714 0x09
178#define ASIC_REV_5755 0x0a
179#define ASIC_REV_5787 0x0b
180#define ASIC_REV_5906 0x0c
181#define ASIC_REV_USE_PROD_ID_REG 0x0f
182#define ASIC_REV_5784 0x5784
183#define ASIC_REV_5761 0x5761
184#define ASIC_REV_5785 0x5785
185#define ASIC_REV_57780 0x57780
186#define ASIC_REV_5717 0x5717
187#define ASIC_REV_57765 0x57785
188#define ASIC_REV_5719 0x5719
189#define ASIC_REV_5720 0x5720
190#define ASIC_REV_57766 0x57766
191#define ASIC_REV_5762 0x5762
192#define CHIPREV_5700_AX 0x70
193#define CHIPREV_5700_BX 0x71
194#define CHIPREV_5700_CX 0x72
195#define CHIPREV_5701_AX 0x00
196#define CHIPREV_5703_AX 0x10
197#define CHIPREV_5704_AX 0x20
198#define CHIPREV_5704_BX 0x21
199#define CHIPREV_5750_AX 0x40
200#define CHIPREV_5750_BX 0x41
201#define CHIPREV_5784_AX 0x57840
202#define CHIPREV_5761_AX 0x57610
203#define CHIPREV_57765_AX 0x577650
204#define METAL_REV_A0 0x00
205#define METAL_REV_A1 0x01
206#define METAL_REV_B0 0x00
207#define METAL_REV_B1 0x01
208#define METAL_REV_B2 0x02
209#define TG3PCI_DMA_RW_CTRL 0x0000006c
210#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
211#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
212#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
213#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
214#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
215#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
216#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
217#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
218#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
219#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
220#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
221#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
222#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
223#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
224#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
225#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
226#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
227#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
228#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
229#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
230#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
231#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
232#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
233#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
234#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
235#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
236#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
237#define DMA_RWCTRL_ONE_DMA 0x00004000
238#define DMA_RWCTRL_READ_WATER 0x00070000
239#define DMA_RWCTRL_READ_WATER_SHIFT 16
240#define DMA_RWCTRL_WRITE_WATER 0x00380000
241#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
242#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
243#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
244#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
245#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
246#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
247#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
248#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
249#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
250#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
251#define TG3PCI_PCISTATE 0x00000070
252#define PCISTATE_FORCE_RESET 0x00000001
253#define PCISTATE_INT_NOT_ACTIVE 0x00000002
254#define PCISTATE_CONV_PCI_MODE 0x00000004
255#define PCISTATE_BUS_SPEED_HIGH 0x00000008
256#define PCISTATE_BUS_32BIT 0x00000010
257#define PCISTATE_ROM_ENABLE 0x00000020
258#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
259#define PCISTATE_FLAT_VIEW 0x00000100
260#define PCISTATE_RETRY_SAME_DMA 0x00002000
261#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
262#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
263#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
264#define TG3PCI_CLOCK_CTRL 0x00000074
265#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
266#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
267#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
268#define CLOCK_CTRL_ALTCLK 0x00001000
269#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
270#define CLOCK_CTRL_44MHZ_CORE 0x00040000
271#define CLOCK_CTRL_625_CORE 0x00100000
272#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
273#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
274#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
275#define TG3PCI_REG_BASE_ADDR 0x00000078
276#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
277#define TG3PCI_REG_DATA 0x00000080
278#define TG3PCI_MEM_WIN_DATA 0x00000084
279#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
280
281#define TG3PCI_STD_RING_PROD_IDX 0x00000098
282#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0
283
284#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
285#define DUAL_MAC_CTRL_CH_MASK 0x00000003
286#define DUAL_MAC_CTRL_ID 0x00000004
287#define TG3PCI_PRODID_ASICREV 0x000000bc
288#define PROD_ID_ASIC_REV_MASK 0x0fffffff
289
290
291#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
292#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
293
294
295#define TG3_CORR_ERR_STAT 0x00000110
296#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
297
298
299
300#define MAILBOX_INTERRUPT_0 0x00000200
301#define MAILBOX_INTERRUPT_1 0x00000208
302#define MAILBOX_INTERRUPT_2 0x00000210
303#define MAILBOX_INTERRUPT_3 0x00000218
304#define MAILBOX_GENERAL_0 0x00000220
305#define MAILBOX_GENERAL_1 0x00000228
306#define MAILBOX_GENERAL_2 0x00000230
307#define MAILBOX_GENERAL_3 0x00000238
308#define MAILBOX_GENERAL_4 0x00000240
309#define MAILBOX_GENERAL_5 0x00000248
310#define MAILBOX_GENERAL_6 0x00000250
311#define MAILBOX_GENERAL_7 0x00000258
312#define MAILBOX_RELOAD_STAT 0x00000260
313#define MAILBOX_RCV_STD_PROD_IDX 0x00000268
314#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
315 TG3_64BIT_REG_LOW)
316#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270
317#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
318 TG3_64BIT_REG_LOW)
319#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278
320#define MAILBOX_RCVRET_CON_IDX_0 0x00000280
321#define MAILBOX_RCVRET_CON_IDX_1 0x00000288
322#define MAILBOX_RCVRET_CON_IDX_2 0x00000290
323#define MAILBOX_RCVRET_CON_IDX_3 0x00000298
324#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0
325#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8
326#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0
327#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8
328#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0
329#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8
330#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0
331#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8
332#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0
333#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8
334#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0
335#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8
336#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300
337#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308
338#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310
339#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318
340#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320
341#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328
342#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330
343#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338
344#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340
345#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348
346#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350
347#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358
348#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360
349#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368
350#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370
351#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378
352#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380
353#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388
354#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390
355#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398
356#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0
357#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8
358#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0
359#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8
360#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0
361#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8
362#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0
363#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8
364#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0
365#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8
366#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0
367#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8
368
369
370#define MAC_MODE 0x00000400
371#define MAC_MODE_RESET 0x00000001
372#define MAC_MODE_HALF_DUPLEX 0x00000002
373#define MAC_MODE_PORT_MODE_MASK 0x0000000c
374#define MAC_MODE_PORT_MODE_TBI 0x0000000c
375#define MAC_MODE_PORT_MODE_GMII 0x00000008
376#define MAC_MODE_PORT_MODE_MII 0x00000004
377#define MAC_MODE_PORT_MODE_NONE 0x00000000
378#define MAC_MODE_PORT_INT_LPBACK 0x00000010
379#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
380#define MAC_MODE_TX_BURSTING 0x00000100
381#define MAC_MODE_MAX_DEFER 0x00000200
382#define MAC_MODE_LINK_POLARITY 0x00000400
383#define MAC_MODE_RXSTAT_ENABLE 0x00000800
384#define MAC_MODE_RXSTAT_CLEAR 0x00001000
385#define MAC_MODE_RXSTAT_FLUSH 0x00002000
386#define MAC_MODE_TXSTAT_ENABLE 0x00004000
387#define MAC_MODE_TXSTAT_CLEAR 0x00008000
388#define MAC_MODE_TXSTAT_FLUSH 0x00010000
389#define MAC_MODE_SEND_CONFIGS 0x00020000
390#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
391#define MAC_MODE_ACPI_ENABLE 0x00080000
392#define MAC_MODE_MIP_ENABLE 0x00100000
393#define MAC_MODE_TDE_ENABLE 0x00200000
394#define MAC_MODE_RDE_ENABLE 0x00400000
395#define MAC_MODE_FHDE_ENABLE 0x00800000
396#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
397#define MAC_MODE_APE_RX_EN 0x08000000
398#define MAC_MODE_APE_TX_EN 0x10000000
399#define MAC_STATUS 0x00000404
400#define MAC_STATUS_PCS_SYNCED 0x00000001
401#define MAC_STATUS_SIGNAL_DET 0x00000002
402#define MAC_STATUS_RCVD_CFG 0x00000004
403#define MAC_STATUS_CFG_CHANGED 0x00000008
404#define MAC_STATUS_SYNC_CHANGED 0x00000010
405#define MAC_STATUS_PORT_DEC_ERR 0x00000400
406#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
407#define MAC_STATUS_MI_COMPLETION 0x00400000
408#define MAC_STATUS_MI_INTERRUPT 0x00800000
409#define MAC_STATUS_AP_ERROR 0x01000000
410#define MAC_STATUS_ODI_ERROR 0x02000000
411#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
412#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
413#define MAC_EVENT 0x00000408
414#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
415#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
416#define MAC_EVENT_MI_COMPLETION 0x00400000
417#define MAC_EVENT_MI_INTERRUPT 0x00800000
418#define MAC_EVENT_AP_ERROR 0x01000000
419#define MAC_EVENT_ODI_ERROR 0x02000000
420#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
421#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
422#define MAC_LED_CTRL 0x0000040c
423#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
424#define LED_CTRL_1000MBPS_ON 0x00000002
425#define LED_CTRL_100MBPS_ON 0x00000004
426#define LED_CTRL_10MBPS_ON 0x00000008
427#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
428#define LED_CTRL_TRAFFIC_BLINK 0x00000020
429#define LED_CTRL_TRAFFIC_LED 0x00000040
430#define LED_CTRL_1000MBPS_STATUS 0x00000080
431#define LED_CTRL_100MBPS_STATUS 0x00000100
432#define LED_CTRL_10MBPS_STATUS 0x00000200
433#define LED_CTRL_TRAFFIC_STATUS 0x00000400
434#define LED_CTRL_MODE_MAC 0x00000000
435#define LED_CTRL_MODE_PHY_1 0x00000800
436#define LED_CTRL_MODE_PHY_2 0x00001000
437#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
438#define LED_CTRL_MODE_SHARED 0x00004000
439#define LED_CTRL_MODE_COMBO 0x00008000
440#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
441#define LED_CTRL_BLINK_RATE_SHIFT 19
442#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
443#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
444#define MAC_ADDR_0_HIGH 0x00000410
445#define MAC_ADDR_0_LOW 0x00000414
446#define MAC_ADDR_1_HIGH 0x00000418
447#define MAC_ADDR_1_LOW 0x0000041c
448#define MAC_ADDR_2_HIGH 0x00000420
449#define MAC_ADDR_2_LOW 0x00000424
450#define MAC_ADDR_3_HIGH 0x00000428
451#define MAC_ADDR_3_LOW 0x0000042c
452#define MAC_ACPI_MBUF_PTR 0x00000430
453#define MAC_ACPI_LEN_OFFSET 0x00000434
454#define ACPI_LENOFF_LEN_MASK 0x0000ffff
455#define ACPI_LENOFF_LEN_SHIFT 0
456#define ACPI_LENOFF_OFF_MASK 0x0fff0000
457#define ACPI_LENOFF_OFF_SHIFT 16
458#define MAC_TX_BACKOFF_SEED 0x00000438
459#define TX_BACKOFF_SEED_MASK 0x000003ff
460#define MAC_RX_MTU_SIZE 0x0000043c
461#define RX_MTU_SIZE_MASK 0x0000ffff
462#define MAC_PCS_TEST 0x00000440
463#define PCS_TEST_PATTERN_MASK 0x000fffff
464#define PCS_TEST_PATTERN_SHIFT 0
465#define PCS_TEST_ENABLE 0x00100000
466#define MAC_TX_AUTO_NEG 0x00000444
467#define TX_AUTO_NEG_MASK 0x0000ffff
468#define TX_AUTO_NEG_SHIFT 0
469#define MAC_RX_AUTO_NEG 0x00000448
470#define RX_AUTO_NEG_MASK 0x0000ffff
471#define RX_AUTO_NEG_SHIFT 0
472#define MAC_MI_COM 0x0000044c
473#define MI_COM_CMD_MASK 0x0c000000
474#define MI_COM_CMD_WRITE 0x04000000
475#define MI_COM_CMD_READ 0x08000000
476#define MI_COM_READ_FAILED 0x10000000
477#define MI_COM_START 0x20000000
478#define MI_COM_BUSY 0x20000000
479#define MI_COM_PHY_ADDR_MASK 0x03e00000
480#define MI_COM_PHY_ADDR_SHIFT 21
481#define MI_COM_REG_ADDR_MASK 0x001f0000
482#define MI_COM_REG_ADDR_SHIFT 16
483#define MI_COM_DATA_MASK 0x0000ffff
484#define MAC_MI_STAT 0x00000450
485#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
486#define MAC_MI_STAT_10MBPS_MODE 0x00000002
487#define MAC_MI_MODE 0x00000454
488#define MAC_MI_MODE_CLK_10MHZ 0x00000001
489#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
490#define MAC_MI_MODE_AUTO_POLL 0x00000010
491#define MAC_MI_MODE_500KHZ_CONST 0x00008000
492#define MAC_MI_MODE_BASE 0x000c0000
493#define MAC_AUTO_POLL_STATUS 0x00000458
494#define MAC_AUTO_POLL_ERROR 0x00000001
495#define MAC_TX_MODE 0x0000045c
496#define TX_MODE_RESET 0x00000001
497#define TX_MODE_ENABLE 0x00000002
498#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
499#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
500#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
501#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
502#define TX_MODE_JMB_FRM_LEN 0x00400000
503#define TX_MODE_CNT_DN_MODE 0x00800000
504#define MAC_TX_STATUS 0x00000460
505#define TX_STATUS_XOFFED 0x00000001
506#define TX_STATUS_SENT_XOFF 0x00000002
507#define TX_STATUS_SENT_XON 0x00000004
508#define TX_STATUS_LINK_UP 0x00000008
509#define TX_STATUS_ODI_UNDERRUN 0x00000010
510#define TX_STATUS_ODI_OVERRUN 0x00000020
511#define MAC_TX_LENGTHS 0x00000464
512#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
513#define TX_LENGTHS_SLOT_TIME_SHIFT 0
514#define TX_LENGTHS_IPG_MASK 0x00000f00
515#define TX_LENGTHS_IPG_SHIFT 8
516#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
517#define TX_LENGTHS_IPG_CRS_SHIFT 12
518#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
519#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
520#define MAC_RX_MODE 0x00000468
521#define RX_MODE_RESET 0x00000001
522#define RX_MODE_ENABLE 0x00000002
523#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
524#define RX_MODE_KEEP_MAC_CTRL 0x00000008
525#define RX_MODE_KEEP_PAUSE 0x00000010
526#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
527#define RX_MODE_ACCEPT_RUNTS 0x00000040
528#define RX_MODE_LEN_CHECK 0x00000080
529#define RX_MODE_PROMISC 0x00000100
530#define RX_MODE_NO_CRC_CHECK 0x00000200
531#define RX_MODE_KEEP_VLAN_TAG 0x00000400
532#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
533#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
534#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
535#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
536#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
537#define RX_MODE_RSS_ENABLE 0x00800000
538#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
539#define RX_MODE_IPV4_FRAG_FIX 0x02000000
540#define MAC_RX_STATUS 0x0000046c
541#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
542#define RX_STATUS_XOFF_RCVD 0x00000002
543#define RX_STATUS_XON_RCVD 0x00000004
544#define MAC_HASH_REG_0 0x00000470
545#define MAC_HASH_REG_1 0x00000474
546#define MAC_HASH_REG_2 0x00000478
547#define MAC_HASH_REG_3 0x0000047c
548#define MAC_RCV_RULE_0 0x00000480
549#define MAC_RCV_VALUE_0 0x00000484
550#define MAC_RCV_RULE_1 0x00000488
551#define MAC_RCV_VALUE_1 0x0000048c
552#define MAC_RCV_RULE_2 0x00000490
553#define MAC_RCV_VALUE_2 0x00000494
554#define MAC_RCV_RULE_3 0x00000498
555#define MAC_RCV_VALUE_3 0x0000049c
556#define MAC_RCV_RULE_4 0x000004a0
557#define MAC_RCV_VALUE_4 0x000004a4
558#define MAC_RCV_RULE_5 0x000004a8
559#define MAC_RCV_VALUE_5 0x000004ac
560#define MAC_RCV_RULE_6 0x000004b0
561#define MAC_RCV_VALUE_6 0x000004b4
562#define MAC_RCV_RULE_7 0x000004b8
563#define MAC_RCV_VALUE_7 0x000004bc
564#define MAC_RCV_RULE_8 0x000004c0
565#define MAC_RCV_VALUE_8 0x000004c4
566#define MAC_RCV_RULE_9 0x000004c8
567#define MAC_RCV_VALUE_9 0x000004cc
568#define MAC_RCV_RULE_10 0x000004d0
569#define MAC_RCV_VALUE_10 0x000004d4
570#define MAC_RCV_RULE_11 0x000004d8
571#define MAC_RCV_VALUE_11 0x000004dc
572#define MAC_RCV_RULE_12 0x000004e0
573#define MAC_RCV_VALUE_12 0x000004e4
574#define MAC_RCV_RULE_13 0x000004e8
575#define MAC_RCV_VALUE_13 0x000004ec
576#define MAC_RCV_RULE_14 0x000004f0
577#define MAC_RCV_VALUE_14 0x000004f4
578#define MAC_RCV_RULE_15 0x000004f8
579#define MAC_RCV_VALUE_15 0x000004fc
580#define RCV_RULE_DISABLE_MASK 0x7fffffff
581#define MAC_RCV_RULE_CFG 0x00000500
582#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
583#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
584
585#define MAC_HASHREGU_0 0x00000520
586#define MAC_HASHREGU_1 0x00000524
587#define MAC_HASHREGU_2 0x00000528
588#define MAC_HASHREGU_3 0x0000052c
589#define MAC_EXTADDR_0_HIGH 0x00000530
590#define MAC_EXTADDR_0_LOW 0x00000534
591#define MAC_EXTADDR_1_HIGH 0x00000538
592#define MAC_EXTADDR_1_LOW 0x0000053c
593#define MAC_EXTADDR_2_HIGH 0x00000540
594#define MAC_EXTADDR_2_LOW 0x00000544
595#define MAC_EXTADDR_3_HIGH 0x00000548
596#define MAC_EXTADDR_3_LOW 0x0000054c
597#define MAC_EXTADDR_4_HIGH 0x00000550
598#define MAC_EXTADDR_4_LOW 0x00000554
599#define MAC_EXTADDR_5_HIGH 0x00000558
600#define MAC_EXTADDR_5_LOW 0x0000055c
601#define MAC_EXTADDR_6_HIGH 0x00000560
602#define MAC_EXTADDR_6_LOW 0x00000564
603#define MAC_EXTADDR_7_HIGH 0x00000568
604#define MAC_EXTADDR_7_LOW 0x0000056c
605#define MAC_EXTADDR_8_HIGH 0x00000570
606#define MAC_EXTADDR_8_LOW 0x00000574
607#define MAC_EXTADDR_9_HIGH 0x00000578
608#define MAC_EXTADDR_9_LOW 0x0000057c
609#define MAC_EXTADDR_10_HIGH 0x00000580
610#define MAC_EXTADDR_10_LOW 0x00000584
611#define MAC_EXTADDR_11_HIGH 0x00000588
612#define MAC_EXTADDR_11_LOW 0x0000058c
613#define MAC_SERDES_CFG 0x00000590
614#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
615#define MAC_SERDES_STAT 0x00000594
616
617#define MAC_PHYCFG1 0x000005a0
618#define MAC_PHYCFG1_RGMII_INT 0x00000001
619#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
620#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
621#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
622#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
623#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
624#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
625#define MAC_PHYCFG1_TXC_DRV 0x20000000
626#define MAC_PHYCFG2 0x000005a4
627#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
628#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
629#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
630#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
631#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
632#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
633#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
634#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
635#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
636#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
637#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
638#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
639#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
640#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
641#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
642#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
643#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
644#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
645#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
646#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
647#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
648#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
649#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
650#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
651#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
652#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
653#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
654#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
655#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
656#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
657#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
658#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
659#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
660#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
661#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
662#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
663#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
664#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
665#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
666#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
667#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
668#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
669#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
670#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
671#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
672#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
673#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
674#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
675#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
676#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
677#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
678#define MAC_PHYCFG2_50610_LED_MODES \
679 (MAC_PHYCFG2_EMODE_MASK_50610 | \
680 MAC_PHYCFG2_EMODE_COMP_50610 | \
681 MAC_PHYCFG2_FMODE_MASK_50610 | \
682 MAC_PHYCFG2_FMODE_COMP_50610 | \
683 MAC_PHYCFG2_GMODE_MASK_50610 | \
684 MAC_PHYCFG2_GMODE_COMP_50610 | \
685 MAC_PHYCFG2_ACT_MASK_50610 | \
686 MAC_PHYCFG2_ACT_COMP_50610 | \
687 MAC_PHYCFG2_QUAL_MASK_50610 | \
688 MAC_PHYCFG2_QUAL_COMP_50610)
689#define MAC_PHYCFG2_AC131_LED_MODES \
690 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
691 MAC_PHYCFG2_EMODE_COMP_AC131 | \
692 MAC_PHYCFG2_FMODE_MASK_AC131 | \
693 MAC_PHYCFG2_FMODE_COMP_AC131 | \
694 MAC_PHYCFG2_GMODE_MASK_AC131 | \
695 MAC_PHYCFG2_GMODE_COMP_AC131 | \
696 MAC_PHYCFG2_ACT_MASK_AC131 | \
697 MAC_PHYCFG2_ACT_COMP_AC131 | \
698 MAC_PHYCFG2_QUAL_MASK_AC131 | \
699 MAC_PHYCFG2_QUAL_COMP_AC131)
700#define MAC_PHYCFG2_RTL8211C_LED_MODES \
701 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
702 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
703 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
704 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
705 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
706 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
707 MAC_PHYCFG2_ACT_MASK_RT8211 | \
708 MAC_PHYCFG2_ACT_COMP_RT8211 | \
709 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
710 MAC_PHYCFG2_QUAL_COMP_RT8211)
711#define MAC_PHYCFG2_RTL8201E_LED_MODES \
712 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
713 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
714 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
715 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
716 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
717 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
718 MAC_PHYCFG2_ACT_MASK_RT8201 | \
719 MAC_PHYCFG2_ACT_COMP_RT8201 | \
720 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
721 MAC_PHYCFG2_QUAL_COMP_RT8201)
722#define MAC_EXT_RGMII_MODE 0x000005a8
723#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
724#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
725#define MAC_RGMII_MODE_TX_RESET 0x00000004
726#define MAC_RGMII_MODE_RX_INT_B 0x00000100
727#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
728#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
729#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
730
731#define SERDES_RX_CTRL 0x000005b0
732#define SERDES_RX_SIG_DETECT 0x00000400
733#define SG_DIG_CTRL 0x000005b0
734#define SG_DIG_USING_HW_AUTONEG 0x80000000
735#define SG_DIG_SOFT_RESET 0x40000000
736#define SG_DIG_DISABLE_LINKRDY 0x20000000
737#define SG_DIG_CRC16_CLEAR_N 0x01000000
738#define SG_DIG_EN10B 0x00800000
739#define SG_DIG_CLEAR_STATUS 0x00400000
740#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
741#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
742#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
743#define SG_DIG_SPEED_STATUS_SHIFT 18
744#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
745#define SG_DIG_RESTART_AUTONEG 0x00010000
746#define SG_DIG_FIBER_MODE 0x00008000
747#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
748#define SG_DIG_PAUSE_MASK 0x00001800
749#define SG_DIG_PAUSE_CAP 0x00000800
750#define SG_DIG_ASYM_PAUSE 0x00001000
751#define SG_DIG_GBIC_ENABLE 0x00000400
752#define SG_DIG_CHECK_END_ENABLE 0x00000200
753#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
754#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
755#define SG_DIG_GMII_INPUT_SELECT 0x00000040
756#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
757#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
758#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
759#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
760#define SG_DIG_REMOTE_LOOPBACK 0x00000002
761#define SG_DIG_LOOPBACK 0x00000001
762#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
763 SG_DIG_LOCAL_DUPLEX_STATUS | \
764 SG_DIG_LOCAL_LINK_STATUS | \
765 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
766 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
767#define SG_DIG_STATUS 0x000005b4
768#define SG_DIG_CRC16_BUS_MASK 0xffff0000
769#define SG_DIG_PARTNER_FAULT_MASK 0x00600000
770#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000
771#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000
772#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000
773#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000
774#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000
775#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
776#define SG_DIG_IS_SERDES 0x00000100
777#define SG_DIG_COMMA_DETECTOR 0x00000008
778#define SG_DIG_MAC_ACK_STATUS 0x00000004
779#define SG_DIG_AUTONEG_COMPLETE 0x00000002
780#define SG_DIG_AUTONEG_ERROR 0x00000001
781#define TG3_TX_TSTAMP_LSB 0x000005c0
782#define TG3_TX_TSTAMP_MSB 0x000005c4
783#define TG3_TSTAMP_MASK 0x7fffffffffffffffLL
784
785#define MAC_TX_MAC_STATE_BASE 0x00000600
786#define MAC_RX_MAC_STATE_BASE 0x00000610
787
788
789#define MAC_RSS_INDIR_TBL_0 0x00000630
790
791#define MAC_RSS_HASH_KEY_0 0x00000670
792#define MAC_RSS_HASH_KEY_1 0x00000674
793#define MAC_RSS_HASH_KEY_2 0x00000678
794#define MAC_RSS_HASH_KEY_3 0x0000067c
795#define MAC_RSS_HASH_KEY_4 0x00000680
796#define MAC_RSS_HASH_KEY_5 0x00000684
797#define MAC_RSS_HASH_KEY_6 0x00000688
798#define MAC_RSS_HASH_KEY_7 0x0000068c
799#define MAC_RSS_HASH_KEY_8 0x00000690
800#define MAC_RSS_HASH_KEY_9 0x00000694
801
802
803#define TG3_RX_TSTAMP_LSB 0x000006b0
804#define TG3_RX_TSTAMP_MSB 0x000006b4
805
806
807#define TG3_RX_PTP_CTL 0x000006c8
808#define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001
809#define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002
810#define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004
811#define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008
812#define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
813 TG3_RX_PTP_CTL_DELAY_REQ)
814#define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
815 TG3_RX_PTP_CTL_DELAY_REQ | \
816 TG3_RX_PTP_CTL_PDLAY_REQ | \
817 TG3_RX_PTP_CTL_PDLAY_RES)
818#define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100
819#define TG3_RX_PTP_CTL_DELAY_RES 0x00000200
820#define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400
821#define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800
822#define TG3_RX_PTP_CTL_SIGNALING 0x00001000
823#define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000
824#define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000
825#define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000
826#define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \
827 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN)
828#define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000
829#define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000
830
831
832#define MAC_TX_STATS_OCTETS 0x00000800
833#define MAC_TX_STATS_RESV1 0x00000804
834#define MAC_TX_STATS_COLLISIONS 0x00000808
835#define MAC_TX_STATS_XON_SENT 0x0000080c
836#define MAC_TX_STATS_XOFF_SENT 0x00000810
837#define MAC_TX_STATS_RESV2 0x00000814
838#define MAC_TX_STATS_MAC_ERRORS 0x00000818
839#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
840#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
841#define MAC_TX_STATS_DEFERRED 0x00000824
842#define MAC_TX_STATS_RESV3 0x00000828
843#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
844#define MAC_TX_STATS_LATE_COL 0x00000830
845#define MAC_TX_STATS_RESV4_1 0x00000834
846#define MAC_TX_STATS_RESV4_2 0x00000838
847#define MAC_TX_STATS_RESV4_3 0x0000083c
848#define MAC_TX_STATS_RESV4_4 0x00000840
849#define MAC_TX_STATS_RESV4_5 0x00000844
850#define MAC_TX_STATS_RESV4_6 0x00000848
851#define MAC_TX_STATS_RESV4_7 0x0000084c
852#define MAC_TX_STATS_RESV4_8 0x00000850
853#define MAC_TX_STATS_RESV4_9 0x00000854
854#define MAC_TX_STATS_RESV4_10 0x00000858
855#define MAC_TX_STATS_RESV4_11 0x0000085c
856#define MAC_TX_STATS_RESV4_12 0x00000860
857#define MAC_TX_STATS_RESV4_13 0x00000864
858#define MAC_TX_STATS_RESV4_14 0x00000868
859#define MAC_TX_STATS_UCAST 0x0000086c
860#define MAC_TX_STATS_MCAST 0x00000870
861#define MAC_TX_STATS_BCAST 0x00000874
862#define MAC_TX_STATS_RESV5_1 0x00000878
863#define MAC_TX_STATS_RESV5_2 0x0000087c
864#define MAC_RX_STATS_OCTETS 0x00000880
865#define MAC_RX_STATS_RESV1 0x00000884
866#define MAC_RX_STATS_FRAGMENTS 0x00000888
867#define MAC_RX_STATS_UCAST 0x0000088c
868#define MAC_RX_STATS_MCAST 0x00000890
869#define MAC_RX_STATS_BCAST 0x00000894
870#define MAC_RX_STATS_FCS_ERRORS 0x00000898
871#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
872#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
873#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
874#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
875#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
876#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
877#define MAC_RX_STATS_JABBERS 0x000008b4
878#define MAC_RX_STATS_UNDERSIZE 0x000008b8
879
880
881
882#define SNDDATAI_MODE 0x00000c00
883#define SNDDATAI_MODE_RESET 0x00000001
884#define SNDDATAI_MODE_ENABLE 0x00000002
885#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
886#define SNDDATAI_STATUS 0x00000c04
887#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
888#define SNDDATAI_STATSCTRL 0x00000c08
889#define SNDDATAI_SCTRL_ENABLE 0x00000001
890#define SNDDATAI_SCTRL_FASTUPD 0x00000002
891#define SNDDATAI_SCTRL_CLEAR 0x00000004
892#define SNDDATAI_SCTRL_FLUSH 0x00000008
893#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
894#define SNDDATAI_STATSENAB 0x00000c0c
895#define SNDDATAI_STATSINCMASK 0x00000c10
896#define ISO_PKT_TX 0x00000c20
897
898#define SNDDATAI_COS_CNT_0 0x00000c80
899#define SNDDATAI_COS_CNT_1 0x00000c84
900#define SNDDATAI_COS_CNT_2 0x00000c88
901#define SNDDATAI_COS_CNT_3 0x00000c8c
902#define SNDDATAI_COS_CNT_4 0x00000c90
903#define SNDDATAI_COS_CNT_5 0x00000c94
904#define SNDDATAI_COS_CNT_6 0x00000c98
905#define SNDDATAI_COS_CNT_7 0x00000c9c
906#define SNDDATAI_COS_CNT_8 0x00000ca0
907#define SNDDATAI_COS_CNT_9 0x00000ca4
908#define SNDDATAI_COS_CNT_10 0x00000ca8
909#define SNDDATAI_COS_CNT_11 0x00000cac
910#define SNDDATAI_COS_CNT_12 0x00000cb0
911#define SNDDATAI_COS_CNT_13 0x00000cb4
912#define SNDDATAI_COS_CNT_14 0x00000cb8
913#define SNDDATAI_COS_CNT_15 0x00000cbc
914#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
915#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
916#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
917#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
918#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
919#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
920#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
921#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
922
923
924
925#define SNDDATAC_MODE 0x00001000
926#define SNDDATAC_MODE_RESET 0x00000001
927#define SNDDATAC_MODE_ENABLE 0x00000002
928#define SNDDATAC_MODE_CDELAY 0x00000010
929
930
931
932#define SNDBDS_MODE 0x00001400
933#define SNDBDS_MODE_RESET 0x00000001
934#define SNDBDS_MODE_ENABLE 0x00000002
935#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
936#define SNDBDS_STATUS 0x00001404
937#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
938#define SNDBDS_HWDIAG 0x00001408
939
940#define SNDBDS_SEL_CON_IDX_0 0x00001440
941#define SNDBDS_SEL_CON_IDX_1 0x00001444
942#define SNDBDS_SEL_CON_IDX_2 0x00001448
943#define SNDBDS_SEL_CON_IDX_3 0x0000144c
944#define SNDBDS_SEL_CON_IDX_4 0x00001450
945#define SNDBDS_SEL_CON_IDX_5 0x00001454
946#define SNDBDS_SEL_CON_IDX_6 0x00001458
947#define SNDBDS_SEL_CON_IDX_7 0x0000145c
948#define SNDBDS_SEL_CON_IDX_8 0x00001460
949#define SNDBDS_SEL_CON_IDX_9 0x00001464
950#define SNDBDS_SEL_CON_IDX_10 0x00001468
951#define SNDBDS_SEL_CON_IDX_11 0x0000146c
952#define SNDBDS_SEL_CON_IDX_12 0x00001470
953#define SNDBDS_SEL_CON_IDX_13 0x00001474
954#define SNDBDS_SEL_CON_IDX_14 0x00001478
955#define SNDBDS_SEL_CON_IDX_15 0x0000147c
956
957
958
959#define SNDBDI_MODE 0x00001800
960#define SNDBDI_MODE_RESET 0x00000001
961#define SNDBDI_MODE_ENABLE 0x00000002
962#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
963#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
964#define SNDBDI_STATUS 0x00001804
965#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
966#define SNDBDI_IN_PROD_IDX_0 0x00001808
967#define SNDBDI_IN_PROD_IDX_1 0x0000180c
968#define SNDBDI_IN_PROD_IDX_2 0x00001810
969#define SNDBDI_IN_PROD_IDX_3 0x00001814
970#define SNDBDI_IN_PROD_IDX_4 0x00001818
971#define SNDBDI_IN_PROD_IDX_5 0x0000181c
972#define SNDBDI_IN_PROD_IDX_6 0x00001820
973#define SNDBDI_IN_PROD_IDX_7 0x00001824
974#define SNDBDI_IN_PROD_IDX_8 0x00001828
975#define SNDBDI_IN_PROD_IDX_9 0x0000182c
976#define SNDBDI_IN_PROD_IDX_10 0x00001830
977#define SNDBDI_IN_PROD_IDX_11 0x00001834
978#define SNDBDI_IN_PROD_IDX_12 0x00001838
979#define SNDBDI_IN_PROD_IDX_13 0x0000183c
980#define SNDBDI_IN_PROD_IDX_14 0x00001840
981#define SNDBDI_IN_PROD_IDX_15 0x00001844
982
983
984
985#define SNDBDC_MODE 0x00001c00
986#define SNDBDC_MODE_RESET 0x00000001
987#define SNDBDC_MODE_ENABLE 0x00000002
988#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
989
990
991
992#define RCVLPC_MODE 0x00002000
993#define RCVLPC_MODE_RESET 0x00000001
994#define RCVLPC_MODE_ENABLE 0x00000002
995#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
996#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
997#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
998#define RCVLPC_STATUS 0x00002004
999#define RCVLPC_STATUS_CLASS0 0x00000004
1000#define RCVLPC_STATUS_MAPOOR 0x00000008
1001#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1002#define RCVLPC_LOCK 0x00002008
1003#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1004#define RCVLPC_LOCK_REQ_SHIFT 0
1005#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1006#define RCVLPC_LOCK_GRANT_SHIFT 16
1007#define RCVLPC_NON_EMPTY_BITS 0x0000200c
1008#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1009#define RCVLPC_CONFIG 0x00002010
1010#define RCVLPC_STATSCTRL 0x00002014
1011#define RCVLPC_STATSCTRL_ENABLE 0x00000001
1012#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1013#define RCVLPC_STATS_ENABLE 0x00002018
1014#define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1015#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1016#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1017#define RCVLPC_STATS_INCMASK 0x0000201c
1018
1019#define RCVLPC_SELLST_BASE 0x00002100
1020#define SELLST_TAIL 0x00000004
1021#define SELLST_CONT 0x00000008
1022#define SELLST_UNUSED 0x0000000c
1023#define RCVLPC_COS_CNTL_BASE 0x00002200
1024#define RCVLPC_DROP_FILTER_CNT 0x00002240
1025#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1026#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1027#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1028#define RCVLPC_IN_DISCARDS_CNT 0x00002250
1029#define RCVLPC_IN_ERRORS_CNT 0x00002254
1030#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1031
1032
1033
1034#define RCVDBDI_MODE 0x00002400
1035#define RCVDBDI_MODE_RESET 0x00000001
1036#define RCVDBDI_MODE_ENABLE 0x00000002
1037#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1038#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1039#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1040#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1041#define RCVDBDI_STATUS 0x00002404
1042#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1043#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1044#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1045#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1046
1047#define RCVDBDI_JUMBO_BD 0x00002440
1048#define RCVDBDI_STD_BD 0x00002450
1049#define RCVDBDI_MINI_BD 0x00002460
1050#define RCVDBDI_JUMBO_CON_IDX 0x00002470
1051#define RCVDBDI_STD_CON_IDX 0x00002474
1052#define RCVDBDI_MINI_CON_IDX 0x00002478
1053
1054#define RCVDBDI_BD_PROD_IDX_0 0x00002480
1055#define RCVDBDI_BD_PROD_IDX_1 0x00002484
1056#define RCVDBDI_BD_PROD_IDX_2 0x00002488
1057#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1058#define RCVDBDI_BD_PROD_IDX_4 0x00002490
1059#define RCVDBDI_BD_PROD_IDX_5 0x00002494
1060#define RCVDBDI_BD_PROD_IDX_6 0x00002498
1061#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1062#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1063#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1064#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1065#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1066#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1067#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1068#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1069#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1070#define RCVDBDI_HWDIAG 0x000024c0
1071
1072
1073
1074#define RCVDCC_MODE 0x00002800
1075#define RCVDCC_MODE_RESET 0x00000001
1076#define RCVDCC_MODE_ENABLE 0x00000002
1077#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1078
1079
1080
1081#define RCVBDI_MODE 0x00002c00
1082#define RCVBDI_MODE_RESET 0x00000001
1083#define RCVBDI_MODE_ENABLE 0x00000002
1084#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1085#define RCVBDI_STATUS 0x00002c04
1086#define RCVBDI_STATUS_RCB_ATTN 0x00000004
1087#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1088#define RCVBDI_STD_PROD_IDX 0x00002c0c
1089#define RCVBDI_MINI_PROD_IDX 0x00002c10
1090#define RCVBDI_MINI_THRESH 0x00002c14
1091#define RCVBDI_STD_THRESH 0x00002c18
1092#define RCVBDI_JUMBO_THRESH 0x00002c1c
1093
1094
1095#define STD_REPLENISH_LWM 0x00002d00
1096#define JMB_REPLENISH_LWM 0x00002d04
1097
1098
1099
1100#define RCVCC_MODE 0x00003000
1101#define RCVCC_MODE_RESET 0x00000001
1102#define RCVCC_MODE_ENABLE 0x00000002
1103#define RCVCC_MODE_ATTN_ENABLE 0x00000004
1104#define RCVCC_STATUS 0x00003004
1105#define RCVCC_STATUS_ERROR_ATTN 0x00000004
1106#define RCVCC_JUMP_PROD_IDX 0x00003008
1107#define RCVCC_STD_PROD_IDX 0x0000300c
1108#define RCVCC_MINI_PROD_IDX 0x00003010
1109
1110
1111
1112#define RCVLSC_MODE 0x00003400
1113#define RCVLSC_MODE_RESET 0x00000001
1114#define RCVLSC_MODE_ENABLE 0x00000002
1115#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1116#define RCVLSC_STATUS 0x00003404
1117#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1118
1119
1120#define TG3_CPMU_DRV_STATUS 0x0000344c
1121
1122
1123#define TG3_CPMU_CTRL 0x00003600
1124#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1125#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1126#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1127#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1128#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1129#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1130#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1131
1132
1133#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1134#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1135#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1136#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1137#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1138#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1139#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1140
1141
1142#define TG3_CPMU_HST_ACC 0x0000361c
1143#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1144#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1145
1146
1147#define TG3_CPMU_CLCK_ORIDE 0x00003624
1148#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1149
1150#define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628
1151#define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13)
1152
1153#define TG3_CPMU_STATUS 0x0000362c
1154#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1155#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1156#define TG3_CPMU_STATUS_FSHFT_5719 30
1157#define TG3_CPMU_STATUS_LINK_MASK 0x180000
1158
1159#define TG3_CPMU_CLCK_STAT 0x00003630
1160#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1161#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1162#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1163#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1164
1165
1166#define TG3_CPMU_MUTEX_REQ 0x0000365c
1167#define CPMU_MUTEX_REQ_DRIVER 0x00001000
1168#define TG3_CPMU_MUTEX_GNT 0x00003660
1169#define CPMU_MUTEX_GNT_DRIVER 0x00001000
1170#define TG3_CPMU_PHY_STRAP 0x00003664
1171#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1172#define TG3_CPMU_PADRNG_CTL 0x00003668
1173#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000
1174
1175
1176#define TG3_CPMU_EEE_MODE 0x000036b0
1177#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1178#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1179#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1180#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1181#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1182#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1183#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1184#define TG3_CPMU_EEE_DBTMR1 0x000036b4
1185#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1186#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
1187#define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff
1188#define TG3_CPMU_EEE_DBTMR2 0x000036b8
1189#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1190#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
1191#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1192#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1193#define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1194#define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002
1195
1196
1197#define TG3_CPMU_EEE_CTRL 0x000036d0
1198#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1199#define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1200#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1201
1202
1203
1204#define MBFREE_MODE 0x00003800
1205#define MBFREE_MODE_RESET 0x00000001
1206#define MBFREE_MODE_ENABLE 0x00000002
1207#define MBFREE_STATUS 0x00003804
1208
1209
1210
1211#define HOSTCC_MODE 0x00003c00
1212#define HOSTCC_MODE_RESET 0x00000001
1213#define HOSTCC_MODE_ENABLE 0x00000002
1214#define HOSTCC_MODE_ATTN 0x00000004
1215#define HOSTCC_MODE_NOW 0x00000008
1216#define HOSTCC_MODE_FULL_STATUS 0x00000000
1217#define HOSTCC_MODE_64BYTE 0x00000080
1218#define HOSTCC_MODE_32BYTE 0x00000100
1219#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1220#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1221#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1222#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1223#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1224#define HOSTCC_STATUS 0x00003c04
1225#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1226#define HOSTCC_RXCOL_TICKS 0x00003c08
1227#define LOW_RXCOL_TICKS 0x00000032
1228#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1229#define DEFAULT_RXCOL_TICKS 0x00000048
1230#define HIGH_RXCOL_TICKS 0x00000096
1231#define MAX_RXCOL_TICKS 0x000003ff
1232#define HOSTCC_TXCOL_TICKS 0x00003c0c
1233#define LOW_TXCOL_TICKS 0x00000096
1234#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1235#define DEFAULT_TXCOL_TICKS 0x0000012c
1236#define HIGH_TXCOL_TICKS 0x00000145
1237#define MAX_TXCOL_TICKS 0x000003ff
1238#define HOSTCC_RXMAX_FRAMES 0x00003c10
1239#define LOW_RXMAX_FRAMES 0x00000005
1240#define DEFAULT_RXMAX_FRAMES 0x00000008
1241#define HIGH_RXMAX_FRAMES 0x00000012
1242#define MAX_RXMAX_FRAMES 0x000000ff
1243#define HOSTCC_TXMAX_FRAMES 0x00003c14
1244#define LOW_TXMAX_FRAMES 0x00000035
1245#define DEFAULT_TXMAX_FRAMES 0x0000004b
1246#define HIGH_TXMAX_FRAMES 0x00000052
1247#define MAX_TXMAX_FRAMES 0x000000ff
1248#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1249#define DEFAULT_RXCOAL_TICK_INT 0x00000019
1250#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1251#define MAX_RXCOAL_TICK_INT 0x000003ff
1252#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1253#define DEFAULT_TXCOAL_TICK_INT 0x00000019
1254#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1255#define MAX_TXCOAL_TICK_INT 0x000003ff
1256#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1257#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1258#define MAX_RXCOAL_MAXF_INT 0x000000ff
1259#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1260#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1261#define MAX_TXCOAL_MAXF_INT 0x000000ff
1262#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1263#define DEFAULT_STAT_COAL_TICKS 0x000f4240
1264#define MAX_STAT_COAL_TICKS 0xd693d400
1265#define MIN_STAT_COAL_TICKS 0x00000064
1266
1267#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30
1268#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38
1269#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1270#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1271#define HOSTCC_FLOW_ATTN 0x00003c48
1272#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1273
1274#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1275#define HOSTCC_STD_CON_IDX 0x00003c54
1276#define HOSTCC_MINI_CON_IDX 0x00003c58
1277
1278#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1279#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1280#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1281#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1282#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1283#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1284#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1285#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1286#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1287#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1288#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1289#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1290#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1291#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1292#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1293#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1294#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1295#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1296#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1297#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1298#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1299#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1300#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1301#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1302#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1303#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1304#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1305#define HOSTCC_SND_CON_IDX_11 0x00003cec
1306#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1307#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1308#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1309#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1310#define HOSTCC_STATBLCK_RING1 0x00003d00
1311
1312
1313#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1314#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1315#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1316#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1317#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1318#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1319
1320
1321
1322#define MEMARB_MODE 0x00004000
1323#define MEMARB_MODE_RESET 0x00000001
1324#define MEMARB_MODE_ENABLE 0x00000002
1325#define MEMARB_STATUS 0x00004004
1326#define MEMARB_TRAP_ADDR_LOW 0x00004008
1327#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1328
1329
1330
1331#define BUFMGR_MODE 0x00004400
1332#define BUFMGR_MODE_RESET 0x00000001
1333#define BUFMGR_MODE_ENABLE 0x00000002
1334#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1335#define BUFMGR_MODE_BM_TEST 0x00000008
1336#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1337#define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1338#define BUFMGR_STATUS 0x00004404
1339#define BUFMGR_STATUS_ERROR 0x00000004
1340#define BUFMGR_STATUS_MBLOW 0x00000010
1341#define BUFMGR_MB_POOL_ADDR 0x00004408
1342#define BUFMGR_MB_POOL_SIZE 0x0000440c
1343#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1344#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1345#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1346#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1347#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1348#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1349#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1350#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1351#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1352#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1353#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1354#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1355#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1356#define BUFMGR_MB_HIGH_WATER 0x00004418
1357#define DEFAULT_MB_HIGH_WATER 0x00000060
1358#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1359#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1360#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1361#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1362#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1363#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1364#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1365#define BUFMGR_MB_ALLOC_BIT 0x10000000
1366#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1367#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1368#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1369#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1370#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1371#define BUFMGR_DMA_LOW_WATER 0x00004434
1372#define DEFAULT_DMA_LOW_WATER 0x00000005
1373#define BUFMGR_DMA_HIGH_WATER 0x00004438
1374#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1375#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1376#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1377#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1378#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1379#define BUFMGR_HWDIAG_0 0x0000444c
1380#define BUFMGR_HWDIAG_1 0x00004450
1381#define BUFMGR_HWDIAG_2 0x00004454
1382
1383
1384
1385#define RDMAC_MODE 0x00004800
1386#define RDMAC_MODE_RESET 0x00000001
1387#define RDMAC_MODE_ENABLE 0x00000002
1388#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1389#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1390#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1391#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1392#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1393#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1394#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1395#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1396#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1397#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1398#define RDMAC_MODE_SPLIT_RESET 0x00001000
1399#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1400#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1401#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1402#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1403#define RDMAC_MODE_JMB_2K_MMRR 0x00800000
1404#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1405#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1406#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1407#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1408#define RDMAC_STATUS 0x00004804
1409#define RDMAC_STATUS_TGTABORT 0x00000004
1410#define RDMAC_STATUS_MSTABORT 0x00000008
1411#define RDMAC_STATUS_PARITYERR 0x00000010
1412#define RDMAC_STATUS_ADDROFLOW 0x00000020
1413#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1414#define RDMAC_STATUS_FIFOURUN 0x00000080
1415#define RDMAC_STATUS_FIFOOREAD 0x00000100
1416#define RDMAC_STATUS_LNGREAD 0x00000200
1417
1418
1419#define TG3_RDMA_RSRVCTRL_REG2 0x00004890
1420#define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0
1421
1422#define TG3_RDMA_RSRVCTRL_REG 0x00004900
1423#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1424#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1425#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1426#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1427#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1428#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1429#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1430
1431
1432#define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1433#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1434#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1435#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000
1436#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000
1437
1438
1439#define TG3_NUM_RDMA_CHANNELS 4
1440#define TG3_RDMA_LENGTH 0x00004be0
1441
1442
1443#define WDMAC_MODE 0x00004c00
1444#define WDMAC_MODE_RESET 0x00000001
1445#define WDMAC_MODE_ENABLE 0x00000002
1446#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1447#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1448#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1449#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1450#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1451#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1452#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1453#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1454#define WDMAC_MODE_RX_ACCEL 0x00000400
1455#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1456#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1457#define WDMAC_STATUS 0x00004c04
1458#define WDMAC_STATUS_TGTABORT 0x00000004
1459#define WDMAC_STATUS_MSTABORT 0x00000008
1460#define WDMAC_STATUS_PARITYERR 0x00000010
1461#define WDMAC_STATUS_ADDROFLOW 0x00000020
1462#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1463#define WDMAC_STATUS_FIFOURUN 0x00000080
1464#define WDMAC_STATUS_FIFOOREAD 0x00000100
1465#define WDMAC_STATUS_LNGREAD 0x00000200
1466
1467
1468
1469#define CPU_MODE 0x00000000
1470#define CPU_MODE_RESET 0x00000001
1471#define CPU_MODE_HALT 0x00000400
1472#define CPU_STATE 0x00000004
1473#define CPU_EVTMASK 0x00000008
1474
1475#define CPU_PC 0x0000001c
1476#define CPU_INSN 0x00000020
1477#define CPU_SPAD_UFLOW 0x00000024
1478#define CPU_WDOG_CLEAR 0x00000028
1479#define CPU_WDOG_VECTOR 0x0000002c
1480#define CPU_WDOG_PC 0x00000030
1481#define CPU_HW_BP 0x00000034
1482
1483#define CPU_WDOG_SAVED_STATE 0x00000044
1484#define CPU_LAST_BRANCH_ADDR 0x00000048
1485#define CPU_SPAD_UFLOW_SET 0x0000004c
1486
1487#define CPU_R0 0x00000200
1488#define CPU_R1 0x00000204
1489#define CPU_R2 0x00000208
1490#define CPU_R3 0x0000020c
1491#define CPU_R4 0x00000210
1492#define CPU_R5 0x00000214
1493#define CPU_R6 0x00000218
1494#define CPU_R7 0x0000021c
1495#define CPU_R8 0x00000220
1496#define CPU_R9 0x00000224
1497#define CPU_R10 0x00000228
1498#define CPU_R11 0x0000022c
1499#define CPU_R12 0x00000230
1500#define CPU_R13 0x00000234
1501#define CPU_R14 0x00000238
1502#define CPU_R15 0x0000023c
1503#define CPU_R16 0x00000240
1504#define CPU_R17 0x00000244
1505#define CPU_R18 0x00000248
1506#define CPU_R19 0x0000024c
1507#define CPU_R20 0x00000250
1508#define CPU_R21 0x00000254
1509#define CPU_R22 0x00000258
1510#define CPU_R23 0x0000025c
1511#define CPU_R24 0x00000260
1512#define CPU_R25 0x00000264
1513#define CPU_R26 0x00000268
1514#define CPU_R27 0x0000026c
1515#define CPU_R28 0x00000270
1516#define CPU_R29 0x00000274
1517#define CPU_R30 0x00000278
1518#define CPU_R31 0x0000027c
1519
1520
1521#define RX_CPU_BASE 0x00005000
1522#define RX_CPU_MODE 0x00005000
1523#define RX_CPU_STATE 0x00005004
1524#define RX_CPU_PGMCTR 0x0000501c
1525#define RX_CPU_HWBKPT 0x00005034
1526#define TX_CPU_BASE 0x00005400
1527#define TX_CPU_MODE 0x00005400
1528#define TX_CPU_STATE 0x00005404
1529#define TX_CPU_PGMCTR 0x0000541c
1530
1531#define VCPU_STATUS 0x00005100
1532#define VCPU_STATUS_INIT_DONE 0x04000000
1533#define VCPU_STATUS_DRV_RESET 0x08000000
1534
1535#define VCPU_CFGSHDW 0x00005104
1536#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1537#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1538#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1539
1540
1541#define GRCMBOX_BASE 0x00005600
1542#define GRCMBOX_INTERRUPT_0 0x00005800
1543#define GRCMBOX_INTERRUPT_1 0x00005808
1544#define GRCMBOX_INTERRUPT_2 0x00005810
1545#define GRCMBOX_INTERRUPT_3 0x00005818
1546#define GRCMBOX_GENERAL_0 0x00005820
1547#define GRCMBOX_GENERAL_1 0x00005828
1548#define GRCMBOX_GENERAL_2 0x00005830
1549#define GRCMBOX_GENERAL_3 0x00005838
1550#define GRCMBOX_GENERAL_4 0x00005840
1551#define GRCMBOX_GENERAL_5 0x00005848
1552#define GRCMBOX_GENERAL_6 0x00005850
1553#define GRCMBOX_GENERAL_7 0x00005858
1554#define GRCMBOX_RELOAD_STAT 0x00005860
1555#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868
1556#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870
1557#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878
1558#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880
1559#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888
1560#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890
1561#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898
1562#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0
1563#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8
1564#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0
1565#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8
1566#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0
1567#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8
1568#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0
1569#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8
1570#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0
1571#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8
1572#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0
1573#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8
1574#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900
1575#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908
1576#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910
1577#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918
1578#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920
1579#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928
1580#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930
1581#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938
1582#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940
1583#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948
1584#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950
1585#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958
1586#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960
1587#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968
1588#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970
1589#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978
1590#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980
1591#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988
1592#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990
1593#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998
1594#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0
1595#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8
1596#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0
1597#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8
1598#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0
1599#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8
1600#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0
1601#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8
1602#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0
1603#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8
1604#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0
1605#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8
1606#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1607#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1608#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1609#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1610
1611
1612
1613#define FTQ_RESET 0x00005c00
1614
1615#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1616#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1617#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1618#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1619#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1620#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1621#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1622#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1623#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1624#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1625#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1626#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1627#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1628#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1629#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1630#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1631#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1632#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1633#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1634#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1635#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1636#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1637#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1638#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1639#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1640#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1641#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1642#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1643#define FTQ_SWTYPE1_CTL 0x00005c80
1644#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1645#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1646#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1647#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1648#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1649#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1650#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1651#define FTQ_HOST_COAL_CTL 0x00005ca0
1652#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1653#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1654#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1655#define FTQ_MAC_TX_CTL 0x00005cb0
1656#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1657#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1658#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1659#define FTQ_MB_FREE_CTL 0x00005cc0
1660#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1661#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1662#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1663#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1664#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1665#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1666#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1667#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1668#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1669#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1670#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1671#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1672#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1673#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1674#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1675#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1676#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1677#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1678#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1679#define FTQ_SWTYPE2_CTL 0x00005d10
1680#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1681#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1682#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1683
1684
1685
1686#define MSGINT_MODE 0x00006000
1687#define MSGINT_MODE_RESET 0x00000001
1688#define MSGINT_MODE_ENABLE 0x00000002
1689#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1690#define MSGINT_MODE_MULTIVEC_EN 0x00000080
1691#define MSGINT_STATUS 0x00006004
1692#define MSGINT_STATUS_MSI_REQ 0x00000001
1693#define MSGINT_FIFO 0x00006008
1694
1695
1696
1697#define DMAC_MODE 0x00006400
1698#define DMAC_MODE_RESET 0x00000001
1699#define DMAC_MODE_ENABLE 0x00000002
1700
1701
1702
1703#define GRC_MODE 0x00006800
1704#define GRC_MODE_UPD_ON_COAL 0x00000001
1705#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1706#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1707#define GRC_MODE_BSWAP_DATA 0x00000010
1708#define GRC_MODE_WSWAP_DATA 0x00000020
1709#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1710#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1711#define GRC_MODE_SPLITHDR 0x00000100
1712#define GRC_MODE_NOFRM_CRACKING 0x00000200
1713#define GRC_MODE_INCL_CRC 0x00000400
1714#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1715#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1716#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1717#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1718#define GRC_MODE_B2HRX_ENABLE 0x00008000
1719#define GRC_MODE_HOST_STACKUP 0x00010000
1720#define GRC_MODE_HOST_SENDBDS 0x00020000
1721#define GRC_MODE_HTX2B_ENABLE 0x00040000
1722#define GRC_MODE_TIME_SYNC_ENABLE 0x00080000
1723#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1724#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1725#define GRC_MODE_PCIE_TL_SEL 0x00000000
1726#define GRC_MODE_PCIE_PL_SEL 0x00400000
1727#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1728#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1729#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1730#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1731#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1732#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1733#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1734#define GRC_MODE_PCIE_DL_SEL 0x20000000
1735#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1736#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1737#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1738 GRC_MODE_PCIE_PL_SEL | \
1739 GRC_MODE_PCIE_DL_SEL | \
1740 GRC_MODE_PCIE_HI_1K_EN)
1741#define GRC_MISC_CFG 0x00006804
1742#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1743#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1744#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1745#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1746#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1747#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1748#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1749#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1750#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1751#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1752#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1753#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1754#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1755#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1756#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1757#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1758#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1759#define GRC_LOCAL_CTRL 0x00006808
1760#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1761#define GRC_LCLCTRL_CLEARINT 0x00000002
1762#define GRC_LCLCTRL_SETINT 0x00000004
1763#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1764#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010
1765#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010
1766#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020
1767#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1768#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1769#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1770#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1771#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1772#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1773#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1774#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1775#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1776#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1777#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1778#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1779#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1780#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1781#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1782#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1783#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1784#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1785#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1786#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1787#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1788#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1789#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1790#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1791#define GRC_TIMER 0x0000680c
1792#define GRC_RX_CPU_EVENT 0x00006810
1793#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1794#define GRC_RX_TIMER_REF 0x00006814
1795#define GRC_RX_CPU_SEM 0x00006818
1796#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1797#define GRC_TX_CPU_EVENT 0x00006820
1798#define GRC_TX_TIMER_REF 0x00006824
1799#define GRC_TX_CPU_SEM 0x00006828
1800#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1801#define GRC_MEM_POWER_UP 0x00006830
1802#define GRC_EEPROM_ADDR 0x00006838
1803#define EEPROM_ADDR_WRITE 0x00000000
1804#define EEPROM_ADDR_READ 0x80000000
1805#define EEPROM_ADDR_COMPLETE 0x40000000
1806#define EEPROM_ADDR_FSM_RESET 0x20000000
1807#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1808#define EEPROM_ADDR_DEVID_SHIFT 26
1809#define EEPROM_ADDR_START 0x02000000
1810#define EEPROM_ADDR_CLKPERD_SHIFT 16
1811#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1812#define EEPROM_ADDR_ADDR_SHIFT 0
1813#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1814#define EEPROM_CHIP_SIZE (64 * 1024)
1815#define GRC_EEPROM_DATA 0x0000683c
1816#define GRC_EEPROM_CTRL 0x00006840
1817#define GRC_MDI_CTRL 0x00006844
1818#define GRC_SEEPROM_DELAY 0x00006848
1819
1820#define GRC_VCPU_EXT_CTRL 0x00006890
1821#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1822#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1823#define GRC_FASTBOOT_PC 0x00006894
1824
1825#define TG3_EAV_REF_CLCK_LSB 0x00006900
1826#define TG3_EAV_REF_CLCK_MSB 0x00006904
1827#define TG3_EAV_REF_CLCK_CTL 0x00006908
1828#define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002
1829#define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004
1830#define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16)
1831#define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17)
1832
1833#define TG3_EAV_WATCHDOG0_LSB 0x00006918
1834#define TG3_EAV_WATCHDOG0_MSB 0x0000691c
1835#define TG3_EAV_WATCHDOG0_EN (1 << 31)
1836#define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff
1837
1838#define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928
1839#define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31)
1840#define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30)
1841
1842#define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff
1843
1844
1845
1846
1847#define NVRAM_CMD 0x00007000
1848#define NVRAM_CMD_RESET 0x00000001
1849#define NVRAM_CMD_DONE 0x00000008
1850#define NVRAM_CMD_GO 0x00000010
1851#define NVRAM_CMD_WR 0x00000020
1852#define NVRAM_CMD_RD 0x00000000
1853#define NVRAM_CMD_ERASE 0x00000040
1854#define NVRAM_CMD_FIRST 0x00000080
1855#define NVRAM_CMD_LAST 0x00000100
1856#define NVRAM_CMD_WREN 0x00010000
1857#define NVRAM_CMD_WRDI 0x00020000
1858#define NVRAM_STAT 0x00007004
1859#define NVRAM_WRDATA 0x00007008
1860#define NVRAM_ADDR 0x0000700c
1861#define NVRAM_ADDR_MSK 0x00ffffff
1862#define NVRAM_RDDATA 0x00007010
1863#define NVRAM_CFG1 0x00007014
1864#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1865#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1866#define NVRAM_CFG1_PASS_THRU 0x00000004
1867#define NVRAM_CFG1_STATUS_BITS 0x00000070
1868#define NVRAM_CFG1_BIT_BANG 0x00000008
1869#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1870#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1871#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1872#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1873#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1874#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1875#define FLASH_VENDOR_ST 0x03000001
1876#define FLASH_VENDOR_SAIFUN 0x01000003
1877#define FLASH_VENDOR_SST_SMALL 0x00000001
1878#define FLASH_VENDOR_SST_LARGE 0x02000001
1879#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1880#define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003
1881#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1882#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1883#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1884#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1885#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1886#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1887#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1888#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1889#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1890#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1891#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1892#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1893#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1894#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1895#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1896#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1897#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1898#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1899#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1900#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1901#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1902#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1903#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1904#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1905#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1906#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1907#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1908#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1909#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1910#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1911#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1912#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1913#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1914#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1915#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1916#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1917#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1918#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1919#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1920#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1921#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1922#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1923#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1924#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1925#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1926#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1927#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1928#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1929#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1930#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1931#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1932#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1933#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1934#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1935#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1936#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1937#define FLASH_5717VENDOR_ST_25USPT 0x03400002
1938#define FLASH_5717VENDOR_ST_45USPT 0x03400001
1939#define FLASH_5720_EEPROM_HD 0x00000001
1940#define FLASH_5720_EEPROM_LD 0x00000003
1941#define FLASH_5762_EEPROM_HD 0x02000001
1942#define FLASH_5762_EEPROM_LD 0x02000003
1943#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1944#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1945#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1946#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1947#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1948#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1949#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1950#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1951#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1952#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1953#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1954#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1955#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1956#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1957#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1958#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1959#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1960#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1961#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1962#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
1963#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
1964#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
1965#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
1966#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
1967#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
1968#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
1969#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
1970#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
1971#define FLASH_5720VENDOR_ST_25USPT 0x03c00002
1972#define FLASH_5720VENDOR_ST_45USPT 0x03c00001
1973#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1974#define FLASH_5752PAGE_SIZE_256 0x00000000
1975#define FLASH_5752PAGE_SIZE_512 0x10000000
1976#define FLASH_5752PAGE_SIZE_1K 0x20000000
1977#define FLASH_5752PAGE_SIZE_2K 0x30000000
1978#define FLASH_5752PAGE_SIZE_4K 0x40000000
1979#define FLASH_5752PAGE_SIZE_264 0x50000000
1980#define FLASH_5752PAGE_SIZE_528 0x60000000
1981#define NVRAM_CFG2 0x00007018
1982#define NVRAM_CFG3 0x0000701c
1983#define NVRAM_SWARB 0x00007020
1984#define SWARB_REQ_SET0 0x00000001
1985#define SWARB_REQ_SET1 0x00000002
1986#define SWARB_REQ_SET2 0x00000004
1987#define SWARB_REQ_SET3 0x00000008
1988#define SWARB_REQ_CLR0 0x00000010
1989#define SWARB_REQ_CLR1 0x00000020
1990#define SWARB_REQ_CLR2 0x00000040
1991#define SWARB_REQ_CLR3 0x00000080
1992#define SWARB_GNT0 0x00000100
1993#define SWARB_GNT1 0x00000200
1994#define SWARB_GNT2 0x00000400
1995#define SWARB_GNT3 0x00000800
1996#define SWARB_REQ0 0x00001000
1997#define SWARB_REQ1 0x00002000
1998#define SWARB_REQ2 0x00004000
1999#define SWARB_REQ3 0x00008000
2000#define NVRAM_ACCESS 0x00007024
2001#define ACCESS_ENABLE 0x00000001
2002#define ACCESS_WR_ENABLE 0x00000002
2003#define NVRAM_WRITE1 0x00007028
2004
2005
2006#define NVRAM_ADDR_LOCKOUT 0x00007030
2007
2008
2009#define OTP_MODE 0x00007500
2010#define OTP_MODE_OTP_THRU_GRC 0x00000001
2011#define OTP_CTRL 0x00007504
2012#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
2013#define OTP_CTRL_OTP_CMD_READ 0x00000000
2014#define OTP_CTRL_OTP_CMD_INIT 0x00000008
2015#define OTP_CTRL_OTP_CMD_START 0x00000001
2016#define OTP_STATUS 0x00007508
2017#define OTP_STATUS_CMD_DONE 0x00000001
2018#define OTP_ADDRESS 0x0000750c
2019#define OTP_ADDRESS_MAGIC1 0x000000a0
2020#define OTP_ADDRESS_MAGIC2 0x00000080
2021
2022
2023#define OTP_READ_DATA 0x00007514
2024
2025
2026#define PCIE_TRANSACTION_CFG 0x00007c04
2027#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
2028#define PCIE_TRANS_CFG_LOM 0x00000020
2029
2030
2031#define PCIE_PWR_MGMT_THRESH 0x00007d28
2032#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2033#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2034#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2035
2036
2037#define TG3_PCIE_LNKCTL 0x00007d54
2038#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2039#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2040
2041
2042#define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2043#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2044#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2045
2046#define TG3_PCIE_EIDLE_DELAY 0x00007e70
2047#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2048#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2049
2050
2051
2052
2053#define TG3_PCIE_TLDLPL_PORT 0x00007c00
2054#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2055#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2056#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2057#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2058#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2059#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2060#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2061
2062#define TG3_REG_BLK_SIZE 0x00008000
2063
2064
2065#define TG3_OTP_AGCTGT_MASK 0x000000e0
2066#define TG3_OTP_AGCTGT_SHIFT 1
2067#define TG3_OTP_HPFFLTR_MASK 0x00000300
2068#define TG3_OTP_HPFFLTR_SHIFT 1
2069#define TG3_OTP_HPFOVER_MASK 0x00000400
2070#define TG3_OTP_HPFOVER_SHIFT 1
2071#define TG3_OTP_LPFDIS_MASK 0x00000800
2072#define TG3_OTP_LPFDIS_SHIFT 11
2073#define TG3_OTP_VDAC_MASK 0xff000000
2074#define TG3_OTP_VDAC_SHIFT 24
2075#define TG3_OTP_10BTAMP_MASK 0x0000f000
2076#define TG3_OTP_10BTAMP_SHIFT 8
2077#define TG3_OTP_ROFF_MASK 0x00e00000
2078#define TG3_OTP_ROFF_SHIFT 11
2079#define TG3_OTP_RCOFF_MASK 0x001c0000
2080#define TG3_OTP_RCOFF_SHIFT 16
2081
2082#define TG3_OTP_DEFAULT 0x286c1640
2083
2084
2085
2086#define TG3_NVM_VPD_OFF 0x100
2087#define TG3_NVM_VPD_LEN 256
2088
2089
2090#define TG3_NVM_HWSB_CFG1 0x00000004
2091#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2092#define TG3_NVM_HWSB_CFG1_MAJSFT 27
2093#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2094#define TG3_NVM_HWSB_CFG1_MINSFT 22
2095
2096#define TG3_EEPROM_MAGIC 0x669955aa
2097#define TG3_EEPROM_MAGIC_FW 0xa5000000
2098#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2099#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2100#define TG3_EEPROM_SB_FORMAT_1 0x00200000
2101#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2102#define TG3_EEPROM_SB_REVISION_0 0x00000000
2103#define TG3_EEPROM_SB_REVISION_2 0x00020000
2104#define TG3_EEPROM_SB_REVISION_3 0x00030000
2105#define TG3_EEPROM_SB_REVISION_4 0x00040000
2106#define TG3_EEPROM_SB_REVISION_5 0x00050000
2107#define TG3_EEPROM_SB_REVISION_6 0x00060000
2108#define TG3_EEPROM_MAGIC_HW 0xabcd
2109#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2110
2111#define TG3_NVM_DIR_START 0x18
2112#define TG3_NVM_DIR_END 0x78
2113#define TG3_NVM_DIRENT_SIZE 0xc
2114#define TG3_NVM_DIRTYPE_SHIFT 24
2115#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2116#define TG3_NVM_DIRTYPE_ASFINI 1
2117#define TG3_NVM_DIRTYPE_EXTVPD 20
2118#define TG3_NVM_PTREV_BCVER 0x94
2119#define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2120#define TG3_NVM_BCVER_MAJSFT 8
2121#define TG3_NVM_BCVER_MINMSK 0x000000ff
2122
2123#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2124#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2125#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2126#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2127#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2128#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2129#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2130#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2131#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2132#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2133#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2134#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2135
2136
2137
2138#define NIC_SRAM_WIN_BASE 0x00008000
2139
2140
2141#define NIC_SRAM_PAGE_ZERO 0x00000000
2142#define NIC_SRAM_SEND_RCB 0x00000100
2143#define NIC_SRAM_RCV_RET_RCB 0x00000200
2144#define NIC_SRAM_STATS_BLK 0x00000300
2145#define NIC_SRAM_STATUS_BLK 0x00000b00
2146
2147#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2148#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2149#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b
2150
2151#define NIC_SRAM_DATA_SIG 0x00000b54
2152#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654
2153
2154#define NIC_SRAM_DATA_CFG 0x00000b58
2155#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2156#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2157#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2158#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2159#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2160#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2161#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2162#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2163#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2164#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2165#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2166#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2167#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2168#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2169#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2170
2171#define NIC_SRAM_DATA_VER 0x00000b5c
2172#define NIC_SRAM_DATA_VER_SHIFT 16
2173
2174#define NIC_SRAM_DATA_PHY_ID 0x00000b74
2175#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2176#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2177
2178#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2179#define FWCMD_NICDRV_ALIVE 0x00000001
2180#define FWCMD_NICDRV_PAUSE_FW 0x00000002
2181#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2182#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2183#define FWCMD_NICDRV_FIX_DMAR 0x00000005
2184#define FWCMD_NICDRV_FIX_DMAW 0x00000006
2185#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2186#define FWCMD_NICDRV_ALIVE2 0x0000000d
2187#define FWCMD_NICDRV_ALIVE3 0x0000000e
2188#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2189#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2190#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2191#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2192#define DRV_STATE_START 0x00000001
2193#define DRV_STATE_START_DONE 0x80000001
2194#define DRV_STATE_UNLOAD 0x00000002
2195#define DRV_STATE_UNLOAD_DONE 0x80000002
2196#define DRV_STATE_WOL 0x00000003
2197#define DRV_STATE_SUSPEND 0x00000004
2198
2199#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2200
2201#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2202#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2203
2204#define NIC_SRAM_WOL_MBOX 0x00000d30
2205#define WOL_SIGNATURE 0x474c0000
2206#define WOL_DRV_STATE_SHUTDOWN 0x00000001
2207#define WOL_DRV_WOL 0x00000002
2208#define WOL_SET_MAGIC_PKT 0x00000004
2209
2210#define NIC_SRAM_DATA_CFG_2 0x00000d38
2211
2212#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000
2213#define SHASTA_EXT_LED_MODE_MASK 0x00018000
2214#define SHASTA_EXT_LED_LEGACY 0x00000000
2215#define SHASTA_EXT_LED_SHARED 0x00008000
2216#define SHASTA_EXT_LED_MAC 0x00010000
2217#define SHASTA_EXT_LED_COMBO 0x00018000
2218
2219#define NIC_SRAM_DATA_CFG_3 0x00000d3c
2220#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2221#define NIC_SRAM_LNK_FLAP_AVOID 0x00400000
2222#define NIC_SRAM_1G_ON_VAUX_OK 0x00800000
2223
2224#define NIC_SRAM_DATA_CFG_4 0x00000d60
2225#define NIC_SRAM_GMII_MODE 0x00000002
2226#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2227#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2228#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2229
2230#define NIC_SRAM_CPMU_STATUS 0x00000e00
2231#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2232#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2233
2234#define NIC_SRAM_DATA_CFG_5 0x00000e0c
2235#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002
2236
2237#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2238
2239#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2240#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2241#define NIC_SRAM_TX_BUFFER_DESC 0x00004000
2242#define NIC_SRAM_RX_BUFFER_DESC 0x00006000
2243#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000
2244#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2245#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2246#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2247#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2248#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2249
2250#define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000
2251#define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000
2252#define TG3_57766_FW_BASE_ADDR 0x00030000
2253#define TG3_57766_FW_HANDSHAKE 0x0003fccc
2254#define TG3_SBROM_IN_SERVICE_LOOP 0x51
2255
2256#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2257#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2258#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2259
2260#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2261#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2262
2263
2264
2265#define TG3_PHY_MII_ADDR 0x01
2266
2267
2268
2269#define MII_TG3_MMD_CTRL 0x0d
2270#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2271#define MII_TG3_MMD_ADDRESS 0x0e
2272
2273#define MII_TG3_EXT_CTRL 0x10
2274#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2275#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2276#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2277#define MII_TG3_EXT_CTRL_TBI 0x8000
2278
2279#define MII_TG3_EXT_STAT 0x11
2280#define MII_TG3_EXT_STAT_MDIX 0x2000
2281#define MII_TG3_EXT_STAT_LPASS 0x0100
2282
2283#define MII_TG3_RXR_COUNTERS 0x14
2284#define MII_TG3_DSP_RW_PORT 0x15
2285#define MII_TG3_DSP_CONTROL 0x16
2286#define MII_TG3_DSP_ADDRESS 0x17
2287
2288#define MII_TG3_DSP_TAP1 0x0001
2289#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2290#define MII_TG3_DSP_TAP26 0x001a
2291#define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2292#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2293#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2294#define MII_TG3_DSP_AADJ1CH0 0x001f
2295#define MII_TG3_DSP_CH34TP2 0x4022
2296#define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff
2297#define MII_TG3_DSP_AADJ1CH3 0x601f
2298#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2299#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2300#define MII_TG3_DSP_EXP8 0x0f08
2301#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2302#define MII_TG3_DSP_EXP8_AEDW 0x0200
2303#define MII_TG3_DSP_EXP75 0x0f75
2304#define MII_TG3_DSP_EXP96 0x0f96
2305#define MII_TG3_DSP_EXP97 0x0f97
2306
2307#define MII_TG3_AUX_CTRL 0x18
2308
2309#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2310#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2311#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2312#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2313#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
2314
2315#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2316#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2317#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2318#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2319#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2320#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2321
2322#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2323
2324#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2325#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2326#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2327#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2328#define MII_TG3_AUXCTL_MISC_WREN 0x8000
2329
2330
2331#define MII_TG3_AUX_STAT 0x19
2332#define MII_TG3_AUX_STAT_LPASS 0x0004
2333#define MII_TG3_AUX_STAT_SPDMASK 0x0700
2334#define MII_TG3_AUX_STAT_10HALF 0x0100
2335#define MII_TG3_AUX_STAT_10FULL 0x0200
2336#define MII_TG3_AUX_STAT_100HALF 0x0300
2337#define MII_TG3_AUX_STAT_100_4 0x0400
2338#define MII_TG3_AUX_STAT_100FULL 0x0500
2339#define MII_TG3_AUX_STAT_1000HALF 0x0600
2340#define MII_TG3_AUX_STAT_1000FULL 0x0700
2341#define MII_TG3_AUX_STAT_100 0x0008
2342#define MII_TG3_AUX_STAT_FULL 0x0001
2343
2344#define MII_TG3_ISTAT 0x1a
2345#define MII_TG3_IMASK 0x1b
2346
2347
2348#define MII_TG3_INT_LINKCHG 0x0002
2349#define MII_TG3_INT_SPEEDCHG 0x0004
2350#define MII_TG3_INT_DUPLEXCHG 0x0008
2351#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2352
2353#define MII_TG3_MISC_SHDW 0x1c
2354#define MII_TG3_MISC_SHDW_WREN 0x8000
2355
2356#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2357#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2358#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2359
2360#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2361#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2362#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2363#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2364#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2365#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2366
2367#define MII_TG3_TEST1 0x1e
2368#define MII_TG3_TEST1_TRIM_EN 0x0010
2369#define MII_TG3_TEST1_CRC_EN 0x8000
2370
2371
2372#define TG3_CL45_D7_EEERES_STAT 0x803e
2373#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2374#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2375
2376
2377
2378#define MII_TG3_FET_PTEST 0x17
2379#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
2380#define MII_TG3_FET_PTEST_TRIM_2 0x0002
2381#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2382#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2383
2384#define MII_TG3_FET_GEN_STAT 0x1c
2385#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2386
2387#define MII_TG3_FET_TEST 0x1f
2388#define MII_TG3_FET_SHADOW_EN 0x0080
2389
2390#define MII_TG3_FET_SHDW_MISCCTRL 0x10
2391#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2392
2393#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2394#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2395
2396#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2397#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2398
2399
2400#define SERDES_TG3_1000X_STATUS 0x14
2401#define SERDES_TG3_SGMII_MODE 0x0001
2402#define SERDES_TG3_LINK_UP 0x0002
2403#define SERDES_TG3_FULL_DUPLEX 0x0004
2404#define SERDES_TG3_SPEED_100 0x0008
2405#define SERDES_TG3_SPEED_1000 0x0010
2406
2407
2408#define TG3_APE_GPIO_MSG 0x0008
2409#define TG3_APE_GPIO_MSG_SHIFT 4
2410#define TG3_APE_EVENT 0x000c
2411#define APE_EVENT_1 0x00000001
2412#define TG3_APE_LOCK_REQ 0x002c
2413#define APE_LOCK_REQ_DRIVER 0x00001000
2414#define TG3_APE_LOCK_GRANT 0x004c
2415#define APE_LOCK_GRANT_DRIVER 0x00001000
2416#define TG3_APE_OTP_CTRL 0x00e8
2417#define APE_OTP_CTRL_PROG_EN 0x200000
2418#define APE_OTP_CTRL_CMD_RD 0x000000
2419#define APE_OTP_CTRL_START 0x000001
2420#define TG3_APE_OTP_STATUS 0x00ec
2421#define APE_OTP_STATUS_CMD_DONE 0x000001
2422#define TG3_APE_OTP_ADDR 0x00f0
2423#define APE_OTP_ADDR_CPU_ENABLE 0x80000000
2424#define TG3_APE_OTP_RD_DATA 0x00f8
2425
2426#define OTP_ADDRESS_MAGIC0 0x00000050
2427#define TG3_OTP_MAGIC0_VALID(val) \
2428 ((((val) & 0xf0000000) == 0xa0000000) ||\
2429 (((val) & 0x0f000000) == 0x0a000000))
2430
2431
2432#define TG3_APE_SHMEM_BASE 0x4000
2433#define TG3_APE_SEG_SIG 0x4000
2434#define APE_SEG_SIG_MAGIC 0x41504521
2435#define TG3_APE_FW_STATUS 0x400c
2436#define APE_FW_STATUS_READY 0x00000100
2437#define TG3_APE_FW_FEATURES 0x4010
2438#define TG3_APE_FW_FEATURE_NCSI 0x00000002
2439#define TG3_APE_FW_VERSION 0x4018
2440#define APE_FW_VERSION_MAJMSK 0xff000000
2441#define APE_FW_VERSION_MAJSFT 24
2442#define APE_FW_VERSION_MINMSK 0x00ff0000
2443#define APE_FW_VERSION_MINSFT 16
2444#define APE_FW_VERSION_REVMSK 0x0000ff00
2445#define APE_FW_VERSION_REVSFT 8
2446#define APE_FW_VERSION_BLDMSK 0x000000ff
2447#define TG3_APE_SEG_MSG_BUF_OFF 0x401c
2448#define TG3_APE_SEG_MSG_BUF_LEN 0x4020
2449#define TG3_APE_HOST_SEG_SIG 0x4200
2450#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2451#define TG3_APE_HOST_SEG_LEN 0x4204
2452#define APE_HOST_SEG_LEN_MAGIC 0x00000020
2453#define TG3_APE_HOST_INIT_COUNT 0x4208
2454#define TG3_APE_HOST_DRIVER_ID 0x420c
2455#define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2456#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2457 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2458#define TG3_APE_HOST_BEHAVIOR 0x4210
2459#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2460#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2461#define APE_HOST_HEARTBEAT_INT_DISABLE 0
2462#define APE_HOST_HEARTBEAT_INT_5SEC 5000
2463#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2464#define TG3_APE_HOST_DRVR_STATE 0x421c
2465#define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2466#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2467#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2468#define TG3_APE_HOST_WOL_SPEED 0x4224
2469#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2470
2471#define TG3_APE_EVENT_STATUS 0x4300
2472
2473#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2474#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2475#define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600
2476#define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2477#define APE_EVENT_STATUS_STATE_START 0x00010000
2478#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2479#define APE_EVENT_STATUS_STATE_WOL 0x00030000
2480#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2481#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2482
2483#define TG3_APE_PER_LOCK_REQ 0x8400
2484#define APE_LOCK_PER_REQ_DRIVER 0x00001000
2485#define TG3_APE_PER_LOCK_GRANT 0x8420
2486#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2487
2488
2489#define TG3_APE_LOCK_PHY0 0
2490#define TG3_APE_LOCK_GRC 1
2491#define TG3_APE_LOCK_PHY1 2
2492#define TG3_APE_LOCK_PHY2 3
2493#define TG3_APE_LOCK_MEM 4
2494#define TG3_APE_LOCK_PHY3 5
2495#define TG3_APE_LOCK_GPIO 7
2496
2497#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2498
2499
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2527
2528
2529
2530
2531
2532
2533
2534
2535
2536struct tg3_tx_buffer_desc {
2537 u32 addr_hi;
2538 u32 addr_lo;
2539
2540 u32 len_flags;
2541#define TXD_FLAG_TCPUDP_CSUM 0x0001
2542#define TXD_FLAG_IP_CSUM 0x0002
2543#define TXD_FLAG_END 0x0004
2544#define TXD_FLAG_IP_FRAG 0x0008
2545#define TXD_FLAG_JMB_PKT 0x0008
2546#define TXD_FLAG_IP_FRAG_END 0x0010
2547#define TXD_FLAG_HWTSTAMP 0x0020
2548#define TXD_FLAG_VLAN 0x0040
2549#define TXD_FLAG_COAL_NOW 0x0080
2550#define TXD_FLAG_CPU_PRE_DMA 0x0100
2551#define TXD_FLAG_CPU_POST_DMA 0x0200
2552#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2553#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2554#define TXD_FLAG_NO_CRC 0x8000
2555#define TXD_LEN_SHIFT 16
2556
2557 u32 vlan_tag;
2558#define TXD_VLAN_TAG_SHIFT 0
2559#define TXD_MSS_SHIFT 16
2560};
2561
2562#define TXD_ADDR 0x00UL
2563#define TXD_LEN_FLAGS 0x08UL
2564#define TXD_VLAN_TAG 0x0cUL
2565#define TXD_SIZE 0x10UL
2566
2567struct tg3_rx_buffer_desc {
2568 u32 addr_hi;
2569 u32 addr_lo;
2570
2571 u32 idx_len;
2572#define RXD_IDX_MASK 0xffff0000
2573#define RXD_IDX_SHIFT 16
2574#define RXD_LEN_MASK 0x0000ffff
2575#define RXD_LEN_SHIFT 0
2576
2577 u32 type_flags;
2578#define RXD_TYPE_SHIFT 16
2579#define RXD_FLAGS_SHIFT 0
2580
2581#define RXD_FLAG_END 0x0004
2582#define RXD_FLAG_MINI 0x0800
2583#define RXD_FLAG_JUMBO 0x0020
2584#define RXD_FLAG_VLAN 0x0040
2585#define RXD_FLAG_ERROR 0x0400
2586#define RXD_FLAG_IP_CSUM 0x1000
2587#define RXD_FLAG_TCPUDP_CSUM 0x2000
2588#define RXD_FLAG_IS_TCP 0x4000
2589#define RXD_FLAG_PTPSTAT_MASK 0x0210
2590#define RXD_FLAG_PTPSTAT_PTPV1 0x0010
2591#define RXD_FLAG_PTPSTAT_PTPV2 0x0200
2592
2593 u32 ip_tcp_csum;
2594#define RXD_IPCSUM_MASK 0xffff0000
2595#define RXD_IPCSUM_SHIFT 16
2596#define RXD_TCPCSUM_MASK 0x0000ffff
2597#define RXD_TCPCSUM_SHIFT 0
2598
2599 u32 err_vlan;
2600
2601#define RXD_VLAN_MASK 0x0000ffff
2602
2603#define RXD_ERR_BAD_CRC 0x00010000
2604#define RXD_ERR_COLLISION 0x00020000
2605#define RXD_ERR_LINK_LOST 0x00040000
2606#define RXD_ERR_PHY_DECODE 0x00080000
2607#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2608#define RXD_ERR_MAC_ABRT 0x00200000
2609#define RXD_ERR_TOO_SMALL 0x00400000
2610#define RXD_ERR_NO_RESOURCES 0x00800000
2611#define RXD_ERR_HUGE_FRAME 0x01000000
2612
2613#define RXD_ERR_MASK (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION | \
2614 RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE | \
2615 RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL | \
2616 RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME)
2617
2618 u32 reserved;
2619 u32 opaque;
2620#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2621#define RXD_OPAQUE_INDEX_SHIFT 0
2622#define RXD_OPAQUE_RING_STD 0x00010000
2623#define RXD_OPAQUE_RING_JUMBO 0x00020000
2624#define RXD_OPAQUE_RING_MINI 0x00040000
2625#define RXD_OPAQUE_RING_MASK 0x00070000
2626};
2627
2628struct tg3_ext_rx_buffer_desc {
2629 struct {
2630 u32 addr_hi;
2631 u32 addr_lo;
2632 } addrlist[3];
2633 u32 len2_len1;
2634 u32 resv_len3;
2635 struct tg3_rx_buffer_desc std;
2636};
2637
2638
2639
2640
2641
2642struct tg3_internal_buffer_desc {
2643 u32 addr_hi;
2644 u32 addr_lo;
2645 u32 nic_mbuf;
2646
2647#ifdef __BIG_ENDIAN
2648 u16 cqid_sqid;
2649 u16 len;
2650#else
2651 u16 len;
2652 u16 cqid_sqid;
2653#endif
2654 u32 flags;
2655 u32 __cookie1;
2656 u32 __cookie2;
2657 u32 __cookie3;
2658};
2659
2660#define TG3_HW_STATUS_SIZE 0x50
2661struct tg3_hw_status {
2662 u32 status;
2663#define SD_STATUS_UPDATED 0x00000001
2664#define SD_STATUS_LINK_CHG 0x00000002
2665#define SD_STATUS_ERROR 0x00000004
2666
2667 u32 status_tag;
2668
2669#ifdef __BIG_ENDIAN
2670 u16 rx_consumer;
2671 u16 rx_jumbo_consumer;
2672#else
2673 u16 rx_jumbo_consumer;
2674 u16 rx_consumer;
2675#endif
2676
2677#ifdef __BIG_ENDIAN
2678 u16 reserved;
2679 u16 rx_mini_consumer;
2680#else
2681 u16 rx_mini_consumer;
2682 u16 reserved;
2683#endif
2684 struct {
2685#ifdef __BIG_ENDIAN
2686 u16 tx_consumer;
2687 u16 rx_producer;
2688#else
2689 u16 rx_producer;
2690 u16 tx_consumer;
2691#endif
2692 } idx[16];
2693};
2694
2695typedef struct {
2696 u32 high, low;
2697} tg3_stat64_t;
2698
2699struct tg3_hw_stats {
2700 u8 __reserved0[0x400-0x300];
2701
2702
2703 tg3_stat64_t rx_octets;
2704 u64 __reserved1;
2705 tg3_stat64_t rx_fragments;
2706 tg3_stat64_t rx_ucast_packets;
2707 tg3_stat64_t rx_mcast_packets;
2708 tg3_stat64_t rx_bcast_packets;
2709 tg3_stat64_t rx_fcs_errors;
2710 tg3_stat64_t rx_align_errors;
2711 tg3_stat64_t rx_xon_pause_rcvd;
2712 tg3_stat64_t rx_xoff_pause_rcvd;
2713 tg3_stat64_t rx_mac_ctrl_rcvd;
2714 tg3_stat64_t rx_xoff_entered;
2715 tg3_stat64_t rx_frame_too_long_errors;
2716 tg3_stat64_t rx_jabbers;
2717 tg3_stat64_t rx_undersize_packets;
2718 tg3_stat64_t rx_in_length_errors;
2719 tg3_stat64_t rx_out_length_errors;
2720 tg3_stat64_t rx_64_or_less_octet_packets;
2721 tg3_stat64_t rx_65_to_127_octet_packets;
2722 tg3_stat64_t rx_128_to_255_octet_packets;
2723 tg3_stat64_t rx_256_to_511_octet_packets;
2724 tg3_stat64_t rx_512_to_1023_octet_packets;
2725 tg3_stat64_t rx_1024_to_1522_octet_packets;
2726 tg3_stat64_t rx_1523_to_2047_octet_packets;
2727 tg3_stat64_t rx_2048_to_4095_octet_packets;
2728 tg3_stat64_t rx_4096_to_8191_octet_packets;
2729 tg3_stat64_t rx_8192_to_9022_octet_packets;
2730
2731 u64 __unused0[37];
2732
2733
2734 tg3_stat64_t tx_octets;
2735 u64 __reserved2;
2736 tg3_stat64_t tx_collisions;
2737 tg3_stat64_t tx_xon_sent;
2738 tg3_stat64_t tx_xoff_sent;
2739 tg3_stat64_t tx_flow_control;
2740 tg3_stat64_t tx_mac_errors;
2741 tg3_stat64_t tx_single_collisions;
2742 tg3_stat64_t tx_mult_collisions;
2743 tg3_stat64_t tx_deferred;
2744 u64 __reserved3;
2745 tg3_stat64_t tx_excessive_collisions;
2746 tg3_stat64_t tx_late_collisions;
2747 tg3_stat64_t tx_collide_2times;
2748 tg3_stat64_t tx_collide_3times;
2749 tg3_stat64_t tx_collide_4times;
2750 tg3_stat64_t tx_collide_5times;
2751 tg3_stat64_t tx_collide_6times;
2752 tg3_stat64_t tx_collide_7times;
2753 tg3_stat64_t tx_collide_8times;
2754 tg3_stat64_t tx_collide_9times;
2755 tg3_stat64_t tx_collide_10times;
2756 tg3_stat64_t tx_collide_11times;
2757 tg3_stat64_t tx_collide_12times;
2758 tg3_stat64_t tx_collide_13times;
2759 tg3_stat64_t tx_collide_14times;
2760 tg3_stat64_t tx_collide_15times;
2761 tg3_stat64_t tx_ucast_packets;
2762 tg3_stat64_t tx_mcast_packets;
2763 tg3_stat64_t tx_bcast_packets;
2764 tg3_stat64_t tx_carrier_sense_errors;
2765 tg3_stat64_t tx_discards;
2766 tg3_stat64_t tx_errors;
2767
2768 u64 __unused1[31];
2769
2770
2771 tg3_stat64_t COS_rx_packets[16];
2772 tg3_stat64_t COS_rx_filter_dropped;
2773 tg3_stat64_t dma_writeq_full;
2774 tg3_stat64_t dma_write_prioq_full;
2775 tg3_stat64_t rxbds_empty;
2776 tg3_stat64_t rx_discards;
2777 tg3_stat64_t rx_errors;
2778 tg3_stat64_t rx_threshold_hit;
2779
2780 u64 __unused2[9];
2781
2782
2783 tg3_stat64_t COS_out_packets[16];
2784 tg3_stat64_t dma_readq_full;
2785 tg3_stat64_t dma_read_prioq_full;
2786 tg3_stat64_t tx_comp_queue_full;
2787
2788
2789 tg3_stat64_t ring_set_send_prod_index;
2790 tg3_stat64_t ring_status_update;
2791 tg3_stat64_t nic_irqs;
2792 tg3_stat64_t nic_avoided_irqs;
2793 tg3_stat64_t nic_tx_threshold_hit;
2794
2795
2796
2797
2798 tg3_stat64_t mbuf_lwm_thresh_hit;
2799
2800 u8 __reserved4[0xb00-0x9c8];
2801};
2802
2803#define TG3_SD_NUM_RECS 3
2804#define TG3_OCIR_LEN (sizeof(struct tg3_ocir))
2805#define TG3_OCIR_SIG_MAGIC 0x5253434f
2806#define TG3_OCIR_FLAG_ACTIVE 0x00000001
2807
2808#define TG3_TEMP_CAUTION_OFFSET 0xc8
2809#define TG3_TEMP_MAX_OFFSET 0xcc
2810#define TG3_TEMP_SENSOR_OFFSET 0xd4
2811
2812
2813struct tg3_ocir {
2814 u32 signature;
2815 u16 version_flags;
2816 u16 refresh_int;
2817 u32 refresh_tmr;
2818 u32 update_tmr;
2819 u32 dst_base_addr;
2820 u16 src_hdr_offset;
2821 u16 src_hdr_length;
2822 u16 src_data_offset;
2823 u16 src_data_length;
2824 u16 dst_hdr_offset;
2825 u16 dst_data_offset;
2826 u16 dst_reg_upd_offset;
2827 u16 dst_sem_offset;
2828 u32 reserved1[2];
2829 u32 port0_flags;
2830 u32 port1_flags;
2831 u32 port2_flags;
2832 u32 port3_flags;
2833 u32 reserved2[1];
2834};
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845struct ring_info {
2846 u8 *data;
2847 DEFINE_DMA_UNMAP_ADDR(mapping);
2848};
2849
2850struct tg3_tx_ring_info {
2851 struct sk_buff *skb;
2852 DEFINE_DMA_UNMAP_ADDR(mapping);
2853 bool fragmented;
2854};
2855
2856struct tg3_link_config {
2857
2858 u32 advertising;
2859 u16 speed;
2860 u8 duplex;
2861 u8 autoneg;
2862 u8 flowctrl;
2863
2864
2865 u8 active_flowctrl;
2866
2867 u8 active_duplex;
2868 u16 active_speed;
2869 u32 rmt_adv;
2870};
2871
2872struct tg3_bufmgr_config {
2873 u32 mbuf_read_dma_low_water;
2874 u32 mbuf_mac_rx_low_water;
2875 u32 mbuf_high_water;
2876
2877 u32 mbuf_read_dma_low_water_jumbo;
2878 u32 mbuf_mac_rx_low_water_jumbo;
2879 u32 mbuf_high_water_jumbo;
2880
2881 u32 dma_low_water;
2882 u32 dma_high_water;
2883};
2884
2885struct tg3_ethtool_stats {
2886
2887 u64 rx_octets;
2888 u64 rx_fragments;
2889 u64 rx_ucast_packets;
2890 u64 rx_mcast_packets;
2891 u64 rx_bcast_packets;
2892 u64 rx_fcs_errors;
2893 u64 rx_align_errors;
2894 u64 rx_xon_pause_rcvd;
2895 u64 rx_xoff_pause_rcvd;
2896 u64 rx_mac_ctrl_rcvd;
2897 u64 rx_xoff_entered;
2898 u64 rx_frame_too_long_errors;
2899 u64 rx_jabbers;
2900 u64 rx_undersize_packets;
2901 u64 rx_in_length_errors;
2902 u64 rx_out_length_errors;
2903 u64 rx_64_or_less_octet_packets;
2904 u64 rx_65_to_127_octet_packets;
2905 u64 rx_128_to_255_octet_packets;
2906 u64 rx_256_to_511_octet_packets;
2907 u64 rx_512_to_1023_octet_packets;
2908 u64 rx_1024_to_1522_octet_packets;
2909 u64 rx_1523_to_2047_octet_packets;
2910 u64 rx_2048_to_4095_octet_packets;
2911 u64 rx_4096_to_8191_octet_packets;
2912 u64 rx_8192_to_9022_octet_packets;
2913
2914
2915 u64 tx_octets;
2916 u64 tx_collisions;
2917 u64 tx_xon_sent;
2918 u64 tx_xoff_sent;
2919 u64 tx_flow_control;
2920 u64 tx_mac_errors;
2921 u64 tx_single_collisions;
2922 u64 tx_mult_collisions;
2923 u64 tx_deferred;
2924 u64 tx_excessive_collisions;
2925 u64 tx_late_collisions;
2926 u64 tx_collide_2times;
2927 u64 tx_collide_3times;
2928 u64 tx_collide_4times;
2929 u64 tx_collide_5times;
2930 u64 tx_collide_6times;
2931 u64 tx_collide_7times;
2932 u64 tx_collide_8times;
2933 u64 tx_collide_9times;
2934 u64 tx_collide_10times;
2935 u64 tx_collide_11times;
2936 u64 tx_collide_12times;
2937 u64 tx_collide_13times;
2938 u64 tx_collide_14times;
2939 u64 tx_collide_15times;
2940 u64 tx_ucast_packets;
2941 u64 tx_mcast_packets;
2942 u64 tx_bcast_packets;
2943 u64 tx_carrier_sense_errors;
2944 u64 tx_discards;
2945 u64 tx_errors;
2946
2947
2948 u64 dma_writeq_full;
2949 u64 dma_write_prioq_full;
2950 u64 rxbds_empty;
2951 u64 rx_discards;
2952 u64 rx_errors;
2953 u64 rx_threshold_hit;
2954
2955
2956 u64 dma_readq_full;
2957 u64 dma_read_prioq_full;
2958 u64 tx_comp_queue_full;
2959
2960
2961 u64 ring_set_send_prod_index;
2962 u64 ring_status_update;
2963 u64 nic_irqs;
2964 u64 nic_avoided_irqs;
2965 u64 nic_tx_threshold_hit;
2966
2967 u64 mbuf_lwm_thresh_hit;
2968};
2969
2970struct tg3_rx_prodring_set {
2971 u32 rx_std_prod_idx;
2972 u32 rx_std_cons_idx;
2973 u32 rx_jmb_prod_idx;
2974 u32 rx_jmb_cons_idx;
2975 struct tg3_rx_buffer_desc *rx_std;
2976 struct tg3_ext_rx_buffer_desc *rx_jmb;
2977 struct ring_info *rx_std_buffers;
2978 struct ring_info *rx_jmb_buffers;
2979 dma_addr_t rx_std_mapping;
2980 dma_addr_t rx_jmb_mapping;
2981};
2982
2983#define TG3_RSS_MAX_NUM_QS 4
2984#define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1)
2985#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2986
2987struct tg3_napi {
2988 struct napi_struct napi ____cacheline_aligned;
2989 struct tg3 *tp;
2990 struct tg3_hw_status *hw_status;
2991
2992 u32 chk_msi_cnt;
2993 u32 last_tag;
2994 u32 last_irq_tag;
2995 u32 int_mbox;
2996 u32 coal_now;
2997
2998 u32 consmbox ____cacheline_aligned;
2999 u32 rx_rcb_ptr;
3000 u32 last_rx_cons;
3001 u16 *rx_rcb_prod_idx;
3002 struct tg3_rx_prodring_set prodring;
3003 struct tg3_rx_buffer_desc *rx_rcb;
3004
3005 u32 tx_prod ____cacheline_aligned;
3006 u32 tx_cons;
3007 u32 tx_pending;
3008 u32 last_tx_cons;
3009 u32 prodmbox;
3010 struct tg3_tx_buffer_desc *tx_ring;
3011 struct tg3_tx_ring_info *tx_buffers;
3012
3013 dma_addr_t status_mapping;
3014 dma_addr_t rx_rcb_mapping;
3015 dma_addr_t tx_desc_mapping;
3016
3017 char irq_lbl[IFNAMSIZ];
3018 unsigned int irq_vec;
3019};
3020
3021enum TG3_FLAGS {
3022 TG3_FLAG_TAGGED_STATUS = 0,
3023 TG3_FLAG_TXD_MBOX_HWBUG,
3024 TG3_FLAG_USE_LINKCHG_REG,
3025 TG3_FLAG_ERROR_PROCESSED,
3026 TG3_FLAG_ENABLE_ASF,
3027 TG3_FLAG_ASPM_WORKAROUND,
3028 TG3_FLAG_POLL_SERDES,
3029 TG3_FLAG_POLL_CPMU_LINK,
3030 TG3_FLAG_MBOX_WRITE_REORDER,
3031 TG3_FLAG_PCIX_TARGET_HWBUG,
3032 TG3_FLAG_WOL_SPEED_100MB,
3033 TG3_FLAG_WOL_ENABLE,
3034 TG3_FLAG_EEPROM_WRITE_PROT,
3035 TG3_FLAG_NVRAM,
3036 TG3_FLAG_NVRAM_BUFFERED,
3037 TG3_FLAG_SUPPORT_MSI,
3038 TG3_FLAG_SUPPORT_MSIX,
3039 TG3_FLAG_USING_MSI,
3040 TG3_FLAG_USING_MSIX,
3041 TG3_FLAG_PCIX_MODE,
3042 TG3_FLAG_PCI_HIGH_SPEED,
3043 TG3_FLAG_PCI_32BIT,
3044 TG3_FLAG_SRAM_USE_CONFIG,
3045 TG3_FLAG_TX_RECOVERY_PENDING,
3046 TG3_FLAG_WOL_CAP,
3047 TG3_FLAG_JUMBO_RING_ENABLE,
3048 TG3_FLAG_PAUSE_AUTONEG,
3049 TG3_FLAG_CPMU_PRESENT,
3050 TG3_FLAG_40BIT_DMA_BUG,
3051 TG3_FLAG_BROKEN_CHECKSUMS,
3052 TG3_FLAG_JUMBO_CAPABLE,
3053 TG3_FLAG_CHIP_RESETTING,
3054 TG3_FLAG_INIT_COMPLETE,
3055 TG3_FLAG_MAX_RXPEND_64,
3056 TG3_FLAG_PCI_EXPRESS,
3057 TG3_FLAG_ASF_NEW_HANDSHAKE,
3058 TG3_FLAG_HW_AUTONEG,
3059 TG3_FLAG_IS_NIC,
3060 TG3_FLAG_FLASH,
3061 TG3_FLAG_FW_TSO,
3062 TG3_FLAG_HW_TSO_1,
3063 TG3_FLAG_HW_TSO_2,
3064 TG3_FLAG_HW_TSO_3,
3065 TG3_FLAG_TSO_CAPABLE,
3066 TG3_FLAG_TSO_BUG,
3067 TG3_FLAG_ICH_WORKAROUND,
3068 TG3_FLAG_1SHOT_MSI,
3069 TG3_FLAG_NO_FWARE_REPORTED,
3070 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
3071 TG3_FLAG_ENABLE_APE,
3072 TG3_FLAG_PROTECTED_NVRAM,
3073 TG3_FLAG_5701_DMA_BUG,
3074 TG3_FLAG_USE_PHYLIB,
3075 TG3_FLAG_MDIOBUS_INITED,
3076 TG3_FLAG_LRG_PROD_RING_CAP,
3077 TG3_FLAG_RGMII_INBAND_DISABLE,
3078 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
3079 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
3080 TG3_FLAG_CLKREQ_BUG,
3081 TG3_FLAG_NO_NVRAM,
3082 TG3_FLAG_ENABLE_RSS,
3083 TG3_FLAG_ENABLE_TSS,
3084 TG3_FLAG_SHORT_DMA_BUG,
3085 TG3_FLAG_USE_JUMBO_BDFLAG,
3086 TG3_FLAG_L1PLLPD_EN,
3087 TG3_FLAG_APE_HAS_NCSI,
3088 TG3_FLAG_TX_TSTAMP_EN,
3089 TG3_FLAG_4K_FIFO_LIMIT,
3090 TG3_FLAG_5719_5720_RDMA_BUG,
3091 TG3_FLAG_RESET_TASK_PENDING,
3092 TG3_FLAG_PTP_CAPABLE,
3093 TG3_FLAG_5705_PLUS,
3094 TG3_FLAG_IS_5788,
3095 TG3_FLAG_5750_PLUS,
3096 TG3_FLAG_5780_CLASS,
3097 TG3_FLAG_5755_PLUS,
3098 TG3_FLAG_57765_PLUS,
3099 TG3_FLAG_57765_CLASS,
3100 TG3_FLAG_5717_PLUS,
3101 TG3_FLAG_IS_SSB_CORE,
3102 TG3_FLAG_FLUSH_POSTED_WRITES,
3103 TG3_FLAG_ROBOSWITCH,
3104 TG3_FLAG_ONE_DMA_AT_ONCE,
3105 TG3_FLAG_RGMII_MODE,
3106
3107
3108 TG3_FLAG_NUMBER_OF_FLAGS,
3109};
3110
3111struct tg3_firmware_hdr {
3112 __be32 version;
3113 __be32 base_addr;
3114 __be32 len;
3115};
3116#define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr))
3117
3118struct tg3 {
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136 unsigned int irq_sync;
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157 spinlock_t lock;
3158 spinlock_t indirect_lock;
3159
3160 u32 (*read32) (struct tg3 *, u32);
3161 void (*write32) (struct tg3 *, u32, u32);
3162 u32 (*read32_mbox) (struct tg3 *, u32);
3163 void (*write32_mbox) (struct tg3 *, u32,
3164 u32);
3165 void __iomem *regs;
3166 void __iomem *aperegs;
3167 struct net_device *dev;
3168 struct pci_dev *pdev;
3169
3170 u32 coal_now;
3171 u32 msg_enable;
3172
3173 struct ptp_clock_info ptp_info;
3174 struct ptp_clock *ptp_clock;
3175 s64 ptp_adjust;
3176
3177
3178 void (*write32_tx_mbox) (struct tg3 *, u32,
3179 u32);
3180 u32 dma_limit;
3181 u32 txq_req;
3182 u32 txq_cnt;
3183 u32 txq_max;
3184
3185
3186 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
3187 void (*write32_rx_mbox) (struct tg3 *, u32,
3188 u32);
3189 u32 rx_copy_thresh;
3190 u32 rx_std_ring_mask;
3191 u32 rx_jmb_ring_mask;
3192 u32 rx_ret_ring_mask;
3193 u32 rx_pending;
3194 u32 rx_jumbo_pending;
3195 u32 rx_std_max_post;
3196 u32 rx_offset;
3197 u32 rx_pkt_map_sz;
3198 u32 rxq_req;
3199 u32 rxq_cnt;
3200 u32 rxq_max;
3201 bool rx_refill;
3202
3203
3204
3205 unsigned long rx_dropped;
3206 unsigned long tx_dropped;
3207 struct rtnl_link_stats64 net_stats_prev;
3208 struct tg3_ethtool_stats estats_prev;
3209
3210 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3211
3212 union {
3213 unsigned long phy_crc_errors;
3214 unsigned long last_event_jiffies;
3215 };
3216
3217 struct timer_list timer;
3218 u16 timer_counter;
3219 u16 timer_multiplier;
3220 u32 timer_offset;
3221 u16 asf_counter;
3222 u16 asf_multiplier;
3223
3224
3225 u32 serdes_counter;
3226#define SERDES_AN_TIMEOUT_5704S 2
3227#define SERDES_PARALLEL_DET_TIMEOUT 1
3228#define SERDES_AN_TIMEOUT_5714S 1
3229
3230 struct tg3_link_config link_config;
3231 struct tg3_bufmgr_config bufmgr_config;
3232
3233
3234 u32 rx_mode;
3235 u32 tx_mode;
3236 u32 mac_mode;
3237 u32 mi_mode;
3238 u32 misc_host_ctrl;
3239 u32 grc_mode;
3240 u32 grc_local_ctrl;
3241 u32 dma_rwctrl;
3242 u32 coalesce_mode;
3243 u32 pwrmgmt_thresh;
3244 u32 rxptpctl;
3245
3246
3247 u32 pci_chip_rev_id;
3248 u16 pci_cmd;
3249 u8 pci_cacheline_sz;
3250 u8 pci_lat_timer;
3251
3252 int pci_fn;
3253 int msi_cap;
3254 int pcix_cap;
3255 int pcie_readrq;
3256
3257 struct mii_bus *mdio_bus;
3258 int old_link;
3259
3260 u8 phy_addr;
3261 u8 phy_ape_lock;
3262
3263
3264 u32 phy_id;
3265#define TG3_PHY_ID_MASK 0xfffffff0
3266#define TG3_PHY_ID_BCM5400 0x60008040
3267#define TG3_PHY_ID_BCM5401 0x60008050
3268#define TG3_PHY_ID_BCM5411 0x60008070
3269#define TG3_PHY_ID_BCM5701 0x60008110
3270#define TG3_PHY_ID_BCM5703 0x60008160
3271#define TG3_PHY_ID_BCM5704 0x60008190
3272#define TG3_PHY_ID_BCM5705 0x600081a0
3273#define TG3_PHY_ID_BCM5750 0x60008180
3274#define TG3_PHY_ID_BCM5752 0x60008100
3275#define TG3_PHY_ID_BCM5714 0x60008340
3276#define TG3_PHY_ID_BCM5780 0x60008350
3277#define TG3_PHY_ID_BCM5755 0xbc050cc0
3278#define TG3_PHY_ID_BCM5787 0xbc050ce0
3279#define TG3_PHY_ID_BCM5756 0xbc050ed0
3280#define TG3_PHY_ID_BCM5784 0xbc050fa0
3281#define TG3_PHY_ID_BCM5761 0xbc050fd0
3282#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3283#define TG3_PHY_ID_BCM5718S 0xbc050ff0
3284#define TG3_PHY_ID_BCM57765 0x5c0d8a40
3285#define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3286#define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3287#define TG3_PHY_ID_BCM5762 0x85803780
3288#define TG3_PHY_ID_BCM5906 0xdc00ac40
3289#define TG3_PHY_ID_BCM8002 0x60010140
3290#define TG3_PHY_ID_INVALID 0xffffffff
3291
3292#define PHY_ID_RTL8211C 0x001cc910
3293#define PHY_ID_RTL8201E 0x00008200
3294
3295#define TG3_PHY_ID_REV_MASK 0x0000000f
3296#define TG3_PHY_REV_BCM5401_B0 0x1
3297
3298
3299
3300
3301#define TG3_KNOWN_PHY_ID(X) \
3302 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3303 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3304 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3305 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3306 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3307 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3308 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3309 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3310 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3311 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3312 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \
3313 (X) == TG3_PHY_ID_BCM8002)
3314
3315 u32 phy_flags;
3316#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3317#define TG3_PHYFLG_IS_CONNECTED 0x00000002
3318#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3319#define TG3_PHYFLG_USER_CONFIGURED 0x00000008
3320#define TG3_PHYFLG_PHY_SERDES 0x00000010
3321#define TG3_PHYFLG_MII_SERDES 0x00000020
3322#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3323 TG3_PHYFLG_MII_SERDES)
3324#define TG3_PHYFLG_IS_FET 0x00000040
3325#define TG3_PHYFLG_10_100_ONLY 0x00000080
3326#define TG3_PHYFLG_ENABLE_APD 0x00000100
3327#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3328#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3329#define TG3_PHYFLG_JITTER_BUG 0x00000800
3330#define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3331#define TG3_PHYFLG_ADC_BUG 0x00002000
3332#define TG3_PHYFLG_5704_A0_BUG 0x00004000
3333#define TG3_PHYFLG_BER_BUG 0x00008000
3334#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3335#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3336#define TG3_PHYFLG_EEE_CAP 0x00040000
3337#define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000
3338#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000
3339#define TG3_PHYFLG_MDIX_STATE 0x00200000
3340#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000
3341
3342 u32 led_ctrl;
3343 u32 phy_otp;
3344 u32 setlpicnt;
3345 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3346
3347#define TG3_BPN_SIZE 24
3348 char board_part_number[TG3_BPN_SIZE];
3349#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
3350 char fw_ver[TG3_VER_SIZE];
3351 u32 nic_sram_data_cfg;
3352 u32 pci_clock_ctrl;
3353 struct pci_dev *pdev_peer;
3354
3355 struct tg3_hw_stats *hw_stats;
3356 dma_addr_t stats_mapping;
3357 struct work_struct reset_task;
3358
3359 int nvram_lock_cnt;
3360 u32 nvram_size;
3361#define TG3_NVRAM_SIZE_2KB 0x00000800
3362#define TG3_NVRAM_SIZE_64KB 0x00010000
3363#define TG3_NVRAM_SIZE_128KB 0x00020000
3364#define TG3_NVRAM_SIZE_256KB 0x00040000
3365#define TG3_NVRAM_SIZE_512KB 0x00080000
3366#define TG3_NVRAM_SIZE_1MB 0x00100000
3367#define TG3_NVRAM_SIZE_2MB 0x00200000
3368
3369 u32 nvram_pagesize;
3370 u32 nvram_jedecnum;
3371
3372#define JEDEC_ATMEL 0x1f
3373#define JEDEC_ST 0x20
3374#define JEDEC_SAIFUN 0x4f
3375#define JEDEC_SST 0xbf
3376
3377#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3378#define ATMEL_AT24C02_PAGE_SIZE (8)
3379
3380#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3381#define ATMEL_AT24C64_PAGE_SIZE (32)
3382
3383#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3384#define ATMEL_AT24C512_PAGE_SIZE (128)
3385
3386#define ATMEL_AT45DB0X1B_PAGE_POS 9
3387#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3388
3389#define ATMEL_AT25F512_PAGE_SIZE 256
3390
3391#define ST_M45PEX0_PAGE_SIZE 256
3392
3393#define SAIFUN_SA25F0XX_PAGE_SIZE 256
3394
3395#define SST_25VF0X0_PAGE_SIZE 4098
3396
3397 unsigned int irq_max;
3398 unsigned int irq_cnt;
3399
3400 struct ethtool_coalesce coal;
3401 struct ethtool_eee eee;
3402
3403
3404 const char *fw_needed;
3405 const struct firmware *fw;
3406 u32 fw_len;
3407
3408 struct device *hwmon_dev;
3409 bool link_up;
3410 bool pcierr_recovery;
3411};
3412
3413
3414
3415
3416
3417
3418
3419
3420#define tg3_chip_rev_id(tp) \
3421 ((tp)->pci_chip_rev_id)
3422#define tg3_asic_rev(tp) \
3423 ((tp)->pci_chip_rev_id >> 12)
3424#define tg3_chip_rev(tp) \
3425 ((tp)->pci_chip_rev_id >> 8)
3426
3427#endif
3428