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15#ifndef MTK_ETH_H
16#define MTK_ETH_H
17
18#define MTK_QDMA_PAGE_SIZE 2048
19#define MTK_MAX_RX_LENGTH 1536
20#define MTK_TX_DMA_BUF_LEN 0x3fff
21#define MTK_DMA_SIZE 256
22#define MTK_NAPI_WEIGHT 64
23#define MTK_MAC_COUNT 2
24#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
25#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
26#define MTK_DMA_DUMMY_DESC 0xffffffff
27#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
28 NETIF_MSG_PROBE | \
29 NETIF_MSG_LINK | \
30 NETIF_MSG_TIMER | \
31 NETIF_MSG_IFDOWN | \
32 NETIF_MSG_IFUP | \
33 NETIF_MSG_RX_ERR | \
34 NETIF_MSG_TX_ERR)
35#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
36 NETIF_F_RXCSUM | \
37 NETIF_F_HW_VLAN_CTAG_TX | \
38 NETIF_F_HW_VLAN_CTAG_RX | \
39 NETIF_F_SG | NETIF_F_TSO | \
40 NETIF_F_TSO6 | \
41 NETIF_F_IPV6_CSUM)
42#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
43
44#define MTK_MAX_RX_RING_NUM 4
45#define MTK_HW_LRO_DMA_SIZE 8
46
47#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
48#define MTK_MAX_LRO_IP_CNT 2
49#define MTK_HW_LRO_TIMER_UNIT 1
50#define MTK_HW_LRO_REFRESH_TIME 50000
51#define MTK_HW_LRO_AGG_TIME 10
52#define MTK_HW_LRO_AGE_TIME 50
53#define MTK_HW_LRO_MAX_AGG_CNT 64
54#define MTK_HW_LRO_BW_THRE 3000
55#define MTK_HW_LRO_REPLACE_DELTA 1000
56#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
57
58
59#define MTK_RST_GL 0x04
60#define RST_GL_PSE BIT(0)
61
62
63#define MTK_INT_STATUS2 0x08
64#define MTK_GDM1_AF BIT(28)
65#define MTK_GDM2_AF BIT(29)
66
67
68#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
69
70
71#define MTK_FE_INT_GRP 0x20
72
73
74#define MTK_CDMQ_IG_CTRL 0x1400
75#define MTK_CDMQ_STAG_EN BIT(0)
76
77
78#define MTK_CDMP_EG_CTRL 0x404
79
80
81#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
82#define MTK_GDMA_ICS_EN BIT(22)
83#define MTK_GDMA_TCS_EN BIT(21)
84#define MTK_GDMA_UCS_EN BIT(20)
85
86
87#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
88
89
90#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
91
92
93#define MTK_PRX_BASE_PTR0 0x900
94#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
95
96
97#define MTK_PRX_MAX_CNT0 0x904
98#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
99
100
101#define MTK_PRX_CRX_IDX0 0x908
102#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
103
104
105#define MTK_PDMA_LRO_CTRL_DW0 0x980
106#define MTK_LRO_EN BIT(0)
107#define MTK_L3_CKS_UPD_EN BIT(7)
108#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
109#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
110#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
111
112#define MTK_PDMA_LRO_CTRL_DW1 0x984
113#define MTK_PDMA_LRO_CTRL_DW2 0x988
114#define MTK_PDMA_LRO_CTRL_DW3 0x98c
115#define MTK_ADMA_MODE BIT(15)
116#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
117
118
119#define MTK_PDMA_GLO_CFG 0xa04
120#define MTK_MULTI_EN BIT(10)
121
122
123#define MTK_PDMA_RST_IDX 0xa08
124#define MTK_PST_DRX_IDX0 BIT(16)
125#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
126
127
128#define MTK_PDMA_DELAY_INT 0xa0c
129#define MTK_PDMA_DELAY_RX_EN BIT(15)
130#define MTK_PDMA_DELAY_RX_PINT 4
131#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
132#define MTK_PDMA_DELAY_RX_PTIME 4
133#define MTK_PDMA_DELAY_RX_DELAY \
134 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
135 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
136
137
138#define MTK_PDMA_INT_STATUS 0xa20
139
140
141#define MTK_PDMA_INT_MASK 0xa28
142
143
144#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
145
146
147#define MTK_PDMA_INT_GRP1 0xa50
148#define MTK_PDMA_INT_GRP2 0xa54
149
150
151#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
152#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
153#define MTK_RING_MYIP_VLD BIT(9)
154
155
156#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
157#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
158#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
159#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
160#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
161#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
162#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
163#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
164#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
165#define MTK_RING_VLD BIT(8)
166#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
167#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
168#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
169
170
171#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
172#define QDMA_RES_THRES 4
173
174
175#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
176
177
178#define MTK_QRX_BASE_PTR0 0x1900
179
180
181#define MTK_QRX_MAX_CNT0 0x1904
182
183
184#define MTK_QRX_CRX_IDX0 0x1908
185
186
187#define MTK_QRX_DRX_IDX0 0x190C
188
189
190#define MTK_QDMA_GLO_CFG 0x1A04
191#define MTK_RX_2B_OFFSET BIT(31)
192#define MTK_RX_BT_32DWORDS (3 << 11)
193#define MTK_NDP_CO_PRO BIT(10)
194#define MTK_TX_WB_DDONE BIT(6)
195#define MTK_DMA_SIZE_16DWORDS (2 << 4)
196#define MTK_RX_DMA_BUSY BIT(3)
197#define MTK_TX_DMA_BUSY BIT(1)
198#define MTK_RX_DMA_EN BIT(2)
199#define MTK_TX_DMA_EN BIT(0)
200#define MTK_DMA_BUSY_TIMEOUT HZ
201
202
203#define MTK_QDMA_RST_IDX 0x1A08
204
205
206#define MTK_QDMA_DELAY_INT 0x1A0C
207
208
209#define MTK_QDMA_FC_THRES 0x1A10
210#define FC_THRES_DROP_MODE BIT(20)
211#define FC_THRES_DROP_EN (7 << 16)
212#define FC_THRES_MIN 0x4444
213
214
215#define MTK_QMTK_INT_STATUS 0x1A18
216#define MTK_RX_DONE_DLY BIT(30)
217#define MTK_RX_DONE_INT3 BIT(19)
218#define MTK_RX_DONE_INT2 BIT(18)
219#define MTK_RX_DONE_INT1 BIT(17)
220#define MTK_RX_DONE_INT0 BIT(16)
221#define MTK_TX_DONE_INT3 BIT(3)
222#define MTK_TX_DONE_INT2 BIT(2)
223#define MTK_TX_DONE_INT1 BIT(1)
224#define MTK_TX_DONE_INT0 BIT(0)
225#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
226#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
227 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
228
229
230#define MTK_QDMA_INT_GRP1 0x1a20
231#define MTK_QDMA_INT_GRP2 0x1a24
232#define MTK_RLS_DONE_INT BIT(0)
233
234
235#define MTK_QDMA_INT_MASK 0x1A1C
236
237
238#define MTK_QDMA_HRED2 0x1A44
239
240
241#define MTK_QTX_CTX_PTR 0x1B00
242
243
244#define MTK_QTX_DTX_PTR 0x1B04
245
246
247#define MTK_QTX_CRX_PTR 0x1B10
248
249
250#define MTK_QTX_DRX_PTR 0x1B14
251
252
253#define MTK_QDMA_FQ_HEAD 0x1B20
254
255
256#define MTK_QDMA_FQ_TAIL 0x1B24
257
258
259#define MTK_QDMA_FQ_CNT 0x1B28
260
261
262#define MTK_QDMA_FQ_BLEN 0x1B2C
263
264
265#define MTK_GDM1_TX_GBCNT 0x2400
266#define MTK_STAT_OFFSET 0x40
267
268
269#define TX_DMA_CHKSUM (0x7 << 29)
270#define TX_DMA_TSO BIT(28)
271#define TX_DMA_FPORT_SHIFT 25
272#define TX_DMA_FPORT_MASK 0x7
273#define TX_DMA_INS_VLAN BIT(16)
274
275
276#define TX_DMA_OWNER_CPU BIT(31)
277#define TX_DMA_LS0 BIT(30)
278#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
279#define TX_DMA_SWC BIT(14)
280#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
281
282
283#define RX_DMA_DONE BIT(31)
284#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
285#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
286
287
288#define RX_DMA_VID(_x) ((_x) & 0xfff)
289
290
291#define RX_DMA_L4_VALID BIT(24)
292#define RX_DMA_FPORT_SHIFT 19
293#define RX_DMA_FPORT_MASK 0x7
294
295
296#define MTK_PHY_IAC 0x10004
297#define PHY_IAC_ACCESS BIT(31)
298#define PHY_IAC_READ BIT(19)
299#define PHY_IAC_WRITE BIT(18)
300#define PHY_IAC_START BIT(16)
301#define PHY_IAC_ADDR_SHIFT 20
302#define PHY_IAC_REG_SHIFT 25
303#define PHY_IAC_TIMEOUT HZ
304
305#define MTK_MAC_MISC 0x1000c
306#define MTK_MUX_TO_ESW BIT(0)
307
308
309#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
310#define MAC_MCR_MAX_RX_1536 BIT(24)
311#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
312#define MAC_MCR_FORCE_MODE BIT(15)
313#define MAC_MCR_TX_EN BIT(14)
314#define MAC_MCR_RX_EN BIT(13)
315#define MAC_MCR_BACKOFF_EN BIT(9)
316#define MAC_MCR_BACKPR_EN BIT(8)
317#define MAC_MCR_FORCE_RX_FC BIT(5)
318#define MAC_MCR_FORCE_TX_FC BIT(4)
319#define MAC_MCR_SPEED_1000 BIT(3)
320#define MAC_MCR_SPEED_100 BIT(2)
321#define MAC_MCR_FORCE_DPX BIT(1)
322#define MAC_MCR_FORCE_LINK BIT(0)
323#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
324 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
325 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
326 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
327 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
328 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
329
330
331#define TRGMII_RCK_CTRL 0x10300
332#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
333#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
334#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
335#define RXC_DQSISEL BIT(30)
336#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
337#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
338
339
340#define TRGMII_TCK_CTRL 0x10340
341#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
342#define TXC_INV BIT(30)
343#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
344#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
345
346
347#define INTF_MODE 0x10390
348#define TRGMII_INTF_DIS BIT(0)
349#define TRGMII_MODE BIT(1)
350#define TRGMII_CENTRAL_ALIGNED BIT(2)
351#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
352#define INTF_MODE_RGMII_10_100 0
353
354
355#define GPIO_OD33_CTRL8 0x4c0
356#define GPIO_BIAS_CTRL 0xed0
357#define GPIO_DRV_SEL10 0xf00
358
359
360#define ETHSYS_CHIPID0_3 0x0
361#define ETHSYS_CHIPID4_7 0x4
362#define MT7623_ETH 7623
363#define MT7622_ETH 7622
364
365
366#define ETHSYS_SYSCFG0 0x14
367#define SYSCFG0_GE_MASK 0x3
368#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
369#define SYSCFG0_SGMII_MASK (3 << 8)
370#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8))
371#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8))
372
373
374#define ETHSYS_CLKCFG0 0x2c
375#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
376
377
378#define ETHSYS_RSTCTRL 0x34
379#define RSTCTRL_FE BIT(6)
380#define RSTCTRL_PPE BIT(31)
381
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383
384#define SGMSYS_PCS_CONTROL_1 0x0
385#define SGMII_AN_RESTART BIT(9)
386
387
388#define SGMSYS_PCS_LINK_TIMER 0x18
389#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
390
391
392#define SGMSYS_SGMII_MODE 0x20
393#define SGMII_REMOTE_FAULT_DIS BIT(8)
394
395
396#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
397#define SGMII_PHYA_PWD BIT(4)
398
399struct mtk_rx_dma {
400 unsigned int rxd1;
401 unsigned int rxd2;
402 unsigned int rxd3;
403 unsigned int rxd4;
404} __packed __aligned(4);
405
406struct mtk_tx_dma {
407 unsigned int txd1;
408 unsigned int txd2;
409 unsigned int txd3;
410 unsigned int txd4;
411} __packed __aligned(4);
412
413struct mtk_eth;
414struct mtk_mac;
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425struct mtk_hw_stats {
426 u64 tx_bytes;
427 u64 tx_packets;
428 u64 tx_skip;
429 u64 tx_collisions;
430 u64 rx_bytes;
431 u64 rx_packets;
432 u64 rx_overflow;
433 u64 rx_fcs_errors;
434 u64 rx_short_errors;
435 u64 rx_long_errors;
436 u64 rx_checksum_errors;
437 u64 rx_flow_control_packets;
438
439 spinlock_t stats_lock;
440 u32 reg_offset;
441 struct u64_stats_sync syncp;
442};
443
444enum mtk_tx_flags {
445
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448 MTK_TX_FLAGS_SINGLE0 = 0x01,
449 MTK_TX_FLAGS_PAGE0 = 0x02,
450
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454 MTK_TX_FLAGS_FPORT0 = 0x04,
455 MTK_TX_FLAGS_FPORT1 = 0x08,
456};
457
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460
461enum mtk_clks_map {
462 MTK_CLK_ETHIF,
463 MTK_CLK_ESW,
464 MTK_CLK_GP0,
465 MTK_CLK_GP1,
466 MTK_CLK_GP2,
467 MTK_CLK_TRGPLL,
468 MTK_CLK_SGMII_TX_250M,
469 MTK_CLK_SGMII_RX_250M,
470 MTK_CLK_SGMII_CDR_REF,
471 MTK_CLK_SGMII_CDR_FB,
472 MTK_CLK_SGMII_CK,
473 MTK_CLK_ETH2PLL,
474 MTK_CLK_MAX
475};
476
477#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
478 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
479 BIT(MTK_CLK_TRGPLL))
480#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
481 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
482 BIT(MTK_CLK_GP2) | \
483 BIT(MTK_CLK_SGMII_TX_250M) | \
484 BIT(MTK_CLK_SGMII_RX_250M) | \
485 BIT(MTK_CLK_SGMII_CDR_REF) | \
486 BIT(MTK_CLK_SGMII_CDR_FB) | \
487 BIT(MTK_CLK_SGMII_CK) | \
488 BIT(MTK_CLK_ETH2PLL))
489enum mtk_dev_state {
490 MTK_HW_INIT,
491 MTK_RESETTING
492};
493
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502struct mtk_tx_buf {
503 struct sk_buff *skb;
504 u32 flags;
505 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
506 DEFINE_DMA_UNMAP_LEN(dma_len0);
507 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
508 DEFINE_DMA_UNMAP_LEN(dma_len1);
509};
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520
521struct mtk_tx_ring {
522 struct mtk_tx_dma *dma;
523 struct mtk_tx_buf *buf;
524 dma_addr_t phys;
525 struct mtk_tx_dma *next_free;
526 struct mtk_tx_dma *last_free;
527 u16 thresh;
528 atomic_t free_count;
529};
530
531
532enum mtk_rx_flags {
533 MTK_RX_FLAGS_NORMAL = 0,
534 MTK_RX_FLAGS_HWLRO,
535 MTK_RX_FLAGS_QDMA,
536};
537
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546struct mtk_rx_ring {
547 struct mtk_rx_dma *dma;
548 u8 **data;
549 dma_addr_t phys;
550 u16 frag_size;
551 u16 buf_size;
552 u16 dma_size;
553 bool calc_idx_update;
554 u16 calc_idx;
555 u32 crx_idx_reg;
556};
557
558#define MTK_TRGMII BIT(0)
559#define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII)
560#define MTK_ESW BIT(4)
561#define MTK_GMAC1_ESW (BIT(5) | MTK_ESW)
562#define MTK_SGMII BIT(8)
563#define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII)
564#define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII)
565#define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \
566 MTK_GMAC2_SGMII)
567#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
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574
575struct mtk_soc_data {
576 u32 caps;
577 u32 required_clks;
578};
579
580
581#define MTK_MAX_DEVS 2
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618struct mtk_eth {
619 struct device *dev;
620 void __iomem *base;
621 spinlock_t page_lock;
622 spinlock_t tx_irq_lock;
623 spinlock_t rx_irq_lock;
624 struct net_device dummy_dev;
625 struct net_device *netdev[MTK_MAX_DEVS];
626 struct mtk_mac *mac[MTK_MAX_DEVS];
627 int irq[3];
628 u32 msg_enable;
629 unsigned long sysclk;
630 struct regmap *ethsys;
631 struct regmap *sgmiisys;
632 struct regmap *pctl;
633 u32 chip_id;
634 bool hwlro;
635 atomic_t dma_refcnt;
636 struct mtk_tx_ring tx_ring;
637 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
638 struct mtk_rx_ring rx_ring_qdma;
639 struct napi_struct tx_napi;
640 struct napi_struct rx_napi;
641 struct mtk_tx_dma *scratch_ring;
642 dma_addr_t phy_scratch_ring;
643 void *scratch_head;
644 struct clk *clks[MTK_CLK_MAX];
645
646 struct mii_bus *mii_bus;
647 struct work_struct pending_work;
648 unsigned long state;
649
650 const struct mtk_soc_data *soc;
651};
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663struct mtk_mac {
664 int id;
665 int ge_mode;
666 struct device_node *of_node;
667 struct mtk_eth *hw;
668 struct mtk_hw_stats *hw_stats;
669 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
670 int hwlro_ip_cnt;
671 bool trgmii;
672};
673
674
675extern const struct of_device_id of_mtk_match[];
676
677
678void mtk_stats_update_mac(struct mtk_mac *mac);
679
680void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
681u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
682
683#endif
684