LXR linux/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h

   1/*
   2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 *
  32 */
  33
  34#ifndef __MLX5_ACCEL_IPSEC_H__
  35#define __MLX5_ACCEL_IPSEC_H__
  36
  37#ifdef CONFIG_MLX5_ACCEL
  38
  39#include <linux/mlx5/driver.h>
  40
  41enum {
  42        MLX5_ACCEL_IPSEC_DEVICE = BIT(1),
  43        MLX5_ACCEL_IPSEC_IPV6 = BIT(2),
  44        MLX5_ACCEL_IPSEC_ESP = BIT(3),
  45        MLX5_ACCEL_IPSEC_LSO = BIT(4),
  46};
  47
  48#define MLX5_IPSEC_SADB_IP_AH       BIT(7)
  49#define MLX5_IPSEC_SADB_IP_ESP      BIT(6)
  50#define MLX5_IPSEC_SADB_SA_VALID    BIT(5)
  51#define MLX5_IPSEC_SADB_SPI_EN      BIT(4)
  52#define MLX5_IPSEC_SADB_DIR_SX      BIT(3)
  53#define MLX5_IPSEC_SADB_IPV6        BIT(2)
  54
  55enum {
  56        MLX5_IPSEC_CMD_ADD_SA = 0,
  57        MLX5_IPSEC_CMD_DEL_SA = 1,
  58};
  59
  60enum mlx5_accel_ipsec_enc_mode {
  61        MLX5_IPSEC_SADB_MODE_NONE = 0,
  62        MLX5_IPSEC_SADB_MODE_AES_GCM_128_AUTH_128 = 1,
  63        MLX5_IPSEC_SADB_MODE_AES_GCM_256_AUTH_128 = 3,
  64};
  65
  66#define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
  67                              MLX5_ACCEL_IPSEC_DEVICE)
  68
  69struct mlx5_accel_ipsec_sa {
  70        __be32 cmd;
  71        u8 key_enc[32];
  72        u8 key_auth[32];
  73        __be32 sip[4];
  74        __be32 dip[4];
  75        union {
  76                struct {
  77                        __be32 reserved;
  78                        u8 salt_iv[8];
  79                        __be32 salt;
  80                } __packed gcm;
  81                struct {
  82                        u8 salt[16];
  83                } __packed cbc;
  84        };
  85        __be32 spi;
  86        __be32 sw_sa_handle;
  87        __be16 tfclen;
  88        u8 enc_mode;
  89        u8 sip_masklen;
  90        u8 dip_masklen;
  91        u8 flags;
  92        u8 reserved[2];
  93} __packed;
  94
  95/**
  96 * mlx5_accel_ipsec_sa_cmd_exec - Execute an IPSec SADB command
  97 * @mdev: mlx5 device
  98 * @cmd: command to execute
  99 * May be called from atomic context. Returns context pointer, or error
 100 * Caller must eventually call mlx5_accel_ipsec_sa_cmd_wait from non-atomic
 101 * context, to cleanup the context pointer
 102 */
 103void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
 104                                   struct mlx5_accel_ipsec_sa *cmd);
 105
 106/**
 107 * mlx5_accel_ipsec_sa_cmd_wait - Wait for command execution completion
 108 * @context: Context pointer returned from call to mlx5_accel_ipsec_sa_cmd_exec
 109 * Sleeps (killable) until command execution is complete.
 110 * Returns the command result, or -EINTR if killed
 111 */
 112int mlx5_accel_ipsec_sa_cmd_wait(void *context);
 113
 114u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
 115
 116unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev);
 117int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
 118                                   unsigned int count);
 119
 120int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
 121void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev);
 122
 123#else
 124
 125#define MLX5_IPSEC_DEV(mdev) false
 126
 127static inline int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
 128{
 129        return 0;
 130}
 131
 132static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
 133{
 134}
 135
 136#endif
 137
 138#endif  /* __MLX5_ACCEL_IPSEC_H__ */
 139