1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _RX_DESC_H_ 19#define _RX_DESC_H_ 20 21enum rx_attention_flags { 22 RX_ATTENTION_FLAGS_FIRST_MPDU = 1 << 0, 23 RX_ATTENTION_FLAGS_LAST_MPDU = 1 << 1, 24 RX_ATTENTION_FLAGS_MCAST_BCAST = 1 << 2, 25 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = 1 << 3, 26 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = 1 << 4, 27 RX_ATTENTION_FLAGS_POWER_MGMT = 1 << 5, 28 RX_ATTENTION_FLAGS_NON_QOS = 1 << 6, 29 RX_ATTENTION_FLAGS_NULL_DATA = 1 << 7, 30 RX_ATTENTION_FLAGS_MGMT_TYPE = 1 << 8, 31 RX_ATTENTION_FLAGS_CTRL_TYPE = 1 << 9, 32 RX_ATTENTION_FLAGS_MORE_DATA = 1 << 10, 33 RX_ATTENTION_FLAGS_EOSP = 1 << 11, 34 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = 1 << 12, 35 RX_ATTENTION_FLAGS_FRAGMENT = 1 << 13, 36 RX_ATTENTION_FLAGS_ORDER = 1 << 14, 37 RX_ATTENTION_FLAGS_CLASSIFICATION = 1 << 15, 38 RX_ATTENTION_FLAGS_OVERFLOW_ERR = 1 << 16, 39 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = 1 << 17, 40 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = 1 << 18, 41 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = 1 << 19, 42 RX_ATTENTION_FLAGS_SA_IDX_INVALID = 1 << 20, 43 RX_ATTENTION_FLAGS_DA_IDX_INVALID = 1 << 21, 44 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = 1 << 22, 45 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = 1 << 23, 46 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = 1 << 24, 47 RX_ATTENTION_FLAGS_DIRECTED = 1 << 25, 48 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = 1 << 26, 49 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = 1 << 27, 50 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = 1 << 28, 51 RX_ATTENTION_FLAGS_DECRYPT_ERR = 1 << 29, 52 RX_ATTENTION_FLAGS_FCS_ERR = 1 << 30, 53 RX_ATTENTION_FLAGS_MSDU_DONE = 1 << 31, 54}; 55 56struct rx_attention { 57 __le32 flags; /* %RX_ATTENTION_FLAGS_ */ 58} __packed; 59 60/* 61 * first_mpdu 62 * Indicates the first MSDU of the PPDU. If both first_mpdu 63 * and last_mpdu are set in the MSDU then this is a not an 64 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 65 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 66 * 0. The PPDU start status will only be valid when this bit 67 * is set. 68 * 69 * last_mpdu 70 * Indicates the last MSDU of the last MPDU of the PPDU. The 71 * PPDU end status will only be valid when this bit is set. 72 * 73 * mcast_bcast 74 * Multicast / broadcast indicator. Only set when the MAC 75 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 76 * matches one of the 4 BSSID registers. Only set when 77 * first_msdu is set. 78 * 79 * peer_idx_invalid 80 * Indicates no matching entries within the the max search 81 * count. Only set when first_msdu is set. 82 * 83 * peer_idx_timeout 84 * Indicates an unsuccessful search for the peer index due to 85 * timeout. Only set when first_msdu is set. 86 * 87 * power_mgmt 88 * Power management bit set in the 802.11 header. Only set 89 * when first_msdu is set. 90 * 91 * non_qos 92 * Set if packet is not a non-QoS data frame. Only set when 93 * first_msdu is set. 94 * 95 * null_data 96 * Set if frame type indicates either null data or QoS null 97 * data format. Only set when first_msdu is set. 98 * 99 * mgmt_type 100 * Set if packet is a management packet. Only set when 101 * first_msdu is set. 102 * 103 * ctrl_type 104 * Set if packet is a control packet. Only set when first_msdu 105 * is set. 106 * 107 * more_data 108 * Set if more bit in frame control is set. Only set when 109 * first_msdu is set. 110 * 111 * eosp 112 * Set if the EOSP (end of service period) bit in the QoS 113 * control field is set. Only set when first_msdu is set. 114 * 115 * u_apsd_trigger 116 * Set if packet is U-APSD trigger. Key table will have bits 117 * per TID to indicate U-APSD trigger. 118 * 119 * fragment 120 * Indicates that this is an 802.11 fragment frame. This is 121 * set when either the more_frag bit is set in the frame 122 * control or the fragment number is not zero. Only set when 123 * first_msdu is set. 124 * 125 * order 126 * Set if the order bit in the frame control is set. Only set 127 * when first_msdu is set. 128 * 129 * classification 130 * Indicates that this status has a corresponding MSDU that 131 * requires FW processing. The OLE will have classification 132 * ring mask registers which will indicate the ring(s) for 133 * packets and descriptors which need FW attention. 134 * 135 * overflow_err 136 * PCU Receive FIFO does not have enough space to store the 137 * full receive packet. Enough space is reserved in the 138 * receive FIFO for the status is written. This MPDU remaining 139 * packets in the PPDU will be filtered and no Ack response 140 * will be transmitted. 141 * 142 * msdu_length_err 143 * Indicates that the MSDU length from the 802.3 encapsulated 144 * length field extends beyond the MPDU boundary. 145 * 146 * tcp_udp_chksum_fail 147 * Indicates that the computed checksum (tcp_udp_chksum) did 148 * not match the checksum in the TCP/UDP header. 149 * 150 * ip_chksum_fail 151 * Indicates that the computed checksum did not match the 152 * checksum in the IP header. 153 * 154 * sa_idx_invalid 155 * Indicates no matching entry was found in the address search 156 * table for the source MAC address. 157 * 158 * da_idx_invalid 159 * Indicates no matching entry was found in the address search 160 * table for the destination MAC address. 161 * 162 * sa_idx_timeout 163 * Indicates an unsuccessful search for the source MAC address 164 * due to the expiring of the search timer. 165 * 166 * da_idx_timeout 167 * Indicates an unsuccessful search for the destination MAC 168 * address due to the expiring of the search timer. 169 * 170 * encrypt_required 171 * Indicates that this data type frame is not encrypted even if 172 * the policy for this MPDU requires encryption as indicated in 173 * the peer table key type. 174 * 175 * directed 176 * MPDU is a directed packet which means that the RA matched 177 * our STA addresses. In proxySTA it means that the TA matched 178 * an entry in our address search table with the corresponding 179 * 'no_ack' bit is the address search entry cleared. 180 * 181 * buffer_fragment 182 * Indicates that at least one of the rx buffers has been 183 * fragmented. If set the FW should look at the rx_frag_info 184 * descriptor described below. 185 * 186 * mpdu_length_err 187 * Indicates that the MPDU was pre-maturely terminated 188 * resulting in a truncated MPDU. Don't trust the MPDU length 189 * field. 190 * 191 * tkip_mic_err 192 * Indicates that the MPDU Michael integrity check failed 193 * 194 * decrypt_err 195 * Indicates that the MPDU decrypt integrity check failed 196 * 197 * fcs_err 198 * Indicates that the MPDU FCS check failed 199 * 200 * msdu_done 201 * If set indicates that the RX packet data, RX header data, RX 202 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 203 * start/end descriptors and RX Attention descriptor are all 204 * valid. This bit must be in the last octet of the 205 * descriptor. 206 */ 207 208struct rx_frag_info { 209 u8 ring0_more_count; 210 u8 ring1_more_count; 211 u8 ring2_more_count; 212 u8 ring3_more_count; 213} __packed; 214 215/* 216 * ring0_more_count 217 * Indicates the number of more buffers associated with RX DMA 218 * ring 0. Field is filled in by the RX_DMA. 219 * 220 * ring1_more_count 221 * Indicates the number of more buffers associated with RX DMA 222 * ring 1. Field is filled in by the RX_DMA. 223 * 224 * ring2_more_count 225 * Indicates the number of more buffers associated with RX DMA 226 * ring 2. Field is filled in by the RX_DMA. 227 * 228 * ring3_more_count 229 * Indicates the number of more buffers associated with RX DMA 230 * ring 3. Field is filled in by the RX_DMA. 231 */ 232 233enum htt_rx_mpdu_encrypt_type { 234 HTT_RX_MPDU_ENCRYPT_WEP40 = 0, 235 HTT_RX_MPDU_ENCRYPT_WEP104 = 1, 236 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2, 237 HTT_RX_MPDU_ENCRYPT_WEP128 = 3, 238 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4, 239 HTT_RX_MPDU_ENCRYPT_WAPI = 5, 240 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6, 241 HTT_RX_MPDU_ENCRYPT_NONE = 7, 242 HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2 = 8, 243 HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2 = 9, 244 HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10, 245}; 246 247#define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff 248#define RX_MPDU_START_INFO0_PEER_IDX_LSB 0 249#define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000 250#define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16 251#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000 252#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28 253#define RX_MPDU_START_INFO0_FROM_DS (1 << 11) 254#define RX_MPDU_START_INFO0_TO_DS (1 << 12) 255#define RX_MPDU_START_INFO0_ENCRYPTED (1 << 13) 256#define RX_MPDU_START_INFO0_RETRY (1 << 14) 257#define RX_MPDU_START_INFO0_TXBF_H_INFO (1 << 15) 258 259#define RX_MPDU_START_INFO1_TID_MASK 0xf0000000 260#define RX_MPDU_START_INFO1_TID_LSB 28 261#define RX_MPDU_START_INFO1_DIRECTED (1 << 16) 262 263struct rx_mpdu_start { 264 __le32 info0; 265 union { 266 struct { 267 __le32 pn31_0; 268 __le32 info1; /* %RX_MPDU_START_INFO1_ */ 269 } __packed; 270 struct { 271 u8 pn[6]; 272 } __packed; 273 } __packed; 274} __packed; 275 276/* 277 * peer_idx 278 * The index of the address search table which associated with 279 * the peer table entry corresponding to this MPDU. Only valid 280 * when first_msdu is set. 281 * 282 * fr_ds 283 * Set if the from DS bit is set in the frame control. Only 284 * valid when first_msdu is set. 285 * 286 * to_ds 287 * Set if the to DS bit is set in the frame control. Only 288 * valid when first_msdu is set. 289 * 290 * encrypted 291 * Protected bit from the frame control. Only valid when 292 * first_msdu is set. 293 * 294 * retry 295 * Retry bit from the frame control. Only valid when 296 * first_msdu is set. 297 * 298 * txbf_h_info 299 * The MPDU data will contain H information. Primarily used 300 * for debug. 301 * 302 * seq_num 303 * The sequence number from the 802.11 header. Only valid when 304 * first_msdu is set. 305 * 306 * encrypt_type 307 * Indicates type of decrypt cipher used (as defined in the 308 * peer table) 309 * 0: WEP40 310 * 1: WEP104 311 * 2: TKIP without MIC 312 * 3: WEP128 313 * 4: TKIP (WPA) 314 * 5: WAPI 315 * 6: AES-CCM (WPA2) 316 * 7: No cipher 317 * Only valid when first_msdu_is set 318 * 319 * pn_31_0 320 * Bits [31:0] of the PN number extracted from the IV field 321 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is 322 * valid. 323 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 324 * WEPSeed[1], pn1}. Only pn[47:0] is valid. 325 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 326 * pn0}. Only pn[47:0] is valid. 327 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 328 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 329 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and 330 * pn[47:0] are valid. 331 * Only valid when first_msdu is set. 332 * 333 * pn_47_32 334 * Bits [47:32] of the PN number. See description for 335 * pn_31_0. The remaining PN fields are in the rx_msdu_end 336 * descriptor 337 * 338 * pn 339 * Use this field to access the pn without worrying about 340 * byte-order and bitmasking/bitshifting. 341 * 342 * directed 343 * See definition in RX attention descriptor 344 * 345 * reserved_2 346 * Reserved: HW should fill with zero. FW should ignore. 347 * 348 * tid 349 * The TID field in the QoS control field 350 */ 351 352#define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff 353#define RX_MPDU_END_INFO0_RESERVED_0_LSB 0 354#define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000 355#define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16 356#define RX_MPDU_END_INFO0_OVERFLOW_ERR (1 << 13) 357#define RX_MPDU_END_INFO0_LAST_MPDU (1 << 14) 358#define RX_MPDU_END_INFO0_POST_DELIM_ERR (1 << 15) 359#define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR (1 << 28) 360#define RX_MPDU_END_INFO0_TKIP_MIC_ERR (1 << 29) 361#define RX_MPDU_END_INFO0_DECRYPT_ERR (1 << 30) 362#define RX_MPDU_END_INFO0_FCS_ERR (1 << 31) 363 364struct rx_mpdu_end { 365 __le32 info0; 366} __packed; 367 368/* 369 * reserved_0 370 * Reserved 371 * 372 * overflow_err 373 * PCU Receive FIFO does not have enough space to store the 374 * full receive packet. Enough space is reserved in the 375 * receive FIFO for the status is written. This MPDU remaining 376 * packets in the PPDU will be filtered and no Ack response 377 * will be transmitted. 378 * 379 * last_mpdu 380 * Indicates that this is the last MPDU of a PPDU. 381 * 382 * post_delim_err 383 * Indicates that a delimiter FCS error occurred after this 384 * MPDU before the next MPDU. Only valid when last_msdu is 385 * set. 386 * 387 * post_delim_cnt 388 * Count of the delimiters after this MPDU. This requires the 389 * last MPDU to be held until all the EOF descriptors have been 390 * received. This may be inefficient in the future when 391 * ML-MIMO is used. Only valid when last_mpdu is set. 392 * 393 * mpdu_length_err 394 * See definition in RX attention descriptor 395 * 396 * tkip_mic_err 397 * See definition in RX attention descriptor 398 * 399 * decrypt_err 400 * See definition in RX attention descriptor 401 * 402 * fcs_err 403 * See definition in RX attention descriptor 404 */ 405 406#define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff 407#define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0 408#define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000 409#define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14 410#define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000 411#define RX_MSDU_START_INFO0_RING_MASK_LSB 20 412#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000 413#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24 414 415#define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff 416#define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0 417#define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300 418#define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8 419#define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000 420#define RX_MSDU_START_INFO1_SA_IDX_LSB 16 421#define RX_MSDU_START_INFO1_IPV4_PROTO (1 << 10) 422#define RX_MSDU_START_INFO1_IPV6_PROTO (1 << 11) 423#define RX_MSDU_START_INFO1_TCP_PROTO (1 << 12) 424#define RX_MSDU_START_INFO1_UDP_PROTO (1 << 13) 425#define RX_MSDU_START_INFO1_IP_FRAG (1 << 14) 426#define RX_MSDU_START_INFO1_TCP_ONLY_ACK (1 << 15) 427 428#define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff 429#define RX_MSDU_START_INFO2_DA_IDX_LSB 0 430#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000 431#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16 432#define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) 433 434/* The decapped header (rx_hdr_status) contains the following: 435 * a) 802.11 header 436 * [padding to 4 bytes] 437 * b) HW crypto parameter 438 * - 0 bytes for no security 439 * - 4 bytes for WEP 440 * - 8 bytes for TKIP, AES 441 * [padding to 4 bytes] 442 * c) A-MSDU subframe header (14 bytes) if appliable 443 * d) LLC/SNAP (RFC1042, 8 bytes) 444 * 445 * In case of A-MSDU only first frame in sequence contains (a) and (b). 446 */ 447enum rx_msdu_decap_format { 448 RX_MSDU_DECAP_RAW = 0, 449 450 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in 451 * htt_rx_desc contains the original decapped 802.11 header. 452 */ 453 RX_MSDU_DECAP_NATIVE_WIFI = 1, 454 455 /* Payload contains an ethernet header (struct ethhdr). */ 456 RX_MSDU_DECAP_ETHERNET2_DIX = 2, 457 458 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes 459 * total), followed by an RFC1042 header (8 bytes). 460 */ 461 RX_MSDU_DECAP_8023_SNAP_LLC = 3 462}; 463 464struct rx_msdu_start_common { 465 __le32 info0; /* %RX_MSDU_START_INFO0_ */ 466 __le32 flow_id_crc; 467 __le32 info1; /* %RX_MSDU_START_INFO1_ */ 468} __packed; 469 470struct rx_msdu_start_qca99x0 { 471 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 472} __packed; 473 474struct rx_msdu_start { 475 struct rx_msdu_start_common common; 476 union { 477 struct rx_msdu_start_qca99x0 qca99x0; 478 } __packed; 479} __packed; 480 481/* 482 * msdu_length 483 * MSDU length in bytes after decapsulation. This field is 484 * still valid for MPDU frames without A-MSDU. It still 485 * represents MSDU length after decapsulation 486 * 487 * ip_offset 488 * Indicates the IP offset in bytes from the start of the 489 * packet after decapsulation. Only valid if ipv4_proto or 490 * ipv6_proto is set. 491 * 492 * ring_mask 493 * Indicates the destination RX rings for this MSDU. 494 * 495 * tcp_udp_offset 496 * Indicates the offset in bytes to the start of TCP or UDP 497 * header from the start of the IP header after decapsulation. 498 * Only valid if tcp_prot or udp_prot is set. The value 0 499 * indicates that the offset is longer than 127 bytes. 500 * 501 * reserved_0c 502 * Reserved: HW should fill with zero. FW should ignore. 503 * 504 * flow_id_crc 505 * The flow_id_crc runs CRC32 on the following information: 506 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0, 507 * protocol[7:0]}. 508 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0, 509 * next_header[7:0]} 510 * UDP case: sort_port[15:0], dest_port[15:0] 511 * TCP case: sort_port[15:0], dest_port[15:0], 512 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]}, 513 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit 514 * timestamp. 515 * 516 * msdu_number 517 * Indicates the MSDU number within a MPDU. This value is 518 * reset to zero at the start of each MPDU. If the number of 519 * MSDU exceeds 255 this number will wrap using modulo 256. 520 * 521 * decap_format 522 * Indicates the format after decapsulation: 523 * 0: RAW: No decapsulation 524 * 1: Native WiFi 525 * 2: Ethernet 2 (DIX) 526 * 3: 802.3 (SNAP/LLC) 527 * 528 * ipv4_proto 529 * Set if L2 layer indicates IPv4 protocol. 530 * 531 * ipv6_proto 532 * Set if L2 layer indicates IPv6 protocol. 533 * 534 * tcp_proto 535 * Set if the ipv4_proto or ipv6_proto are set and the IP 536 * protocol indicates TCP. 537 * 538 * udp_proto 539 * Set if the ipv4_proto or ipv6_proto are set and the IP 540 * protocol indicates UDP. 541 * 542 * ip_frag 543 * Indicates that either the IP More frag bit is set or IP frag 544 * number is non-zero. If set indicates that this is a 545 * fragmented IP packet. 546 * 547 * tcp_only_ack 548 * Set if only the TCP Ack bit is set in the TCP flags and if 549 * the TCP payload is 0. 550 * 551 * sa_idx 552 * The offset in the address table which matches the MAC source 553 * address. 554 * 555 * reserved_2b 556 * Reserved: HW should fill with zero. FW should ignore. 557 */ 558 559#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff 560#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0 561#define RX_MSDU_END_INFO0_FIRST_MSDU (1 << 14) 562#define RX_MSDU_END_INFO0_LAST_MSDU (1 << 15) 563#define RX_MSDU_END_INFO0_PRE_DELIM_ERR (1 << 30) 564#define RX_MSDU_END_INFO0_RESERVED_3B (1 << 31) 565 566struct rx_msdu_end_common { 567 __le16 ip_hdr_cksum; 568 __le16 tcp_hdr_cksum; 569 u8 key_id_octet; 570 u8 classification_filter; 571 u8 wapi_pn[10]; 572 __le32 info0; 573} __packed; 574 575#define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff 576#define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0 577#define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00 578#define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10 579#define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000 580#define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16 581#define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) 582 583#define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f 584#define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0 585#define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0 586#define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6 587#define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000 588#define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12 589 590struct rx_msdu_end_qca99x0 { 591 __le32 ipv6_crc; 592 __le32 tcp_seq_no; 593 __le32 tcp_ack_no; 594 __le32 info1; 595 __le32 info2; 596} __packed; 597 598struct rx_msdu_end { 599 struct rx_msdu_end_common common; 600 union { 601 struct rx_msdu_end_qca99x0 qca99x0; 602 } __packed; 603} __packed; 604 605/* 606 *ip_hdr_chksum 607 * This can include the IP header checksum or the pseudo header 608 * checksum used by TCP/UDP checksum. 609 * 610 *tcp_udp_chksum 611 * The value of the computed TCP/UDP checksum. A mode bit 612 * selects whether this checksum is the full checksum or the 613 * partial checksum which does not include the pseudo header. 614 * 615 *key_id_octet 616 * The key ID octet from the IV. Only valid when first_msdu is 617 * set. 618 * 619 *classification_filter 620 * Indicates the number classification filter rule 621 * 622 *ext_wapi_pn_63_48 623 * Extension PN (packet number) which is only used by WAPI. 624 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The 625 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start 626 * descriptor. 627 * 628 *ext_wapi_pn_95_64 629 * Extension PN (packet number) which is only used by WAPI. 630 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and 631 * pn11). 632 * 633 *ext_wapi_pn_127_96 634 * Extension PN (packet number) which is only used by WAPI. 635 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, 636 * pn15). 637 * 638 *reported_mpdu_length 639 * MPDU length before decapsulation. Only valid when 640 * first_msdu is set. This field is taken directly from the 641 * length field of the A-MPDU delimiter or the preamble length 642 * field for non-A-MPDU frames. 643 * 644 *first_msdu 645 * Indicates the first MSDU of A-MSDU. If both first_msdu and 646 * last_msdu are set in the MSDU then this is a non-aggregated 647 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 648 * have both first_mpdu and last_mpdu bits set to 0. 649 * 650 *last_msdu 651 * Indicates the last MSDU of the A-MSDU. MPDU end status is 652 * only valid when last_msdu is set. 653 * 654 *reserved_3a 655 * Reserved: HW should fill with zero. FW should ignore. 656 * 657 *pre_delim_err 658 * Indicates that the first delimiter had a FCS failure. Only 659 * valid when first_mpdu and first_msdu are set. 660 * 661 *reserved_3b 662 * Reserved: HW should fill with zero. FW should ignore. 663 */ 664 665#define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 666#define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 667#define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 668#define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C 669#define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D 670 671#define RX_PPDU_START_INFO0_IS_GREENFIELD (1 << 0) 672 673#define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f 674#define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0 675#define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0 676#define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5 677#define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000 678#define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18 679#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000 680#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24 681#define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT (1 << 4) 682#define RX_PPDU_START_INFO1_L_SIG_PARITY (1 << 17) 683 684#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff 685#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0 686 687#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff 688#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0 689#define RX_PPDU_START_INFO3_TXBF_H_INFO (1 << 24) 690 691#define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff 692#define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0 693 694#define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff 695#define RX_PPDU_START_INFO5_SERVICE_LSB 0 696 697/* No idea what this flag means. It seems to be always set in rate. */ 698#define RX_PPDU_START_RATE_FLAG BIT(3) 699 700struct rx_ppdu_start { 701 struct { 702 u8 pri20_mhz; 703 u8 ext20_mhz; 704 u8 ext40_mhz; 705 u8 ext80_mhz; 706 } rssi_chains[4]; 707 u8 rssi_comb; 708 __le16 rsvd0; 709 u8 info0; /* %RX_PPDU_START_INFO0_ */ 710 __le32 info1; /* %RX_PPDU_START_INFO1_ */ 711 __le32 info2; /* %RX_PPDU_START_INFO2_ */ 712 __le32 info3; /* %RX_PPDU_START_INFO3_ */ 713 __le32 info4; /* %RX_PPDU_START_INFO4_ */ 714 __le32 info5; /* %RX_PPDU_START_INFO5_ */ 715} __packed; 716 717/* 718 * rssi_chain0_pri20 719 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 720 * Value of 0x80 indicates invalid. 721 * 722 * rssi_chain0_sec20 723 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth. 724 * Value of 0x80 indicates invalid. 725 * 726 * rssi_chain0_sec40 727 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth. 728 * Value of 0x80 indicates invalid. 729 * 730 * rssi_chain0_sec80 731 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth. 732 * Value of 0x80 indicates invalid. 733 * 734 * rssi_chain1_pri20 735 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 736 * Value of 0x80 indicates invalid. 737 * 738 * rssi_chain1_sec20 739 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth. 740 * Value of 0x80 indicates invalid. 741 * 742 * rssi_chain1_sec40 743 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth. 744 * Value of 0x80 indicates invalid. 745 * 746 * rssi_chain1_sec80 747 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth. 748 * Value of 0x80 indicates invalid. 749 * 750 * rssi_chain2_pri20 751 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 752 * Value of 0x80 indicates invalid. 753 * 754 * rssi_chain2_sec20 755 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth. 756 * Value of 0x80 indicates invalid. 757 * 758 * rssi_chain2_sec40 759 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth. 760 * Value of 0x80 indicates invalid. 761 * 762 * rssi_chain2_sec80 763 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth. 764 * Value of 0x80 indicates invalid. 765 * 766 * rssi_chain3_pri20 767 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 768 * Value of 0x80 indicates invalid. 769 * 770 * rssi_chain3_sec20 771 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth. 772 * Value of 0x80 indicates invalid. 773 * 774 * rssi_chain3_sec40 775 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth. 776 * Value of 0x80 indicates invalid. 777 * 778 * rssi_chain3_sec80 779 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth. 780 * Value of 0x80 indicates invalid. 781 * 782 * rssi_comb 783 * The combined RSSI of RX PPDU of all active chains and 784 * bandwidths. Value of 0x80 indicates invalid. 785 * 786 * reserved_4a 787 * Reserved: HW should fill with 0, FW should ignore. 788 * 789 * is_greenfield 790 * Do we really support this? 791 * 792 * reserved_4b 793 * Reserved: HW should fill with 0, FW should ignore. 794 * 795 * l_sig_rate 796 * If l_sig_rate_select is 0: 797 * 0x8: OFDM 48 Mbps 798 * 0x9: OFDM 24 Mbps 799 * 0xA: OFDM 12 Mbps 800 * 0xB: OFDM 6 Mbps 801 * 0xC: OFDM 54 Mbps 802 * 0xD: OFDM 36 Mbps 803 * 0xE: OFDM 18 Mbps 804 * 0xF: OFDM 9 Mbps 805 * If l_sig_rate_select is 1: 806 * 0x8: CCK 11 Mbps long preamble 807 * 0x9: CCK 5.5 Mbps long preamble 808 * 0xA: CCK 2 Mbps long preamble 809 * 0xB: CCK 1 Mbps long preamble 810 * 0xC: CCK 11 Mbps short preamble 811 * 0xD: CCK 5.5 Mbps short preamble 812 * 0xE: CCK 2 Mbps short preamble 813 * 814 * l_sig_rate_select 815 * Legacy signal rate select. If set then l_sig_rate indicates 816 * CCK rates. If clear then l_sig_rate indicates OFDM rates. 817 * 818 * l_sig_length 819 * Length of legacy frame in octets. 820 * 821 * l_sig_parity 822 * Odd parity over l_sig_rate and l_sig_length 823 * 824 * l_sig_tail 825 * Tail bits for Viterbi decoder 826 * 827 * preamble_type 828 * Indicates the type of preamble ahead: 829 * 0x4: Legacy (OFDM/CCK) 830 * 0x8: HT 831 * 0x9: HT with TxBF 832 * 0xC: VHT 833 * 0xD: VHT with TxBF 834 * 0x80 - 0xFF: Reserved for special baseband data types such 835 * as radar and spectral scan. 836 * 837 * ht_sig_vht_sig_a_1 838 * If preamble_type == 0x8 or 0x9 839 * HT-SIG (first 24 bits) 840 * If preamble_type == 0xC or 0xD 841 * VHT-SIG A (first 24 bits) 842 * Else 843 * Reserved 844 * 845 * reserved_6 846 * Reserved: HW should fill with 0, FW should ignore. 847 * 848 * ht_sig_vht_sig_a_2 849 * If preamble_type == 0x8 or 0x9 850 * HT-SIG (last 24 bits) 851 * If preamble_type == 0xC or 0xD 852 * VHT-SIG A (last 24 bits) 853 * Else 854 * Reserved 855 * 856 * txbf_h_info 857 * Indicates that the packet data carries H information which 858 * is used for TxBF debug. 859 * 860 * reserved_7 861 * Reserved: HW should fill with 0, FW should ignore. 862 * 863 * vht_sig_b 864 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all 865 * 0s since the BB does not plan on decoding VHT SIG-B. 866 * 867 * reserved_8 868 * Reserved: HW should fill with 0, FW should ignore. 869 * 870 * service 871 * Service field from BB for OFDM, HT and VHT packets. CCK 872 * packets will have service field of 0. 873 * 874 * reserved_9 875 * Reserved: HW should fill with 0, FW should ignore. 876 */ 877 878#define RX_PPDU_END_FLAGS_PHY_ERR (1 << 0) 879#define RX_PPDU_END_FLAGS_RX_LOCATION (1 << 1) 880#define RX_PPDU_END_FLAGS_TXBF_H_INFO (1 << 2) 881 882#define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff 883#define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0 884#define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK (1 << 24) 885#define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL (1 << 25) 886 887#define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc 888#define RX_PPDU_END_INFO1_PEER_IDX_LSB 2 889#define RX_PPDU_END_INFO1_BB_DATA BIT(0) 890#define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) 891#define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) 892 893struct rx_ppdu_end_common { 894 __le32 evm_p0; 895 __le32 evm_p1; 896 __le32 evm_p2; 897 __le32 evm_p3; 898 __le32 evm_p4; 899 __le32 evm_p5; 900 __le32 evm_p6; 901 __le32 evm_p7; 902 __le32 evm_p8; 903 __le32 evm_p9; 904 __le32 evm_p10; 905 __le32 evm_p11; 906 __le32 evm_p12; 907 __le32 evm_p13; 908 __le32 evm_p14; 909 __le32 evm_p15; 910 __le32 tsf_timestamp; 911 __le32 wb_timestamp; 912} __packed; 913 914struct rx_ppdu_end_qca988x { 915 u8 locationing_timestamp; 916 u8 phy_err_code; 917 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 918 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 919 __le16 bb_length; 920 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 921} __packed; 922 923#define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff 924#define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0 925#define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000 926#define RX_PPDU_END_RTT_UNUSED_LSB 24 927#define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) 928 929struct rx_ppdu_end_qca6174 { 930 u8 locationing_timestamp; 931 u8 phy_err_code; 932 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 933 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 934 __le32 rtt; /* %RX_PPDU_END_RTT_ */ 935 __le16 bb_length; 936 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 937} __packed; 938 939#define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) 940#define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) 941#define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) 942#define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) 943#define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) 944#define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) 945 946#define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff 947#define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0 948#define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000 949#define RX_LOCATION_INFO_FAC_STATUS_LSB 18 950#define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000 951#define RX_LOCATION_INFO_PKT_BW_LSB 20 952#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000 953#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23 954#define RX_LOCATION_INFO_CIR_STATUS BIT(17) 955#define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) 956#define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) 957#define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) 958#define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) 959 960struct rx_pkt_end { 961 __le32 info0; /* %RX_PKT_END_INFO0_ */ 962 __le32 phy_timestamp_1; 963 __le32 phy_timestamp_2; 964} __packed; 965 966#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff 967#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 968#define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 969#define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 970#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 971#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 972#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) 973#define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) 974 975#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c 976#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 977#define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 978#define RX_LOCATION_INFO1_PKT_BW_LSB 4 979#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 980#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 981#define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 982#define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 983#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 984#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 985#define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 986#define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 987#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 988#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 989#define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) 990#define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) 991#define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) 992#define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) 993#define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) 994#define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) 995 996struct rx_location_info { 997 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 998 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 999} __packed; 1000
1001enum rx_phy_ppdu_end_info0 { 1002 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), 1003 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), 1004 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), 1005 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), 1006 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), 1007 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), 1008 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), 1009 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), 1010 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), 1011 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), 1012 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), 1013 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), 1014 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), 1015 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), 1016 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), 1017 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), 1018 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), 1019 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), 1020 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), 1021 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), 1022 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), 1023 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), 1024 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), 1025 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), 1026 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), 1027 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), 1028 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), 1029 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), 1030 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), 1031 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), 1032}; 1033 1034enum rx_phy_ppdu_end_info1 { 1035 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), 1036 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), 1037 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), 1038 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), 1039 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), 1040 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), 1041 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), 1042 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), 1043 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), 1044 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), 1045 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), 1046 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), 1047 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), 1048 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), 1049}; 1050 1051struct rx_phy_ppdu_end { 1052 __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */ 1053 __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */ 1054} __packed; 1055 1056#define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff 1057#define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0 1058 1059#define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff 1060#define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0 1061#define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) 1062#define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) 1063#define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) 1064#define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) 1065#define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) 1066#define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) 1067#define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) 1068 1069struct rx_ppdu_end_qca99x0 { 1070 struct rx_pkt_end rx_pkt_end; 1071 __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ 1072 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1073 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1074 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1075 __le16 bb_length; 1076 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1077} __packed; 1078 1079struct rx_ppdu_end_qca9984 { 1080 struct rx_pkt_end rx_pkt_end; 1081 struct rx_location_info rx_location_info; 1082 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1083 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1084 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1085 __le16 bb_length; 1086 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1087} __packed; 1088 1089struct rx_ppdu_end { 1090 struct rx_ppdu_end_common common; 1091 union { 1092 struct rx_ppdu_end_qca988x qca988x; 1093 struct rx_ppdu_end_qca6174 qca6174; 1094 struct rx_ppdu_end_qca99x0 qca99x0; 1095 struct rx_ppdu_end_qca9984 qca9984; 1096 } __packed; 1097} __packed; 1098 1099/* 1100 * evm_p0 1101 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3. 1102 * 1103 * evm_p1 1104 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3. 1105 * 1106 * evm_p2 1107 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3. 1108 * 1109 * evm_p3 1110 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3. 1111 * 1112 * evm_p4 1113 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3. 1114 * 1115 * evm_p5 1116 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3. 1117 * 1118 * evm_p6 1119 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3. 1120 * 1121 * evm_p7 1122 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3. 1123 * 1124 * evm_p8 1125 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3. 1126 * 1127 * evm_p9 1128 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3. 1129 * 1130 * evm_p10 1131 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3. 1132 * 1133 * evm_p11 1134 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3. 1135 * 1136 * evm_p12 1137 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3. 1138 * 1139 * evm_p13 1140 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3. 1141 * 1142 * evm_p14 1143 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3. 1144 * 1145 * evm_p15 1146 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3. 1147 * 1148 * tsf_timestamp 1149 * Receive TSF timestamp sampled on the rising edge of 1150 * rx_clear. For PHY errors this may be the current TSF when 1151 * phy_error is asserted if the rx_clear does not assert before 1152 * the end of the PHY error. 1153 * 1154 * wb_timestamp 1155 * WLAN/BT timestamp is a 1 usec resolution timestamp which 1156 * does not get updated based on receive beacon like TSF. The 1157 * same rules for capturing tsf_timestamp are used to capture 1158 * the wb_timestamp. 1159 * 1160 * locationing_timestamp 1161 * Timestamp used for locationing. This timestamp is used to 1162 * indicate fractions of usec. For example if the MAC clock is 1163 * running at 80 MHz, the timestamp will increment every 12.5 1164 * nsec. The value starts at 0 and increments to 79 and 1165 * returns to 0 and repeats. This information is valid for 1166 * every PPDU. This information can be used in conjunction 1167 * with wb_timestamp to capture large delta times. 1168 * 1169 * phy_err_code 1170 * See the 1.10.8.1.2 for the list of the PHY error codes. 1171 * 1172 * phy_err 1173 * Indicates a PHY error was detected for this PPDU. 1174 * 1175 * rx_location 1176 * Indicates that location information was requested. 1177 * 1178 * txbf_h_info 1179 * Indicates that the packet data carries H information which 1180 * is used for TxBF debug. 1181 * 1182 * reserved_18 1183 * Reserved: HW should fill with 0, FW should ignore. 1184 * 1185 * rx_antenna 1186 * Receive antenna value 1187 * 1188 * tx_ht_vht_ack 1189 * Indicates that a HT or VHT Ack/BA frame was transmitted in 1190 * response to this receive packet. 1191 * 1192 * bb_captured_channel 1193 * Indicates that the BB has captured a channel dump. FW can 1194 * then read the channel dump memory. This may indicate that 1195 * the channel was captured either based on PCU setting the 1196 * capture_channel bit BB descriptor or FW setting the 1197 * capture_channel mode bit. 1198 * 1199 * reserved_19 1200 * Reserved: HW should fill with 0, FW should ignore. 1201 * 1202 * bb_length 1203 * Indicates the number of bytes of baseband information for 1204 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF 1205 * which indicates that this is not a normal PPDU but rather 1206 * contains baseband debug information. 1207 * 1208 * reserved_20 1209 * Reserved: HW should fill with 0, FW should ignore. 1210 * 1211 * ppdu_done 1212 * PPDU end status is only valid when ppdu_done bit is set. 1213 * Every time HW sets this bit in memory FW/SW must clear this 1214 * bit in memory. FW will initialize all the ppdu_done dword 1215 * to 0. 1216 */ 1217 1218#define FW_RX_DESC_INFO0_DISCARD (1 << 0) 1219#define FW_RX_DESC_INFO0_FORWARD (1 << 1) 1220#define FW_RX_DESC_INFO0_INSPECT (1 << 5) 1221#define FW_RX_DESC_INFO0_EXT_MASK 0xC0 1222#define FW_RX_DESC_INFO0_EXT_LSB 6 1223 1224struct fw_rx_desc_base { 1225 u8 info0; 1226} __packed; 1227 1228#endif /* _RX_DESC_H_ */ 1229