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26#ifndef __RTL8821AE_DEF_H__
27#define __RTL8821AE_DEF_H__
28
29
30#define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN 1
31
32
33
34#define MGN_1M 0x02
35#define MGN_2M 0x04
36#define MGN_5_5M 0x0b
37#define MGN_11M 0x16
38
39#define MGN_6M 0x0c
40#define MGN_9M 0x12
41#define MGN_12M 0x18
42#define MGN_18M 0x24
43#define MGN_24M 0x30
44#define MGN_36M 0x48
45#define MGN_48M 0x60
46#define MGN_54M 0x6c
47
48
49#define MGN_MCS0 0x80
50#define MGN_MCS1 0x81
51#define MGN_MCS2 0x82
52#define MGN_MCS3 0x83
53#define MGN_MCS4 0x84
54#define MGN_MCS5 0x85
55#define MGN_MCS6 0x86
56#define MGN_MCS7 0x87
57#define MGN_MCS8 0x88
58#define MGN_MCS9 0x89
59#define MGN_MCS10 0x8a
60#define MGN_MCS11 0x8b
61#define MGN_MCS12 0x8c
62#define MGN_MCS13 0x8d
63#define MGN_MCS14 0x8e
64#define MGN_MCS15 0x8f
65
66#define MGN_VHT1SS_MCS0 0x90
67#define MGN_VHT1SS_MCS1 0x91
68#define MGN_VHT1SS_MCS2 0x92
69#define MGN_VHT1SS_MCS3 0x93
70#define MGN_VHT1SS_MCS4 0x94
71#define MGN_VHT1SS_MCS5 0x95
72#define MGN_VHT1SS_MCS6 0x96
73#define MGN_VHT1SS_MCS7 0x97
74#define MGN_VHT1SS_MCS8 0x98
75#define MGN_VHT1SS_MCS9 0x99
76#define MGN_VHT2SS_MCS0 0x9a
77#define MGN_VHT2SS_MCS1 0x9b
78#define MGN_VHT2SS_MCS2 0x9c
79#define MGN_VHT2SS_MCS3 0x9d
80#define MGN_VHT2SS_MCS4 0x9e
81#define MGN_VHT2SS_MCS5 0x9f
82#define MGN_VHT2SS_MCS6 0xa0
83#define MGN_VHT2SS_MCS7 0xa1
84#define MGN_VHT2SS_MCS8 0xa2
85#define MGN_VHT2SS_MCS9 0xa3
86
87#define MGN_VHT3SS_MCS0 0xa4
88#define MGN_VHT3SS_MCS1 0xa5
89#define MGN_VHT3SS_MCS2 0xa6
90#define MGN_VHT3SS_MCS3 0xa7
91#define MGN_VHT3SS_MCS4 0xa8
92#define MGN_VHT3SS_MCS5 0xa9
93#define MGN_VHT3SS_MCS6 0xaa
94#define MGN_VHT3SS_MCS7 0xab
95#define MGN_VHT3SS_MCS8 0xac
96#define MGN_VHT3SS_MCS9 0xad
97
98#define MGN_MCS0_SG 0xc0
99#define MGN_MCS1_SG 0xc1
100#define MGN_MCS2_SG 0xc2
101#define MGN_MCS3_SG 0xc3
102#define MGN_MCS4_SG 0xc4
103#define MGN_MCS5_SG 0xc5
104#define MGN_MCS6_SG 0xc6
105#define MGN_MCS7_SG 0xc7
106#define MGN_MCS8_SG 0xc8
107#define MGN_MCS9_SG 0xc9
108#define MGN_MCS10_SG 0xca
109#define MGN_MCS11_SG 0xcb
110#define MGN_MCS12_SG 0xcc
111#define MGN_MCS13_SG 0xcd
112#define MGN_MCS14_SG 0xce
113#define MGN_MCS15_SG 0xcf
114
115#define MGN_UNKNOWN 0xff
116
117
118#define WIFI_NAV_UPPER_US 30000
119#define HAL_92C_NAV_UPPER_UNIT 128
120
121#define MAX_RX_DMA_BUFFER_SIZE 0x3E80
122
123#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
124#define HAL_PRIME_CHNL_OFFSET_LOWER 1
125#define HAL_PRIME_CHNL_OFFSET_UPPER 2
126
127#define RX_MPDU_QUEUE 0
128#define RX_CMD_QUEUE 1
129
130#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80
131
132#define C2H_RX_CMD_HDR_LEN 8
133#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
134 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
135#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
136 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
137#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
138 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
139#define GET_C2H_CMD_CONTINUE(__prxhdr) \
140 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
141#define GET_C2H_CMD_CONTENT(__prxhdr) \
142 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
143
144#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
145 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
146#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
147 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
148#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
149 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
150#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
151 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
152#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
153 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
154#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
155 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
156#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
157 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
158#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
159 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
160#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
161 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
162
163#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
164
165#define CHIP_8812 BIT(2)
166#define CHIP_8821 (BIT(0)|BIT(2))
167
168#define CHIP_8821A (BIT(0)|BIT(2))
169#define NORMAL_CHIP BIT(3)
170#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
171#define RF_TYPE_1T2R BIT(4)
172#define RF_TYPE_2T2R BIT(5)
173#define CHIP_VENDOR_UMC BIT(7)
174#define B_CUT_VERSION BIT(12)
175#define C_CUT_VERSION BIT(13)
176#define D_CUT_VERSION ((BIT(12)|BIT(13)))
177#define E_CUT_VERSION BIT(14)
178#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
179
180enum version_8821ae {
181 VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
182 VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
183 VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
184 VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
185 VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
186 VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
187 VERSION_TEST_CHIP_8821 = 0x0005,
188 VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
189 VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
190 VERSION_UNKNOWN = 0xFF,
191};
192
193enum vht_data_sc {
194 VHT_DATA_SC_DONOT_CARE = 0,
195 VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
196 VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
197 VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
198 VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
199 VHT_DATA_SC_20_RECV1 = 5,
200 VHT_DATA_SC_20_RECV2 = 6,
201 VHT_DATA_SC_20_RECV3 = 7,
202 VHT_DATA_SC_20_RECV4 = 8,
203 VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
204 VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
205};
206
207
208#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
209#define CHIP_TYPE_MASK BIT(3)
210#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
211#define MANUFACTUER_MASK BIT(7)
212#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
213#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
214
215
216#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
217#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
218#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
219#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
220#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
221#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
222
223#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
224#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
225 ? true : false)
226#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
227 ? true : false)
228
229#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
230 true : false)
231#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
232 true : false)
233
234#define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
235 ((IS_NORMAL_CHIP(version)) ? \
236 false : true) : false)
237#define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
238 ((IS_NORMAL_CHIP(version)) ? \
239 true : false) : false)
240#define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
241 ((GET_CVID_CUT_VERSION(version) == \
242 C_CUT_VERSION) ? \
243 true : false) : false)
244
245#define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
246 ((IS_NORMAL_CHIP(version)) ? \
247 false : true) : false)
248#define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
249 ((IS_NORMAL_CHIP(version)) ? \
250 true : false) : false)
251#define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
252 ((GET_CVID_CUT_VERSION(version) == \
253 B_CUT_VERSION) ? \
254 true : false) : false)
255enum board_type {
256 ODM_BOARD_DEFAULT = 0,
257 ODM_BOARD_MINICARD = BIT(0),
258 ODM_BOARD_SLIM = BIT(1),
259 ODM_BOARD_BT = BIT(2),
260 ODM_BOARD_EXT_PA = BIT(3),
261 ODM_BOARD_EXT_LNA = BIT(4),
262 ODM_BOARD_EXT_TRSW = BIT(5),
263 ODM_BOARD_EXT_PA_5G = BIT(6),
264 ODM_BOARD_EXT_LNA_5G = BIT(7),
265};
266
267enum rf_optype {
268 RF_OP_BY_SW_3WIRE = 0,
269 RF_OP_BY_FW,
270 RF_OP_MAX
271};
272
273enum rf_power_state {
274 RF_ON,
275 RF_OFF,
276 RF_SLEEP,
277 RF_SHUT_DOWN,
278};
279
280enum power_save_mode {
281 POWER_SAVE_MODE_ACTIVE,
282 POWER_SAVE_MODE_SAVE,
283};
284
285enum power_polocy_config {
286 POWERCFG_MAX_POWER_SAVINGS,
287 POWERCFG_GLOBAL_POWER_SAVINGS,
288 POWERCFG_LOCAL_POWER_SAVINGS,
289 POWERCFG_LENOVO,
290};
291
292enum interface_select_pci {
293 INTF_SEL1_MINICARD = 0,
294 INTF_SEL0_PCIE = 1,
295 INTF_SEL2_RSV = 2,
296 INTF_SEL3_RSV = 3,
297};
298
299enum hal_fw_c2h_cmd_id {
300 HAL_FW_C2H_CMD_READ_MACREG = 0,
301 HAL_FW_C2H_CMD_READ_BBREG = 1,
302 HAL_FW_C2H_CMD_READ_RFREG = 2,
303 HAL_FW_C2H_CMD_READ_EEPROM = 3,
304 HAL_FW_C2H_CMD_READ_EFUSE = 4,
305 HAL_FW_C2H_CMD_READ_CAM = 5,
306 HAL_FW_C2H_CMD_GET_BASICRATE = 6,
307 HAL_FW_C2H_CMD_GET_DATARATE = 7,
308 HAL_FW_C2H_CMD_SURVEY = 8,
309 HAL_FW_C2H_CMD_SURVEYDONE = 9,
310 HAL_FW_C2H_CMD_JOINBSS = 10,
311 HAL_FW_C2H_CMD_ADDSTA = 11,
312 HAL_FW_C2H_CMD_DELSTA = 12,
313 HAL_FW_C2H_CMD_ATIMDONE = 13,
314 HAL_FW_C2H_CMD_TX_REPORT = 14,
315 HAL_FW_C2H_CMD_CCX_REPORT = 15,
316 HAL_FW_C2H_CMD_DTM_REPORT = 16,
317 HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
318 HAL_FW_C2H_CMD_C2HLBK = 18,
319 HAL_FW_C2H_CMD_C2HDBG = 19,
320 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
321 HAL_FW_C2H_CMD_MAX
322};
323
324enum rtl_desc_qsel {
325 QSLT_BK = 0x2,
326 QSLT_BE = 0x0,
327 QSLT_VI = 0x5,
328 QSLT_VO = 0x7,
329 QSLT_BEACON = 0x10,
330 QSLT_HIGH = 0x11,
331 QSLT_MGNT = 0x12,
332 QSLT_CMD = 0x13,
333};
334
335enum rx_packet_type {
336 NORMAL_RX,
337 TX_REPORT1,
338 TX_REPORT2,
339 HIS_REPORT,
340 C2H_PACKET,
341};
342
343struct phy_sts_cck_8821ae_t {
344 u8 adc_pwdb_X[4];
345 u8 sq_rpt;
346 u8 cck_agc_rpt;
347};
348
349struct h2c_cmd_8821ae {
350 u8 element_id;
351 u32 cmd_len;
352 u8 *p_cmdbuffer;
353};
354
355#endif
356
