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15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/msi.h>
18#include <linux/clk.h>
19#include <linux/module.h>
20#include <linux/mbus.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/irqchip/arm-gic-v3.h>
25#include <linux/platform_device.h>
26#include <linux/of_address.h>
27#include <linux/of_pci.h>
28#include <linux/of_irq.h>
29#include <linux/of_platform.h>
30#include <linux/phy/phy.h>
31
32#include "pcie-iproc.h"
33
34#define EP_PERST_SOURCE_SELECT_SHIFT 2
35#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
36#define EP_MODE_SURVIVE_PERST_SHIFT 1
37#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
38#define RC_PCIE_RST_OUTPUT_SHIFT 0
39#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
40#define PAXC_RESET_MASK 0x7f
41
42#define GIC_V3_CFG_SHIFT 0
43#define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)
44
45#define MSI_ENABLE_CFG_SHIFT 0
46#define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)
47
48#define CFG_IND_ADDR_MASK 0x00001ffc
49
50#define CFG_ADDR_BUS_NUM_SHIFT 20
51#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
52#define CFG_ADDR_DEV_NUM_SHIFT 15
53#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
54#define CFG_ADDR_FUNC_NUM_SHIFT 12
55#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
56#define CFG_ADDR_REG_NUM_SHIFT 2
57#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
58#define CFG_ADDR_CFG_TYPE_SHIFT 0
59#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
60
61#define SYS_RC_INTX_MASK 0xf
62
63#define PCIE_PHYLINKUP_SHIFT 3
64#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
65#define PCIE_DL_ACTIVE_SHIFT 2
66#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
67
68#define APB_ERR_EN_SHIFT 0
69#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
70
71#define CFG_RETRY_STATUS 0xffff0001
72#define CFG_RETRY_STATUS_TIMEOUT_US 500000
73
74
75#define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
76
77
78
79
80
81#define MAX_NUM_OB_WINDOW_SIZES 4
82
83#define OARR_VALID_SHIFT 0
84#define OARR_VALID BIT(OARR_VALID_SHIFT)
85#define OARR_SIZE_CFG_SHIFT 1
86
87
88
89
90
91#define MAX_NUM_IB_REGION_SIZES 9
92
93#define IMAP_VALID_SHIFT 0
94#define IMAP_VALID BIT(IMAP_VALID_SHIFT)
95
96#define IPROC_PCI_EXP_CAP 0xac
97
98#define IPROC_PCIE_REG_INVALID 0xffff
99
100
101
102
103
104
105
106struct iproc_pcie_ob_map {
107 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
108 unsigned int nr_sizes;
109};
110
111static const struct iproc_pcie_ob_map paxb_ob_map[] = {
112 {
113
114 .window_sizes = { 128, 256 },
115 .nr_sizes = 2,
116 },
117 {
118
119 .window_sizes = { 128, 256 },
120 .nr_sizes = 2,
121 },
122};
123
124static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
125 {
126
127 .window_sizes = { 128, 256 },
128 .nr_sizes = 2,
129 },
130 {
131
132 .window_sizes = { 128, 256 },
133 .nr_sizes = 2,
134 },
135 {
136
137 .window_sizes = { 128, 256, 512, 1024 },
138 .nr_sizes = 4,
139 },
140 {
141
142 .window_sizes = { 128, 256, 512, 1024 },
143 .nr_sizes = 4,
144 },
145};
146
147
148
149
150enum iproc_pcie_ib_map_type {
151
152 IPROC_PCIE_IB_MAP_MEM = 0,
153
154
155 IPROC_PCIE_IB_MAP_IO,
156
157
158 IPROC_PCIE_IB_MAP_INVALID
159};
160
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174
175struct iproc_pcie_ib_map {
176 enum iproc_pcie_ib_map_type type;
177 unsigned int size_unit;
178 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
179 unsigned int nr_sizes;
180 unsigned int nr_windows;
181 u16 imap_addr_offset;
182 u16 imap_window_offset;
183};
184
185static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
186 {
187
188 .type = IPROC_PCIE_IB_MAP_IO,
189 .size_unit = SZ_1K,
190 .region_sizes = { 32 },
191 .nr_sizes = 1,
192 .nr_windows = 8,
193 .imap_addr_offset = 0x40,
194 .imap_window_offset = 0x4,
195 },
196 {
197
198 .type = IPROC_PCIE_IB_MAP_INVALID,
199 },
200 {
201
202 .type = IPROC_PCIE_IB_MAP_MEM,
203 .size_unit = SZ_1M,
204 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
205 16384 },
206 .nr_sizes = 9,
207 .nr_windows = 1,
208 .imap_addr_offset = 0x4,
209 .imap_window_offset = 0x8,
210 },
211 {
212
213 .type = IPROC_PCIE_IB_MAP_MEM,
214 .size_unit = SZ_1G,
215 .region_sizes = { 1, 2, 4, 8, 16, 32 },
216 .nr_sizes = 6,
217 .nr_windows = 8,
218 .imap_addr_offset = 0x4,
219 .imap_window_offset = 0x8,
220 },
221 {
222
223 .type = IPROC_PCIE_IB_MAP_MEM,
224 .size_unit = SZ_1G,
225 .region_sizes = { 32, 64, 128, 256, 512 },
226 .nr_sizes = 5,
227 .nr_windows = 8,
228 .imap_addr_offset = 0x4,
229 .imap_window_offset = 0x8,
230 },
231};
232
233
234
235
236enum iproc_pcie_reg {
237
238 IPROC_PCIE_CLK_CTRL = 0,
239
240
241
242
243
244 IPROC_PCIE_MSI_GIC_MODE,
245
246
247
248
249
250
251 IPROC_PCIE_MSI_BASE_ADDR,
252 IPROC_PCIE_MSI_WINDOW_SIZE,
253
254
255
256
257
258
259 IPROC_PCIE_MSI_ADDR_LO,
260 IPROC_PCIE_MSI_ADDR_HI,
261
262
263 IPROC_PCIE_MSI_EN_CFG,
264
265
266 IPROC_PCIE_CFG_IND_ADDR,
267 IPROC_PCIE_CFG_IND_DATA,
268
269
270 IPROC_PCIE_CFG_ADDR,
271 IPROC_PCIE_CFG_DATA,
272
273
274 IPROC_PCIE_INTX_EN,
275
276
277 IPROC_PCIE_OARR0,
278 IPROC_PCIE_OMAP0,
279 IPROC_PCIE_OARR1,
280 IPROC_PCIE_OMAP1,
281 IPROC_PCIE_OARR2,
282 IPROC_PCIE_OMAP2,
283 IPROC_PCIE_OARR3,
284 IPROC_PCIE_OMAP3,
285
286
287 IPROC_PCIE_IARR0,
288 IPROC_PCIE_IMAP0,
289 IPROC_PCIE_IARR1,
290 IPROC_PCIE_IMAP1,
291 IPROC_PCIE_IARR2,
292 IPROC_PCIE_IMAP2,
293 IPROC_PCIE_IARR3,
294 IPROC_PCIE_IMAP3,
295 IPROC_PCIE_IARR4,
296 IPROC_PCIE_IMAP4,
297
298
299 IPROC_PCIE_LINK_STATUS,
300
301
302 IPROC_PCIE_APB_ERR_EN,
303
304
305 IPROC_PCIE_MAX_NUM_REG,
306};
307
308
309static const u16 iproc_pcie_reg_paxb_bcma[] = {
310 [IPROC_PCIE_CLK_CTRL] = 0x000,
311 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
312 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
313 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
314 [IPROC_PCIE_CFG_DATA] = 0x1fc,
315 [IPROC_PCIE_INTX_EN] = 0x330,
316 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
317};
318
319
320static const u16 iproc_pcie_reg_paxb[] = {
321 [IPROC_PCIE_CLK_CTRL] = 0x000,
322 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
323 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
324 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
325 [IPROC_PCIE_CFG_DATA] = 0x1fc,
326 [IPROC_PCIE_INTX_EN] = 0x330,
327 [IPROC_PCIE_OARR0] = 0xd20,
328 [IPROC_PCIE_OMAP0] = 0xd40,
329 [IPROC_PCIE_OARR1] = 0xd28,
330 [IPROC_PCIE_OMAP1] = 0xd48,
331 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
332 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
333};
334
335
336static const u16 iproc_pcie_reg_paxb_v2[] = {
337 [IPROC_PCIE_CLK_CTRL] = 0x000,
338 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
339 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
340 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
341 [IPROC_PCIE_CFG_DATA] = 0x1fc,
342 [IPROC_PCIE_INTX_EN] = 0x330,
343 [IPROC_PCIE_OARR0] = 0xd20,
344 [IPROC_PCIE_OMAP0] = 0xd40,
345 [IPROC_PCIE_OARR1] = 0xd28,
346 [IPROC_PCIE_OMAP1] = 0xd48,
347 [IPROC_PCIE_OARR2] = 0xd60,
348 [IPROC_PCIE_OMAP2] = 0xd68,
349 [IPROC_PCIE_OARR3] = 0xdf0,
350 [IPROC_PCIE_OMAP3] = 0xdf8,
351 [IPROC_PCIE_IARR0] = 0xd00,
352 [IPROC_PCIE_IMAP0] = 0xc00,
353 [IPROC_PCIE_IARR2] = 0xd10,
354 [IPROC_PCIE_IMAP2] = 0xcc0,
355 [IPROC_PCIE_IARR3] = 0xe00,
356 [IPROC_PCIE_IMAP3] = 0xe08,
357 [IPROC_PCIE_IARR4] = 0xe68,
358 [IPROC_PCIE_IMAP4] = 0xe70,
359 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
360 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
361};
362
363
364static const u16 iproc_pcie_reg_paxc[] = {
365 [IPROC_PCIE_CLK_CTRL] = 0x000,
366 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
367 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
368 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
369 [IPROC_PCIE_CFG_DATA] = 0x1fc,
370};
371
372
373static const u16 iproc_pcie_reg_paxc_v2[] = {
374 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
375 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
376 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
377 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
378 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
379 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
380 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
381 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
382 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
383 [IPROC_PCIE_CFG_DATA] = 0x1fc,
384};
385
386static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
387{
388 struct iproc_pcie *pcie;
389#ifdef CONFIG_ARM
390 struct pci_sys_data *sys = bus->sysdata;
391
392 pcie = sys->private_data;
393#else
394 pcie = bus->sysdata;
395#endif
396 return pcie;
397}
398
399static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
400{
401 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
402}
403
404static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
405 enum iproc_pcie_reg reg)
406{
407 return pcie->reg_offsets[reg];
408}
409
410static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
411 enum iproc_pcie_reg reg)
412{
413 u16 offset = iproc_pcie_reg_offset(pcie, reg);
414
415 if (iproc_pcie_reg_is_invalid(offset))
416 return 0;
417
418 return readl(pcie->base + offset);
419}
420
421static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
422 enum iproc_pcie_reg reg, u32 val)
423{
424 u16 offset = iproc_pcie_reg_offset(pcie, reg);
425
426 if (iproc_pcie_reg_is_invalid(offset))
427 return;
428
429 writel(val, pcie->base + offset);
430}
431
432
433
434
435
436
437
438static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
439 bool disable)
440{
441 struct iproc_pcie *pcie = iproc_data(bus);
442 u32 val;
443
444 if (bus->number && pcie->has_apb_err_disable) {
445 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
446 if (disable)
447 val &= ~APB_ERR_EN;
448 else
449 val |= APB_ERR_EN;
450 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
451 }
452}
453
454static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
455 unsigned int busno,
456 unsigned int slot,
457 unsigned int fn,
458 int where)
459{
460 u16 offset;
461 u32 val;
462
463
464 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
465 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
466 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
467 (where & CFG_ADDR_REG_NUM_MASK) |
468 (1 & CFG_ADDR_CFG_TYPE_MASK);
469
470 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
471 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
472
473 if (iproc_pcie_reg_is_invalid(offset))
474 return NULL;
475
476 return (pcie->base + offset);
477}
478
479static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
480{
481 int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
482 unsigned int data;
483
484
485
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498
499
500
501 data = readl(cfg_data_p);
502 while (data == CFG_RETRY_STATUS && timeout--) {
503 udelay(1);
504 data = readl(cfg_data_p);
505 }
506
507 if (data == CFG_RETRY_STATUS)
508 data = 0xffffffff;
509
510 return data;
511}
512
513static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
514 int where, int size, u32 *val)
515{
516 struct iproc_pcie *pcie = iproc_data(bus);
517 unsigned int slot = PCI_SLOT(devfn);
518 unsigned int fn = PCI_FUNC(devfn);
519 unsigned int busno = bus->number;
520 void __iomem *cfg_data_p;
521 unsigned int data;
522 int ret;
523
524
525 if (busno == 0) {
526 ret = pci_generic_config_read32(bus, devfn, where, size, val);
527 if (ret != PCIBIOS_SUCCESSFUL)
528 return ret;
529
530
531 if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL)
532 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
533 return PCIBIOS_SUCCESSFUL;
534 }
535
536 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
537
538 if (!cfg_data_p)
539 return PCIBIOS_DEVICE_NOT_FOUND;
540
541 data = iproc_pcie_cfg_retry(cfg_data_p);
542
543 *val = data;
544 if (size <= 2)
545 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
546
547 return PCIBIOS_SUCCESSFUL;
548}
549
550
551
552
553
554static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,
555 int busno, unsigned int devfn,
556 int where)
557{
558 unsigned slot = PCI_SLOT(devfn);
559 unsigned fn = PCI_FUNC(devfn);
560 u16 offset;
561
562
563 if (busno == 0) {
564 if (slot > 0 || fn > 0)
565 return NULL;
566
567 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
568 where & CFG_IND_ADDR_MASK);
569 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
570 if (iproc_pcie_reg_is_invalid(offset))
571 return NULL;
572 else
573 return (pcie->base + offset);
574 }
575
576
577
578
579
580 if (pcie->ep_is_internal)
581 if (slot > 0)
582 return NULL;
583
584 return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
585}
586
587static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus,
588 unsigned int devfn,
589 int where)
590{
591 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn,
592 where);
593}
594
595static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
596 unsigned int devfn, int where,
597 int size, u32 *val)
598{
599 void __iomem *addr;
600
601 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
602 if (!addr) {
603 *val = ~0;
604 return PCIBIOS_DEVICE_NOT_FOUND;
605 }
606
607 *val = readl(addr);
608
609 if (size <= 2)
610 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
611
612 return PCIBIOS_SUCCESSFUL;
613}
614
615static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
616 unsigned int devfn, int where,
617 int size, u32 val)
618{
619 void __iomem *addr;
620 u32 mask, tmp;
621
622 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
623 if (!addr)
624 return PCIBIOS_DEVICE_NOT_FOUND;
625
626 if (size == 4) {
627 writel(val, addr);
628 return PCIBIOS_SUCCESSFUL;
629 }
630
631 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
632 tmp = readl(addr) & mask;
633 tmp |= val << ((where & 0x3) * 8);
634 writel(tmp, addr);
635
636 return PCIBIOS_SUCCESSFUL;
637}
638
639static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
640 int where, int size, u32 *val)
641{
642 int ret;
643 struct iproc_pcie *pcie = iproc_data(bus);
644
645 iproc_pcie_apb_err_disable(bus, true);
646 if (pcie->type == IPROC_PCIE_PAXB_V2)
647 ret = iproc_pcie_config_read(bus, devfn, where, size, val);
648 else
649 ret = pci_generic_config_read32(bus, devfn, where, size, val);
650 iproc_pcie_apb_err_disable(bus, false);
651
652 return ret;
653}
654
655static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn,
656 int where, int size, u32 val)
657{
658 int ret;
659
660 iproc_pcie_apb_err_disable(bus, true);
661 ret = pci_generic_config_write32(bus, devfn, where, size, val);
662 iproc_pcie_apb_err_disable(bus, false);
663
664 return ret;
665}
666
667static struct pci_ops iproc_pcie_ops = {
668 .map_bus = iproc_pcie_bus_map_cfg_bus,
669 .read = iproc_pcie_config_read32,
670 .write = iproc_pcie_config_write32,
671};
672
673static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert)
674{
675 u32 val;
676
677
678
679
680
681
682 if (pcie->ep_is_internal)
683 return;
684
685 if (assert) {
686 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
687 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
688 ~RC_PCIE_RST_OUTPUT;
689 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
690 udelay(250);
691 } else {
692 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
693 val |= RC_PCIE_RST_OUTPUT;
694 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
695 msleep(100);
696 }
697}
698
699int iproc_pcie_shutdown(struct iproc_pcie *pcie)
700{
701 iproc_pcie_perst_ctrl(pcie, true);
702 msleep(500);
703
704 return 0;
705}
706EXPORT_SYMBOL_GPL(iproc_pcie_shutdown);
707
708static int iproc_pcie_check_link(struct iproc_pcie *pcie)
709{
710 struct device *dev = pcie->dev;
711 u32 hdr_type, link_ctrl, link_status, class, val;
712 bool link_is_active = false;
713
714
715
716
717
718 if (pcie->ep_is_internal)
719 return 0;
720
721 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
722 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
723 dev_err(dev, "PHY or data link is INACTIVE!\n");
724 return -ENODEV;
725 }
726
727
728 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
729 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
730 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type);
731 return -EFAULT;
732 }
733
734
735#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
736#define PCI_CLASS_BRIDGE_MASK 0xffff00
737#define PCI_CLASS_BRIDGE_SHIFT 8
738 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
739 4, &class);
740 class &= ~PCI_CLASS_BRIDGE_MASK;
741 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
742 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
743 4, class);
744
745
746 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
747 2, &link_status);
748 if (link_status & PCI_EXP_LNKSTA_NLW)
749 link_is_active = true;
750
751 if (!link_is_active) {
752
753#define PCI_TARGET_LINK_SPEED_MASK 0xf
754#define PCI_TARGET_LINK_SPEED_GEN2 0x2
755#define PCI_TARGET_LINK_SPEED_GEN1 0x1
756 iproc_pci_raw_config_read32(pcie, 0,
757 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
758 4, &link_ctrl);
759 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
760 PCI_TARGET_LINK_SPEED_GEN2) {
761 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
762 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
763 iproc_pci_raw_config_write32(pcie, 0,
764 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
765 4, link_ctrl);
766 msleep(100);
767
768 iproc_pci_raw_config_read32(pcie, 0,
769 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
770 2, &link_status);
771 if (link_status & PCI_EXP_LNKSTA_NLW)
772 link_is_active = true;
773 }
774 }
775
776 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
777
778 return link_is_active ? 0 : -ENODEV;
779}
780
781static void iproc_pcie_enable(struct iproc_pcie *pcie)
782{
783 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
784}
785
786static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
787 int window_idx)
788{
789 u32 val;
790
791 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
792
793 return !!(val & OARR_VALID);
794}
795
796static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
797 int size_idx, u64 axi_addr, u64 pci_addr)
798{
799 struct device *dev = pcie->dev;
800 u16 oarr_offset, omap_offset;
801
802
803
804
805
806 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
807 window_idx));
808 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
809 window_idx));
810 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
811 iproc_pcie_reg_is_invalid(omap_offset))
812 return -EINVAL;
813
814
815
816
817
818 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
819 OARR_VALID, pcie->base + oarr_offset);
820 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
821
822
823 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
824 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
825
826 dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
827 window_idx, oarr_offset, &axi_addr, &pci_addr);
828 dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n",
829 readl(pcie->base + oarr_offset),
830 readl(pcie->base + oarr_offset + 4));
831 dev_info(dev, "omap lo 0x%x omap hi 0x%x\n",
832 readl(pcie->base + omap_offset),
833 readl(pcie->base + omap_offset + 4));
834
835 return 0;
836}
837
838
839
840
841
842
843
844
845
846
847
848
849static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
850 u64 pci_addr, resource_size_t size)
851{
852 struct iproc_pcie_ob *ob = &pcie->ob;
853 struct device *dev = pcie->dev;
854 int ret = -EINVAL, window_idx, size_idx;
855
856 if (axi_addr < ob->axi_offset) {
857 dev_err(dev, "axi address %pap less than offset %pap\n",
858 &axi_addr, &ob->axi_offset);
859 return -EINVAL;
860 }
861
862
863
864
865
866 axi_addr -= ob->axi_offset;
867
868
869 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
870 const struct iproc_pcie_ob_map *ob_map =
871 &pcie->ob_map[window_idx];
872
873
874
875
876
877 if (iproc_pcie_ob_is_valid(pcie, window_idx))
878 continue;
879
880
881
882
883
884
885 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
886 size_idx--) {
887 resource_size_t window_size =
888 ob_map->window_sizes[size_idx] * SZ_1M;
889
890 if (size < window_size)
891 continue;
892
893 if (!IS_ALIGNED(axi_addr, window_size) ||
894 !IS_ALIGNED(pci_addr, window_size)) {
895 dev_err(dev,
896 "axi %pap or pci %pap not aligned\n",
897 &axi_addr, &pci_addr);
898 return -EINVAL;
899 }
900
901
902
903
904
905 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
906 axi_addr, pci_addr);
907 if (ret)
908 goto err_ob;
909
910 size -= window_size;
911 if (size == 0)
912 return 0;
913
914
915
916
917
918
919 axi_addr += window_size;
920 pci_addr += window_size;
921 break;
922 }
923 }
924
925err_ob:
926 dev_err(dev, "unable to configure outbound mapping\n");
927 dev_err(dev,
928 "axi %pap, axi offset %pap, pci %pap, res size %pap\n",
929 &axi_addr, &ob->axi_offset, &pci_addr, &size);
930
931 return ret;
932}
933
934static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
935 struct list_head *resources)
936{
937 struct device *dev = pcie->dev;
938 struct resource_entry *window;
939 int ret;
940
941 resource_list_for_each_entry(window, resources) {
942 struct resource *res = window->res;
943 u64 res_type = resource_type(res);
944
945 switch (res_type) {
946 case IORESOURCE_IO:
947 case IORESOURCE_BUS:
948 break;
949 case IORESOURCE_MEM:
950 ret = iproc_pcie_setup_ob(pcie, res->start,
951 res->start - window->offset,
952 resource_size(res));
953 if (ret)
954 return ret;
955 break;
956 default:
957 dev_err(dev, "invalid resource %pR\n", res);
958 return -EINVAL;
959 }
960 }
961
962 return 0;
963}
964
965static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
966 int region_idx)
967{
968 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
969 u32 val;
970
971 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
972
973 return !!(val & (BIT(ib_map->nr_sizes) - 1));
974}
975
976static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
977 enum iproc_pcie_ib_map_type type)
978{
979 return !!(ib_map->type == type);
980}
981
982static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
983 int size_idx, int nr_windows, u64 axi_addr,
984 u64 pci_addr, resource_size_t size)
985{
986 struct device *dev = pcie->dev;
987 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
988 u16 iarr_offset, imap_offset;
989 u32 val;
990 int window_idx;
991
992 iarr_offset = iproc_pcie_reg_offset(pcie,
993 MAP_REG(IPROC_PCIE_IARR0, region_idx));
994 imap_offset = iproc_pcie_reg_offset(pcie,
995 MAP_REG(IPROC_PCIE_IMAP0, region_idx));
996 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
997 iproc_pcie_reg_is_invalid(imap_offset))
998 return -EINVAL;
999
1000 dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
1001 region_idx, iarr_offset, &axi_addr, &pci_addr);
1002
1003
1004
1005
1006
1007 writel(lower_32_bits(pci_addr) | BIT(size_idx),
1008 pcie->base + iarr_offset);
1009 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
1010
1011 dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n",
1012 readl(pcie->base + iarr_offset),
1013 readl(pcie->base + iarr_offset + 4));
1014
1015
1016
1017
1018
1019 size >>= ilog2(nr_windows);
1020 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
1021 val = readl(pcie->base + imap_offset);
1022 val |= lower_32_bits(axi_addr) | IMAP_VALID;
1023 writel(val, pcie->base + imap_offset);
1024 writel(upper_32_bits(axi_addr),
1025 pcie->base + imap_offset + ib_map->imap_addr_offset);
1026
1027 dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
1028 window_idx, readl(pcie->base + imap_offset),
1029 readl(pcie->base + imap_offset +
1030 ib_map->imap_addr_offset));
1031
1032 imap_offset += ib_map->imap_window_offset;
1033 axi_addr += size;
1034 }
1035
1036 return 0;
1037}
1038
1039static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
1040 struct of_pci_range *range,
1041 enum iproc_pcie_ib_map_type type)
1042{
1043 struct device *dev = pcie->dev;
1044 struct iproc_pcie_ib *ib = &pcie->ib;
1045 int ret;
1046 unsigned int region_idx, size_idx;
1047 u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
1048 resource_size_t size = range->size;
1049
1050
1051 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1052 const struct iproc_pcie_ib_map *ib_map =
1053 &pcie->ib_map[region_idx];
1054
1055
1056
1057
1058
1059 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1060 !iproc_pcie_ib_check_type(ib_map, type))
1061 continue;
1062
1063
1064 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1065 resource_size_t region_size =
1066 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1067
1068 if (size != region_size)
1069 continue;
1070
1071 if (!IS_ALIGNED(axi_addr, region_size) ||
1072 !IS_ALIGNED(pci_addr, region_size)) {
1073 dev_err(dev,
1074 "axi %pap or pci %pap not aligned\n",
1075 &axi_addr, &pci_addr);
1076 return -EINVAL;
1077 }
1078
1079
1080 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1081 ib_map->nr_windows, axi_addr,
1082 pci_addr, size);
1083 if (ret)
1084 goto err_ib;
1085 else
1086 return 0;
1087
1088 }
1089 }
1090 ret = -EINVAL;
1091
1092err_ib:
1093 dev_err(dev, "unable to configure inbound mapping\n");
1094 dev_err(dev, "axi %pap, pci %pap, res size %pap\n",
1095 &axi_addr, &pci_addr, &size);
1096
1097 return ret;
1098}
1099
1100static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
1101 struct device_node *node)
1102{
1103 const int na = 3, ns = 2;
1104 int rlen;
1105
1106 parser->node = node;
1107 parser->pna = of_n_addr_cells(node);
1108 parser->np = parser->pna + na + ns;
1109
1110 parser->range = of_get_property(node, "dma-ranges", &rlen);
1111 if (!parser->range)
1112 return -ENOENT;
1113
1114 parser->end = parser->range + rlen / sizeof(__be32);
1115 return 0;
1116}
1117
1118static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1119{
1120 struct of_pci_range range;
1121 struct of_pci_range_parser parser;
1122 int ret;
1123
1124
1125 ret = pci_dma_range_parser_init(&parser, pcie->dev->of_node);
1126 if (ret)
1127 return ret;
1128
1129 for_each_of_pci_range(&parser, &range) {
1130
1131 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
1132 if (ret)
1133 return ret;
1134 }
1135
1136 return 0;
1137}
1138
1139static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
1140 struct device_node *msi_node,
1141 u64 *msi_addr)
1142{
1143 struct device *dev = pcie->dev;
1144 int ret;
1145 struct resource res;
1146
1147
1148
1149
1150
1151 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) {
1152 dev_err(dev, "unable to find compatible MSI controller\n");
1153 return -ENODEV;
1154 }
1155
1156
1157 ret = of_address_to_resource(msi_node, 0, &res);
1158 if (ret < 0) {
1159 dev_err(dev, "unable to obtain MSI controller resources\n");
1160 return ret;
1161 }
1162
1163 *msi_addr = res.start + GITS_TRANSLATER;
1164 return 0;
1165}
1166
1167static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1168{
1169 int ret;
1170 struct of_pci_range range;
1171
1172 memset(&range, 0, sizeof(range));
1173 range.size = SZ_32K;
1174 range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1);
1175
1176 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO);
1177 return ret;
1178}
1179
1180static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1181{
1182 u32 val;
1183
1184
1185
1186
1187
1188
1189
1190 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR,
1191 (u32)(msi_addr >> 13));
1192
1193
1194 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);
1195
1196
1197 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE);
1198 val |= GIC_V3_CFG;
1199 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val);
1200
1201
1202
1203
1204
1205 msi_addr >>= 2;
1206 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI,
1207 upper_32_bits(msi_addr));
1208 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO,
1209 lower_32_bits(msi_addr));
1210
1211
1212 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1213 val |= MSI_ENABLE_CFG;
1214 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1215}
1216
1217static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
1218 struct device_node *msi_node)
1219{
1220 struct device *dev = pcie->dev;
1221 int ret;
1222 u64 msi_addr;
1223
1224 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr);
1225 if (ret < 0) {
1226 dev_err(dev, "msi steering failed\n");
1227 return ret;
1228 }
1229
1230 switch (pcie->type) {
1231 case IPROC_PCIE_PAXB_V2:
1232 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr);
1233 if (ret)
1234 return ret;
1235 break;
1236 case IPROC_PCIE_PAXC_V2:
1237 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr);
1238 break;
1239 default:
1240 return -EINVAL;
1241 }
1242
1243 return 0;
1244}
1245
1246static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
1247{
1248 struct device_node *msi_node;
1249 int ret;
1250
1251
1252
1253
1254
1255
1256 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
1257 if (!msi_node) {
1258 const __be32 *msi_map = NULL;
1259 int len;
1260 u32 phandle;
1261
1262 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len);
1263 if (!msi_map)
1264 return -ENODEV;
1265
1266 phandle = be32_to_cpup(msi_map + 1);
1267 msi_node = of_find_node_by_phandle(phandle);
1268 if (!msi_node)
1269 return -ENODEV;
1270 }
1271
1272
1273
1274
1275
1276
1277 if (pcie->need_msi_steer) {
1278 ret = iproc_pcie_msi_steer(pcie, msi_node);
1279 if (ret)
1280 return ret;
1281 }
1282
1283
1284
1285
1286
1287 return iproc_msi_init(pcie, msi_node);
1288}
1289
1290static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
1291{
1292 iproc_msi_exit(pcie);
1293}
1294
1295static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
1296{
1297 struct device *dev = pcie->dev;
1298 unsigned int reg_idx;
1299 const u16 *regs;
1300
1301 switch (pcie->type) {
1302 case IPROC_PCIE_PAXB_BCMA:
1303 regs = iproc_pcie_reg_paxb_bcma;
1304 break;
1305 case IPROC_PCIE_PAXB:
1306 regs = iproc_pcie_reg_paxb;
1307 pcie->has_apb_err_disable = true;
1308 if (pcie->need_ob_cfg) {
1309 pcie->ob_map = paxb_ob_map;
1310 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map);
1311 }
1312 break;
1313 case IPROC_PCIE_PAXB_V2:
1314 regs = iproc_pcie_reg_paxb_v2;
1315 pcie->has_apb_err_disable = true;
1316 if (pcie->need_ob_cfg) {
1317 pcie->ob_map = paxb_v2_ob_map;
1318 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
1319 }
1320 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
1321 pcie->ib_map = paxb_v2_ib_map;
1322 pcie->need_msi_steer = true;
1323 dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n",
1324 CFG_RETRY_STATUS);
1325 break;
1326 case IPROC_PCIE_PAXC:
1327 regs = iproc_pcie_reg_paxc;
1328 pcie->ep_is_internal = true;
1329 break;
1330 case IPROC_PCIE_PAXC_V2:
1331 regs = iproc_pcie_reg_paxc_v2;
1332 pcie->ep_is_internal = true;
1333 pcie->need_msi_steer = true;
1334 break;
1335 default:
1336 dev_err(dev, "incompatible iProc PCIe interface\n");
1337 return -EINVAL;
1338 }
1339
1340 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,
1341 sizeof(*pcie->reg_offsets),
1342 GFP_KERNEL);
1343 if (!pcie->reg_offsets)
1344 return -ENOMEM;
1345
1346
1347 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
1348 IPROC_PCIE_REG_INVALID : regs[0];
1349 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++)
1350 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
1351 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
1352
1353 return 0;
1354}
1355
1356int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
1357{
1358 struct device *dev;
1359 int ret;
1360 void *sysdata;
1361 struct pci_bus *child;
1362 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1363
1364 dev = pcie->dev;
1365
1366 ret = iproc_pcie_rev_init(pcie);
1367 if (ret) {
1368 dev_err(dev, "unable to initialize controller parameters\n");
1369 return ret;
1370 }
1371
1372 ret = devm_request_pci_bus_resources(dev, res);
1373 if (ret)
1374 return ret;
1375
1376 ret = phy_init(pcie->phy);
1377 if (ret) {
1378 dev_err(dev, "unable to initialize PCIe PHY\n");
1379 return ret;
1380 }
1381
1382 ret = phy_power_on(pcie->phy);
1383 if (ret) {
1384 dev_err(dev, "unable to power on PCIe PHY\n");
1385 goto err_exit_phy;
1386 }
1387
1388 iproc_pcie_perst_ctrl(pcie, true);
1389 iproc_pcie_perst_ctrl(pcie, false);
1390
1391 if (pcie->need_ob_cfg) {
1392 ret = iproc_pcie_map_ranges(pcie, res);
1393 if (ret) {
1394 dev_err(dev, "map failed\n");
1395 goto err_power_off_phy;
1396 }
1397 }
1398
1399 ret = iproc_pcie_map_dma_ranges(pcie);
1400 if (ret && ret != -ENOENT)
1401 goto err_power_off_phy;
1402
1403#ifdef CONFIG_ARM
1404 pcie->sysdata.private_data = pcie;
1405 sysdata = &pcie->sysdata;
1406#else
1407 sysdata = pcie;
1408#endif
1409
1410 ret = iproc_pcie_check_link(pcie);
1411 if (ret) {
1412 dev_err(dev, "no PCIe EP device detected\n");
1413 goto err_power_off_phy;
1414 }
1415
1416 iproc_pcie_enable(pcie);
1417
1418 if (IS_ENABLED(CONFIG_PCI_MSI))
1419 if (iproc_pcie_msi_enable(pcie))
1420 dev_info(dev, "not using iProc MSI\n");
1421
1422 list_splice_init(res, &host->windows);
1423 host->busnr = 0;
1424 host->dev.parent = dev;
1425 host->ops = &iproc_pcie_ops;
1426 host->sysdata = sysdata;
1427 host->map_irq = pcie->map_irq;
1428 host->swizzle_irq = pci_common_swizzle;
1429
1430 ret = pci_scan_root_bus_bridge(host);
1431 if (ret < 0) {
1432 dev_err(dev, "failed to scan host: %d\n", ret);
1433 goto err_power_off_phy;
1434 }
1435
1436 pci_assign_unassigned_bus_resources(host->bus);
1437
1438 pcie->root_bus = host->bus;
1439
1440 list_for_each_entry(child, &host->bus->children, node)
1441 pcie_bus_configure_settings(child);
1442
1443 pci_bus_add_devices(host->bus);
1444
1445 return 0;
1446
1447err_power_off_phy:
1448 phy_power_off(pcie->phy);
1449err_exit_phy:
1450 phy_exit(pcie->phy);
1451 return ret;
1452}
1453EXPORT_SYMBOL(iproc_pcie_setup);
1454
1455int iproc_pcie_remove(struct iproc_pcie *pcie)
1456{
1457 pci_stop_root_bus(pcie->root_bus);
1458 pci_remove_root_bus(pcie->root_bus);
1459
1460 iproc_pcie_msi_disable(pcie);
1461
1462 phy_power_off(pcie->phy);
1463 phy_exit(pcie->phy);
1464
1465 return 0;
1466}
1467EXPORT_SYMBOL(iproc_pcie_remove);
1468
1469MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1470MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
1471MODULE_LICENSE("GPL v2");
1472