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6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28#include <linux/btree.h>
29
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_transport_fc.h>
35#include <scsi/scsi_bsg_fc.h>
36
37#include "qla_bsg.h"
38#include "qla_nx.h"
39#include "qla_nx2.h"
40#include "qla_nvme.h"
41#define QLA2XXX_DRIVER_NAME "qla2xxx"
42#define QLA2XXX_APIDEV "ql2xapidev"
43#define QLA2XXX_MANUFACTURER "QLogic Corporation"
44
45
46
47
48
49
50#define MAILBOX_REGISTER_COUNT_2100 8
51#define MAILBOX_REGISTER_COUNT_2200 24
52#define MAILBOX_REGISTER_COUNT 32
53
54#define QLA2200A_RISC_ROM_VER 4
55#define FPM_2300 6
56#define FPM_2310 7
57
58#include "qla_settings.h"
59
60#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
61
62
63
64
65#define BIT_0 0x1
66#define BIT_1 0x2
67#define BIT_2 0x4
68#define BIT_3 0x8
69#define BIT_4 0x10
70#define BIT_5 0x20
71#define BIT_6 0x40
72#define BIT_7 0x80
73#define BIT_8 0x100
74#define BIT_9 0x200
75#define BIT_10 0x400
76#define BIT_11 0x800
77#define BIT_12 0x1000
78#define BIT_13 0x2000
79#define BIT_14 0x4000
80#define BIT_15 0x8000
81#define BIT_16 0x10000
82#define BIT_17 0x20000
83#define BIT_18 0x40000
84#define BIT_19 0x80000
85#define BIT_20 0x100000
86#define BIT_21 0x200000
87#define BIT_22 0x400000
88#define BIT_23 0x800000
89#define BIT_24 0x1000000
90#define BIT_25 0x2000000
91#define BIT_26 0x4000000
92#define BIT_27 0x8000000
93#define BIT_28 0x10000000
94#define BIT_29 0x20000000
95#define BIT_30 0x40000000
96#define BIT_31 0x80000000
97
98#define LSB(x) ((uint8_t)(x))
99#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
100
101#define LSW(x) ((uint16_t)(x))
102#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
103
104#define LSD(x) ((uint32_t)((uint64_t)(x)))
105#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
106
107#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
108
109
110
111
112
113#define RD_REG_BYTE(addr) readb(addr)
114#define RD_REG_WORD(addr) readw(addr)
115#define RD_REG_DWORD(addr) readl(addr)
116#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
117#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
118#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
119#define WRT_REG_BYTE(addr, data) writeb(data,addr)
120#define WRT_REG_WORD(addr, data) writew(data,addr)
121#define WRT_REG_DWORD(addr, data) writel(data,addr)
122
123
124
125
126#define QLA83XX_LED_PORT0 0x00201320
127#define QLA83XX_LED_PORT1 0x00201328
128#define QLA83XX_IDC_DEV_STATE 0x22102384
129#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
130#define QLA83XX_IDC_MINOR_VERSION 0x22102398
131#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
132#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
133#define QLA83XX_IDC_CONTROL 0x22102390
134#define QLA83XX_IDC_AUDIT 0x22102394
135#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
136#define QLA83XX_DRIVER_LOCKID 0x22102104
137#define QLA83XX_DRIVER_LOCK 0x8111c028
138#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
139#define QLA83XX_FLASH_LOCKID 0x22102100
140#define QLA83XX_FLASH_LOCK 0x8111c010
141#define QLA83XX_FLASH_UNLOCK 0x8111c014
142#define QLA83XX_DEV_PARTINFO1 0x221023e0
143#define QLA83XX_DEV_PARTINFO2 0x221023e4
144#define QLA83XX_FW_HEARTBEAT 0x221020b0
145#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
146#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
147
148
149#define IDC_DEVICE_STATE_CHANGE BIT_0
150#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
151#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
152#define IDC_HEARTBEAT_FAILURE BIT_3
153
154
155#define ERR_LEVEL_NON_FATAL 0x1
156#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
157#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
158
159
160#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
161#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
162
163
164#define QLA83XX_NIC_CORE_RESET 0x1
165#define QLA83XX_IDC_STATE_HANDLER 0x2
166#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
167
168
169#define QLA83XX_IDC_RESET_DISABLED BIT_0
170#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
171
172
173#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
174#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
175#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
176
177
178#define QLA83XX_CLASS_TYPE_NONE 0x0
179#define QLA83XX_CLASS_TYPE_NIC 0x1
180#define QLA83XX_CLASS_TYPE_FCOE 0x2
181#define QLA83XX_CLASS_TYPE_ISCSI 0x3
182
183
184#define IDC_LOCK_RECOVERY_STAGE1 0x1
185
186
187#define IDC_LOCK_RECOVERY_STAGE2 0x2
188
189
190#define IDC_AUDIT_TIMESTAMP 0x0
191
192
193
194#define IDC_AUDIT_COMPLETION 0x1
195
196
197
198
199#define PORT_0_2031 0x00201340
200#define PORT_1_2031 0x00201350
201#define LASER_ON_2031 0x01800100
202#define LASER_OFF_2031 0x01800180
203
204
205
206
207
208#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
209#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
210
211
212
213
214#define WWN_SIZE 8
215#define MAX_FIBRE_DEVICES_2100 512
216#define MAX_FIBRE_DEVICES_2400 2048
217#define MAX_FIBRE_DEVICES_LOOP 128
218#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
219#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
220#define MAX_FIBRE_LUNS 0xFFFF
221#define MAX_HOST_COUNT 16
222
223
224
225
226#define MAX_BUSES 1
227#define MIN_LUNS 8
228#define MAX_LUNS MAX_FIBRE_LUNS
229#define MAX_CMDS_PER_LUN 255
230
231
232
233
234#define SNS_LAST_LOOP_ID_2100 0xfe
235#define SNS_LAST_LOOP_ID_2300 0x7ff
236
237#define LAST_LOCAL_LOOP_ID 0x7d
238#define SNS_FL_PORT 0x7e
239#define FABRIC_CONTROLLER 0x7f
240#define SIMPLE_NAME_SERVER 0x80
241#define SNS_FIRST_LOOP_ID 0x81
242#define MANAGEMENT_SERVER 0xfe
243#define BROADCAST 0xff
244
245
246
247
248
249#define NPH_LAST_HANDLE 0x7ef
250#define NPH_MGMT_SERVER 0x7fa
251#define NPH_SNS 0x7fc
252#define NPH_FABRIC_CONTROLLER 0x7fd
253#define NPH_F_PORT 0x7fe
254#define NPH_IP_BROADCAST 0x7ff
255
256#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
257
258#define MAX_CMDSZ 16
259#include "qla_fw.h"
260
261struct name_list_extended {
262 struct get_name_list_extended *l;
263 dma_addr_t ldma;
264 struct list_head fcports;
265 u32 size;
266 u8 sent;
267};
268
269
270
271#define PORT_RETRY_TIME 1
272#define LOOP_DOWN_TIMEOUT 60
273#define LOOP_DOWN_TIME 255
274#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
275
276#define DEFAULT_OUTSTANDING_COMMANDS 4096
277#define MIN_OUTSTANDING_COMMANDS 128
278
279
280#define REQUEST_ENTRY_CNT_2100 128
281#define REQUEST_ENTRY_CNT_2200 2048
282#define REQUEST_ENTRY_CNT_24XX 2048
283#define REQUEST_ENTRY_CNT_83XX 8192
284#define RESPONSE_ENTRY_CNT_83XX 4096
285#define RESPONSE_ENTRY_CNT_2100 64
286#define RESPONSE_ENTRY_CNT_2300 512
287#define RESPONSE_ENTRY_CNT_MQ 128
288#define ATIO_ENTRY_CNT_24XX 4096
289#define RESPONSE_ENTRY_CNT_FX00 256
290#define FW_DEF_EXCHANGES_CNT 2048
291
292struct req_que;
293struct qla_tgt_sess;
294
295
296
297
298struct srb_cmd {
299 struct scsi_cmnd *cmd;
300 uint32_t request_sense_length;
301 uint32_t fw_sense_length;
302 uint8_t *request_sense_ptr;
303 void *ctx;
304};
305
306
307
308
309#define SRB_DMA_VALID BIT_0
310#define SRB_FCP_CMND_DMA_VALID BIT_12
311#define SRB_CRC_CTX_DMA_VALID BIT_2
312#define SRB_CRC_PROT_DMA_VALID BIT_4
313#define SRB_CRC_CTX_DSD_VALID BIT_5
314
315
316#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
317
318struct els_logo_payload {
319 uint8_t opcode;
320 uint8_t rsvd[3];
321 uint8_t s_id[3];
322 uint8_t rsvd1[1];
323 uint8_t wwpn[WWN_SIZE];
324};
325
326struct ct_arg {
327 void *iocb;
328 u16 nport_handle;
329 dma_addr_t req_dma;
330 dma_addr_t rsp_dma;
331 u32 req_size;
332 u32 rsp_size;
333 void *req;
334 void *rsp;
335};
336
337
338
339
340struct srb_iocb {
341 union {
342 struct {
343 uint16_t flags;
344#define SRB_LOGIN_RETRIED BIT_0
345#define SRB_LOGIN_COND_PLOGI BIT_1
346#define SRB_LOGIN_SKIP_PRLI BIT_2
347#define SRB_LOGIN_NVME_PRLI BIT_3
348 uint16_t data[2];
349 u32 iop[2];
350 } logio;
351 struct {
352#define ELS_DCMD_TIMEOUT 20
353#define ELS_DCMD_LOGO 0x5
354 uint32_t flags;
355 uint32_t els_cmd;
356 struct completion comp;
357 struct els_logo_payload *els_logo_pyld;
358 dma_addr_t els_logo_pyld_dma;
359 } els_logo;
360 struct {
361
362
363
364
365
366 uint64_t lun;
367 uint32_t flags;
368 uint32_t data;
369 struct completion comp;
370 __le16 comp_status;
371 } tmf;
372 struct {
373#define SRB_FXDISC_REQ_DMA_VALID BIT_0
374#define SRB_FXDISC_RESP_DMA_VALID BIT_1
375#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
376#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
377#define FXDISC_TIMEOUT 20
378 uint8_t flags;
379 uint32_t req_len;
380 uint32_t rsp_len;
381 void *req_addr;
382 void *rsp_addr;
383 dma_addr_t req_dma_handle;
384 dma_addr_t rsp_dma_handle;
385 __le32 adapter_id;
386 __le32 adapter_id_hi;
387 __le16 req_func_type;
388 __le32 req_data;
389 __le32 req_data_extra;
390 __le32 result;
391 __le32 seq_number;
392 __le16 fw_flags;
393 struct completion fxiocb_comp;
394 __le32 reserved_0;
395 uint8_t reserved_1;
396 } fxiocb;
397 struct {
398 uint32_t cmd_hndl;
399 __le16 comp_status;
400 struct completion comp;
401 } abt;
402 struct ct_arg ctarg;
403#define MAX_IOCB_MB_REG 28
404#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
405 struct {
406 __le16 in_mb[MAX_IOCB_MB_REG];
407 __le16 out_mb[MAX_IOCB_MB_REG];
408 void *out, *in;
409 dma_addr_t out_dma, in_dma;
410 struct completion comp;
411 int rc;
412 } mbx;
413 struct {
414 struct imm_ntfy_from_isp *ntfy;
415 } nack;
416 struct {
417 __le16 comp_status;
418 uint16_t rsp_pyld_len;
419 uint8_t aen_op;
420 void *desc;
421
422
423 int cmd_len;
424 int rsp_len;
425 dma_addr_t cmd_dma;
426 dma_addr_t rsp_dma;
427 enum nvmefc_fcp_datadir dir;
428 uint32_t dl;
429 uint32_t timeout_sec;
430 struct list_head entry;
431 } nvme;
432 } u;
433
434 struct timer_list timer;
435 void (*timeout)(void *);
436};
437
438
439#define SRB_LOGIN_CMD 1
440#define SRB_LOGOUT_CMD 2
441#define SRB_ELS_CMD_RPT 3
442#define SRB_ELS_CMD_HST 4
443#define SRB_CT_CMD 5
444#define SRB_ADISC_CMD 6
445#define SRB_TM_CMD 7
446#define SRB_SCSI_CMD 8
447#define SRB_BIDI_CMD 9
448#define SRB_FXIOCB_DCMD 10
449#define SRB_FXIOCB_BCMD 11
450#define SRB_ABT_CMD 12
451#define SRB_ELS_DCMD 13
452#define SRB_MB_IOCB 14
453#define SRB_CT_PTHRU_CMD 15
454#define SRB_NACK_PLOGI 16
455#define SRB_NACK_PRLI 17
456#define SRB_NACK_LOGO 18
457#define SRB_NVME_CMD 19
458#define SRB_NVME_LS 20
459#define SRB_PRLI_CMD 21
460
461enum {
462 TYPE_SRB,
463 TYPE_TGT_CMD,
464};
465
466typedef struct srb {
467
468
469
470
471 uint8_t cmd_type;
472 uint8_t pad[3];
473 atomic_t ref_count;
474 wait_queue_head_t nvme_ls_waitq;
475 struct fc_port *fcport;
476 struct scsi_qla_host *vha;
477 uint32_t handle;
478 uint16_t flags;
479 uint16_t type;
480 const char *name;
481 int iocbs;
482 struct qla_qpair *qpair;
483 u32 gen1;
484 u32 gen2;
485 union {
486 struct srb_iocb iocb_cmd;
487 struct bsg_job *bsg_job;
488 struct srb_cmd scmd;
489 } u;
490 void (*done)(void *, int);
491 void (*free)(void *);
492} srb_t;
493
494#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
495#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
496#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
497
498#define GET_CMD_SENSE_LEN(sp) \
499 (sp->u.scmd.request_sense_length)
500#define SET_CMD_SENSE_LEN(sp, len) \
501 (sp->u.scmd.request_sense_length = len)
502#define GET_CMD_SENSE_PTR(sp) \
503 (sp->u.scmd.request_sense_ptr)
504#define SET_CMD_SENSE_PTR(sp, ptr) \
505 (sp->u.scmd.request_sense_ptr = ptr)
506#define GET_FW_SENSE_LEN(sp) \
507 (sp->u.scmd.fw_sense_length)
508#define SET_FW_SENSE_LEN(sp, len) \
509 (sp->u.scmd.fw_sense_length = len)
510
511struct msg_echo_lb {
512 dma_addr_t send_dma;
513 dma_addr_t rcv_dma;
514 uint16_t req_sg_cnt;
515 uint16_t rsp_sg_cnt;
516 uint16_t options;
517 uint32_t transfer_size;
518 uint32_t iteration_count;
519};
520
521
522
523
524struct device_reg_2xxx {
525 uint16_t flash_address;
526 uint16_t flash_data;
527 uint16_t unused_1[1];
528 uint16_t ctrl_status;
529#define CSR_FLASH_64K_BANK BIT_3
530#define CSR_FLASH_ENABLE BIT_1
531#define CSR_ISP_SOFT_RESET BIT_0
532
533 uint16_t ictrl;
534#define ICR_EN_INT BIT_15
535#define ICR_EN_RISC BIT_3
536
537 uint16_t istatus;
538#define ISR_RISC_INT BIT_3
539
540 uint16_t semaphore;
541 uint16_t nvram;
542#define NVR_DESELECT 0
543#define NVR_BUSY BIT_15
544#define NVR_WRT_ENABLE BIT_14
545#define NVR_PR_ENABLE BIT_13
546#define NVR_DATA_IN BIT_3
547#define NVR_DATA_OUT BIT_2
548#define NVR_SELECT BIT_1
549#define NVR_CLOCK BIT_0
550
551#define NVR_WAIT_CNT 20000
552
553 union {
554 struct {
555 uint16_t mailbox0;
556 uint16_t mailbox1;
557 uint16_t mailbox2;
558 uint16_t mailbox3;
559 uint16_t mailbox4;
560 uint16_t mailbox5;
561 uint16_t mailbox6;
562 uint16_t mailbox7;
563 uint16_t unused_2[59];
564 } __attribute__((packed)) isp2100;
565 struct {
566
567 uint16_t req_q_in;
568 uint16_t req_q_out;
569
570 uint16_t rsp_q_in;
571 uint16_t rsp_q_out;
572
573
574 uint32_t host_status;
575#define HSR_RISC_INT BIT_15
576#define HSR_RISC_PAUSED BIT_8
577
578
579 uint16_t host_semaphore;
580 uint16_t unused_3[17];
581 uint16_t mailbox0;
582 uint16_t mailbox1;
583 uint16_t mailbox2;
584 uint16_t mailbox3;
585 uint16_t mailbox4;
586 uint16_t mailbox5;
587 uint16_t mailbox6;
588 uint16_t mailbox7;
589 uint16_t mailbox8;
590 uint16_t mailbox9;
591 uint16_t mailbox10;
592 uint16_t mailbox11;
593 uint16_t mailbox12;
594 uint16_t mailbox13;
595 uint16_t mailbox14;
596 uint16_t mailbox15;
597 uint16_t mailbox16;
598 uint16_t mailbox17;
599 uint16_t mailbox18;
600 uint16_t mailbox19;
601 uint16_t mailbox20;
602 uint16_t mailbox21;
603 uint16_t mailbox22;
604 uint16_t mailbox23;
605 uint16_t mailbox24;
606 uint16_t mailbox25;
607 uint16_t mailbox26;
608 uint16_t mailbox27;
609 uint16_t mailbox28;
610 uint16_t mailbox29;
611 uint16_t mailbox30;
612 uint16_t mailbox31;
613 uint16_t fb_cmd;
614 uint16_t unused_4[10];
615 } __attribute__((packed)) isp2300;
616 } u;
617
618 uint16_t fpm_diag_config;
619 uint16_t unused_5[0x4];
620 uint16_t risc_hw;
621 uint16_t unused_5_1;
622 uint16_t pcr;
623 uint16_t unused_6[0x5];
624 uint16_t mctr;
625 uint16_t unused_7[0x3];
626 uint16_t fb_cmd_2100;
627 uint16_t unused_8[0x3];
628 uint16_t hccr;
629#define HCCR_HOST_INT BIT_7
630#define HCCR_RISC_PAUSE BIT_5
631
632#define HCCR_RESET_RISC 0x1000
633#define HCCR_PAUSE_RISC 0x2000
634#define HCCR_RELEASE_RISC 0x3000
635#define HCCR_SET_HOST_INT 0x5000
636#define HCCR_CLR_HOST_INT 0x6000
637#define HCCR_CLR_RISC_INT 0x7000
638#define HCCR_DISABLE_PARITY_PAUSE 0x4001
639#define HCCR_ENABLE_PARITY 0xA000
640
641 uint16_t unused_9[5];
642 uint16_t gpiod;
643 uint16_t gpioe;
644#define GPIO_LED_MASK 0x00C0
645#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
646#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
647#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
648#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
649#define GPIO_LED_ALL_OFF 0x0000
650#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
651#define GPIO_LED_RGA_ON 0x00C1
652
653 union {
654 struct {
655 uint16_t unused_10[8];
656 uint16_t mailbox8;
657 uint16_t mailbox9;
658 uint16_t mailbox10;
659 uint16_t mailbox11;
660 uint16_t mailbox12;
661 uint16_t mailbox13;
662 uint16_t mailbox14;
663 uint16_t mailbox15;
664 uint16_t mailbox16;
665 uint16_t mailbox17;
666 uint16_t mailbox18;
667 uint16_t mailbox19;
668 uint16_t mailbox20;
669 uint16_t mailbox21;
670 uint16_t mailbox22;
671 uint16_t mailbox23;
672 } __attribute__((packed)) isp2200;
673 } u_end;
674};
675
676struct device_reg_25xxmq {
677 uint32_t req_q_in;
678 uint32_t req_q_out;
679 uint32_t rsp_q_in;
680 uint32_t rsp_q_out;
681 uint32_t atio_q_in;
682 uint32_t atio_q_out;
683};
684
685
686struct device_reg_fx00 {
687 uint32_t mailbox0;
688 uint32_t mailbox1;
689 uint32_t mailbox2;
690 uint32_t mailbox3;
691 uint32_t mailbox4;
692 uint32_t mailbox5;
693 uint32_t mailbox6;
694 uint32_t mailbox7;
695 uint32_t mailbox8;
696 uint32_t mailbox9;
697 uint32_t mailbox10;
698 uint32_t mailbox11;
699 uint32_t mailbox12;
700 uint32_t mailbox13;
701 uint32_t mailbox14;
702 uint32_t mailbox15;
703 uint32_t mailbox16;
704 uint32_t mailbox17;
705 uint32_t mailbox18;
706 uint32_t mailbox19;
707 uint32_t mailbox20;
708 uint32_t mailbox21;
709 uint32_t mailbox22;
710 uint32_t mailbox23;
711 uint32_t mailbox24;
712 uint32_t mailbox25;
713 uint32_t mailbox26;
714 uint32_t mailbox27;
715 uint32_t mailbox28;
716 uint32_t mailbox29;
717 uint32_t mailbox30;
718 uint32_t mailbox31;
719 uint32_t aenmailbox0;
720 uint32_t aenmailbox1;
721 uint32_t aenmailbox2;
722 uint32_t aenmailbox3;
723 uint32_t aenmailbox4;
724 uint32_t aenmailbox5;
725 uint32_t aenmailbox6;
726 uint32_t aenmailbox7;
727
728 uint32_t req_q_in;
729 uint32_t req_q_out;
730
731 uint32_t rsp_q_in;
732 uint32_t rsp_q_out;
733
734 uint32_t initval0;
735 uint32_t initval1;
736 uint32_t initval2;
737 uint32_t initval3;
738 uint32_t initval4;
739 uint32_t initval5;
740 uint32_t initval6;
741 uint32_t initval7;
742 uint32_t fwheartbeat;
743 uint32_t pseudoaen;
744};
745
746
747
748typedef union {
749 struct device_reg_2xxx isp;
750 struct device_reg_24xx isp24;
751 struct device_reg_25xxmq isp25mq;
752 struct device_reg_82xx isp82;
753 struct device_reg_fx00 ispfx00;
754} __iomem device_reg_t;
755
756#define ISP_REQ_Q_IN(ha, reg) \
757 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
758 &(reg)->u.isp2100.mailbox4 : \
759 &(reg)->u.isp2300.req_q_in)
760#define ISP_REQ_Q_OUT(ha, reg) \
761 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
762 &(reg)->u.isp2100.mailbox4 : \
763 &(reg)->u.isp2300.req_q_out)
764#define ISP_RSP_Q_IN(ha, reg) \
765 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
766 &(reg)->u.isp2100.mailbox5 : \
767 &(reg)->u.isp2300.rsp_q_in)
768#define ISP_RSP_Q_OUT(ha, reg) \
769 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
770 &(reg)->u.isp2100.mailbox5 : \
771 &(reg)->u.isp2300.rsp_q_out)
772
773#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
774#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
775
776#define MAILBOX_REG(ha, reg, num) \
777 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
778 (num < 8 ? \
779 &(reg)->u.isp2100.mailbox0 + (num) : \
780 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
781 &(reg)->u.isp2300.mailbox0 + (num))
782#define RD_MAILBOX_REG(ha, reg, num) \
783 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
784#define WRT_MAILBOX_REG(ha, reg, num, data) \
785 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
786
787#define FB_CMD_REG(ha, reg) \
788 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
789 &(reg)->fb_cmd_2100 : \
790 &(reg)->u.isp2300.fb_cmd)
791#define RD_FB_CMD_REG(ha, reg) \
792 RD_REG_WORD(FB_CMD_REG(ha, reg))
793#define WRT_FB_CMD_REG(ha, reg, data) \
794 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
795
796typedef struct {
797 uint32_t out_mb;
798 uint32_t in_mb;
799 uint16_t mb[MAILBOX_REGISTER_COUNT];
800 long buf_size;
801 void *bufp;
802 uint32_t tov;
803 uint8_t flags;
804#define MBX_DMA_IN BIT_0
805#define MBX_DMA_OUT BIT_1
806#define IOCTL_CMD BIT_2
807} mbx_cmd_t;
808
809struct mbx_cmd_32 {
810 uint32_t out_mb;
811 uint32_t in_mb;
812 uint32_t mb[MAILBOX_REGISTER_COUNT];
813 long buf_size;
814 void *bufp;
815 uint32_t tov;
816 uint8_t flags;
817#define MBX_DMA_IN BIT_0
818#define MBX_DMA_OUT BIT_1
819#define IOCTL_CMD BIT_2
820};
821
822
823#define MBX_TOV_SECONDS 30
824
825
826
827
828#define PROD_ID_1 0x4953
829#define PROD_ID_2 0x0000
830#define PROD_ID_2a 0x5020
831#define PROD_ID_3 0x2020
832
833
834
835
836#define MBS_FRM_ALIVE 0
837#define MBS_CHKSUM_ERR 1
838#define MBS_BUSY 4
839
840
841
842
843#define MBS_COMMAND_COMPLETE 0x4000
844#define MBS_INVALID_COMMAND 0x4001
845#define MBS_HOST_INTERFACE_ERROR 0x4002
846#define MBS_TEST_FAILED 0x4003
847#define MBS_COMMAND_ERROR 0x4005
848#define MBS_COMMAND_PARAMETER_ERROR 0x4006
849#define MBS_PORT_ID_USED 0x4007
850#define MBS_LOOP_ID_USED 0x4008
851#define MBS_ALL_IDS_IN_USE 0x4009
852#define MBS_NOT_LOGGED_IN 0x400A
853#define MBS_LINK_DOWN_ERROR 0x400B
854#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
855
856
857
858
859#define MBA_ASYNC_EVENT 0x8000
860#define MBA_RESET 0x8001
861#define MBA_SYSTEM_ERR 0x8002
862#define MBA_REQ_TRANSFER_ERR 0x8003
863#define MBA_RSP_TRANSFER_ERR 0x8004
864#define MBA_WAKEUP_THRES 0x8005
865#define MBA_LIP_OCCURRED 0x8010
866
867#define MBA_LOOP_UP 0x8011
868#define MBA_LOOP_DOWN 0x8012
869#define MBA_LIP_RESET 0x8013
870#define MBA_PORT_UPDATE 0x8014
871#define MBA_RSCN_UPDATE 0x8015
872#define MBA_LIP_F8 0x8016
873#define MBA_LOOP_INIT_ERR 0x8017
874#define MBA_FABRIC_AUTH_REQ 0x801b
875#define MBA_SCSI_COMPLETION 0x8020
876#define MBA_CTIO_COMPLETION 0x8021
877#define MBA_IP_COMPLETION 0x8022
878#define MBA_IP_RECEIVE 0x8023
879#define MBA_IP_BROADCAST 0x8024
880#define MBA_IP_LOW_WATER_MARK 0x8025
881#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
882#define MBA_IP_HDR_DATA_SPLIT 0x8027
883
884#define MBA_TRACE_NOTIFICATION 0x8028
885#define MBA_POINT_TO_POINT 0x8030
886#define MBA_CMPLT_1_16BIT 0x8031
887#define MBA_CMPLT_2_16BIT 0x8032
888#define MBA_CMPLT_3_16BIT 0x8033
889#define MBA_CMPLT_4_16BIT 0x8034
890#define MBA_CMPLT_5_16BIT 0x8035
891#define MBA_CHG_IN_CONNECTION 0x8036
892#define MBA_RIO_RESPONSE 0x8040
893#define MBA_ZIO_RESPONSE 0x8040
894#define MBA_CMPLT_2_32BIT 0x8042
895#define MBA_BYPASS_NOTIFICATION 0x8043
896#define MBA_DISCARD_RND_FRAME 0x8048
897#define MBA_REJECTED_FCP_CMD 0x8049
898#define MBA_FW_NOT_STARTED 0x8050
899#define MBA_FW_STARTING 0x8051
900#define MBA_FW_RESTART_CMPLT 0x8060
901#define MBA_INIT_REQUIRED 0x8061
902#define MBA_SHUTDOWN_REQUESTED 0x8062
903#define MBA_TEMPERATURE_ALERT 0x8070
904#define MBA_DPORT_DIAGNOSTICS 0x8080
905#define MBA_TRANS_INSERT 0x8130
906#define MBA_FW_INIT_FAILURE 0x8401
907#define MBA_MIRROR_LUN_CHANGE 0x8402
908
909#define MBA_FW_POLL_STATE 0x8600
910#define MBA_FW_RESET_FCT 0x8502
911#define MBA_FW_INIT_INPROGRESS 0x8500
912
913#define MBA_IDC_AEN 0x8200
914
915
916#define INTR_ROM_MB_SUCCESS 0x1
917#define INTR_ROM_MB_FAILED 0x2
918#define INTR_MB_SUCCESS 0x10
919#define INTR_MB_FAILED 0x11
920#define INTR_ASYNC_EVENT 0x12
921#define INTR_RSP_QUE_UPDATE 0x13
922#define INTR_RSP_QUE_UPDATE_83XX 0x14
923#define INTR_ATIO_QUE_UPDATE 0x1C
924#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
925
926
927#define MBS_LB_RESET 0x17
928
929
930
931#define FO1_AE_ON_LIPF8 BIT_0
932#define FO1_AE_ALL_LIP_RESET BIT_1
933#define FO1_CTIO_RETRY BIT_3
934#define FO1_DISABLE_LIP_F7_SW BIT_4
935#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
936#define FO1_DISABLE_GPIO6_7 BIT_6
937#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
938#define FO1_SET_EMPHASIS_SWING BIT_8
939#define FO1_AE_AUTO_BYPASS BIT_9
940#define FO1_ENABLE_PURE_IOCB BIT_10
941#define FO1_AE_PLOGI_RJT BIT_11
942#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
943#define FO1_AE_QUEUE_FULL BIT_13
944
945#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
946#define FO2_REV_LOOPBACK BIT_1
947
948#define FO3_ENABLE_EMERG_IOCB BIT_0
949#define FO3_AE_RND_ERROR BIT_1
950
951
952#define ADD_FO_COUNT 3
953#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
954#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
955
956#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
957
958#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
959
960
961
962
963#define MBC_LOAD_RAM 1
964#define MBC_EXECUTE_FIRMWARE 2
965#define MBC_READ_RAM_WORD 5
966#define MBC_MAILBOX_REGISTER_TEST 6
967#define MBC_VERIFY_CHECKSUM 7
968#define MBC_GET_FIRMWARE_VERSION 8
969#define MBC_LOAD_RISC_RAM 9
970#define MBC_DUMP_RISC_RAM 0xa
971#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
972#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
973#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
974#define MBC_READ_RAM_EXTENDED 0xf
975#define MBC_IOCB_COMMAND 0x12
976#define MBC_STOP_FIRMWARE 0x14
977#define MBC_ABORT_COMMAND 0x15
978#define MBC_ABORT_DEVICE 0x16
979#define MBC_ABORT_TARGET 0x17
980#define MBC_RESET 0x18
981#define MBC_GET_ADAPTER_LOOP_ID 0x20
982#define MBC_GET_SET_ZIO_THRESHOLD 0x21
983#define MBC_GET_RETRY_COUNT 0x22
984#define MBC_DISABLE_VI 0x24
985#define MBC_ENABLE_VI 0x25
986#define MBC_GET_FIRMWARE_OPTION 0x28
987#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
988#define MBC_SET_FIRMWARE_OPTION 0x38
989#define MBC_LOOP_PORT_BYPASS 0x40
990#define MBC_LOOP_PORT_ENABLE 0x41
991#define MBC_GET_RESOURCE_COUNTS 0x42
992#define MBC_NON_PARTICIPATE 0x43
993#define MBC_DIAGNOSTIC_ECHO 0x44
994#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
995#define MBC_ONLINE_SELF_TEST 0x46
996#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
997#define MBC_CONFIGURE_VF 0x4b
998#define MBC_RESET_LINK_STATUS 0x52
999#define MBC_IOCB_COMMAND_A64 0x54
1000#define MBC_PORT_LOGOUT 0x56
1001#define MBC_SEND_RNID_ELS 0x57
1002#define MBC_SET_RNID_PARAMS 0x59
1003#define MBC_GET_RNID_PARAMS 0x5a
1004#define MBC_DATA_RATE 0x5d
1005#define MBC_INITIALIZE_FIRMWARE 0x60
1006#define MBC_INITIATE_LIP 0x62
1007
1008#define MBC_GET_FC_AL_POSITION_MAP 0x63
1009#define MBC_GET_PORT_DATABASE 0x64
1010#define MBC_CLEAR_ACA 0x65
1011#define MBC_TARGET_RESET 0x66
1012#define MBC_CLEAR_TASK_SET 0x67
1013#define MBC_ABORT_TASK_SET 0x68
1014#define MBC_GET_FIRMWARE_STATE 0x69
1015#define MBC_GET_PORT_NAME 0x6a
1016#define MBC_GET_LINK_STATUS 0x6b
1017#define MBC_LIP_RESET 0x6c
1018#define MBC_SEND_SNS_COMMAND 0x6e
1019
1020#define MBC_LOGIN_FABRIC_PORT 0x6f
1021#define MBC_SEND_CHANGE_REQUEST 0x70
1022#define MBC_LOGOUT_FABRIC_PORT 0x71
1023#define MBC_LIP_FULL_LOGIN 0x72
1024#define MBC_LOGIN_LOOP_PORT 0x74
1025#define MBC_PORT_NODE_NAME_LIST 0x75
1026#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1027#define MBC_UNLOAD_IP 0x79
1028#define MBC_GET_ID_LIST 0x7C
1029#define MBC_SEND_LFA_COMMAND 0x7D
1030#define MBC_LUN_RESET 0x7E
1031
1032
1033
1034
1035
1036#define MBC_MR_DRV_SHUTDOWN 0x6A
1037
1038
1039
1040
1041#define MBC_WRITE_SERDES 0x3
1042#define MBC_READ_SERDES 0x4
1043#define MBC_LOAD_DUMP_MPI_RAM 0x5
1044#define MBC_SERDES_PARAMS 0x10
1045#define MBC_GET_IOCB_STATUS 0x12
1046#define MBC_PORT_PARAMS 0x1A
1047#define MBC_GET_TIMEOUT_PARAMS 0x22
1048#define MBC_TRACE_CONTROL 0x27
1049#define MBC_GEN_SYSTEM_ERROR 0x2a
1050#define MBC_WRITE_SFP 0x30
1051#define MBC_READ_SFP 0x31
1052#define MBC_SET_TIMEOUT_PARAMS 0x32
1053#define MBC_DPORT_DIAGNOSTICS 0x47
1054#define MBC_MID_INITIALIZE_FIRMWARE 0x48
1055#define MBC_MID_GET_VP_DATABASE 0x49
1056#define MBC_MID_GET_VP_ENTRY 0x4a
1057#define MBC_HOST_MEMORY_COPY 0x53
1058#define MBC_SEND_RNFT_ELS 0x5e
1059#define MBC_GET_LINK_PRIV_STATS 0x6d
1060#define MBC_LINK_INITIALIZATION 0x72
1061#define MBC_SET_VENDOR_ID 0x76
1062#define MBC_PORT_RESET 0x120
1063#define MBC_SET_PORT_CONFIG 0x122
1064#define MBC_GET_PORT_CONFIG 0x123
1065
1066
1067
1068
1069#define MBC_WRITE_MPI_REGISTER 0x01
1070
1071
1072
1073
1074#define MBC_SET_GET_ETH_SERDES_REG 0x150
1075#define HCS_WRITE_SERDES 0x3
1076#define HCS_READ_SERDES 0x4
1077
1078
1079#define FCAL_MAP_SIZE 128
1080
1081
1082#define MBX_31 BIT_31
1083#define MBX_30 BIT_30
1084#define MBX_29 BIT_29
1085#define MBX_28 BIT_28
1086#define MBX_27 BIT_27
1087#define MBX_26 BIT_26
1088#define MBX_25 BIT_25
1089#define MBX_24 BIT_24
1090#define MBX_23 BIT_23
1091#define MBX_22 BIT_22
1092#define MBX_21 BIT_21
1093#define MBX_20 BIT_20
1094#define MBX_19 BIT_19
1095#define MBX_18 BIT_18
1096#define MBX_17 BIT_17
1097#define MBX_16 BIT_16
1098#define MBX_15 BIT_15
1099#define MBX_14 BIT_14
1100#define MBX_13 BIT_13
1101#define MBX_12 BIT_12
1102#define MBX_11 BIT_11
1103#define MBX_10 BIT_10
1104#define MBX_9 BIT_9
1105#define MBX_8 BIT_8
1106#define MBX_7 BIT_7
1107#define MBX_6 BIT_6
1108#define MBX_5 BIT_5
1109#define MBX_4 BIT_4
1110#define MBX_3 BIT_3
1111#define MBX_2 BIT_2
1112#define MBX_1 BIT_1
1113#define MBX_0 BIT_0
1114
1115#define RNID_TYPE_PORT_LOGIN 0x7
1116#define RNID_TYPE_SET_VERSION 0x9
1117#define RNID_TYPE_ASIC_TEMP 0xC
1118
1119
1120
1121
1122#define FSTATE_CONFIG_WAIT 0
1123#define FSTATE_WAIT_AL_PA 1
1124#define FSTATE_WAIT_LOGIN 2
1125#define FSTATE_READY 3
1126#define FSTATE_LOSS_OF_SYNC 4
1127#define FSTATE_ERROR 5
1128#define FSTATE_REINIT 6
1129#define FSTATE_NON_PART 7
1130
1131#define FSTATE_CONFIG_CORRECT 0
1132#define FSTATE_P2P_RCV_LIP 1
1133#define FSTATE_P2P_CHOOSE_LOOP 2
1134#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1135#define FSTATE_FATAL_ERROR 4
1136#define FSTATE_LOOP_BACK_CONN 5
1137
1138#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1139#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1140#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1141#define QLA27XX_PRIMARY_IMAGE 1
1142#define QLA27XX_SECONDARY_IMAGE 2
1143
1144
1145
1146
1147
1148#define PORT_DATABASE_SIZE 128
1149typedef struct {
1150 uint8_t options;
1151 uint8_t control;
1152 uint8_t master_state;
1153 uint8_t slave_state;
1154 uint8_t reserved[2];
1155 uint8_t hard_address;
1156 uint8_t reserved_1;
1157 uint8_t port_id[4];
1158 uint8_t node_name[WWN_SIZE];
1159 uint8_t port_name[WWN_SIZE];
1160 uint16_t execution_throttle;
1161 uint16_t execution_count;
1162 uint8_t reset_count;
1163 uint8_t reserved_2;
1164 uint16_t resource_allocation;
1165 uint16_t current_allocation;
1166 uint16_t queue_head;
1167 uint16_t queue_tail;
1168 uint16_t transmit_execution_list_next;
1169 uint16_t transmit_execution_list_previous;
1170 uint16_t common_features;
1171 uint16_t total_concurrent_sequences;
1172 uint16_t RO_by_information_category;
1173 uint8_t recipient;
1174 uint8_t initiator;
1175 uint16_t receive_data_size;
1176 uint16_t concurrent_sequences;
1177 uint16_t open_sequences_per_exchange;
1178 uint16_t lun_abort_flags;
1179 uint16_t lun_stop_flags;
1180 uint16_t stop_queue_head;
1181 uint16_t stop_queue_tail;
1182 uint16_t port_retry_timer;
1183 uint16_t next_sequence_id;
1184 uint16_t frame_count;
1185 uint16_t PRLI_payload_length;
1186 uint8_t prli_svc_param_word_0[2];
1187
1188 uint8_t prli_svc_param_word_3[2];
1189
1190 uint16_t loop_id;
1191 uint16_t extended_lun_info_list_pointer;
1192 uint16_t extended_lun_stop_list_pointer;
1193} port_database_t;
1194
1195
1196
1197
1198#define PD_STATE_DISCOVERY 0
1199#define PD_STATE_WAIT_DISCOVERY_ACK 1
1200#define PD_STATE_PORT_LOGIN 2
1201#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1202#define PD_STATE_PROCESS_LOGIN 4
1203#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1204#define PD_STATE_PORT_LOGGED_IN 6
1205#define PD_STATE_PORT_UNAVAILABLE 7
1206#define PD_STATE_PROCESS_LOGOUT 8
1207#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1208#define PD_STATE_PORT_LOGOUT 10
1209#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1210
1211
1212#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1213#define QLA_ZIO_DISABLED 0
1214#define QLA_ZIO_DEFAULT_TIMER 2
1215
1216
1217
1218
1219
1220#define ICB_VERSION 1
1221typedef struct {
1222 uint8_t version;
1223 uint8_t reserved_1;
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244 uint8_t firmware_options[2];
1245
1246 uint16_t frame_payload_size;
1247 uint16_t max_iocb_allocation;
1248 uint16_t execution_throttle;
1249 uint8_t retry_count;
1250 uint8_t retry_delay;
1251 uint8_t port_name[WWN_SIZE];
1252 uint16_t hard_address;
1253 uint8_t inquiry_data;
1254 uint8_t login_timeout;
1255 uint8_t node_name[WWN_SIZE];
1256
1257 uint16_t request_q_outpointer;
1258 uint16_t response_q_inpointer;
1259 uint16_t request_q_length;
1260 uint16_t response_q_length;
1261 uint32_t request_q_address[2];
1262 uint32_t response_q_address[2];
1263
1264 uint16_t lun_enables;
1265 uint8_t command_resource_count;
1266 uint8_t immediate_notify_resource_count;
1267 uint16_t timeout;
1268 uint8_t reserved_2[2];
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289 uint8_t add_firmware_options[2];
1290
1291 uint8_t response_accumulation_timer;
1292 uint8_t interrupt_delay_timer;
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313 uint8_t special_options[2];
1314
1315 uint8_t reserved_3[26];
1316} init_cb_t;
1317
1318
1319
1320
1321#define GLSO_SEND_RPS BIT_0
1322#define GLSO_USE_DID BIT_3
1323
1324struct link_statistics {
1325 uint32_t link_fail_cnt;
1326 uint32_t loss_sync_cnt;
1327 uint32_t loss_sig_cnt;
1328 uint32_t prim_seq_err_cnt;
1329 uint32_t inval_xmit_word_cnt;
1330 uint32_t inval_crc_cnt;
1331 uint32_t lip_cnt;
1332 uint32_t link_up_cnt;
1333 uint32_t link_down_loop_init_tmo;
1334 uint32_t link_down_los;
1335 uint32_t link_down_loss_rcv_clk;
1336 uint32_t reserved0[5];
1337 uint32_t port_cfg_chg;
1338 uint32_t reserved1[11];
1339 uint32_t rsp_q_full;
1340 uint32_t atio_q_full;
1341 uint32_t drop_ae;
1342 uint32_t els_proto_err;
1343 uint32_t reserved2;
1344 uint32_t tx_frames;
1345 uint32_t rx_frames;
1346 uint32_t discarded_frames;
1347 uint32_t dropped_frames;
1348 uint32_t reserved3;
1349 uint32_t nos_rcvd;
1350 uint32_t reserved4[4];
1351 uint32_t tx_prjt;
1352 uint32_t rcv_exfail;
1353 uint32_t rcv_abts;
1354 uint32_t seq_frm_miss;
1355 uint32_t corr_err;
1356 uint32_t mb_rqst;
1357 uint32_t nport_full;
1358 uint32_t eofa;
1359 uint32_t reserved5;
1360 uint32_t fpm_recv_word_cnt_lo;
1361 uint32_t fpm_recv_word_cnt_hi;
1362 uint32_t fpm_disc_word_cnt_lo;
1363 uint32_t fpm_disc_word_cnt_hi;
1364 uint32_t fpm_xmit_word_cnt_lo;
1365 uint32_t fpm_xmit_word_cnt_hi;
1366 uint32_t reserved6[70];
1367};
1368
1369
1370
1371
1372#define NV_START_BIT BIT_2
1373#define NV_WRITE_OP (BIT_26+BIT_24)
1374#define NV_READ_OP (BIT_26+BIT_25)
1375#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1376#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1377#define NV_DELAY_COUNT 10
1378
1379
1380
1381
1382typedef struct {
1383
1384
1385
1386 uint8_t id[4];
1387 uint8_t nvram_version;
1388 uint8_t reserved_0;
1389
1390
1391
1392
1393 uint8_t parameter_block_version;
1394 uint8_t reserved_1;
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415 uint8_t firmware_options[2];
1416
1417 uint16_t frame_payload_size;
1418 uint16_t max_iocb_allocation;
1419 uint16_t execution_throttle;
1420 uint8_t retry_count;
1421 uint8_t retry_delay;
1422 uint8_t port_name[WWN_SIZE];
1423 uint16_t hard_address;
1424 uint8_t inquiry_data;
1425 uint8_t login_timeout;
1426 uint8_t node_name[WWN_SIZE];
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447 uint8_t add_firmware_options[2];
1448
1449 uint8_t response_accumulation_timer;
1450 uint8_t interrupt_delay_timer;
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471 uint8_t special_options[2];
1472
1473
1474 uint8_t reserved_2[22];
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513 uint8_t seriallink_options[4];
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536 uint8_t host_p[2];
1537
1538 uint8_t boot_node_name[WWN_SIZE];
1539 uint8_t boot_lun_number;
1540 uint8_t reset_delay;
1541 uint8_t port_down_retry_count;
1542 uint8_t boot_id_number;
1543 uint16_t max_luns_per_target;
1544 uint8_t fcode_boot_port_name[WWN_SIZE];
1545 uint8_t alternate_port_name[WWN_SIZE];
1546 uint8_t alternate_node_name[WWN_SIZE];
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558 uint8_t efi_parameters;
1559
1560 uint8_t link_down_timeout;
1561
1562 uint8_t adapter_id[16];
1563
1564 uint8_t alt1_boot_node_name[WWN_SIZE];
1565 uint16_t alt1_boot_lun_number;
1566 uint8_t alt2_boot_node_name[WWN_SIZE];
1567 uint16_t alt2_boot_lun_number;
1568 uint8_t alt3_boot_node_name[WWN_SIZE];
1569 uint16_t alt3_boot_lun_number;
1570 uint8_t alt4_boot_node_name[WWN_SIZE];
1571 uint16_t alt4_boot_lun_number;
1572 uint8_t alt5_boot_node_name[WWN_SIZE];
1573 uint16_t alt5_boot_lun_number;
1574 uint8_t alt6_boot_node_name[WWN_SIZE];
1575 uint16_t alt6_boot_lun_number;
1576 uint8_t alt7_boot_node_name[WWN_SIZE];
1577 uint16_t alt7_boot_lun_number;
1578
1579 uint8_t reserved_3[2];
1580
1581
1582 uint8_t model_number[16];
1583
1584
1585 uint8_t oem_specific[16];
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608 uint8_t adapter_features[2];
1609
1610 uint8_t reserved_4[16];
1611
1612
1613 uint16_t subsystem_vendor_id_2200;
1614
1615
1616 uint16_t subsystem_device_id_2200;
1617
1618 uint8_t reserved_5;
1619 uint8_t checksum;
1620} nvram_t;
1621
1622
1623
1624
1625typedef struct {
1626 uint8_t entry_type;
1627 uint8_t entry_count;
1628 uint8_t sys_define;
1629 uint8_t entry_status;
1630 uint32_t handle;
1631 uint8_t data[52];
1632 uint32_t signature;
1633#define RESPONSE_PROCESSED 0xDEADDEAD
1634} response_t;
1635
1636
1637
1638
1639struct atio {
1640 uint8_t entry_type;
1641 uint8_t entry_count;
1642 __le16 attr_n_length;
1643 uint8_t data[56];
1644 uint32_t signature;
1645#define ATIO_PROCESSED 0xDEADDEAD
1646};
1647
1648typedef union {
1649 uint16_t extended;
1650 struct {
1651 uint8_t reserved;
1652 uint8_t standard;
1653 } id;
1654} target_id_t;
1655
1656#define SET_TARGET_ID(ha, to, from) \
1657do { \
1658 if (HAS_EXTENDED_IDS(ha)) \
1659 to.extended = cpu_to_le16(from); \
1660 else \
1661 to.id.standard = (uint8_t)from; \
1662} while (0)
1663
1664
1665
1666
1667#define COMMAND_TYPE 0x11
1668typedef struct {
1669 uint8_t entry_type;
1670 uint8_t entry_count;
1671 uint8_t sys_define;
1672 uint8_t entry_status;
1673 uint32_t handle;
1674 target_id_t target;
1675 uint16_t lun;
1676 uint16_t control_flags;
1677#define CF_WRITE BIT_6
1678#define CF_READ BIT_5
1679#define CF_SIMPLE_TAG BIT_3
1680#define CF_ORDERED_TAG BIT_2
1681#define CF_HEAD_TAG BIT_1
1682 uint16_t reserved_1;
1683 uint16_t timeout;
1684 uint16_t dseg_count;
1685 uint8_t scsi_cdb[MAX_CMDSZ];
1686 uint32_t byte_count;
1687 uint32_t dseg_0_address;
1688 uint32_t dseg_0_length;
1689 uint32_t dseg_1_address;
1690 uint32_t dseg_1_length;
1691 uint32_t dseg_2_address;
1692 uint32_t dseg_2_length;
1693} cmd_entry_t;
1694
1695
1696
1697
1698#define COMMAND_A64_TYPE 0x19
1699typedef struct {
1700 uint8_t entry_type;
1701 uint8_t entry_count;
1702 uint8_t sys_define;
1703 uint8_t entry_status;
1704 uint32_t handle;
1705 target_id_t target;
1706 uint16_t lun;
1707 uint16_t control_flags;
1708 uint16_t reserved_1;
1709 uint16_t timeout;
1710 uint16_t dseg_count;
1711 uint8_t scsi_cdb[MAX_CMDSZ];
1712 uint32_t byte_count;
1713 uint32_t dseg_0_address[2];
1714 uint32_t dseg_0_length;
1715 uint32_t dseg_1_address[2];
1716 uint32_t dseg_1_length;
1717} cmd_a64_entry_t, request_t;
1718
1719
1720
1721
1722#define CONTINUE_TYPE 0x02
1723typedef struct {
1724 uint8_t entry_type;
1725 uint8_t entry_count;
1726 uint8_t sys_define;
1727 uint8_t entry_status;
1728 uint32_t reserved;
1729 uint32_t dseg_0_address;
1730 uint32_t dseg_0_length;
1731 uint32_t dseg_1_address;
1732 uint32_t dseg_1_length;
1733 uint32_t dseg_2_address;
1734 uint32_t dseg_2_length;
1735 uint32_t dseg_3_address;
1736 uint32_t dseg_3_length;
1737 uint32_t dseg_4_address;
1738 uint32_t dseg_4_length;
1739 uint32_t dseg_5_address;
1740 uint32_t dseg_5_length;
1741 uint32_t dseg_6_address;
1742 uint32_t dseg_6_length;
1743} cont_entry_t;
1744
1745
1746
1747
1748#define CONTINUE_A64_TYPE 0x0A
1749typedef struct {
1750 uint8_t entry_type;
1751 uint8_t entry_count;
1752 uint8_t sys_define;
1753 uint8_t entry_status;
1754 uint32_t dseg_0_address[2];
1755 uint32_t dseg_0_length;
1756 uint32_t dseg_1_address[2];
1757 uint32_t dseg_1_length;
1758 uint32_t dseg_2_address [2];
1759 uint32_t dseg_2_length;
1760 uint32_t dseg_3_address[2];
1761 uint32_t dseg_3_length;
1762 uint32_t dseg_4_address[2];
1763 uint32_t dseg_4_length;
1764} cont_a64_entry_t;
1765
1766#define PO_MODE_DIF_INSERT 0
1767#define PO_MODE_DIF_REMOVE 1
1768#define PO_MODE_DIF_PASS 2
1769#define PO_MODE_DIF_REPLACE 3
1770#define PO_MODE_DIF_TCP_CKSUM 6
1771#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1772#define PO_DISABLE_GUARD_CHECK BIT_4
1773#define PO_DISABLE_INCR_REF_TAG BIT_5
1774#define PO_DIS_HEADER_MODE BIT_7
1775#define PO_ENABLE_DIF_BUNDLING BIT_8
1776#define PO_DIS_FRAME_MODE BIT_9
1777#define PO_DIS_VALD_APP_ESC BIT_10
1778#define PO_DIS_VALD_APP_REF_ESC BIT_11
1779
1780#define PO_DIS_APP_TAG_REPL BIT_12
1781#define PO_DIS_REF_TAG_REPL BIT_13
1782#define PO_DIS_APP_TAG_VALD BIT_14
1783#define PO_DIS_REF_TAG_VALD BIT_15
1784
1785
1786
1787
1788struct crc_context {
1789 uint32_t handle;
1790 __le32 ref_tag;
1791 __le16 app_tag;
1792 uint8_t ref_tag_mask[4];
1793 uint8_t app_tag_mask[2];
1794 __le16 guard_seed;
1795 __le16 prot_opts;
1796 __le16 blk_size;
1797 uint16_t runt_blk_guard;
1798
1799 __le32 byte_count;
1800
1801 union {
1802 struct {
1803 uint32_t reserved_1;
1804 uint16_t reserved_2;
1805 uint16_t reserved_3;
1806 uint32_t reserved_4;
1807 uint32_t data_address[2];
1808 uint32_t data_length;
1809 uint32_t reserved_5[2];
1810 uint32_t reserved_6;
1811 } nobundling;
1812 struct {
1813 __le32 dif_byte_count;
1814
1815 uint16_t reserved_1;
1816 __le16 dseg_count;
1817 uint32_t reserved_2;
1818 uint32_t data_address[2];
1819 uint32_t data_length;
1820 uint32_t dif_address[2];
1821 uint32_t dif_length;
1822
1823 } bundling;
1824 } u;
1825
1826 struct fcp_cmnd fcp_cmnd;
1827 dma_addr_t crc_ctx_dma;
1828
1829 struct list_head dsd_list;
1830
1831
1832};
1833
1834#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1835#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1836
1837
1838
1839
1840#define STATUS_TYPE 0x03
1841typedef struct {
1842 uint8_t entry_type;
1843 uint8_t entry_count;
1844 uint8_t sys_define;
1845 uint8_t entry_status;
1846 uint32_t handle;
1847 uint16_t scsi_status;
1848 uint16_t comp_status;
1849 uint16_t state_flags;
1850 uint16_t status_flags;
1851 uint16_t rsp_info_len;
1852 uint16_t req_sense_length;
1853 uint32_t residual_length;
1854 uint8_t rsp_info[8];
1855 uint8_t req_sense_data[32];
1856} sts_entry_t;
1857
1858
1859
1860
1861#define RF_RQ_DMA_ERROR BIT_6
1862#define RF_INV_E_ORDER BIT_5
1863#define RF_INV_E_COUNT BIT_4
1864#define RF_INV_E_PARAM BIT_3
1865#define RF_INV_E_TYPE BIT_2
1866#define RF_BUSY BIT_1
1867#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1868 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1869#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1870 RF_INV_E_TYPE)
1871
1872
1873
1874
1875#define SS_MASK 0xfff
1876#define SS_RESIDUAL_UNDER BIT_11
1877#define SS_RESIDUAL_OVER BIT_10
1878#define SS_SENSE_LEN_VALID BIT_9
1879#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1880#define SS_SCSI_STATUS_BYTE 0xff
1881
1882#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1883#define SS_BUSY_CONDITION BIT_3
1884#define SS_CONDITION_MET BIT_2
1885#define SS_CHECK_CONDITION BIT_1
1886
1887
1888
1889
1890#define CS_COMPLETE 0x0
1891#define CS_INCOMPLETE 0x1
1892#define CS_DMA 0x2
1893#define CS_TRANSPORT 0x3
1894#define CS_RESET 0x4
1895#define CS_ABORTED 0x5
1896#define CS_TIMEOUT 0x6
1897#define CS_DATA_OVERRUN 0x7
1898#define CS_DIF_ERROR 0xC
1899
1900#define CS_DATA_UNDERRUN 0x15
1901#define CS_QUEUE_FULL 0x1C
1902#define CS_PORT_UNAVAILABLE 0x28
1903
1904#define CS_PORT_LOGGED_OUT 0x29
1905#define CS_PORT_CONFIG_CHG 0x2A
1906#define CS_PORT_BUSY 0x2B
1907#define CS_COMPLETE_CHKCOND 0x30
1908#define CS_IOCB_ERROR 0x31
1909
1910#define CS_BAD_PAYLOAD 0x80
1911#define CS_UNKNOWN 0x81
1912#define CS_RETRY 0x82
1913#define CS_LOOP_DOWN_ABORT 0x83
1914
1915#define CS_BIDIR_RD_OVERRUN 0x700
1916#define CS_BIDIR_RD_WR_OVERRUN 0x707
1917#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1918#define CS_BIDIR_RD_UNDERRUN 0x1500
1919#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1920#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1921#define CS_BIDIR_DMA 0x200
1922
1923
1924
1925#define SF_ABTS_TERMINATED BIT_10
1926#define SF_LOGOUT_SENT BIT_13
1927
1928
1929
1930
1931#define STATUS_CONT_TYPE 0x10
1932typedef struct {
1933 uint8_t entry_type;
1934 uint8_t entry_count;
1935 uint8_t sys_define;
1936 uint8_t entry_status;
1937 uint8_t data[60];
1938} sts_cont_entry_t;
1939
1940
1941
1942
1943
1944#define STATUS_TYPE_21 0x21
1945typedef struct {
1946 uint8_t entry_type;
1947 uint8_t entry_count;
1948 uint8_t handle_count;
1949 uint8_t entry_status;
1950 uint32_t handle[15];
1951} sts21_entry_t;
1952
1953
1954
1955
1956
1957#define STATUS_TYPE_22 0x22
1958typedef struct {
1959 uint8_t entry_type;
1960 uint8_t entry_count;
1961 uint8_t handle_count;
1962 uint8_t entry_status;
1963 uint16_t handle[30];
1964} sts22_entry_t;
1965
1966
1967
1968
1969#define MARKER_TYPE 0x04
1970typedef struct {
1971 uint8_t entry_type;
1972 uint8_t entry_count;
1973 uint8_t handle_count;
1974 uint8_t entry_status;
1975 uint32_t sys_define_2;
1976 target_id_t target;
1977 uint8_t modifier;
1978#define MK_SYNC_ID_LUN 0
1979#define MK_SYNC_ID 1
1980#define MK_SYNC_ALL 2
1981#define MK_SYNC_LIP 3
1982
1983
1984 uint8_t reserved_1;
1985 uint16_t sequence_number;
1986 uint16_t lun;
1987 uint8_t reserved_2[48];
1988} mrk_entry_t;
1989
1990
1991
1992
1993#define MS_IOCB_TYPE 0x29
1994typedef struct {
1995 uint8_t entry_type;
1996 uint8_t entry_count;
1997 uint8_t handle_count;
1998 uint8_t entry_status;
1999 uint32_t handle1;
2000 target_id_t loop_id;
2001 uint16_t status;
2002 uint16_t control_flags;
2003 uint16_t reserved2;
2004 uint16_t timeout;
2005 uint16_t cmd_dsd_count;
2006 uint16_t total_dsd_count;
2007 uint8_t type;
2008 uint8_t r_ctl;
2009 uint16_t rx_id;
2010 uint16_t reserved3;
2011 uint32_t handle2;
2012 uint32_t rsp_bytecount;
2013 uint32_t req_bytecount;
2014 uint32_t dseg_req_address[2];
2015 uint32_t dseg_req_length;
2016 uint32_t dseg_rsp_address[2];
2017 uint32_t dseg_rsp_length;
2018} ms_iocb_entry_t;
2019
2020
2021
2022
2023
2024#define MBX_IOCB_TYPE 0x39
2025struct mbx_entry {
2026 uint8_t entry_type;
2027 uint8_t entry_count;
2028 uint8_t sys_define1;
2029
2030#define SOURCE_SCSI 0x00
2031#define SOURCE_IP 0x01
2032#define SOURCE_VI 0x02
2033#define SOURCE_SCTP 0x03
2034#define SOURCE_MP 0x04
2035#define SOURCE_MPIOCTL 0x05
2036#define SOURCE_ASYNC_IOCB 0x07
2037
2038 uint8_t entry_status;
2039
2040 uint32_t handle;
2041 target_id_t loop_id;
2042
2043 uint16_t status;
2044 uint16_t state_flags;
2045 uint16_t status_flags;
2046
2047 uint32_t sys_define2[2];
2048
2049 uint16_t mb0;
2050 uint16_t mb1;
2051 uint16_t mb2;
2052 uint16_t mb3;
2053 uint16_t mb6;
2054 uint16_t mb7;
2055 uint16_t mb9;
2056 uint16_t mb10;
2057 uint32_t reserved_2[2];
2058 uint8_t node_name[WWN_SIZE];
2059 uint8_t port_name[WWN_SIZE];
2060};
2061
2062#ifndef IMMED_NOTIFY_TYPE
2063#define IMMED_NOTIFY_TYPE 0x0D
2064
2065
2066
2067
2068
2069
2070
2071struct imm_ntfy_from_isp {
2072 uint8_t entry_type;
2073 uint8_t entry_count;
2074 uint8_t sys_define;
2075 uint8_t entry_status;
2076 union {
2077 struct {
2078 uint32_t sys_define_2;
2079 target_id_t target;
2080 uint16_t lun;
2081 uint8_t target_id;
2082 uint8_t reserved_1;
2083 uint16_t status_modifier;
2084 uint16_t status;
2085 uint16_t task_flags;
2086 uint16_t seq_id;
2087 uint16_t srr_rx_id;
2088 uint32_t srr_rel_offs;
2089 uint16_t srr_ui;
2090#define SRR_IU_DATA_IN 0x1
2091#define SRR_IU_DATA_OUT 0x5
2092#define SRR_IU_STATUS 0x7
2093 uint16_t srr_ox_id;
2094 uint8_t reserved_2[28];
2095 } isp2x;
2096 struct {
2097 uint32_t reserved;
2098 uint16_t nport_handle;
2099 uint16_t reserved_2;
2100 uint16_t flags;
2101#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2102#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2103 uint16_t srr_rx_id;
2104 uint16_t status;
2105 uint8_t status_subcode;
2106 uint8_t fw_handle;
2107 uint32_t exchange_address;
2108 uint32_t srr_rel_offs;
2109 uint16_t srr_ui;
2110 uint16_t srr_ox_id;
2111 union {
2112 struct {
2113 uint8_t node_name[8];
2114 } plogi;
2115 struct {
2116
2117 uint16_t wd3_lo;
2118 uint8_t resv0[6];
2119 } prli;
2120 struct {
2121 uint8_t port_id[3];
2122 uint8_t resv1;
2123 uint16_t nport_handle;
2124 uint16_t resv2;
2125 } req_els;
2126 } u;
2127 uint8_t port_name[8];
2128 uint8_t resv3[3];
2129 uint8_t vp_index;
2130 uint32_t reserved_5;
2131 uint8_t port_id[3];
2132 uint8_t reserved_6;
2133 } isp24;
2134 } u;
2135 uint16_t reserved_7;
2136 uint16_t ox_id;
2137} __packed;
2138#endif
2139
2140
2141
2142
2143#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2144#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2145
2146
2147
2148
2149
2150typedef union {
2151 uint32_t b24 : 24;
2152
2153 struct {
2154#ifdef __BIG_ENDIAN
2155 uint8_t domain;
2156 uint8_t area;
2157 uint8_t al_pa;
2158#elif defined(__LITTLE_ENDIAN)
2159 uint8_t al_pa;
2160 uint8_t area;
2161 uint8_t domain;
2162#else
2163#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
2164#endif
2165 uint8_t rsvd_1;
2166 } b;
2167} port_id_t;
2168#define INVALID_PORT_ID 0xFFFFFF
2169
2170
2171
2172
2173typedef struct {
2174 port_id_t d_id;
2175 uint8_t node_name[WWN_SIZE];
2176 uint8_t port_name[WWN_SIZE];
2177 uint8_t fabric_port_name[WWN_SIZE];
2178 uint16_t fp_speed;
2179 uint8_t fc4_type;
2180 uint8_t fc4f_nvme;
2181} sw_info_t;
2182
2183
2184#define FC4_TYPE_FCP_SCSI 0x08
2185#define FC4_TYPE_OTHER 0x0
2186#define FC4_TYPE_UNKNOWN 0xff
2187
2188
2189struct mbx_24xx_entry {
2190 uint8_t entry_type;
2191 uint8_t entry_count;
2192 uint8_t sys_define1;
2193 uint8_t entry_status;
2194 uint32_t handle;
2195 uint16_t mb[28];
2196};
2197
2198#define IOCB_SIZE 64
2199
2200
2201
2202
2203typedef enum {
2204 FCT_UNKNOWN,
2205 FCT_RSCN,
2206 FCT_SWITCH,
2207 FCT_BROADCAST,
2208 FCT_INITIATOR,
2209 FCT_TARGET,
2210 FCT_NVME
2211} fc_port_type_t;
2212
2213enum qla_sess_deletion {
2214 QLA_SESS_DELETION_NONE = 0,
2215 QLA_SESS_DELETION_IN_PROGRESS,
2216 QLA_SESS_DELETED,
2217};
2218
2219enum qlt_plogi_link_t {
2220 QLT_PLOGI_LINK_SAME_WWN,
2221 QLT_PLOGI_LINK_CONFLICT,
2222 QLT_PLOGI_LINK_MAX
2223};
2224
2225struct qlt_plogi_ack_t {
2226 struct list_head list;
2227 struct imm_ntfy_from_isp iocb;
2228 port_id_t id;
2229 int ref_count;
2230 void *fcport;
2231};
2232
2233struct ct_sns_desc {
2234 struct ct_sns_pkt *ct_sns;
2235 dma_addr_t ct_sns_dma;
2236};
2237
2238enum discovery_state {
2239 DSC_DELETED,
2240 DSC_GID_PN,
2241 DSC_GNL,
2242 DSC_LOGIN_PEND,
2243 DSC_LOGIN_FAILED,
2244 DSC_GPDB,
2245 DSC_GPSC,
2246 DSC_UPD_FCPORT,
2247 DSC_LOGIN_COMPLETE,
2248 DSC_DELETE_PEND,
2249};
2250
2251enum login_state {
2252 DSC_LS_LLIOCB_SENT = 2,
2253 DSC_LS_PLOGI_PEND,
2254 DSC_LS_PLOGI_COMP,
2255 DSC_LS_PRLI_PEND,
2256 DSC_LS_PRLI_COMP,
2257 DSC_LS_PORT_UNAVAIL,
2258 DSC_LS_PRLO_PEND = 9,
2259 DSC_LS_LOGO_PEND,
2260};
2261
2262enum fcport_mgt_event {
2263 FCME_RELOGIN = 1,
2264 FCME_RSCN,
2265 FCME_GIDPN_DONE,
2266 FCME_PLOGI_DONE,
2267 FCME_PRLI_DONE,
2268 FCME_GNL_DONE,
2269 FCME_GPSC_DONE,
2270 FCME_GPDB_DONE,
2271 FCME_GPNID_DONE,
2272 FCME_GFFID_DONE,
2273 FCME_DELETE_DONE,
2274};
2275
2276enum rscn_addr_format {
2277 RSCN_PORT_ADDR,
2278 RSCN_AREA_ADDR,
2279 RSCN_DOM_ADDR,
2280 RSCN_FAB_ADDR,
2281};
2282
2283
2284
2285
2286typedef struct fc_port {
2287 struct list_head list;
2288 struct scsi_qla_host *vha;
2289
2290 uint8_t node_name[WWN_SIZE];
2291 uint8_t port_name[WWN_SIZE];
2292 port_id_t d_id;
2293 uint16_t loop_id;
2294 uint16_t old_loop_id;
2295
2296 unsigned int conf_compl_supported:1;
2297 unsigned int deleted:2;
2298 unsigned int local:1;
2299 unsigned int logout_on_delete:1;
2300 unsigned int logo_ack_needed:1;
2301 unsigned int keep_nport_handle:1;
2302 unsigned int send_els_logo:1;
2303 unsigned int login_pause:1;
2304 unsigned int login_succ:1;
2305
2306 struct work_struct nvme_del_work;
2307 struct completion nvme_del_done;
2308 uint32_t nvme_prli_service_param;
2309#define NVME_PRLI_SP_CONF BIT_7
2310#define NVME_PRLI_SP_INITIATOR BIT_5
2311#define NVME_PRLI_SP_TARGET BIT_4
2312#define NVME_PRLI_SP_DISCOVERY BIT_3
2313 uint8_t nvme_flag;
2314#define NVME_FLAG_REGISTERED 4
2315
2316 struct fc_port *conflict;
2317 unsigned char logout_completed;
2318 int generation;
2319
2320 struct se_session *se_sess;
2321 struct kref sess_kref;
2322 struct qla_tgt *tgt;
2323 unsigned long expires;
2324 struct list_head del_list_entry;
2325 struct work_struct free_work;
2326
2327 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2328
2329 uint16_t tgt_id;
2330 uint16_t old_tgt_id;
2331
2332 uint8_t fcp_prio;
2333
2334 uint8_t fabric_port_name[WWN_SIZE];
2335 uint16_t fp_speed;
2336
2337 fc_port_type_t port_type;
2338
2339 atomic_t state;
2340 uint32_t flags;
2341
2342 int login_retry;
2343
2344 struct fc_rport *rport, *drport;
2345 u32 supported_classes;
2346
2347 uint8_t fc4_type;
2348 uint8_t fc4f_nvme;
2349 uint8_t scan_state;
2350
2351 unsigned long last_queue_full;
2352 unsigned long last_ramp_up;
2353
2354 uint16_t port_id;
2355
2356 struct nvme_fc_remote_port *nvme_remote_port;
2357
2358 unsigned long retry_delay_timestamp;
2359 struct qla_tgt_sess *tgt_session;
2360 struct ct_sns_desc ct_desc;
2361 enum discovery_state disc_state;
2362 enum login_state fw_login_state;
2363 unsigned long plogi_nack_done_deadline;
2364
2365 u32 login_gen, last_login_gen;
2366 u32 rscn_gen, last_rscn_gen;
2367 u32 chip_reset;
2368 struct list_head gnl_entry;
2369 struct work_struct del_work;
2370 u8 iocb[IOCB_SIZE];
2371} fc_port_t;
2372
2373#define QLA_FCPORT_SCAN 1
2374#define QLA_FCPORT_FOUND 2
2375
2376struct event_arg {
2377 enum fcport_mgt_event event;
2378 fc_port_t *fcport;
2379 srb_t *sp;
2380 port_id_t id;
2381 u16 data[2], rc;
2382 u8 port_name[WWN_SIZE];
2383 u32 iop[2];
2384};
2385
2386#include "qla_mr.h"
2387
2388
2389
2390
2391#define FCS_UNCONFIGURED 1
2392#define FCS_DEVICE_DEAD 2
2393#define FCS_DEVICE_LOST 3
2394#define FCS_ONLINE 4
2395
2396static const char * const port_state_str[] = {
2397 "Unknown",
2398 "UNCONFIGURED",
2399 "DEAD",
2400 "LOST",
2401 "ONLINE"
2402};
2403
2404
2405
2406
2407#define FCF_FABRIC_DEVICE BIT_0
2408#define FCF_LOGIN_NEEDED BIT_1
2409#define FCF_FCP2_DEVICE BIT_2
2410#define FCF_ASYNC_SENT BIT_3
2411#define FCF_CONF_COMP_SUPPORTED BIT_4
2412
2413
2414#define FC_NO_LOOP_ID 0x1000
2415
2416
2417
2418
2419
2420
2421
2422#define CT_REJECT_RESPONSE 0x8001
2423#define CT_ACCEPT_RESPONSE 0x8002
2424#define CT_REASON_INVALID_COMMAND_CODE 0x01
2425#define CT_REASON_CANNOT_PERFORM 0x09
2426#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2427#define CT_EXPL_ALREADY_REGISTERED 0x10
2428#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2429#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2430#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2431#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2432#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2433#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2434#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2435#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2436#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2437#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2438#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2439
2440#define NS_N_PORT_TYPE 0x01
2441#define NS_NL_PORT_TYPE 0x02
2442#define NS_NX_PORT_TYPE 0x7F
2443
2444#define GA_NXT_CMD 0x100
2445#define GA_NXT_REQ_SIZE (16 + 4)
2446#define GA_NXT_RSP_SIZE (16 + 620)
2447
2448#define GID_PT_CMD 0x1A1
2449#define GID_PT_REQ_SIZE (16 + 4)
2450
2451#define GPN_ID_CMD 0x112
2452#define GPN_ID_REQ_SIZE (16 + 4)
2453#define GPN_ID_RSP_SIZE (16 + 8)
2454
2455#define GNN_ID_CMD 0x113
2456#define GNN_ID_REQ_SIZE (16 + 4)
2457#define GNN_ID_RSP_SIZE (16 + 8)
2458
2459#define GFT_ID_CMD 0x117
2460#define GFT_ID_REQ_SIZE (16 + 4)
2461#define GFT_ID_RSP_SIZE (16 + 32)
2462
2463#define GID_PN_CMD 0x121
2464#define GID_PN_REQ_SIZE (16 + 8)
2465#define GID_PN_RSP_SIZE (16 + 4)
2466
2467#define RFT_ID_CMD 0x217
2468#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2469#define RFT_ID_RSP_SIZE 16
2470
2471#define RFF_ID_CMD 0x21F
2472#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2473#define RFF_ID_RSP_SIZE 16
2474
2475#define RNN_ID_CMD 0x213
2476#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2477#define RNN_ID_RSP_SIZE 16
2478
2479#define RSNN_NN_CMD 0x239
2480#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2481#define RSNN_NN_RSP_SIZE 16
2482
2483#define GFPN_ID_CMD 0x11C
2484#define GFPN_ID_REQ_SIZE (16 + 4)
2485#define GFPN_ID_RSP_SIZE (16 + 8)
2486
2487#define GPSC_CMD 0x127
2488#define GPSC_REQ_SIZE (16 + 8)
2489#define GPSC_RSP_SIZE (16 + 2 + 2)
2490
2491#define GFF_ID_CMD 0x011F
2492#define GFF_ID_REQ_SIZE (16 + 4)
2493#define GFF_ID_RSP_SIZE (16 + 128)
2494
2495
2496
2497
2498#define FDMI_HBA_ATTR_COUNT 9
2499#define FDMIV2_HBA_ATTR_COUNT 17
2500#define FDMI_HBA_NODE_NAME 0x1
2501#define FDMI_HBA_MANUFACTURER 0x2
2502#define FDMI_HBA_SERIAL_NUMBER 0x3
2503#define FDMI_HBA_MODEL 0x4
2504#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2505#define FDMI_HBA_HARDWARE_VERSION 0x6
2506#define FDMI_HBA_DRIVER_VERSION 0x7
2507#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2508#define FDMI_HBA_FIRMWARE_VERSION 0x9
2509#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2510#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2511#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2512#define FDMI_HBA_VENDOR_ID 0xd
2513#define FDMI_HBA_NUM_PORTS 0xe
2514#define FDMI_HBA_FABRIC_NAME 0xf
2515#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2516#define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2517
2518struct ct_fdmi_hba_attr {
2519 uint16_t type;
2520 uint16_t len;
2521 union {
2522 uint8_t node_name[WWN_SIZE];
2523 uint8_t manufacturer[64];
2524 uint8_t serial_num[32];
2525 uint8_t model[16+1];
2526 uint8_t model_desc[80];
2527 uint8_t hw_version[32];
2528 uint8_t driver_version[32];
2529 uint8_t orom_version[16];
2530 uint8_t fw_version[32];
2531 uint8_t os_version[128];
2532 uint32_t max_ct_len;
2533 } a;
2534};
2535
2536struct ct_fdmi_hba_attributes {
2537 uint32_t count;
2538 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2539};
2540
2541struct ct_fdmiv2_hba_attr {
2542 uint16_t type;
2543 uint16_t len;
2544 union {
2545 uint8_t node_name[WWN_SIZE];
2546 uint8_t manufacturer[64];
2547 uint8_t serial_num[32];
2548 uint8_t model[16+1];
2549 uint8_t model_desc[80];
2550 uint8_t hw_version[16];
2551 uint8_t driver_version[32];
2552 uint8_t orom_version[16];
2553 uint8_t fw_version[32];
2554 uint8_t os_version[128];
2555 uint32_t max_ct_len;
2556 uint8_t sym_name[256];
2557 uint32_t vendor_id;
2558 uint32_t num_ports;
2559 uint8_t fabric_name[WWN_SIZE];
2560 uint8_t bios_name[32];
2561 uint8_t vendor_identifier[8];
2562 } a;
2563};
2564
2565struct ct_fdmiv2_hba_attributes {
2566 uint32_t count;
2567 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2568};
2569
2570
2571
2572
2573#define FDMI_PORT_ATTR_COUNT 6
2574#define FDMIV2_PORT_ATTR_COUNT 16
2575#define FDMI_PORT_FC4_TYPES 0x1
2576#define FDMI_PORT_SUPPORT_SPEED 0x2
2577#define FDMI_PORT_CURRENT_SPEED 0x3
2578#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2579#define FDMI_PORT_OS_DEVICE_NAME 0x5
2580#define FDMI_PORT_HOST_NAME 0x6
2581#define FDMI_PORT_NODE_NAME 0x7
2582#define FDMI_PORT_NAME 0x8
2583#define FDMI_PORT_SYM_NAME 0x9
2584#define FDMI_PORT_TYPE 0xa
2585#define FDMI_PORT_SUPP_COS 0xb
2586#define FDMI_PORT_FABRIC_NAME 0xc
2587#define FDMI_PORT_FC4_TYPE 0xd
2588#define FDMI_PORT_STATE 0x101
2589#define FDMI_PORT_COUNT 0x102
2590#define FDMI_PORT_ID 0x103
2591
2592#define FDMI_PORT_SPEED_1GB 0x1
2593#define FDMI_PORT_SPEED_2GB 0x2
2594#define FDMI_PORT_SPEED_10GB 0x4
2595#define FDMI_PORT_SPEED_4GB 0x8
2596#define FDMI_PORT_SPEED_8GB 0x10
2597#define FDMI_PORT_SPEED_16GB 0x20
2598#define FDMI_PORT_SPEED_32GB 0x40
2599#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2600
2601#define FC_CLASS_2 0x04
2602#define FC_CLASS_3 0x08
2603#define FC_CLASS_2_3 0x0C
2604
2605struct ct_fdmiv2_port_attr {
2606 uint16_t type;
2607 uint16_t len;
2608 union {
2609 uint8_t fc4_types[32];
2610 uint32_t sup_speed;
2611 uint32_t cur_speed;
2612 uint32_t max_frame_size;
2613 uint8_t os_dev_name[32];
2614 uint8_t host_name[256];
2615 uint8_t node_name[WWN_SIZE];
2616 uint8_t port_name[WWN_SIZE];
2617 uint8_t port_sym_name[128];
2618 uint32_t port_type;
2619 uint32_t port_supported_cos;
2620 uint8_t fabric_name[WWN_SIZE];
2621 uint8_t port_fc4_type[32];
2622 uint32_t port_state;
2623 uint32_t num_ports;
2624 uint32_t port_id;
2625 } a;
2626};
2627
2628
2629
2630
2631struct ct_fdmiv2_port_attributes {
2632 uint32_t count;
2633 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2634};
2635
2636struct ct_fdmi_port_attr {
2637 uint16_t type;
2638 uint16_t len;
2639 union {
2640 uint8_t fc4_types[32];
2641 uint32_t sup_speed;
2642 uint32_t cur_speed;
2643 uint32_t max_frame_size;
2644 uint8_t os_dev_name[32];
2645 uint8_t host_name[256];
2646 } a;
2647};
2648
2649struct ct_fdmi_port_attributes {
2650 uint32_t count;
2651 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2652};
2653
2654
2655#define GRHL_CMD 0x100
2656#define GHAT_CMD 0x101
2657#define GRPL_CMD 0x102
2658#define GPAT_CMD 0x110
2659
2660#define RHBA_CMD 0x200
2661#define RHBA_RSP_SIZE 16
2662
2663#define RHAT_CMD 0x201
2664#define RPRT_CMD 0x210
2665
2666#define RPA_CMD 0x211
2667#define RPA_RSP_SIZE 16
2668
2669#define DHBA_CMD 0x300
2670#define DHBA_REQ_SIZE (16 + 8)
2671#define DHBA_RSP_SIZE 16
2672
2673#define DHAT_CMD 0x301
2674#define DPRT_CMD 0x310
2675#define DPA_CMD 0x311
2676
2677
2678struct ct_cmd_hdr {
2679 uint8_t revision;
2680 uint8_t in_id[3];
2681 uint8_t gs_type;
2682 uint8_t gs_subtype;
2683 uint8_t options;
2684 uint8_t reserved;
2685};
2686
2687
2688struct ct_sns_req {
2689 struct ct_cmd_hdr header;
2690 uint16_t command;
2691 uint16_t max_rsp_size;
2692 uint8_t fragment_id;
2693 uint8_t reserved[3];
2694
2695 union {
2696
2697 struct {
2698 uint8_t reserved;
2699 uint8_t port_id[3];
2700 } port_id;
2701
2702 struct {
2703 uint8_t port_type;
2704 uint8_t domain;
2705 uint8_t area;
2706 uint8_t reserved;
2707 } gid_pt;
2708
2709 struct {
2710 uint8_t reserved;
2711 uint8_t port_id[3];
2712 uint8_t fc4_types[32];
2713 } rft_id;
2714
2715 struct {
2716 uint8_t reserved;
2717 uint8_t port_id[3];
2718 uint16_t reserved2;
2719 uint8_t fc4_feature;
2720 uint8_t fc4_type;
2721 } rff_id;
2722
2723 struct {
2724 uint8_t reserved;
2725 uint8_t port_id[3];
2726 uint8_t node_name[8];
2727 } rnn_id;
2728
2729 struct {
2730 uint8_t node_name[8];
2731 uint8_t name_len;
2732 uint8_t sym_node_name[255];
2733 } rsnn_nn;
2734
2735 struct {
2736 uint8_t hba_identifier[8];
2737 } ghat;
2738
2739 struct {
2740 uint8_t hba_identifier[8];
2741 uint32_t entry_count;
2742 uint8_t port_name[8];
2743 struct ct_fdmi_hba_attributes attrs;
2744 } rhba;
2745
2746 struct {
2747 uint8_t hba_identifier[8];
2748 uint32_t entry_count;
2749 uint8_t port_name[8];
2750 struct ct_fdmiv2_hba_attributes attrs;
2751 } rhba2;
2752
2753 struct {
2754 uint8_t hba_identifier[8];
2755 struct ct_fdmi_hba_attributes attrs;
2756 } rhat;
2757
2758 struct {
2759 uint8_t port_name[8];
2760 struct ct_fdmi_port_attributes attrs;
2761 } rpa;
2762
2763 struct {
2764 uint8_t port_name[8];
2765 struct ct_fdmiv2_port_attributes attrs;
2766 } rpa2;
2767
2768 struct {
2769 uint8_t port_name[8];
2770 } dhba;
2771
2772 struct {
2773 uint8_t port_name[8];
2774 } dhat;
2775
2776 struct {
2777 uint8_t port_name[8];
2778 } dprt;
2779
2780 struct {
2781 uint8_t port_name[8];
2782 } dpa;
2783
2784 struct {
2785 uint8_t port_name[8];
2786 } gpsc;
2787
2788 struct {
2789 uint8_t reserved;
2790 uint8_t port_id[3];
2791 } gff_id;
2792
2793 struct {
2794 uint8_t port_name[8];
2795 } gid_pn;
2796 } req;
2797};
2798
2799
2800struct ct_rsp_hdr {
2801 struct ct_cmd_hdr header;
2802 uint16_t response;
2803 uint16_t residual;
2804 uint8_t fragment_id;
2805 uint8_t reason_code;
2806 uint8_t explanation_code;
2807 uint8_t vendor_unique;
2808};
2809
2810struct ct_sns_gid_pt_data {
2811 uint8_t control_byte;
2812 uint8_t port_id[3];
2813};
2814
2815struct ct_sns_rsp {
2816 struct ct_rsp_hdr header;
2817
2818 union {
2819 struct {
2820 uint8_t port_type;
2821 uint8_t port_id[3];
2822 uint8_t port_name[8];
2823 uint8_t sym_port_name_len;
2824 uint8_t sym_port_name[255];
2825 uint8_t node_name[8];
2826 uint8_t sym_node_name_len;
2827 uint8_t sym_node_name[255];
2828 uint8_t init_proc_assoc[8];
2829 uint8_t node_ip_addr[16];
2830 uint8_t class_of_service[4];
2831 uint8_t fc4_types[32];
2832 uint8_t ip_address[16];
2833 uint8_t fabric_port_name[8];
2834 uint8_t reserved;
2835 uint8_t hard_address[3];
2836 } ga_nxt;
2837
2838 struct {
2839
2840 struct ct_sns_gid_pt_data
2841 entries[MAX_FIBRE_DEVICES_MAX];
2842 } gid_pt;
2843
2844 struct {
2845 uint8_t port_name[8];
2846 } gpn_id;
2847
2848 struct {
2849 uint8_t node_name[8];
2850 } gnn_id;
2851
2852 struct {
2853 uint8_t fc4_types[32];
2854 } gft_id;
2855
2856 struct {
2857 uint32_t entry_count;
2858 uint8_t port_name[8];
2859 struct ct_fdmi_hba_attributes attrs;
2860 } ghat;
2861
2862 struct {
2863 uint8_t port_name[8];
2864 } gfpn_id;
2865
2866 struct {
2867 uint16_t speeds;
2868 uint16_t speed;
2869 } gpsc;
2870
2871#define GFF_FCP_SCSI_OFFSET 7
2872#define GFF_NVME_OFFSET 23
2873 struct {
2874 uint8_t fc4_features[128];
2875 } gff_id;
2876 struct {
2877 uint8_t reserved;
2878 uint8_t port_id[3];
2879 } gid_pn;
2880 } rsp;
2881};
2882
2883struct ct_sns_pkt {
2884 union {
2885 struct ct_sns_req req;
2886 struct ct_sns_rsp rsp;
2887 } p;
2888};
2889
2890
2891
2892
2893#define RFT_ID_SNS_SCMD_LEN 22
2894#define RFT_ID_SNS_CMD_SIZE 60
2895#define RFT_ID_SNS_DATA_SIZE 16
2896
2897#define RNN_ID_SNS_SCMD_LEN 10
2898#define RNN_ID_SNS_CMD_SIZE 36
2899#define RNN_ID_SNS_DATA_SIZE 16
2900
2901#define GA_NXT_SNS_SCMD_LEN 6
2902#define GA_NXT_SNS_CMD_SIZE 28
2903#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2904
2905#define GID_PT_SNS_SCMD_LEN 6
2906#define GID_PT_SNS_CMD_SIZE 28
2907
2908
2909
2910
2911#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2912
2913#define GPN_ID_SNS_SCMD_LEN 6
2914#define GPN_ID_SNS_CMD_SIZE 28
2915#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2916
2917#define GNN_ID_SNS_SCMD_LEN 6
2918#define GNN_ID_SNS_CMD_SIZE 28
2919#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2920
2921struct sns_cmd_pkt {
2922 union {
2923 struct {
2924 uint16_t buffer_length;
2925 uint16_t reserved_1;
2926 uint32_t buffer_address[2];
2927 uint16_t subcommand_length;
2928 uint16_t reserved_2;
2929 uint16_t subcommand;
2930 uint16_t size;
2931 uint32_t reserved_3;
2932 uint8_t param[36];
2933 } cmd;
2934
2935 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2936 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2937 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2938 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2939 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2940 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2941 } p;
2942};
2943
2944struct fw_blob {
2945 char *name;
2946 uint32_t segs[4];
2947 const struct firmware *fw;
2948};
2949
2950
2951struct gid_list_info {
2952 uint8_t al_pa;
2953 uint8_t area;
2954 uint8_t domain;
2955 uint8_t loop_id_2100;
2956 uint16_t loop_id;
2957 uint16_t reserved_1;
2958};
2959
2960
2961typedef struct vport_info {
2962 uint8_t port_name[WWN_SIZE];
2963 uint8_t node_name[WWN_SIZE];
2964 int vp_id;
2965 uint16_t loop_id;
2966 unsigned long host_no;
2967 uint8_t port_id[3];
2968 int loop_state;
2969} vport_info_t;
2970
2971typedef struct vport_params {
2972 uint8_t port_name[WWN_SIZE];
2973 uint8_t node_name[WWN_SIZE];
2974 uint32_t options;
2975#define VP_OPTS_RETRY_ENABLE BIT_0
2976#define VP_OPTS_VP_DISABLE BIT_1
2977} vport_params_t;
2978
2979
2980#define VP_RET_CODE_OK 0
2981#define VP_RET_CODE_FATAL 1
2982#define VP_RET_CODE_WRONG_ID 2
2983#define VP_RET_CODE_WWPN 3
2984#define VP_RET_CODE_RESOURCES 4
2985#define VP_RET_CODE_NO_MEM 5
2986#define VP_RET_CODE_NOT_FOUND 6
2987
2988struct qla_hw_data;
2989struct rsp_que;
2990
2991
2992
2993struct isp_operations {
2994
2995 int (*pci_config) (struct scsi_qla_host *);
2996 void (*reset_chip) (struct scsi_qla_host *);
2997 int (*chip_diag) (struct scsi_qla_host *);
2998 void (*config_rings) (struct scsi_qla_host *);
2999 void (*reset_adapter) (struct scsi_qla_host *);
3000 int (*nvram_config) (struct scsi_qla_host *);
3001 void (*update_fw_options) (struct scsi_qla_host *);
3002 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3003
3004 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3005 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3006
3007 irq_handler_t intr_handler;
3008 void (*enable_intrs) (struct qla_hw_data *);
3009 void (*disable_intrs) (struct qla_hw_data *);
3010
3011 int (*abort_command) (srb_t *);
3012 int (*target_reset) (struct fc_port *, uint64_t, int);
3013 int (*lun_reset) (struct fc_port *, uint64_t, int);
3014 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3015 uint8_t, uint8_t, uint16_t *, uint8_t);
3016 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3017 uint8_t, uint8_t);
3018
3019 uint16_t (*calc_req_entries) (uint16_t);
3020 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3021 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3022 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3023 uint32_t);
3024
3025 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
3026 uint32_t, uint32_t);
3027 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
3028 uint32_t);
3029
3030 void (*fw_dump) (struct scsi_qla_host *, int);
3031
3032 int (*beacon_on) (struct scsi_qla_host *);
3033 int (*beacon_off) (struct scsi_qla_host *);
3034 void (*beacon_blink) (struct scsi_qla_host *);
3035
3036 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
3037 uint32_t, uint32_t);
3038 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
3039 uint32_t);
3040
3041 int (*get_flash_version) (struct scsi_qla_host *, void *);
3042 int (*start_scsi) (srb_t *);
3043 int (*start_scsi_mq) (srb_t *);
3044 int (*abort_isp) (struct scsi_qla_host *);
3045 int (*iospace_config)(struct qla_hw_data*);
3046 int (*initialize_adapter)(struct scsi_qla_host *);
3047};
3048
3049
3050
3051#define QLA_MSIX_CHIP_REV_24XX 3
3052#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3053#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3054
3055#define QLA_BASE_VECTORS 2
3056#define QLA_MSIX_RSP_Q 0x01
3057#define QLA_ATIO_VECTOR 0x02
3058#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3059
3060#define QLA_MIDX_DEFAULT 0
3061#define QLA_MIDX_RSP_Q 1
3062#define QLA_PCI_MSIX_CONTROL 0xa2
3063#define QLA_83XX_PCI_MSIX_CONTROL 0x92
3064
3065struct scsi_qla_host;
3066
3067
3068#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3069
3070struct qla_msix_entry {
3071 int have_irq;
3072 int in_use;
3073 uint32_t vector;
3074 uint16_t entry;
3075 char name[30];
3076 void *handle;
3077 int cpuid;
3078};
3079
3080#define WATCH_INTERVAL 1
3081
3082
3083enum qla_work_type {
3084 QLA_EVT_AEN,
3085 QLA_EVT_IDC_ACK,
3086 QLA_EVT_ASYNC_LOGIN,
3087 QLA_EVT_ASYNC_LOGOUT,
3088 QLA_EVT_ASYNC_LOGOUT_DONE,
3089 QLA_EVT_ASYNC_ADISC,
3090 QLA_EVT_ASYNC_ADISC_DONE,
3091 QLA_EVT_UEVENT,
3092 QLA_EVT_AENFX,
3093 QLA_EVT_GIDPN,
3094 QLA_EVT_GPNID,
3095 QLA_EVT_GPNID_DONE,
3096 QLA_EVT_NEW_SESS,
3097 QLA_EVT_GPDB,
3098 QLA_EVT_PRLI,
3099 QLA_EVT_GPSC,
3100 QLA_EVT_UPD_FCPORT,
3101 QLA_EVT_GNL,
3102 QLA_EVT_NACK,
3103};
3104
3105
3106struct qla_work_evt {
3107 struct list_head list;
3108 enum qla_work_type type;
3109 u32 flags;
3110#define QLA_EVT_FLAG_FREE 0x1
3111
3112 union {
3113 struct {
3114 enum fc_host_event_code code;
3115 u32 data;
3116 } aen;
3117 struct {
3118#define QLA_IDC_ACK_REGS 7
3119 uint16_t mb[QLA_IDC_ACK_REGS];
3120 } idc_ack;
3121 struct {
3122 struct fc_port *fcport;
3123#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3124 u16 data[2];
3125 } logio;
3126 struct {
3127 u32 code;
3128#define QLA_UEVENT_CODE_FW_DUMP 0
3129 } uevent;
3130 struct {
3131 uint32_t evtcode;
3132 uint32_t mbx[8];
3133 uint32_t count;
3134 } aenfx;
3135 struct {
3136 srb_t *sp;
3137 } iosb;
3138 struct {
3139 port_id_t id;
3140 } gpnid;
3141 struct {
3142 port_id_t id;
3143 u8 port_name[8];
3144 void *pla;
3145 } new_sess;
3146 struct {
3147 fc_port_t *fcport;
3148 u8 opt;
3149 } fcport;
3150 struct {
3151 fc_port_t *fcport;
3152 u8 iocb[IOCB_SIZE];
3153 int type;
3154 } nack;
3155 } u;
3156};
3157
3158struct qla_chip_state_84xx {
3159 struct list_head list;
3160 struct kref kref;
3161
3162 void *bus;
3163 spinlock_t access_lock;
3164 struct mutex fw_update_mutex;
3165 uint32_t fw_update;
3166 uint32_t op_fw_version;
3167 uint32_t op_fw_size;
3168 uint32_t op_fw_seq_size;
3169 uint32_t diag_fw_version;
3170 uint32_t gold_fw_version;
3171};
3172
3173struct qla_dif_statistics {
3174 uint64_t dif_input_bytes;
3175 uint64_t dif_output_bytes;
3176 uint64_t dif_input_requests;
3177 uint64_t dif_output_requests;
3178 uint32_t dif_guard_err;
3179 uint32_t dif_ref_tag_err;
3180 uint32_t dif_app_tag_err;
3181};
3182
3183struct qla_statistics {
3184 uint32_t total_isp_aborts;
3185 uint64_t input_bytes;
3186 uint64_t output_bytes;
3187 uint64_t input_requests;
3188 uint64_t output_requests;
3189 uint32_t control_requests;
3190
3191 uint64_t jiffies_at_last_reset;
3192 uint32_t stat_max_pend_cmds;
3193 uint32_t stat_max_qfull_cmds_alloc;
3194 uint32_t stat_max_qfull_cmds_dropped;
3195
3196 struct qla_dif_statistics qla_dif_stats;
3197};
3198
3199struct bidi_statistics {
3200 unsigned long long io_count;
3201 unsigned long long transfer_bytes;
3202};
3203
3204struct qla_tc_param {
3205 struct scsi_qla_host *vha;
3206 uint32_t blk_sz;
3207 uint32_t bufflen;
3208 struct scatterlist *sg;
3209 struct scatterlist *prot_sg;
3210 struct crc_context *ctx;
3211 uint8_t *ctx_dsd_alloced;
3212};
3213
3214
3215#define MBC_INITIALIZE_MULTIQ 0x1f
3216#define QLA_QUE_PAGE 0X1000
3217#define QLA_MQ_SIZE 32
3218#define QLA_MAX_QUEUES 256
3219#define ISP_QUE_REG(ha, id) \
3220 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3221 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3222 ((void __iomem *)ha->iobase))
3223#define QLA_REQ_QUE_ID(tag) \
3224 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3225#define QLA_DEFAULT_QUE_QOS 5
3226#define QLA_PRECONFIG_VPORTS 32
3227#define QLA_MAX_VPORTS_QLA24XX 128
3228#define QLA_MAX_VPORTS_QLA25XX 256
3229
3230struct qla_tgt_counters {
3231 uint64_t qla_core_sbt_cmd;
3232 uint64_t core_qla_que_buf;
3233 uint64_t qla_core_ret_ctio;
3234 uint64_t core_qla_snd_status;
3235 uint64_t qla_core_ret_sta_ctio;
3236 uint64_t core_qla_free_cmd;
3237 uint64_t num_q_full_sent;
3238 uint64_t num_alloc_iocb_failed;
3239 uint64_t num_term_xchg_sent;
3240};
3241
3242struct qla_qpair;
3243
3244
3245struct rsp_que {
3246 dma_addr_t dma;
3247 response_t *ring;
3248 response_t *ring_ptr;
3249 uint32_t __iomem *rsp_q_in;
3250 uint32_t __iomem *rsp_q_out;
3251 uint16_t ring_index;
3252 uint16_t out_ptr;
3253 uint16_t *in_ptr;
3254 uint16_t length;
3255 uint16_t options;
3256 uint16_t rid;
3257 uint16_t id;
3258 uint16_t vp_idx;
3259 struct qla_hw_data *hw;
3260 struct qla_msix_entry *msix;
3261 struct req_que *req;
3262 srb_t *status_srb;
3263 struct qla_qpair *qpair;
3264
3265 dma_addr_t dma_fx00;
3266 response_t *ring_fx00;
3267 uint16_t length_fx00;
3268 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3269};
3270
3271
3272struct req_que {
3273 dma_addr_t dma;
3274 request_t *ring;
3275 request_t *ring_ptr;
3276 uint32_t __iomem *req_q_in;
3277 uint32_t __iomem *req_q_out;
3278 uint16_t ring_index;
3279 uint16_t in_ptr;
3280 uint16_t *out_ptr;
3281 uint16_t cnt;
3282 uint16_t length;
3283 uint16_t options;
3284 uint16_t rid;
3285 uint16_t id;
3286 uint16_t qos;
3287 uint16_t vp_idx;
3288 struct rsp_que *rsp;
3289 srb_t **outstanding_cmds;
3290 uint32_t current_outstanding_cmd;
3291 uint16_t num_outstanding_cmds;
3292 int max_q_depth;
3293
3294 dma_addr_t dma_fx00;
3295 request_t *ring_fx00;
3296 uint16_t length_fx00;
3297 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3298};
3299
3300
3301struct qla_qpair {
3302 spinlock_t qp_lock;
3303 atomic_t ref_count;
3304 uint32_t lun_cnt;
3305
3306
3307
3308
3309 spinlock_t *qp_lock_ptr;
3310 struct scsi_qla_host *vha;
3311 u32 chip_reset;
3312
3313
3314
3315
3316
3317
3318 uint32_t online:1;
3319
3320 uint32_t difdix_supported:1;
3321 uint32_t delete_in_progress:1;
3322 uint32_t fw_started:1;
3323 uint32_t enable_class_2:1;
3324 uint32_t enable_explicit_conf:1;
3325 uint32_t use_shadow_reg:1;
3326
3327 uint16_t id;
3328 uint16_t vp_idx;
3329 mempool_t *srb_mempool;
3330
3331 struct pci_dev *pdev;
3332 void (*reqq_start_iocbs)(struct qla_qpair *);
3333
3334
3335 struct req_que *req;
3336 struct rsp_que *rsp;
3337 struct atio_que *atio;
3338 struct qla_msix_entry *msix;
3339 struct qla_hw_data *hw;
3340 struct work_struct q_work;
3341 struct list_head qp_list_elem;
3342 struct list_head hints_list;
3343 struct list_head nvme_done_list;
3344 uint16_t cpuid;
3345 struct qla_tgt_counters tgt_counters;
3346};
3347
3348
3349struct qlfc_fw {
3350 void *fw_buf;
3351 dma_addr_t fw_dma;
3352 uint32_t len;
3353};
3354
3355struct scsi_qlt_host {
3356 void *target_lport_ptr;
3357 struct mutex tgt_mutex;
3358 struct mutex tgt_host_action_mutex;
3359 struct qla_tgt *qla_tgt;
3360};
3361
3362struct qlt_hw_data {
3363
3364 uint32_t node_name_set:1;
3365
3366 dma_addr_t atio_dma;
3367 struct atio *atio_ring;
3368 struct atio *atio_ring_ptr;
3369 uint16_t atio_ring_index;
3370 uint16_t atio_q_length;
3371 uint32_t __iomem *atio_q_in;
3372 uint32_t __iomem *atio_q_out;
3373
3374 struct qla_tgt_func_tmpl *tgt_ops;
3375 struct qla_tgt_vp_map *tgt_vp_map;
3376
3377 int saved_set;
3378 uint16_t saved_exchange_count;
3379 uint32_t saved_firmware_options_1;
3380 uint32_t saved_firmware_options_2;
3381 uint32_t saved_firmware_options_3;
3382 uint8_t saved_firmware_options[2];
3383 uint8_t saved_add_firmware_options[2];
3384
3385 uint8_t tgt_node_name[WWN_SIZE];
3386
3387 struct dentry *dfs_tgt_sess;
3388 struct dentry *dfs_tgt_port_database;
3389 struct dentry *dfs_naqp;
3390
3391 struct list_head q_full_list;
3392 uint32_t num_pend_cmds;
3393 uint32_t num_qfull_cmds_alloc;
3394 uint32_t num_qfull_cmds_dropped;
3395 spinlock_t q_full_lock;
3396 uint32_t leak_exchg_thresh_hold;
3397 spinlock_t sess_lock;
3398 int num_act_qpairs;
3399#define DEFAULT_NAQP 2
3400 spinlock_t atio_lock ____cacheline_aligned;
3401 struct btree_head32 host_map;
3402};
3403
3404#define MAX_QFULL_CMDS_ALLOC 8192
3405#define Q_FULL_THRESH_HOLD_PERCENT 90
3406#define Q_FULL_THRESH_HOLD(ha) \
3407 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3408
3409#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3410
3411#define QLA_EARLY_LINKUP(_ha) \
3412 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \
3413 _ha->flags.fw_started && !_ha->flags.fw_init_done)
3414
3415
3416
3417
3418struct qla_hw_data {
3419 struct pci_dev *pdev;
3420
3421#define SRB_MIN_REQ 128
3422 mempool_t *srb_mempool;
3423
3424 volatile struct {
3425 uint32_t mbox_int :1;
3426 uint32_t mbox_busy :1;
3427 uint32_t disable_risc_code_load :1;
3428 uint32_t enable_64bit_addressing :1;
3429 uint32_t enable_lip_reset :1;
3430 uint32_t enable_target_reset :1;
3431 uint32_t enable_lip_full_login :1;
3432 uint32_t enable_led_scheme :1;
3433
3434 uint32_t msi_enabled :1;
3435 uint32_t msix_enabled :1;
3436 uint32_t disable_serdes :1;
3437 uint32_t gpsc_supported :1;
3438 uint32_t npiv_supported :1;
3439 uint32_t pci_channel_io_perm_failure :1;
3440 uint32_t fce_enabled :1;
3441 uint32_t fac_supported :1;
3442
3443 uint32_t chip_reset_done :1;
3444 uint32_t running_gold_fw :1;
3445 uint32_t eeh_busy :1;
3446 uint32_t disable_msix_handshake :1;
3447 uint32_t fcp_prio_enabled :1;
3448 uint32_t isp82xx_fw_hung:1;
3449 uint32_t nic_core_hung:1;
3450
3451 uint32_t quiesce_owner:1;
3452 uint32_t nic_core_reset_hdlr_active:1;
3453 uint32_t nic_core_reset_owner:1;
3454 uint32_t isp82xx_no_md_cap:1;
3455 uint32_t host_shutting_down:1;
3456 uint32_t idc_compl_status:1;
3457 uint32_t mr_reset_hdlr_active:1;
3458 uint32_t mr_intr_valid:1;
3459
3460 uint32_t dport_enabled:1;
3461 uint32_t fawwpn_enabled:1;
3462 uint32_t exlogins_enabled:1;
3463 uint32_t exchoffld_enabled:1;
3464
3465 uint32_t lip_ae:1;
3466 uint32_t n2n_ae:1;
3467 uint32_t fw_started:1;
3468 uint32_t fw_init_done:1;
3469
3470 uint32_t detected_lr_sfp:1;
3471 uint32_t using_lr_setting:1;
3472 } flags;
3473
3474 uint16_t long_range_distance;
3475#define LR_DISTANCE_5K 1
3476#define LR_DISTANCE_10K 0
3477
3478
3479
3480
3481
3482
3483
3484
3485 spinlock_t hardware_lock ____cacheline_aligned;
3486 int bars;
3487 int mem_only;
3488 device_reg_t *iobase;
3489 resource_size_t pio_address;
3490
3491#define MIN_IOBASE_LEN 0x100
3492 dma_addr_t bar0_hdl;
3493
3494 void __iomem *cregbase;
3495 dma_addr_t bar2_hdl;
3496#define BAR0_LEN_FX00 (1024 * 1024)
3497#define BAR2_LEN_FX00 (128 * 1024)
3498
3499 uint32_t rqstq_intr_code;
3500 uint32_t mbx_intr_code;
3501 uint32_t req_que_len;
3502 uint32_t rsp_que_len;
3503 uint32_t req_que_off;
3504 uint32_t rsp_que_off;
3505
3506
3507 device_reg_t *mqiobase;
3508 device_reg_t *msixbase;
3509 uint16_t msix_count;
3510 uint8_t mqenable;
3511 struct req_que **req_q_map;
3512 struct rsp_que **rsp_q_map;
3513 struct qla_qpair **queue_pair_map;
3514 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3515 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3516 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3517 / sizeof(unsigned long)];
3518 uint8_t max_req_queues;
3519 uint8_t max_rsp_queues;
3520 uint8_t max_qpairs;
3521 uint8_t num_qpairs;
3522 struct qla_qpair *base_qpair;
3523 struct qla_npiv_entry *npiv_info;
3524 uint16_t nvram_npiv_size;
3525
3526 uint16_t switch_cap;
3527#define FLOGI_SEQ_DEL BIT_8
3528#define FLOGI_MID_SUPPORT BIT_10
3529#define FLOGI_VSAN_SUPPORT BIT_12
3530#define FLOGI_SP_SUPPORT BIT_13
3531
3532 uint8_t port_no;
3533 uint8_t exch_starvation;
3534
3535
3536 uint8_t loop_down_abort_time;
3537 atomic_t loop_down_timer;
3538 uint8_t link_down_timeout;
3539 uint16_t max_loop_id;
3540 uint16_t max_fibre_devices;
3541
3542 uint16_t fb_rev;
3543 uint16_t min_external_loopid;
3544
3545#define PORT_SPEED_UNKNOWN 0xFFFF
3546#define PORT_SPEED_1GB 0x00
3547#define PORT_SPEED_2GB 0x01
3548#define PORT_SPEED_4GB 0x03
3549#define PORT_SPEED_8GB 0x04
3550#define PORT_SPEED_16GB 0x05
3551#define PORT_SPEED_32GB 0x06
3552#define PORT_SPEED_10GB 0x13
3553 uint16_t link_data_rate;
3554
3555 uint8_t current_topology;
3556 uint8_t prev_topology;
3557#define ISP_CFG_NL 1
3558#define ISP_CFG_N 2
3559#define ISP_CFG_FL 4
3560#define ISP_CFG_F 8
3561
3562 uint8_t operating_mode;
3563#define LOOP 0
3564#define P2P 1
3565#define LOOP_P2P 2
3566#define P2P_LOOP 3
3567 uint8_t interrupts_on;
3568 uint32_t isp_abort_cnt;
3569#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3570#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3571#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3572#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3573#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3574#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3575#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3576#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3577
3578 uint32_t isp_type;
3579#define DT_ISP2100 BIT_0
3580#define DT_ISP2200 BIT_1
3581#define DT_ISP2300 BIT_2
3582#define DT_ISP2312 BIT_3
3583#define DT_ISP2322 BIT_4
3584#define DT_ISP6312 BIT_5
3585#define DT_ISP6322 BIT_6
3586#define DT_ISP2422 BIT_7
3587#define DT_ISP2432 BIT_8
3588#define DT_ISP5422 BIT_9
3589#define DT_ISP5432 BIT_10
3590#define DT_ISP2532 BIT_11
3591#define DT_ISP8432 BIT_12
3592#define DT_ISP8001 BIT_13
3593#define DT_ISP8021 BIT_14
3594#define DT_ISP2031 BIT_15
3595#define DT_ISP8031 BIT_16
3596#define DT_ISPFX00 BIT_17
3597#define DT_ISP8044 BIT_18
3598#define DT_ISP2071 BIT_19
3599#define DT_ISP2271 BIT_20
3600#define DT_ISP2261 BIT_21
3601#define DT_ISP_LAST (DT_ISP2261 << 1)
3602
3603 uint32_t device_type;
3604#define DT_T10_PI BIT_25
3605#define DT_IIDMA BIT_26
3606#define DT_FWI2 BIT_27
3607#define DT_ZIO_SUPPORTED BIT_28
3608#define DT_OEM_001 BIT_29
3609#define DT_ISP2200A BIT_30
3610#define DT_EXTENDED_IDS BIT_31
3611
3612#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3613#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3614#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3615#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3616#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3617#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3618#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3619#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3620#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3621#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3622#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3623#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3624#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3625#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3626#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3627#define IS_QLA81XX(ha) (IS_QLA8001(ha))
3628#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3629#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3630#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3631#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3632#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3633#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3634#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3635#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3636
3637#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3638 IS_QLA6312(ha) || IS_QLA6322(ha))
3639#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3640#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3641#define IS_QLA25XX(ha) (IS_QLA2532(ha))
3642#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3643#define IS_QLA84XX(ha) (IS_QLA8432(ha))
3644#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3645#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3646 IS_QLA84XX(ha))
3647#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3648 IS_QLA8031(ha) || IS_QLA8044(ha))
3649#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3650#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3651 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3652 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3653 IS_QLA8044(ha) || IS_QLA27XX(ha))
3654#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3655 IS_QLA27XX(ha))
3656#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3657#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3658 IS_QLA27XX(ha))
3659#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3660 IS_QLA27XX(ha))
3661#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3662
3663#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3664#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3665#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3666#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3667#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3668#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3669#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3670#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3671 IS_QLA27XX(ha))
3672#define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3673
3674#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3675 ((ha)->fw_attributes_ext[0] & BIT_0))
3676#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3677#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3678#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3679#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3680#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3681 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3682#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3683#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3684#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3685#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3686#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3687#define IS_EXCHG_OFFLD_CAPABLE(ha) \
3688 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3689#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3690 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3691
3692
3693 uint8_t serial0;
3694 uint8_t serial1;
3695 uint8_t serial2;
3696
3697
3698#define MAX_NVRAM_SIZE 4096
3699#define VPD_OFFSET MAX_NVRAM_SIZE / 2
3700 uint16_t nvram_size;
3701 uint16_t nvram_base;
3702 void *nvram;
3703 uint16_t vpd_size;
3704 uint16_t vpd_base;
3705 void *vpd;
3706
3707 uint16_t loop_reset_delay;
3708 uint8_t retry_count;
3709 uint8_t login_timeout;
3710 uint16_t r_a_tov;
3711 int port_down_retry_count;
3712 uint8_t mbx_count;
3713 uint8_t aen_mbx_count;
3714
3715 uint32_t login_retry_count;
3716
3717 ms_iocb_entry_t *ms_iocb;
3718 dma_addr_t ms_iocb_dma;
3719 struct ct_sns_pkt *ct_sns;
3720 dma_addr_t ct_sns_dma;
3721
3722 struct sns_cmd_pkt *sns_cmd;
3723 dma_addr_t sns_cmd_dma;
3724
3725#define SFP_DEV_SIZE 512
3726#define SFP_BLOCK_SIZE 64
3727 void *sfp_data;
3728 dma_addr_t sfp_data_dma;
3729
3730#define XGMAC_DATA_SIZE 4096
3731 void *xgmac_data;
3732 dma_addr_t xgmac_data_dma;
3733
3734#define DCBX_TLV_DATA_SIZE 4096
3735 void *dcbx_tlv;
3736 dma_addr_t dcbx_tlv_dma;
3737
3738 struct task_struct *dpc_thread;
3739 uint8_t dpc_active;
3740
3741 dma_addr_t gid_list_dma;
3742 struct gid_list_info *gid_list;
3743 int gid_list_info_size;
3744
3745
3746#define DMA_POOL_SIZE 256
3747 struct dma_pool *s_dma_pool;
3748
3749 dma_addr_t init_cb_dma;
3750 init_cb_t *init_cb;
3751 int init_cb_size;
3752 dma_addr_t ex_init_cb_dma;
3753 struct ex_init_cb_81xx *ex_init_cb;
3754
3755 void *async_pd;
3756 dma_addr_t async_pd_dma;
3757
3758#define ENABLE_EXTENDED_LOGIN BIT_7
3759
3760
3761 void *exlogin_buf;
3762 dma_addr_t exlogin_buf_dma;
3763 int exlogin_size;
3764
3765#define ENABLE_EXCHANGE_OFFLD BIT_2
3766
3767
3768 void *exchoffld_buf;
3769 dma_addr_t exchoffld_buf_dma;
3770 int exchoffld_size;
3771 int exchoffld_count;
3772
3773 void *swl;
3774
3775
3776 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3777 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3778 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3779
3780 mbx_cmd_t *mcp;
3781 struct mbx_cmd_32 *mcp32;
3782
3783 unsigned long mbx_cmd_flags;
3784#define MBX_INTERRUPT 1
3785#define MBX_INTR_WAIT 2
3786#define MBX_UPDATE_FLASH_ACTIVE 3
3787
3788 struct mutex vport_lock;
3789 spinlock_t vport_slock;
3790 struct mutex mq_lock;
3791 struct completion mbx_cmd_comp;
3792 struct completion mbx_intr_comp;
3793 struct completion dcbx_comp;
3794 struct completion lb_portup_comp;
3795
3796#define DCBX_COMP_TIMEOUT 20
3797#define LB_PORTUP_COMP_TIMEOUT 10
3798
3799 int notify_dcbx_comp;
3800 int notify_lb_portup_comp;
3801 struct mutex selflogin_lock;
3802
3803
3804 uint16_t fw_major_version;
3805 uint16_t fw_minor_version;
3806 uint16_t fw_subminor_version;
3807 uint16_t fw_attributes;
3808 uint16_t fw_attributes_h;
3809 uint16_t fw_attributes_ext[2];
3810 uint32_t fw_memory_size;
3811 uint32_t fw_transfer_size;
3812 uint32_t fw_srisc_address;
3813#define RISC_START_ADDRESS_2100 0x1000
3814#define RISC_START_ADDRESS_2300 0x800
3815#define RISC_START_ADDRESS_2400 0x100000
3816
3817 uint16_t orig_fw_tgt_xcb_count;
3818 uint16_t cur_fw_tgt_xcb_count;
3819 uint16_t orig_fw_xcb_count;
3820 uint16_t cur_fw_xcb_count;
3821 uint16_t orig_fw_iocb_count;
3822 uint16_t cur_fw_iocb_count;
3823 uint16_t fw_max_fcf_count;
3824
3825 uint32_t fw_shared_ram_start;
3826 uint32_t fw_shared_ram_end;
3827 uint32_t fw_ddr_ram_start;
3828 uint32_t fw_ddr_ram_end;
3829
3830 uint16_t fw_options[16];
3831 uint8_t fw_seriallink_options[4];
3832 uint16_t fw_seriallink_options24[4];
3833
3834 uint8_t mpi_version[3];
3835 uint32_t mpi_capabilities;
3836 uint8_t phy_version[3];
3837 uint8_t pep_version[3];
3838
3839
3840 void *fw_dump_template;
3841 uint32_t fw_dump_template_len;
3842
3843 struct qla2xxx_fw_dump *fw_dump;
3844 uint32_t fw_dump_len;
3845 int fw_dumped;
3846 unsigned long fw_dump_cap_flags;
3847#define RISC_PAUSE_CMPL 0
3848#define DMA_SHUTDOWN_CMPL 1
3849#define ISP_RESET_CMPL 2
3850#define RISC_RDY_AFT_RESET 3
3851#define RISC_SRAM_DUMP_CMPL 4
3852#define RISC_EXT_MEM_DUMP_CMPL 5
3853#define ISP_MBX_RDY 6
3854#define ISP_SOFT_RESET_CMPL 7
3855 int fw_dump_reading;
3856 int prev_minidump_failed;
3857 dma_addr_t eft_dma;
3858 void *eft;
3859
3860#define MCTP_DUMP_SIZE 0x086064
3861 dma_addr_t mctp_dump_dma;
3862 void *mctp_dump;
3863 int mctp_dumped;
3864 int mctp_dump_reading;
3865 uint32_t chain_offset;
3866 struct dentry *dfs_dir;
3867 struct dentry *dfs_fce;
3868 struct dentry *dfs_tgt_counters;
3869 struct dentry *dfs_fw_resource_cnt;
3870
3871 dma_addr_t fce_dma;
3872 void *fce;
3873 uint32_t fce_bufs;
3874 uint16_t fce_mb[8];
3875 uint64_t fce_wr, fce_rd;
3876 struct mutex fce_mutex;
3877
3878 uint32_t pci_attr;
3879 uint16_t chip_revision;
3880
3881 uint16_t product_id[4];
3882
3883 uint8_t model_number[16+1];
3884#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3885 char model_desc[80];
3886 uint8_t adapter_id[16+1];
3887
3888
3889 char *optrom_buffer;
3890 uint32_t optrom_size;
3891 int optrom_state;
3892#define QLA_SWAITING 0
3893#define QLA_SREADING 1
3894#define QLA_SWRITING 2
3895 uint32_t optrom_region_start;
3896 uint32_t optrom_region_size;
3897 struct mutex optrom_mutex;
3898
3899
3900#define ROM_CODE_TYPE_BIOS 0
3901#define ROM_CODE_TYPE_FCODE 1
3902#define ROM_CODE_TYPE_EFI 3
3903 uint8_t bios_revision[2];
3904 uint8_t efi_revision[2];
3905 uint8_t fcode_revision[16];
3906 uint32_t fw_revision[4];
3907
3908 uint32_t gold_fw_version[4];
3909
3910
3911 uint32_t flash_conf_off;
3912 uint32_t flash_data_off;
3913 uint32_t nvram_conf_off;
3914 uint32_t nvram_data_off;
3915
3916 uint32_t fdt_wrt_disable;
3917 uint32_t fdt_wrt_enable;
3918 uint32_t fdt_erase_cmd;
3919 uint32_t fdt_block_size;
3920 uint32_t fdt_unprotect_sec_cmd;
3921 uint32_t fdt_protect_sec_cmd;
3922 uint32_t fdt_wrt_sts_reg_cmd;
3923
3924 uint32_t flt_region_flt;
3925 uint32_t flt_region_fdt;
3926 uint32_t flt_region_boot;
3927 uint32_t flt_region_boot_sec;
3928 uint32_t flt_region_fw;
3929 uint32_t flt_region_fw_sec;
3930 uint32_t flt_region_vpd_nvram;
3931 uint32_t flt_region_vpd;
3932 uint32_t flt_region_vpd_sec;
3933 uint32_t flt_region_nvram;
3934 uint32_t flt_region_npiv_conf;
3935 uint32_t flt_region_gold_fw;
3936 uint32_t flt_region_fcp_prio;
3937 uint32_t flt_region_bootload;
3938 uint32_t flt_region_img_status_pri;
3939 uint32_t flt_region_img_status_sec;
3940 uint8_t active_image;
3941
3942
3943 uint16_t beacon_blink_led;
3944 uint8_t beacon_color_state;
3945#define QLA_LED_GRN_ON 0x01
3946#define QLA_LED_YLW_ON 0x02
3947#define QLA_LED_ABR_ON 0x04
3948#define QLA_LED_ALL_ON 0x07
3949
3950 uint16_t zio_mode;
3951 uint16_t zio_timer;
3952
3953 struct qla_msix_entry *msix_entries;
3954
3955 struct list_head vp_list;
3956 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3957 sizeof(unsigned long)];
3958 uint16_t num_vhosts;
3959 uint16_t num_vsans;
3960 uint16_t max_npiv_vports;
3961 int cur_vport_count;
3962
3963 struct qla_chip_state_84xx *cs84xx;
3964 struct isp_operations *isp_ops;
3965 struct workqueue_struct *wq;
3966 struct qlfc_fw fw_buf;
3967
3968
3969 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3970
3971 struct dma_pool *dl_dma_pool;
3972#define DSD_LIST_DMA_POOL_SIZE 512
3973
3974 struct dma_pool *fcp_cmnd_dma_pool;
3975 mempool_t *ctx_mempool;
3976#define FCP_CMND_DMA_POOL_SIZE 512
3977
3978 void __iomem *nx_pcibase;
3979 void __iomem *nxdb_rd_ptr;
3980 void __iomem *nxdb_wr_ptr;
3981
3982 uint32_t crb_win;
3983 uint32_t curr_window;
3984 uint32_t ddr_mn_window;
3985 unsigned long mn_win_crb;
3986 unsigned long ms_win_crb;
3987 int qdr_sn_window;
3988 uint32_t fcoe_dev_init_timeout;
3989 uint32_t fcoe_reset_timeout;
3990 rwlock_t hw_lock;
3991 uint16_t portnum;
3992 int link_width;
3993 struct fw_blob *hablob;
3994 struct qla82xx_legacy_intr_set nx_legacy_intr;
3995
3996 uint16_t gbl_dsd_inuse;
3997 uint16_t gbl_dsd_avail;
3998 struct list_head gbl_dsd_list;
3999#define NUM_DSD_CHAIN 4096
4000
4001 uint8_t fw_type;
4002 __le32 file_prd_off;
4003
4004 uint32_t md_template_size;
4005 void *md_tmplt_hdr;
4006 dma_addr_t md_tmplt_hdr_dma;
4007 void *md_dump;
4008 uint32_t md_dump_size;
4009
4010 void *loop_id_map;
4011
4012
4013 uint32_t idc_audit_ts;
4014 uint32_t idc_extend_tmo;
4015
4016
4017 struct workqueue_struct *dpc_lp_wq;
4018 struct work_struct idc_aen;
4019
4020 struct workqueue_struct *dpc_hp_wq;
4021 struct work_struct nic_core_reset;
4022 struct work_struct idc_state_handler;
4023 struct work_struct nic_core_unrecoverable;
4024 struct work_struct board_disable;
4025
4026 struct mr_data_fx00 mr;
4027
4028 struct qlt_hw_data tgt;
4029 int allow_cna_fw_dump;
4030 uint32_t fw_ability_mask;
4031 uint16_t min_link_speed;
4032 uint16_t max_speed_sup;
4033
4034 atomic_t nvme_active_aen_cnt;
4035 uint16_t nvme_last_rptd_aen;
4036};
4037
4038#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4039#define FW_ABILITY_MAX_SPEED_16G 0x0
4040#define FW_ABILITY_MAX_SPEED_32G 0x1
4041#define FW_ABILITY_MAX_SPEED(ha) \
4042 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4043
4044
4045
4046
4047typedef struct scsi_qla_host {
4048 struct list_head list;
4049 struct list_head vp_fcports;
4050 struct list_head work_list;
4051 spinlock_t work_lock;
4052 struct work_struct iocb_work;
4053
4054
4055 struct Scsi_Host *host;
4056 unsigned long host_no;
4057 uint8_t host_str[16];
4058
4059 volatile struct {
4060 uint32_t init_done :1;
4061 uint32_t online :1;
4062 uint32_t reset_active :1;
4063
4064 uint32_t management_server_logged_in :1;
4065 uint32_t process_response_queue :1;
4066 uint32_t difdix_supported:1;
4067 uint32_t delete_progress:1;
4068
4069 uint32_t fw_tgt_reported:1;
4070 uint32_t bbcr_enable:1;
4071 uint32_t qpairs_available:1;
4072 uint32_t qpairs_req_created:1;
4073 uint32_t qpairs_rsp_created:1;
4074 uint32_t nvme_enabled:1;
4075 } flags;
4076
4077 atomic_t loop_state;
4078#define LOOP_TIMEOUT 1
4079#define LOOP_DOWN 2
4080#define LOOP_UP 3
4081#define LOOP_UPDATE 4
4082#define LOOP_READY 5
4083#define LOOP_DEAD 6
4084
4085 unsigned long dpc_flags;
4086#define RESET_MARKER_NEEDED 0
4087#define RESET_ACTIVE 1
4088#define ISP_ABORT_NEEDED 2
4089#define ABORT_ISP_ACTIVE 3
4090#define LOOP_RESYNC_NEEDED 4
4091#define LOOP_RESYNC_ACTIVE 5
4092#define LOCAL_LOOP_UPDATE 6
4093#define RSCN_UPDATE 7
4094#define RELOGIN_NEEDED 8
4095#define REGISTER_FC4_NEEDED 9
4096#define ISP_ABORT_RETRY 10
4097#define BEACON_BLINK_NEEDED 11
4098#define REGISTER_FDMI_NEEDED 12
4099#define FCPORT_UPDATE_NEEDED 13
4100#define VP_DPC_NEEDED 14
4101#define UNLOADING 15
4102#define NPIV_CONFIG_NEEDED 16
4103#define ISP_UNRECOVERABLE 17
4104#define FCOE_CTX_RESET_NEEDED 18
4105#define MPI_RESET_NEEDED 19
4106#define ISP_QUIESCE_NEEDED 20
4107#define FREE_BIT 21
4108#define PORT_UPDATE_NEEDED 22
4109#define FX00_RESET_RECOVERY 23
4110#define FX00_TARGET_SCAN 24
4111#define FX00_CRITEMP_RECOVERY 25
4112#define FX00_HOST_INFO_RESEND 26
4113#define QPAIR_ONLINE_CHECK_NEEDED 27
4114#define SET_ZIO_THRESHOLD_NEEDED 28
4115#define DETECT_SFP_CHANGE 29
4116
4117 unsigned long pci_flags;
4118#define PFLG_DISCONNECTED 0
4119#define PFLG_DRIVER_REMOVING 1
4120#define PFLG_DRIVER_PROBING 2
4121
4122 uint32_t device_flags;
4123#define SWITCH_FOUND BIT_0
4124#define DFLG_NO_CABLE BIT_1
4125#define DFLG_DEV_FAILED BIT_5
4126
4127
4128 uint16_t loop_id;
4129 uint16_t self_login_loop_id;
4130
4131
4132 fc_port_t bidir_fcport;
4133
4134
4135
4136
4137 port_id_t d_id;
4138 uint8_t marker_needed;
4139 uint16_t mgmt_svr_loop_id;
4140
4141
4142
4143
4144 uint8_t loop_down_abort_time;
4145 atomic_t loop_down_timer;
4146 uint8_t link_down_timeout;
4147
4148 uint32_t timer_active;
4149 struct timer_list timer;
4150
4151 uint8_t node_name[WWN_SIZE];
4152 uint8_t port_name[WWN_SIZE];
4153 uint8_t fabric_node_name[WWN_SIZE];
4154
4155 struct nvme_fc_local_port *nvme_local_port;
4156 struct completion nvme_del_done;
4157 struct list_head nvme_rport_list;
4158 atomic_t nvme_active_aen_cnt;
4159 uint16_t nvme_last_rptd_aen;
4160
4161 uint16_t fcoe_vlan_id;
4162 uint16_t fcoe_fcf_idx;
4163 uint8_t fcoe_vn_port_mac[6];
4164
4165
4166 struct list_head qla_cmd_list;
4167 struct list_head qla_sess_op_cmd_list;
4168 struct list_head unknown_atio_list;
4169 spinlock_t cmd_list_lock;
4170 struct delayed_work unknown_atio_work;
4171
4172
4173 atomic_t generation_tick;
4174
4175 int total_fcport_update_gen;
4176
4177 struct list_head logo_list;
4178
4179 struct list_head plogi_ack_list;
4180
4181 struct list_head qp_list;
4182
4183 uint32_t vp_abort_cnt;
4184
4185 struct fc_vport *fc_vport;
4186 uint16_t vp_idx;
4187 struct qla_qpair *qpair;
4188
4189 unsigned long vp_flags;
4190#define VP_IDX_ACQUIRED 0
4191#define VP_CREATE_NEEDED 1
4192#define VP_BIND_NEEDED 2
4193#define VP_DELETE_NEEDED 3
4194#define VP_SCR_NEEDED 4
4195#define VP_CONFIG_OK 5
4196 atomic_t vp_state;
4197#define VP_OFFLINE 0
4198#define VP_ACTIVE 1
4199#define VP_FAILED 2
4200
4201 uint16_t vp_err_state;
4202 uint16_t vp_prev_err_state;
4203#define VP_ERR_UNKWN 0
4204#define VP_ERR_PORTDWN 1
4205#define VP_ERR_FAB_UNSUPPORTED 2
4206#define VP_ERR_FAB_NORESOURCES 3
4207#define VP_ERR_FAB_LOGOUT 4
4208#define VP_ERR_ADAP_NORESOURCES 5
4209 struct qla_hw_data *hw;
4210 struct scsi_qlt_host vha_tgt;
4211 struct req_que *req;
4212 int fw_heartbeat_counter;
4213 int seconds_since_last_heartbeat;
4214 struct fc_host_statistics fc_host_stat;
4215 struct qla_statistics qla_stats;
4216 struct bidi_statistics bidi_stats;
4217 atomic_t vref_count;
4218 struct qla8044_reset_template reset_tmplt;
4219 uint16_t bbcr;
4220 struct name_list_extended gnl;
4221
4222 int fcport_count;
4223 wait_queue_head_t fcport_waitQ;
4224 wait_queue_head_t vref_waitq;
4225 uint8_t min_link_speed_feat;
4226} scsi_qla_host_t;
4227
4228struct qla27xx_image_status {
4229 uint8_t image_status_mask;
4230 uint16_t generation_number;
4231 uint8_t reserved[3];
4232 uint8_t ver_minor;
4233 uint8_t ver_major;
4234 uint32_t checksum;
4235 uint32_t signature;
4236} __packed;
4237
4238#define SET_VP_IDX 1
4239#define SET_AL_PA 2
4240#define RESET_VP_IDX 3
4241#define RESET_AL_PA 4
4242struct qla_tgt_vp_map {
4243 uint8_t idx;
4244 scsi_qla_host_t *vha;
4245};
4246
4247struct qla2_sgx {
4248 dma_addr_t dma_addr;
4249 uint32_t dma_len;
4250
4251 uint32_t tot_bytes;
4252 struct scatterlist *cur_sg;
4253
4254
4255 uint32_t bytes_consumed;
4256 uint32_t num_bytes;
4257 uint32_t tot_partial;
4258
4259
4260 uint32_t num_sg;
4261 srb_t *sp;
4262};
4263
4264#define QLA_FW_STARTED(_ha) { \
4265 int i; \
4266 _ha->flags.fw_started = 1; \
4267 _ha->base_qpair->fw_started = 1; \
4268 for (i = 0; i < _ha->max_qpairs; i++) { \
4269 if (_ha->queue_pair_map[i]) \
4270 _ha->queue_pair_map[i]->fw_started = 1; \
4271 } \
4272}
4273
4274#define QLA_FW_STOPPED(_ha) { \
4275 int i; \
4276 _ha->flags.fw_started = 0; \
4277 _ha->base_qpair->fw_started = 0; \
4278 for (i = 0; i < _ha->max_qpairs; i++) { \
4279 if (_ha->queue_pair_map[i]) \
4280 _ha->queue_pair_map[i]->fw_started = 0; \
4281 } \
4282}
4283
4284
4285
4286
4287#define LOOP_TRANSITION(ha) \
4288 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4289 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4290 atomic_read(&ha->loop_state) == LOOP_DOWN)
4291
4292#define STATE_TRANSITION(ha) \
4293 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4294 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4295
4296#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4297 atomic_inc(&__vha->vref_count); \
4298 mb(); \
4299 if (__vha->flags.delete_progress) { \
4300 atomic_dec(&__vha->vref_count); \
4301 wake_up(&__vha->vref_waitq); \
4302 __bail = 1; \
4303 } else { \
4304 __bail = 0; \
4305 } \
4306} while (0)
4307
4308#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4309 atomic_dec(&__vha->vref_count); \
4310 wake_up(&__vha->vref_waitq); \
4311} while (0) \
4312
4313#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4314 atomic_inc(&__qpair->ref_count); \
4315 mb(); \
4316 if (__qpair->delete_in_progress) { \
4317 atomic_dec(&__qpair->ref_count); \
4318 __bail = 1; \
4319 } else { \
4320 __bail = 0; \
4321 } \
4322} while (0)
4323
4324#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4325 atomic_dec(&__qpair->ref_count); \
4326
4327
4328#define QLA_ENA_CONF(_ha) {\
4329 int i;\
4330 _ha->base_qpair->enable_explicit_conf = 1; \
4331 for (i = 0; i < _ha->max_qpairs; i++) { \
4332 if (_ha->queue_pair_map[i]) \
4333 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4334 } \
4335}
4336
4337#define QLA_DIS_CONF(_ha) {\
4338 int i;\
4339 _ha->base_qpair->enable_explicit_conf = 0; \
4340 for (i = 0; i < _ha->max_qpairs; i++) { \
4341 if (_ha->queue_pair_map[i]) \
4342 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4343 } \
4344}
4345
4346
4347
4348
4349#define MBS_MASK 0x3fff
4350
4351#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4352#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4353#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4354#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4355#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4356#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4357#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4358#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4359#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4360#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4361
4362#define QLA_FUNCTION_TIMEOUT 0x100
4363#define QLA_FUNCTION_PARAMETER_ERROR 0x101
4364#define QLA_FUNCTION_FAILED 0x102
4365#define QLA_MEMORY_ALLOC_FAILED 0x103
4366#define QLA_LOCK_TIMEOUT 0x104
4367#define QLA_ABORTED 0x105
4368#define QLA_SUSPENDED 0x106
4369#define QLA_BUSY 0x107
4370#define QLA_ALREADY_REGISTERED 0x109
4371
4372#define NVRAM_DELAY() udelay(10)
4373
4374
4375
4376
4377#define OPTROM_SIZE_2300 0x20000
4378#define OPTROM_SIZE_2322 0x100000
4379#define OPTROM_SIZE_24XX 0x100000
4380#define OPTROM_SIZE_25XX 0x200000
4381#define OPTROM_SIZE_81XX 0x400000
4382#define OPTROM_SIZE_82XX 0x800000
4383#define OPTROM_SIZE_83XX 0x1000000
4384
4385#define OPTROM_BURST_SIZE 0x1000
4386#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4387
4388#define QLA_DSDS_PER_IOCB 37
4389
4390#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4391
4392#define QLA_SG_ALL 1024
4393
4394enum nexus_wait_type {
4395 WAIT_HOST = 0,
4396 WAIT_TARGET,
4397 WAIT_LUN,
4398};
4399
4400
4401struct sff_8247_a0 {
4402 u8 txid;
4403 u8 ext_txid;
4404 u8 connector;
4405
4406 u8 eth_infi_cc3;
4407 u8 sonet_cc4[2];
4408 u8 eth_cc6;
4409
4410#define FC_LL_VL BIT_7
4411#define FC_LL_S BIT_6
4412#define FC_LL_I BIT_5
4413#define FC_LL_L BIT_4
4414#define FC_LL_M BIT_3
4415#define FC_LL_SA BIT_2
4416#define FC_LL_LC BIT_1
4417#define FC_LL_EL BIT_0
4418 u8 fc_ll_cc7;
4419
4420#define FC_TEC_EL BIT_7
4421#define FC_TEC_SN BIT_6
4422#define FC_TEC_SL BIT_5
4423#define FC_TEC_LL BIT_4
4424#define FC_TEC_ACT BIT_3
4425#define FC_TEC_PAS BIT_2
4426 u8 fc_tec_cc8;
4427
4428#define FC_MED_TW BIT_7
4429#define FC_MED_TP BIT_6
4430#define FC_MED_MI BIT_5
4431#define FC_MED_TV BIT_4
4432#define FC_MED_M6 BIT_3
4433#define FC_MED_M5 BIT_2
4434#define FC_MED_SM BIT_0
4435 u8 fc_med_cc9;
4436
4437#define FC_SP_12 BIT_7
4438#define FC_SP_8 BIT_6
4439#define FC_SP_16 BIT_5
4440#define FC_SP_4 BIT_4
4441#define FC_SP_32 BIT_3
4442#define FC_SP_2 BIT_2
4443#define FC_SP_1 BIT_0
4444 u8 fc_sp_cc10;
4445 u8 encode;
4446 u8 bitrate;
4447 u8 rate_id;
4448 u8 length_km;
4449 u8 length_100m;
4450 u8 length_50um_10m;
4451 u8 length_62um_10m;
4452 u8 length_om4_10m;
4453 u8 length_om3_10m;
4454#define SFF_VEN_NAME_LEN 16
4455 u8 vendor_name[SFF_VEN_NAME_LEN];
4456 u8 tx_compat;
4457 u8 vendor_oui[3];
4458#define SFF_PART_NAME_LEN 16
4459 u8 vendor_pn[SFF_PART_NAME_LEN];
4460 u8 vendor_rev[4];
4461 u8 wavelength[2];
4462 u8 resv;
4463 u8 cc_base;
4464 u8 options[2];
4465 u8 br_max;
4466 u8 br_min;
4467 u8 vendor_sn[16];
4468 u8 date_code[8];
4469 u8 diag;
4470 u8 enh_options;
4471 u8 sff_revision;
4472 u8 cc_ext;
4473 u8 vendor_specific[32];
4474 u8 resv2[128];
4475};
4476
4477#define AUTO_DETECT_SFP_SUPPORT(_vha)\
4478 (ql2xautodetectsfp && !_vha->vp_idx && \
4479 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4480 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw)))
4481
4482#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4483 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha)))
4484
4485#include "qla_target.h"
4486#include "qla_gbl.h"
4487#include "qla_dbg.h"
4488#include "qla_inline.h"
4489#endif
4490