LXR linux/drivers/scsi/ufs/ufshci.h

   1/*
   2 * Universal Flash Storage Host controller driver
   3 *
   4 * This code is based on drivers/scsi/ufs/ufshci.h
   5 * Copyright (C) 2011-2013 Samsung India Software Operations
   6 *
   7 * Authors:
   8 *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9 *      Vinayak Holikatti <h.vinayak@samsung.com>
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License
  13 * as published by the Free Software Foundation; either version 2
  14 * of the License, or (at your option) any later version.
  15 * See the COPYING file in the top-level directory or visit
  16 * <http://www.gnu.org/licenses/gpl-2.0.html>
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
  24 * without warranty of any kind. You are solely responsible for
  25 * determining the appropriateness of using and distributing
  26 * the program and assume all risks associated with your exercise
  27 * of rights with respect to the program, including but not limited
  28 * to infringement of third party rights, the risks and costs of
  29 * program errors, damage to or loss of data, programs or equipment,
  30 * and unavailability or interruption of operations. Under no
  31 * circumstances will the contributor of this Program be liable for
  32 * any damages of any kind arising from your use or distribution of
  33 * this program.
  34 */
  35
  36#ifndef _UFSHCI_H
  37#define _UFSHCI_H
  38
  39enum {
  40        TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  41        TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  42        ALIGNED_UPIU_SIZE               = 512,
  43};
  44
  45/* UFSHCI Registers */
  46enum {
  47        REG_CONTROLLER_CAPABILITIES             = 0x00,
  48        REG_UFS_VERSION                         = 0x08,
  49        REG_CONTROLLER_DEV_ID                   = 0x10,
  50        REG_CONTROLLER_PROD_ID                  = 0x14,
  51        REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
  52        REG_INTERRUPT_STATUS                    = 0x20,
  53        REG_INTERRUPT_ENABLE                    = 0x24,
  54        REG_CONTROLLER_STATUS                   = 0x30,
  55        REG_CONTROLLER_ENABLE                   = 0x34,
  56        REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  57        REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  58        REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  59        REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  60        REG_UIC_ERROR_CODE_DME                  = 0x48,
  61        REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  62        REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  63        REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  64        REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  65        REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  66        REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  67        REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  68        REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  69        REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  70        REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  71        REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  72        REG_UIC_COMMAND                         = 0x90,
  73        REG_UIC_COMMAND_ARG_1                   = 0x94,
  74        REG_UIC_COMMAND_ARG_2                   = 0x98,
  75        REG_UIC_COMMAND_ARG_3                   = 0x9C,
  76
  77        UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  78
  79        REG_UFS_CCAP                            = 0x100,
  80        REG_UFS_CRYPTOCAP                       = 0x104,
  81
  82        UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  83};
  84
  85/* Controller capability masks */
  86enum {
  87        MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  88        MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  89        MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  90        MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  91        MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  92};
  93
  94#define UFS_MASK(mask, offset)          ((mask) << (offset))
  95
  96/* UFS Version 08h */
  97#define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
  98#define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
  99
 100/* Controller UFSHCI version */
 101enum {
 102        UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
 103        UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
 104        UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
 105        UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
 106};
 107
 108/*
 109 * HCDDID - Host Controller Identification Descriptor
 110 *        - Device ID and Device Class 10h
 111 */
 112#define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
 113#define DEVICE_ID       UFS_MASK(0xFF, 24)
 114
 115/*
 116 * HCPMID - Host Controller Identification Descriptor
 117 *        - Product/Manufacturer ID  14h
 118 */
 119#define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 120#define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 121
 122#define UFS_BIT(x)      (1L << (x))
 123
 124#define UTP_TRANSFER_REQ_COMPL                  UFS_BIT(0)
 125#define UIC_DME_END_PT_RESET                    UFS_BIT(1)
 126#define UIC_ERROR                               UFS_BIT(2)
 127#define UIC_TEST_MODE                           UFS_BIT(3)
 128#define UIC_POWER_MODE                          UFS_BIT(4)
 129#define UIC_HIBERNATE_EXIT                      UFS_BIT(5)
 130#define UIC_HIBERNATE_ENTER                     UFS_BIT(6)
 131#define UIC_LINK_LOST                           UFS_BIT(7)
 132#define UIC_LINK_STARTUP                        UFS_BIT(8)
 133#define UTP_TASK_REQ_COMPL                      UFS_BIT(9)
 134#define UIC_COMMAND_COMPL                       UFS_BIT(10)
 135#define DEVICE_FATAL_ERROR                      UFS_BIT(11)
 136#define CONTROLLER_FATAL_ERROR                  UFS_BIT(16)
 137#define SYSTEM_BUS_FATAL_ERROR                  UFS_BIT(17)
 138
 139#define UFSHCD_UIC_PWR_MASK     (UIC_HIBERNATE_ENTER |\
 140                                UIC_HIBERNATE_EXIT |\
 141                                UIC_POWER_MODE)
 142
 143#define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 144
 145#define UFSHCD_ERROR_MASK       (UIC_ERROR |\
 146                                DEVICE_FATAL_ERROR |\
 147                                CONTROLLER_FATAL_ERROR |\
 148                                SYSTEM_BUS_FATAL_ERROR)
 149
 150#define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 151                                CONTROLLER_FATAL_ERROR |\
 152                                SYSTEM_BUS_FATAL_ERROR)
 153
 154/* HCS - Host Controller Status 30h */
 155#define DEVICE_PRESENT                          UFS_BIT(0)
 156#define UTP_TRANSFER_REQ_LIST_READY             UFS_BIT(1)
 157#define UTP_TASK_REQ_LIST_READY                 UFS_BIT(2)
 158#define UIC_COMMAND_READY                       UFS_BIT(3)
 159#define HOST_ERROR_INDICATOR                    UFS_BIT(4)
 160#define DEVICE_ERROR_INDICATOR                  UFS_BIT(5)
 161#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 162
 163#define UFSHCD_STATUS_READY     (UTP_TRANSFER_REQ_LIST_READY |\
 164                                UTP_TASK_REQ_LIST_READY |\
 165                                UIC_COMMAND_READY)
 166
 167enum {
 168        PWR_OK          = 0x0,
 169        PWR_LOCAL       = 0x01,
 170        PWR_REMOTE      = 0x02,
 171        PWR_BUSY        = 0x03,
 172        PWR_ERROR_CAP   = 0x04,
 173        PWR_FATAL_ERROR = 0x05,
 174};
 175
 176/* HCE - Host Controller Enable 34h */
 177#define CONTROLLER_ENABLE       UFS_BIT(0)
 178#define CONTROLLER_DISABLE      0x0
 179#define CRYPTO_GENERAL_ENABLE   UFS_BIT(1)
 180
 181/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 182#define UIC_PHY_ADAPTER_LAYER_ERROR                     UFS_BIT(31)
 183#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 184#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 185
 186/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 187#define UIC_DATA_LINK_LAYER_ERROR               UFS_BIT(31)
 188#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0x7FFF
 189#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       0x2000
 190#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 191#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 192
 193/* UECN - Host UIC Error Code Network Layer 40h */
 194#define UIC_NETWORK_LAYER_ERROR                 UFS_BIT(31)
 195#define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 196
 197/* UECT - Host UIC Error Code Transport Layer 44h */
 198#define UIC_TRANSPORT_LAYER_ERROR               UFS_BIT(31)
 199#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 200
 201/* UECDME - Host UIC Error Code DME 48h */
 202#define UIC_DME_ERROR                   UFS_BIT(31)
 203#define UIC_DME_ERROR_CODE_MASK         0x1
 204
 205#define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 206#define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 207#define INT_AGGR_COUNTER_AND_TIMER_RESET        UFS_BIT(16)
 208#define INT_AGGR_STATUS_BIT                     UFS_BIT(20)
 209#define INT_AGGR_PARAM_WRITE                    UFS_BIT(24)
 210#define INT_AGGR_ENABLE                         UFS_BIT(31)
 211
 212/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 213#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      UFS_BIT(0)
 214
 215/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 216#define UTP_TASK_REQ_LIST_RUN_STOP_BIT          UFS_BIT(0)
 217
 218/* UICCMD - UIC Command */
 219#define COMMAND_OPCODE_MASK             0xFF
 220#define GEN_SELECTOR_INDEX_MASK         0xFFFF
 221
 222#define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 223#define RESET_LEVEL                     0xFF
 224
 225#define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 226#define CONFIG_RESULT_CODE_MASK         0xFF
 227#define GENERIC_ERROR_CODE_MASK         0xFF
 228
 229/* GenSelectorIndex calculation macros for M-PHY attributes */
 230#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 231#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 232
 233#define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 234                                         ((sel) & 0xFFFF))
 235#define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 236#define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 237#define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 238
 239/* Link Status*/
 240enum link_status {
 241        UFSHCD_LINK_IS_DOWN     = 1,
 242        UFSHCD_LINK_IS_UP       = 2,
 243};
 244
 245/* UIC Commands */
 246enum uic_cmd_dme {
 247        UIC_CMD_DME_GET                 = 0x01,
 248        UIC_CMD_DME_SET                 = 0x02,
 249        UIC_CMD_DME_PEER_GET            = 0x03,
 250        UIC_CMD_DME_PEER_SET            = 0x04,
 251        UIC_CMD_DME_POWERON             = 0x10,
 252        UIC_CMD_DME_POWEROFF            = 0x11,
 253        UIC_CMD_DME_ENABLE              = 0x12,
 254        UIC_CMD_DME_RESET               = 0x14,
 255        UIC_CMD_DME_END_PT_RST          = 0x15,
 256        UIC_CMD_DME_LINK_STARTUP        = 0x16,
 257        UIC_CMD_DME_HIBER_ENTER         = 0x17,
 258        UIC_CMD_DME_HIBER_EXIT          = 0x18,
 259        UIC_CMD_DME_TEST_MODE           = 0x1A,
 260};
 261
 262/* UIC Config result code / Generic error code */
 263enum {
 264        UIC_CMD_RESULT_SUCCESS                  = 0x00,
 265        UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 266        UIC_CMD_RESULT_FAILURE                  = 0x01,
 267        UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 268        UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 269        UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 270        UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 271        UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 272        UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 273        UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 274        UIC_CMD_RESULT_BUSY                     = 0x09,
 275        UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 276};
 277
 278#define MASK_UIC_COMMAND_RESULT                 0xFF
 279
 280#define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 281#define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 282
 283/* Interrupt disable masks */
 284enum {
 285        /* Interrupt disable mask for UFSHCI v1.0 */
 286        INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 287        INTERRUPT_MASK_RW_VER_10        = 0x30000,
 288
 289        /* Interrupt disable mask for UFSHCI v1.1 */
 290        INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 291
 292        /* Interrupt disable mask for UFSHCI v2.1 */
 293        INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 294};
 295
 296/*
 297 * Request Descriptor Definitions
 298 */
 299
 300/* Transfer request command type */
 301enum {
 302        UTP_CMD_TYPE_SCSI               = 0x0,
 303        UTP_CMD_TYPE_UFS                = 0x1,
 304        UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 305};
 306
 307/* To accommodate UFS2.0 required Command type */
 308enum {
 309        UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 310};
 311
 312enum {
 313        UTP_SCSI_COMMAND                = 0x00000000,
 314        UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 315        UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 316        UTP_REQ_DESC_INT_CMD            = 0x01000000,
 317};
 318
 319/* UTP Transfer Request Data Direction (DD) */
 320enum {
 321        UTP_NO_DATA_TRANSFER    = 0x00000000,
 322        UTP_HOST_TO_DEVICE      = 0x02000000,
 323        UTP_DEVICE_TO_HOST      = 0x04000000,
 324};
 325
 326/* Overall command status values */
 327enum {
 328        OCS_SUCCESS                     = 0x0,
 329        OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 330        OCS_INVALID_PRDT_ATTR           = 0x2,
 331        OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 332        OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 333        OCS_PEER_COMM_FAILURE           = 0x5,
 334        OCS_ABORTED                     = 0x6,
 335        OCS_FATAL_ERROR                 = 0x7,
 336        OCS_INVALID_COMMAND_STATUS      = 0x0F,
 337        MASK_OCS                        = 0x0F,
 338};
 339
 340/* The maximum length of the data byte count field in the PRDT is 256KB */
 341#define PRDT_DATA_BYTE_COUNT_MAX        (256 * 1024)
 342/* The granularity of the data byte count field in the PRDT is 32-bit */
 343#define PRDT_DATA_BYTE_COUNT_PAD        4
 344
 345/**
 346 * struct ufshcd_sg_entry - UFSHCI PRD Entry
 347 * @base_addr: Lower 32bit physical address DW-0
 348 * @upper_addr: Upper 32bit physical address DW-1
 349 * @reserved: Reserved for future use DW-2
 350 * @size: size of physical segment DW-3
 351 */
 352struct ufshcd_sg_entry {
 353        __le32    base_addr;
 354        __le32    upper_addr;
 355        __le32    reserved;
 356        __le32    size;
 357};
 358
 359/**
 360 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
 361 * @command_upiu: Command UPIU Frame address
 362 * @response_upiu: Response UPIU Frame address
 363 * @prd_table: Physical Region Descriptor
 364 */
 365struct utp_transfer_cmd_desc {
 366        u8 command_upiu[ALIGNED_UPIU_SIZE];
 367        u8 response_upiu[ALIGNED_UPIU_SIZE];
 368        struct ufshcd_sg_entry    prd_table[SG_ALL];
 369};
 370
 371/**
 372 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 373 * @dword0: Descriptor Header DW0
 374 * @dword1: Descriptor Header DW1
 375 * @dword2: Descriptor Header DW2
 376 * @dword3: Descriptor Header DW3
 377 */
 378struct request_desc_header {
 379        __le32 dword_0;
 380        __le32 dword_1;
 381        __le32 dword_2;
 382        __le32 dword_3;
 383};
 384
 385/**
 386 * struct utp_transfer_req_desc - UTRD structure
 387 * @header: UTRD header DW-0 to DW-3
 388 * @command_desc_base_addr_lo: UCD base address low DW-4
 389 * @command_desc_base_addr_hi: UCD base address high DW-5
 390 * @response_upiu_length: response UPIU length DW-6
 391 * @response_upiu_offset: response UPIU offset DW-6
 392 * @prd_table_length: Physical region descriptor length DW-7
 393 * @prd_table_offset: Physical region descriptor offset DW-7
 394 */
 395struct utp_transfer_req_desc {
 396
 397        /* DW 0-3 */
 398        struct request_desc_header header;
 399
 400        /* DW 4-5*/
 401        __le32  command_desc_base_addr_lo;
 402        __le32  command_desc_base_addr_hi;
 403
 404        /* DW 6 */
 405        __le16  response_upiu_length;
 406        __le16  response_upiu_offset;
 407
 408        /* DW 7 */
 409        __le16  prd_table_length;
 410        __le16  prd_table_offset;
 411};
 412
 413/**
 414 * struct utp_task_req_desc - UTMRD structure
 415 * @header: UTMRD header DW-0 to DW-3
 416 * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
 417 * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
 418 */
 419struct utp_task_req_desc {
 420
 421        /* DW 0-3 */
 422        struct request_desc_header header;
 423
 424        /* DW 4-11 */
 425        __le32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
 426
 427        /* DW 12-19 */
 428        __le32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
 429};
 430
 431#endif /* End of Header */
 432