LXR linux/drivers/staging/ccree/ssi

   1/*
   2 * Copyright (C) 2012-2017 ARM Limited or its affiliates.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17/* \file ssi_hash.h
  18 * ARM CryptoCell Hash Crypto API
  19 */
  20
  21#ifndef __SSI_HASH_H__
  22#define __SSI_HASH_H__
  23
  24#include "ssi_buffer_mgr.h"
  25
  26#define HMAC_IPAD_CONST 0x36363636
  27#define HMAC_OPAD_CONST 0x5C5C5C5C
  28#if (DX_DEV_SHA_MAX > 256)
  29#define HASH_LEN_SIZE 16
  30#define SSI_MAX_HASH_DIGEST_SIZE        SHA512_DIGEST_SIZE
  31#define SSI_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE
  32#else
  33#define HASH_LEN_SIZE 8
  34#define SSI_MAX_HASH_DIGEST_SIZE        SHA256_DIGEST_SIZE
  35#define SSI_MAX_HASH_BLCK_SIZE SHA256_BLOCK_SIZE
  36#endif
  37
  38#define XCBC_MAC_K1_OFFSET 0
  39#define XCBC_MAC_K2_OFFSET 16
  40#define XCBC_MAC_K3_OFFSET 32
  41
  42#define CC_EXPORT_MAGIC 0xC2EE1070U
  43
  44// this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used for xcbc/cmac statesize
  45struct aeshash_state {
  46        u8 state[AES_BLOCK_SIZE];
  47        unsigned int count;
  48        u8 buffer[AES_BLOCK_SIZE];
  49};
  50
  51/* ahash state */
  52struct ahash_req_ctx {
  53        u8 *buff0;
  54        u8 *buff1;
  55        u8 *digest_result_buff;
  56        struct async_gen_req_ctx gen_ctx;
  57        enum ssi_req_dma_buf_type data_dma_buf_type;
  58        u8 *digest_buff;
  59        u8 *opad_digest_buff;
  60        u8 *digest_bytes_len;
  61        dma_addr_t opad_digest_dma_addr;
  62        dma_addr_t digest_buff_dma_addr;
  63        dma_addr_t digest_bytes_len_dma_addr;
  64        dma_addr_t digest_result_dma_addr;
  65        u32 buff0_cnt;
  66        u32 buff1_cnt;
  67        u32 buff_index;
  68        u32 xcbc_count; /* count xcbc update operatations */
  69        struct scatterlist buff_sg[2];
  70        struct scatterlist *curr_sg;
  71        u32 in_nents;
  72        u32 mlli_nents;
  73        struct mlli_params mlli_params;
  74};
  75
  76int ssi_hash_alloc(struct ssi_drvdata *drvdata);
  77int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata);
  78int ssi_hash_free(struct ssi_drvdata *drvdata);
  79
  80/*!
  81 * Gets the initial digest length
  82 *
  83 * \param drvdata
  84 * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
  85 *
  86 * \return u32 returns the address of the initial digest length in SRAM
  87 */
  88ssi_sram_addr_t
  89ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode);
  90
  91/*!
  92 * Gets the address of the initial digest in SRAM
  93 * according to the given hash mode
  94 *
  95 * \param drvdata
  96 * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
  97 *
  98 * \return u32 The address of the inital digest in SRAM
  99 */
 100ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode);
 101
 102#endif /*__SSI_HASH_H__*/
 103
 104