1/****************************************************************************** 2 * 3 * Copyright(c) 2016 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25#ifndef __RTL_WLAN_BITDEF_H__ 26#define __RTL_WLAN_BITDEF_H__ 27 28/*-------------------------Modification Log----------------------------------- 29 * Base on MAC_Register.doc SVN391 30 *-------------------------Modification Log----------------------------------- 31 */ 32 33/*--------------------------Include File--------------------------------------*/ 34/*--------------------------Include File--------------------------------------*/ 35 36/* 3 ============Programming guide Start===================== */ 37/* 38 * 1. For all bit define, it should be prefixed by "BIT_" 39 * 2. For all bit mask, it should be prefixed by "BIT_MASK_" 40 * 3. For all bit shift, it should be prefixed by "BIT_SHIFT_" 41 * 4. For other case, prefix is not needed 42 * 43 * Example: 44 * #define BIT_SHIFT_MAX_TXDMA 16 45 * #define BIT_MASK_MAX_TXDMA 0x7 46 * #define BIT_MAX_TXDMA(x) \ 47 * (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) 48 * #define BIT_GET_MAX_TXDMA(x) \ 49 * (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) 50 * 51 */ 52/* 3 ============Programming guide End===================== */ 53 54#define CPU_OPT_WIDTH 0x1F 55 56#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 57#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff 58#define BIT_WATCH_DOG_RECORD_V1(x) \ 59 (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) 60#define BIT_GET_WATCH_DOG_RECORD_V1(x) \ 61 (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) 62 63#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) 64 65#define BIT_ISO_MD2PP BIT(0) 66 67#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 68#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL 69#define BIT_R_WMAC_IPV6_MYIPAD(x) \ 70 (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) 71#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ 72 (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) 73 74/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 75 76#define BIT_SHIFT_SDIO_INT_TIMEOUT 16 77#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff 78#define BIT_SDIO_INT_TIMEOUT(x) \ 79 (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) 80#define BIT_GET_SDIO_INT_TIMEOUT(x) \ 81 (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) 82 83/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 84 85#define BIT_PWC_EV12V BIT(15) 86 87/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 88 89#define BIT_IO_ERR_STATUS BIT(15) 90 91/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 92 93#define BIT_PWC_EV25V BIT(14) 94 95/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 96 97#define BIT_PA33V_EN BIT(13) 98#define BIT_PA12V_EN BIT(12) 99 100/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 101 102#define BIT_UA33V_EN BIT(11) 103#define BIT_UA12V_EN BIT(10) 104 105/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 106 107#define BIT_ISO_RFDIO BIT(9) 108 109/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 110 111#define BIT_REPLY_ERRCRC_IN_DATA BIT(9) 112 113/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 114 115#define BIT_ISO_EB2CORE BIT(8) 116 117/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 118 119#define BIT_EN_CMD53_OVERLAP BIT(8) 120 121/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 122 123#define BIT_ISO_DIOE BIT(7) 124 125/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 126 127#define BIT_REPLY_ERR_IN_R5 BIT(7) 128 129/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 130 131#define BIT_ISO_WLPON2PP BIT(6) 132 133/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 134 135#define BIT_R18A_EN BIT(6) 136 137/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 138 139#define BIT_ISO_IP2MAC_WA2PP BIT(5) 140 141/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 142 143#define BIT_INIT_CMD_EN BIT(5) 144 145/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 146 147#define BIT_ISO_PD2CORE BIT(4) 148 149/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 150 151#define BIT_ISO_PA2PCIE BIT(3) 152 153/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 154 155#define BIT_ISO_UD2CORE BIT(2) 156 157/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 158 159#define BIT_EN_RXDMA_MASK_INT BIT(2) 160 161/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 162 163#define BIT_ISO_UA2USB BIT(1) 164 165/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 166 167#define BIT_EN_MASK_TIMER BIT(1) 168 169/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 170 171#define BIT_ISO_WD2PP BIT(0) 172 173/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 174 175#define BIT_CMD_ERR_STOP_INT_EN BIT(0) 176 177/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 178 179#define BIT_FEN_MREGEN BIT(15) 180#define BIT_FEN_HWPDN BIT(14) 181 182/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 183 184#define BIT_EN_25_1 BIT(13) 185 186/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 187 188#define BIT_FEN_ELDR BIT(12) 189#define BIT_FEN_DCORE BIT(11) 190#define BIT_FEN_CPUEN BIT(10) 191#define BIT_FEN_DIOE BIT(9) 192#define BIT_FEN_PCIED BIT(8) 193#define BIT_FEN_PPLL BIT(7) 194#define BIT_FEN_PCIEA BIT(6) 195#define BIT_FEN_DIO_PCIE BIT(5) 196#define BIT_FEN_USBD BIT(4) 197#define BIT_FEN_UPLL BIT(3) 198#define BIT_FEN_USBA BIT(2) 199 200/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 201 202#define BIT_FEN_BB_GLB_RSTN BIT(1) 203#define BIT_FEN_BBRSTB BIT(0) 204 205/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 206 207#define BIT_SOP_EABM BIT(31) 208 209/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 210 211#define BIT_SOP_ACKF BIT(30) 212#define BIT_SOP_ERCK BIT(29) 213 214/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 215 216#define BIT_SOP_ESWR BIT(28) 217 218/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 219 220#define BIT_SOP_PWMM BIT(27) 221 222/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 223 224#define BIT_SOP_EECK BIT(26) 225 226/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 227 228#define BIT_SOP_EXTL BIT(24) 229 230/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 231 232#define BIT_SYM_OP_RING_12M BIT(22) 233 234/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 235 236#define BIT_ROP_SWPR BIT(21) 237 238/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 239 240#define BIT_DIS_HW_LPLDM BIT(20) 241 242/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 243 244#define BIT_OPT_SWRST_WLMCU BIT(19) 245#define BIT_RDY_SYSPWR BIT(17) 246 247/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 248 249#define BIT_EN_WLON BIT(16) 250 251/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 252 253#define BIT_APDM_HPDN BIT(15) 254 255/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 256 257#define BIT_AFSM_PCIE_SUS_EN BIT(12) 258 259/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 260 261#define BIT_AFSM_WLSUS_EN BIT(11) 262 263/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 264 265#define BIT_APFM_SWLPS BIT(10) 266 267/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 268 269#define BIT_APFM_OFFMAC BIT(9) 270#define BIT_APFN_ONMAC BIT(8) 271 272/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 273 274#define BIT_CHIP_PDN_EN BIT(7) 275 276/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 277 278#define BIT_RDY_MACDIS BIT(6) 279 280/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 281 282#define BIT_RING_CLK_12M_EN BIT(4) 283 284/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 285 286#define BIT_PFM_WOWL BIT(3) 287 288/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 289 290#define BIT_PFM_LDKP BIT(2) 291 292/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 293 294#define BIT_WL_HCI_ALD BIT(1) 295 296/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 297 298#define BIT_PFM_LDALL BIT(0) 299 300/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 301 302#define BIT_LDO_DUMMY BIT(15) 303 304/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 305 306#define BIT_CPU_CLK_EN BIT(14) 307 308/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 309 310#define BIT_SYMREG_CLK_EN BIT(13) 311 312/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 313 314#define BIT_HCI_CLK_EN BIT(12) 315 316/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 317 318#define BIT_MAC_CLK_EN BIT(11) 319#define BIT_SEC_CLK_EN BIT(10) 320 321/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 322 323#define BIT_PHY_SSC_RSTB BIT(9) 324#define BIT_EXT_32K_EN BIT(8) 325 326/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 327 328#define BIT_WL_CLK_TEST BIT(7) 329#define BIT_OP_SPS_PWM_EN BIT(6) 330 331/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 332 333#define BIT_LOADER_CLK_EN BIT(5) 334#define BIT_MACSLP BIT(4) 335#define BIT_WAKEPAD_EN BIT(3) 336#define BIT_ROMD16V_EN BIT(2) 337 338/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 339 340#define BIT_CKANA12M_EN BIT(1) 341 342/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 343 344#define BIT_CNTD16V_EN BIT(0) 345 346/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 347 348#define BIT_SHIFT_VPDIDX 8 349#define BIT_MASK_VPDIDX 0xff 350#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) 351#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) 352 353#define BIT_SHIFT_EEM1_0 6 354#define BIT_MASK_EEM1_0 0x3 355#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) 356#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) 357 358#define BIT_AUTOLOAD_SUS BIT(5) 359 360/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 361 362#define BIT_EERPOMSEL BIT(4) 363 364/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 365 366#define BIT_EECS_V1 BIT(3) 367#define BIT_EESK_V1 BIT(2) 368#define BIT_EEDI_V1 BIT(1) 369#define BIT_EEDO_V1 BIT(0) 370 371/* 2 REG_EE_VPD (Offset 0x000C) */ 372 373#define BIT_SHIFT_VPD_DATA 0 374#define BIT_MASK_VPD_DATA 0xffffffffL 375#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) 376#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) 377 378/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 379 380#define BIT_C2_L_BIT0 BIT(31) 381 382/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 383 384#define BIT_SHIFT_C1_L 29 385#define BIT_MASK_C1_L 0x3 386#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) 387#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) 388 389/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 390 391#define BIT_SHIFT_REG_FREQ_L 25 392#define BIT_MASK_REG_FREQ_L 0x7 393#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) 394#define BIT_GET_REG_FREQ_L(x) \ 395 (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) 396 397#define BIT_REG_EN_DUTY BIT(24) 398 399/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 400 401#define BIT_SHIFT_REG_MODE 22 402#define BIT_MASK_REG_MODE 0x3 403#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) 404#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) 405 406/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 407 408#define BIT_REG_EN_SP BIT(21) 409#define BIT_REG_AUTO_L BIT(20) 410 411/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 412 413#define BIT_SW18_SELD_BIT0 BIT(19) 414 415/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 416 417#define BIT_SW18_POWOCP BIT(18) 418 419/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 420 421#define BIT_SHIFT_OCP_L1 15 422#define BIT_MASK_OCP_L1 0x7 423#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) 424#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) 425 426/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 427 428#define BIT_SHIFT_CF_L 13 429#define BIT_MASK_CF_L 0x3 430#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) 431#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) 432 433/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 434 435#define BIT_SW18_FPWM BIT(11) 436 437/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 438 439#define BIT_SW18_SWEN BIT(9) 440#define BIT_SW18_LDEN BIT(8) 441#define BIT_MAC_ID_EN BIT(7) 442 443/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 444 445#define BIT_AFE_BGEN BIT(0) 446 447/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 448 449#define BIT_POW_ZCD_L BIT(31) 450 451/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 452 453#define BIT_SDIO_CRCERR_MSK BIT(31) 454 455/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 456 457#define BIT_AUTOZCD_L BIT(30) 458#define BIT_SDIO_HSISR3_IND_MSK BIT(30) 459#define BIT_SDIO_HSISR2_IND_MSK BIT(29) 460 461/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 462 463#define BIT_SHIFT_REG_DELAY 28 464#define BIT_MASK_REG_DELAY 0x3 465#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) 466#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) 467 468/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 469 470#define BIT_SDIO_HEISR_IND_MSK BIT(28) 471 472/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 473 474#define BIT_SDIO_CTWEND_MSK BIT(27) 475#define BIT_SDIO_ATIMEND_E_MSK BIT(26) 476 477/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 478 479#define BIT_SDIIO_ATIMEND_MSK BIT(25) 480 481/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 482 483#define BIT_SDIO_OCPINT_MSK BIT(24) 484 485/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 486 487#define BIT_SHIFT_V15ADJ_L1_V1 24 488#define BIT_MASK_V15ADJ_L1_V1 0x7 489#define BIT_V15ADJ_L1_V1(x) \ 490 (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) 491#define BIT_GET_V15ADJ_L1_V1(x) \ 492 (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) 493 494/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 495 496#define BIT_SDIO_PSTIMEOUT_MSK BIT(23) 497 498/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 499 500#define BIT_SDIO_GTINT4_MSK BIT(22) 501 502/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 503 504#define BIT_SDIO_GTINT3_MSK BIT(21) 505 506/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 507 508#define BIT_SDIO_HSISR_IND_MSK BIT(20) 509 510/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 511 512#define BIT_SHIFT_VOL_L1_V1 20 513#define BIT_MASK_VOL_L1_V1 0xf 514#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) 515#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) 516 517/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 518 519#define BIT_SDIO_CPWM2_MSK BIT(19) 520 521/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 522 523#define BIT_SDIO_CPWM1_MSK BIT(18) 524 525/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 526 527#define BIT_SDIO_C2HCMD_INT_MSK BIT(17) 528 529/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 530 531#define BIT_SHIFT_IN_L1_V1 17 532#define BIT_MASK_IN_L1_V1 0x7 533#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) 534#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) 535 536/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 537 538#define BIT_SDIO_BCNERLY_INT_MSK BIT(16) 539 540/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 541 542#define BIT_SHIFT_TBOX_L1 15 543#define BIT_MASK_TBOX_L1 0x3 544#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) 545#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) 546 547/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 548 549#define BIT_SW18_SEL BIT(13) 550 551/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 552 553#define BIT_SW18_SD BIT(10) 554 555/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 556 557#define BIT_SDIO_TXBCNERR_MSK BIT(7) 558 559/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 560 561#define BIT_SHIFT_R3_L 7 562#define BIT_MASK_R3_L 0x3 563#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) 564#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) 565 566/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 567 568#define BIT_SDIO_TXBCNOK_MSK BIT(6) 569 570/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 571 572#define BIT_SHIFT_SW18_R2 5 573#define BIT_MASK_SW18_R2 0x3 574#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) 575#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) 576 577/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 578 579#define BIT_SDIO_RXFOVW_MSK BIT(5) 580#define BIT_SDIO_TXFOVW_MSK BIT(4) 581 582/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 583 584#define BIT_SHIFT_SW18_R1 3 585#define BIT_MASK_SW18_R1 0x3 586#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) 587#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) 588 589/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 590 591#define BIT_SDIO_RXERR_MSK BIT(3) 592#define BIT_SDIO_TXERR_MSK BIT(2) 593 594/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 595 596#define BIT_SDIO_AVAL_MSK BIT(1) 597 598/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 599 600#define BIT_SHIFT_C3_L_C3 1 601#define BIT_MASK_C3_L_C3 0x3 602#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) 603#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) 604 605/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 606 607#define BIT_RX_REQUEST_MSK BIT(0) 608 609/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 610 611#define BIT_C2_L_BIT1 BIT(0) 612 613/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 614 615#define BIT_SPS18_OCP_DIS BIT(31) 616 617/* 2 REG_SDIO_HISR (Offset 0x10250018) */ 618 619#define BIT_SDIO_CRCERR BIT(31) 620 621/* 2 REG_SDIO_HISR (Offset 0x10250018) */ 622 623#define BIT_SDIO_HSISR3_IND BIT(30) 624#define BIT_SDIO_HSISR2_IND BIT(29) 625#define BIT_SDIO_HEISR_IND BIT(28) 626 627/* 2 REG_SDIO_HISR (Offset 0x10250018) */ 628 629#define BIT_SDIO_CTWEND BIT(27) 630#define BIT_SDIO_ATIMEND_E BIT(26) 631#define BIT_SDIO_ATIMEND BIT(25) 632#define BIT_SDIO_OCPINT BIT(24) 633#define BIT_SDIO_PSTIMEOUT BIT(23) 634#define BIT_SDIO_GTINT4 BIT(22) 635#define BIT_SDIO_GTINT3 BIT(21) 636#define BIT_SDIO_HSISR_IND BIT(20) 637#define BIT_SDIO_CPWM2 BIT(19) 638#define BIT_SDIO_CPWM1 BIT(18) 639#define BIT_SDIO_C2HCMD_INT BIT(17) 640 641/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 642 643#define BIT_SHIFT_SPS18_OCP_TH 16 644#define BIT_MASK_SPS18_OCP_TH 0x7fff 645#define BIT_SPS18_OCP_TH(x) \ 646 (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) 647#define BIT_GET_SPS18_OCP_TH(x) \ 648 (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) 649 650/* 2 REG_SDIO_HISR (Offset 0x10250018) */ 651 652#define BIT_SDIO_BCNERLY_INT BIT(16) 653#define BIT_SDIO_TXBCNERR BIT(7) 654#define BIT_SDIO_TXBCNOK BIT(6) 655#define BIT_SDIO_RXFOVW BIT(5) 656#define BIT_SDIO_TXFOVW BIT(4) 657#define BIT_SDIO_RXERR BIT(3) 658#define BIT_SDIO_TXERR BIT(2) 659#define BIT_SDIO_AVAL BIT(1) 660 661/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 662 663#define BIT_SHIFT_OCP_WINDOW 0 664#define BIT_MASK_OCP_WINDOW 0xffff 665#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) 666#define BIT_GET_OCP_WINDOW(x) \ 667 (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) 668 669/* 2 REG_SDIO_HISR (Offset 0x10250018) */ 670 671#define BIT_RX_REQUEST BIT(0) 672 673/* 2 REG_RSV_CTRL (Offset 0x001C) */ 674 675#define BIT_HREG_DBG BIT(23) 676 677/* 2 REG_RSV_CTRL (Offset 0x001C) */ 678 679#define BIT_WLMCUIOIF BIT(8) 680 681/* 2 REG_RSV_CTRL (Offset 0x001C) */ 682 683#define BIT_LOCK_ALL_EN BIT(7) 684 685/* 2 REG_RSV_CTRL (Offset 0x001C) */ 686 687#define BIT_R_DIS_PRST BIT(6) 688 689/* 2 REG_RSV_CTRL (Offset 0x001C) */ 690 691#define BIT_WLOCK_1C_B6 BIT(5) 692 693/* 2 REG_RSV_CTRL (Offset 0x001C) */ 694 695#define BIT_WLOCK_40 BIT(4) 696#define BIT_WLOCK_08 BIT(3) 697#define BIT_WLOCK_04 BIT(2) 698#define BIT_WLOCK_00 BIT(1) 699#define BIT_WLOCK_ALL BIT(0) 700 701/* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ 702 703#define BIT_SHIFT_RX_REQ_LEN_V1 0 704#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff 705#define BIT_RX_REQ_LEN_V1(x) \ 706 (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) 707#define BIT_GET_RX_REQ_LEN_V1(x) \ 708 (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) 709 710/* 2 REG_RF_CTRL (Offset 0x001F) */ 711 712#define BIT_RF_SDMRSTB BIT(2) 713 714/* 2 REG_RF_CTRL (Offset 0x001F) */ 715 716#define BIT_RF_RSTB BIT(1) 717 718/* 2 REG_RF_CTRL (Offset 0x001F) */ 719 720#define BIT_RF_EN BIT(0) 721 722/* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ 723 724#define BIT_SHIFT_FREE_TXPG_SEQ 0 725#define BIT_MASK_FREE_TXPG_SEQ 0xff 726#define BIT_FREE_TXPG_SEQ(x) \ 727 (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) 728#define BIT_GET_FREE_TXPG_SEQ(x) \ 729 (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) 730 731/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 732 733#define BIT_SHIFT_LPLDH12_RSV 29 734#define BIT_MASK_LPLDH12_RSV 0x7 735#define BIT_LPLDH12_RSV(x) \ 736 (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) 737#define BIT_GET_LPLDH12_RSV(x) \ 738 (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) 739 740/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 741 742#define BIT_LPLDH12_SLP BIT(28) 743 744#define BIT_SHIFT_LPLDH12_VADJ 24 745#define BIT_MASK_LPLDH12_VADJ 0xf 746#define BIT_LPLDH12_VADJ(x) \ 747 (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) 748#define BIT_GET_LPLDH12_VADJ(x) \ 749 (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) 750 751/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 752 753#define BIT_LDH12_EN BIT(16) 754 755/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ 756 757#define BIT_SHIFT_MID_FREEPG_V1 16 758#define BIT_MASK_MID_FREEPG_V1 0xfff 759#define BIT_MID_FREEPG_V1(x) \ 760 (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) 761#define BIT_GET_MID_FREEPG_V1(x) \ 762 (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) 763 764/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 765 766#define BIT_WLBBOFF_BIG_PWC_EN BIT(14) 767#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) 768#define BIT_WLMACOFF_BIG_PWC_EN BIT(12) 769#define BIT_WLPON_PWC_EN BIT(11) 770 771/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 772 773#define BIT_POW_REGU_P1 BIT(10) 774 775/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 776 777#define BIT_LDOV12W_EN BIT(8) 778 779/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 780 781#define BIT_EX_XTAL_DRV_DIGI BIT(7) 782#define BIT_EX_XTAL_DRV_USB BIT(6) 783#define BIT_EX_XTAL_DRV_AFE BIT(5) 784 785/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 786 787#define BIT_EX_XTAL_DRV_RF2 BIT(4) 788 789/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 790 791#define BIT_EX_XTAL_DRV_RF1 BIT(3) 792#define BIT_POW_REGU_P0 BIT(2) 793 794/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 795 796#define BIT_POW_PLL_LDO BIT(0) 797 798/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ 799 800#define BIT_SHIFT_HIQ_FREEPG_V1 0 801#define BIT_MASK_HIQ_FREEPG_V1 0xfff 802#define BIT_HIQ_FREEPG_V1(x) \ 803 (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) 804#define BIT_GET_HIQ_FREEPG_V1(x) \ 805 (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) 806 807/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 808 809#define BIT_AGPIO_GPE BIT(31) 810 811/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 812 813#define BIT_SHIFT_XTAL_CAP_XI 25 814#define BIT_MASK_XTAL_CAP_XI 0x3f 815#define BIT_XTAL_CAP_XI(x) \ 816 (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) 817#define BIT_GET_XTAL_CAP_XI(x) \ 818 (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) 819 820/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 821 822#define BIT_SHIFT_XTAL_DRV_DIGI 23 823#define BIT_MASK_XTAL_DRV_DIGI 0x3 824#define BIT_XTAL_DRV_DIGI(x) \ 825 (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) 826#define BIT_GET_XTAL_DRV_DIGI(x) \ 827 (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) 828 829#define BIT_XTAL_DRV_USB_BIT1 BIT(22) 830 831/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 832 833#define BIT_SHIFT_MAC_CLK_SEL 20 834#define BIT_MASK_MAC_CLK_SEL 0x3 835#define BIT_MAC_CLK_SEL(x) \ 836 (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) 837#define BIT_GET_MAC_CLK_SEL(x) \ 838 (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) 839 840/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 841 842#define BIT_XTAL_DRV_USB_BIT0 BIT(19) 843 844/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 845 846#define BIT_SHIFT_XTAL_DRV_AFE 17 847#define BIT_MASK_XTAL_DRV_AFE 0x3 848#define BIT_XTAL_DRV_AFE(x) \ 849 (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) 850#define BIT_GET_XTAL_DRV_AFE(x) \ 851 (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) 852 853/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ 854 855#define BIT_SHIFT_PUB_FREEPG_V1 16 856#define BIT_MASK_PUB_FREEPG_V1 0xfff 857#define BIT_PUB_FREEPG_V1(x) \ 858 (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) 859#define BIT_GET_PUB_FREEPG_V1(x) \ 860 (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) 861 862/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 863 864#define BIT_SHIFT_XTAL_DRV_RF2 15 865#define BIT_MASK_XTAL_DRV_RF2 0x3 866#define BIT_XTAL_DRV_RF2(x) \ 867 (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) 868#define BIT_GET_XTAL_DRV_RF2(x) \ 869 (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) 870 871/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 872 873#define BIT_SHIFT_XTAL_DRV_RF1 13 874#define BIT_MASK_XTAL_DRV_RF1 0x3 875#define BIT_XTAL_DRV_RF1(x) \ 876 (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) 877#define BIT_GET_XTAL_DRV_RF1(x) \ 878 (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) 879 880/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 881 882#define BIT_XTAL_DELAY_DIGI BIT(12) 883 884/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 885 886#define BIT_XTAL_DELAY_USB BIT(11) 887#define BIT_XTAL_DELAY_AFE BIT(10) 888 889/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 890 891#define BIT_SHIFT_XTAL_LDO_VREF 7 892#define BIT_MASK_XTAL_LDO_VREF 0x7 893#define BIT_XTAL_LDO_VREF(x) \ 894 (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) 895#define BIT_GET_XTAL_LDO_VREF(x) \ 896 (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) 897 898/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 899 900#define BIT_XTAL_XQSEL_RF BIT(6) 901#define BIT_XTAL_XQSEL BIT(5) 902 903/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 904 905#define BIT_SHIFT_XTAL_GMN_V2 3 906#define BIT_MASK_XTAL_GMN_V2 0x3 907#define BIT_XTAL_GMN_V2(x) \ 908 (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) 909#define BIT_GET_XTAL_GMN_V2(x) \ 910 (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) 911 912/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 913 914#define BIT_SHIFT_XTAL_GMP_V2 1 915#define BIT_MASK_XTAL_GMP_V2 0x3 916#define BIT_XTAL_GMP_V2(x) \ 917 (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) 918#define BIT_GET_XTAL_GMP_V2(x) \ 919 (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) 920 921/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 922 923#define BIT_XTAL_EN BIT(0) 924 925/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ 926 927#define BIT_SHIFT_LOW_FREEPG_V1 0 928#define BIT_MASK_LOW_FREEPG_V1 0xfff 929#define BIT_LOW_FREEPG_V1(x) \ 930 (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) 931#define BIT_GET_LOW_FREEPG_V1(x) \ 932 (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) 933 934/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 935 936#define BIT_SHIFT_REG_C3_V4 30 937#define BIT_MASK_REG_C3_V4 0x3 938#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) 939#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) 940 941#define BIT_REG_CP_BIT1 BIT(29) 942 943/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 944 945#define BIT_SHIFT_REG_RS_V4 26 946#define BIT_MASK_REG_RS_V4 0x7 947#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) 948#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) 949 950/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ 951 952#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 953#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff 954#define BIT_NOAC_OQT_FREEPG_V1(x) \ 955 (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) 956#define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ 957 (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) 958 959/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 960 961#define BIT_SHIFT_REG__CS 24 962#define BIT_MASK_REG__CS 0x3 963#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) 964#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) 965 966/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 967 968#define BIT_SHIFT_REG_CP_OFFSET 21 969#define BIT_MASK_REG_CP_OFFSET 0x7 970#define BIT_REG_CP_OFFSET(x) \ 971 (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) 972#define BIT_GET_REG_CP_OFFSET(x) \ 973 (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) 974 975/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 976 977#define BIT_SHIFT_CP_BIAS 18 978#define BIT_MASK_CP_BIAS 0x7 979#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) 980#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) 981 982/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 983 984#define BIT_REG_IDOUBLE_V2 BIT(17) 985 986/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 987 988#define BIT_EN_SYN BIT(16) 989 990#define BIT_SHIFT_AC_OQT_FREEPG_V1 16 991#define BIT_MASK_AC_OQT_FREEPG_V1 0xff 992#define BIT_AC_OQT_FREEPG_V1(x) \ 993 (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) 994#define BIT_GET_AC_OQT_FREEPG_V1(x) \ 995 (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) 996 997/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 998 999#define BIT_SHIFT_MCCO 14 1000#define BIT_MASK_MCCO 0x3
1001#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) 1002#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) 1003 1004/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1005 1006#define BIT_SHIFT_REG_LDO_SEL 12 1007#define BIT_MASK_REG_LDO_SEL 0x3 1008#define BIT_REG_LDO_SEL(x) \ 1009 (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) 1010#define BIT_GET_REG_LDO_SEL(x) \ 1011 (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) 1012 1013#define BIT_REG_KVCO_V2 BIT(10) 1014 1015/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1016 1017#define BIT_AGPIO_GPO BIT(9) 1018 1019/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1020 1021#define BIT_SHIFT_AGPIO_DRV 7 1022#define BIT_MASK_AGPIO_DRV 0x3 1023#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) 1024#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) 1025 1026/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1027 1028#define BIT_SHIFT_XTAL_CAP_XO 1 1029#define BIT_MASK_XTAL_CAP_XO 0x3f 1030#define BIT_XTAL_CAP_XO(x) \ 1031 (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) 1032#define BIT_GET_XTAL_CAP_XO(x) \ 1033 (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) 1034 1035/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1036 1037#define BIT_POW_PLL BIT(0) 1038 1039/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ 1040 1041#define BIT_SHIFT_EXQ_FREEPG_V1 0 1042#define BIT_MASK_EXQ_FREEPG_V1 0xfff 1043#define BIT_EXQ_FREEPG_V1(x) \ 1044 (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) 1045#define BIT_GET_EXQ_FREEPG_V1(x) \ 1046 (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) 1047 1048/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1049 1050#define BIT_SHIFT_PS 7 1051#define BIT_MASK_PS 0x7 1052#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) 1053#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) 1054 1055/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1056 1057#define BIT_PSEN BIT(6) 1058#define BIT_DOGENB BIT(5) 1059 1060/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1061 1062#define BIT_REG_MBIAS BIT(4) 1063 1064/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1065 1066#define BIT_SHIFT_REG_R3_V4 1 1067#define BIT_MASK_REG_R3_V4 0x7 1068#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) 1069#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) 1070 1071/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1072 1073#define BIT_REG_CP_BIT0 BIT(0) 1074 1075/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1076 1077#define BIT_EF_FLAG BIT(31) 1078 1079#define BIT_SHIFT_EF_PGPD 28 1080#define BIT_MASK_EF_PGPD 0x7 1081#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) 1082#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) 1083 1084#define BIT_SHIFT_EF_RDT 24 1085#define BIT_MASK_EF_RDT 0xf 1086#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) 1087#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) 1088 1089#define BIT_SHIFT_EF_PGTS 20 1090#define BIT_MASK_EF_PGTS 0xf 1091#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) 1092#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) 1093 1094/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1095 1096#define BIT_EF_PDWN BIT(19) 1097 1098/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1099 1100#define BIT_EF_ALDEN BIT(18) 1101 1102/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ 1103 1104#define BIT_SHIFT_HTSFR1 16 1105#define BIT_MASK_HTSFR1 0xffff 1106#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) 1107#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) 1108 1109/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1110 1111#define BIT_SHIFT_EF_ADDR 8 1112#define BIT_MASK_EF_ADDR 0x3ff 1113#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) 1114#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) 1115 1116#define BIT_SHIFT_EF_DATA 0 1117#define BIT_MASK_EF_DATA 0xff 1118#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) 1119#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) 1120 1121/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ 1122 1123#define BIT_SHIFT_HTSFR0 0 1124#define BIT_MASK_HTSFR0 0xffff 1125#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) 1126#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) 1127 1128/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1129 1130#define BIT_LDOE25_EN BIT(31) 1131 1132/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1133 1134#define BIT_SHIFT_LDOE25_V12ADJ_L 27 1135#define BIT_MASK_LDOE25_V12ADJ_L 0xf 1136#define BIT_LDOE25_V12ADJ_L(x) \ 1137 (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) 1138#define BIT_GET_LDOE25_V12ADJ_L(x) \ 1139 (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) 1140 1141/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1142 1143#define BIT_EF_CRES_SEL BIT(26) 1144 1145/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1146 1147#define BIT_SHIFT_EF_SCAN_START_V1 16 1148#define BIT_MASK_EF_SCAN_START_V1 0x3ff 1149#define BIT_EF_SCAN_START_V1(x) \ 1150 (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) 1151#define BIT_GET_EF_SCAN_START_V1(x) \ 1152 (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) 1153 1154/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1155 1156#define BIT_SHIFT_EF_SCAN_END 12 1157#define BIT_MASK_EF_SCAN_END 0xf 1158#define BIT_EF_SCAN_END(x) \ 1159 (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) 1160#define BIT_GET_EF_SCAN_END(x) \ 1161 (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) 1162 1163/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1164 1165#define BIT_EF_PD_DIS BIT(11) 1166 1167/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1168 1169#define BIT_SHIFT_EF_CELL_SEL 8 1170#define BIT_MASK_EF_CELL_SEL 0x3 1171#define BIT_EF_CELL_SEL(x) \ 1172 (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) 1173#define BIT_GET_EF_CELL_SEL(x) \ 1174 (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) 1175 1176/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1177 1178#define BIT_EF_TRPT BIT(7) 1179 1180#define BIT_SHIFT_EF_TTHD 0 1181#define BIT_MASK_EF_TTHD 0x7f 1182#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) 1183#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) 1184 1185/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1186 1187#define BIT_SHIFT_DBG_SEL_V1 16 1188#define BIT_MASK_DBG_SEL_V1 0xff 1189#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) 1190#define BIT_GET_DBG_SEL_V1(x) \ 1191 (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) 1192 1193/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1194 1195#define BIT_SHIFT_DBG_SEL_BYTE 14 1196#define BIT_MASK_DBG_SEL_BYTE 0x3 1197#define BIT_DBG_SEL_BYTE(x) \ 1198 (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) 1199#define BIT_GET_DBG_SEL_BYTE(x) \ 1200 (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) 1201 1202/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1203 1204#define BIT_SHIFT_STD_L1_V1 12 1205#define BIT_MASK_STD_L1_V1 0x3 1206#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) 1207#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) 1208 1209/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1210 1211#define BIT_SYSON_DBG_PAD_E2 BIT(11) 1212 1213/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1214 1215#define BIT_SYSON_LED_PAD_E2 BIT(10) 1216 1217/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1218 1219#define BIT_SYSON_GPEE_PAD_E2 BIT(9) 1220 1221/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1222 1223#define BIT_SYSON_PCI_PAD_E2 BIT(8) 1224 1225#define BIT_SHIFT_MATCH_CNT 8 1226#define BIT_MASK_MATCH_CNT 0xff 1227#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) 1228#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) 1229 1230/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1231 1232#define BIT_AUTO_SW_LDO_VOL_EN BIT(7) 1233 1234/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1235 1236#define BIT_SHIFT_SYSON_SPS0WWV_WT 4 1237#define BIT_MASK_SYSON_SPS0WWV_WT 0x3 1238#define BIT_SYSON_SPS0WWV_WT(x) \ 1239 (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) 1240#define BIT_GET_SYSON_SPS0WWV_WT(x) \ 1241 (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) 1242 1243/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1244 1245#define BIT_SHIFT_SYSON_SPS0LDO_WT 2 1246#define BIT_MASK_SYSON_SPS0LDO_WT 0x3 1247#define BIT_SYSON_SPS0LDO_WT(x) \ 1248 (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) 1249#define BIT_GET_SYSON_SPS0LDO_WT(x) \ 1250 (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) 1251 1252/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1253 1254#define BIT_SHIFT_SYSON_RCLK_SCALE 0 1255#define BIT_MASK_SYSON_RCLK_SCALE 0x3 1256#define BIT_SYSON_RCLK_SCALE(x) \ 1257 (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) 1258#define BIT_GET_SYSON_RCLK_SCALE(x) \ 1259 (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) 1260 1261/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ 1262 1263#define BIT_SYS_CLK BIT(0) 1264 1265/* 2 REG_CAL_TIMER (Offset 0x003C) */ 1266 1267#define BIT_SHIFT_CAL_SCAL 0 1268#define BIT_MASK_CAL_SCAL 0xff 1269#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) 1270#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) 1271 1272/* 2 REG_ACLK_MON (Offset 0x003E) */ 1273 1274#define BIT_SHIFT_RCLK_MON 5 1275#define BIT_MASK_RCLK_MON 0x7ff 1276#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) 1277#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) 1278 1279#define BIT_CAL_EN BIT(4) 1280 1281#define BIT_SHIFT_DPSTU 2 1282#define BIT_MASK_DPSTU 0x3 1283#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) 1284#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) 1285 1286#define BIT_SUS_16X BIT(1) 1287 1288/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1289 1290#define BIT_INDIRECT_REG_RDY BIT(20) 1291 1292/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1293 1294#define BIT_FSPI_EN BIT(19) 1295 1296/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1297 1298#define BIT_INDIRECT_REG_R BIT(19) 1299 1300/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1301 1302#define BIT_WL_RTS_EXT_32K_SEL BIT(18) 1303 1304/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1305 1306#define BIT_INDIRECT_REG_W BIT(18) 1307 1308/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1309 1310#define BIT_WLGP_SPI_EN BIT(16) 1311 1312/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1313 1314#define BIT_SHIFT_INDIRECT_REG_SIZE 16 1315#define BIT_MASK_INDIRECT_REG_SIZE 0x3 1316#define BIT_INDIRECT_REG_SIZE(x) \ 1317 (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) 1318#define BIT_GET_INDIRECT_REG_SIZE(x) \ 1319 (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) 1320 1321/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1322 1323#define BIT_SIC_LBK BIT(15) 1324#define BIT_ENHTP BIT(14) 1325 1326/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1327 1328#define BIT_ENSIC BIT(12) 1329#define BIT_SIC_SWRST BIT(11) 1330 1331/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1332 1333#define BIT_PO_WIFI_PTA_PINS BIT(10) 1334 1335/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1336 1337#define BIT_PO_BT_PTA_PINS BIT(9) 1338 1339/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1340 1341#define BIT_ENUART BIT(8) 1342 1343#define BIT_SHIFT_BTMODE 6 1344#define BIT_MASK_BTMODE 0x3 1345#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) 1346#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) 1347 1348#define BIT_ENBT BIT(5) 1349#define BIT_EROM_EN BIT(4) 1350 1351/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1352 1353#define BIT_WLRFE_6_7_EN BIT(3) 1354 1355/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1356 1357#define BIT_WLRFE_4_5_EN BIT(2) 1358 1359/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1360 1361#define BIT_SHIFT_GPIOSEL 0 1362#define BIT_MASK_GPIOSEL 0x3 1363#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) 1364#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) 1365 1366/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1367 1368#define BIT_SHIFT_INDIRECT_REG_ADDR 0 1369#define BIT_MASK_INDIRECT_REG_ADDR 0xffff 1370#define BIT_INDIRECT_REG_ADDR(x) \ 1371 (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) 1372#define BIT_GET_INDIRECT_REG_ADDR(x) \ 1373 (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) 1374 1375/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ 1376 1377#define BIT_SHIFT_GPIO_MOD_7_TO_0 24 1378#define BIT_MASK_GPIO_MOD_7_TO_0 0xff 1379#define BIT_GPIO_MOD_7_TO_0(x) \ 1380 (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) 1381#define BIT_GET_GPIO_MOD_7_TO_0(x) \ 1382 (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) 1383 1384#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 1385#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff 1386#define BIT_GPIO_IO_SEL_7_TO_0(x) \ 1387 (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) 1388#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ 1389 (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) 1390 1391#define BIT_SHIFT_GPIO_OUT_7_TO_0 8 1392#define BIT_MASK_GPIO_OUT_7_TO_0 0xff 1393#define BIT_GPIO_OUT_7_TO_0(x) \ 1394 (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) 1395#define BIT_GET_GPIO_OUT_7_TO_0(x) \ 1396 (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) 1397 1398#define BIT_SHIFT_GPIO_IN_7_TO_0 0 1399#define BIT_MASK_GPIO_IN_7_TO_0 0xff 1400#define BIT_GPIO_IN_7_TO_0(x) \ 1401 (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) 1402#define BIT_GET_GPIO_IN_7_TO_0(x) \ 1403 (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) 1404 1405/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ 1406 1407#define BIT_SHIFT_INDIRECT_REG_DATA 0 1408#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL 1409#define BIT_INDIRECT_REG_DATA(x) \ 1410 (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) 1411#define BIT_GET_INDIRECT_REG_DATA(x) \ 1412 (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) 1413 1414/* 2 REG_GPIO_INTM (Offset 0x0048) */ 1415 1416#define BIT_SHIFT_MUXDBG_SEL 30 1417#define BIT_MASK_MUXDBG_SEL 0x3 1418#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) 1419#define BIT_GET_MUXDBG_SEL(x) \ 1420 (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) 1421 1422/* 2 REG_GPIO_INTM (Offset 0x0048) */ 1423 1424#define BIT_EXTWOL_SEL BIT(17) 1425 1426/* 2 REG_GPIO_INTM (Offset 0x0048) */ 1427 1428#define BIT_EXTWOL_EN BIT(16) 1429 1430/* 2 REG_GPIO_INTM (Offset 0x0048) */ 1431 1432#define BIT_GPIOF_INT_MD BIT(15) 1433#define BIT_GPIOE_INT_MD BIT(14) 1434#define BIT_GPIOD_INT_MD BIT(13) 1435#define BIT_GPIOC_INT_MD BIT(12) 1436#define BIT_GPIOB_INT_MD BIT(11) 1437#define BIT_GPIOA_INT_MD BIT(10) 1438#define BIT_GPIO9_INT_MD BIT(9) 1439#define BIT_GPIO8_INT_MD BIT(8) 1440#define BIT_GPIO7_INT_MD BIT(7) 1441#define BIT_GPIO6_INT_MD BIT(6) 1442#define BIT_GPIO5_INT_MD BIT(5) 1443#define BIT_GPIO4_INT_MD BIT(4) 1444#define BIT_GPIO3_INT_MD BIT(3) 1445#define BIT_GPIO2_INT_MD BIT(2) 1446#define BIT_GPIO1_INT_MD BIT(1) 1447#define BIT_GPIO0_INT_MD BIT(0) 1448 1449/* 2 REG_LED_CFG (Offset 0x004C) */ 1450 1451#define BIT_GPIO3_WL_CTRL_EN BIT(27) 1452 1453/* 2 REG_LED_CFG (Offset 0x004C) */ 1454 1455#define BIT_LNAON_SEL_EN BIT(26) 1456 1457/* 2 REG_LED_CFG (Offset 0x004C) */ 1458 1459#define BIT_PAPE_SEL_EN BIT(25) 1460 1461/* 2 REG_LED_CFG (Offset 0x004C) */ 1462 1463#define BIT_DPDT_WLBT_SEL BIT(24) 1464 1465/* 2 REG_LED_CFG (Offset 0x004C) */ 1466 1467#define BIT_DPDT_SEL_EN BIT(23) 1468 1469/* 2 REG_LED_CFG (Offset 0x004C) */ 1470 1471#define BIT_GPIO13_14_WL_CTRL_EN BIT(22) 1472 1473/* 2 REG_LED_CFG (Offset 0x004C) */ 1474 1475#define BIT_LED2DIS BIT(21) 1476 1477/* 2 REG_LED_CFG (Offset 0x004C) */ 1478 1479#define BIT_LED2PL BIT(20) 1480#define BIT_LED2SV BIT(19) 1481 1482#define BIT_SHIFT_LED2CM 16 1483#define BIT_MASK_LED2CM 0x7 1484#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) 1485#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) 1486 1487#define BIT_LED1DIS BIT(15) 1488#define BIT_LED1PL BIT(12) 1489#define BIT_LED1SV BIT(11) 1490 1491#define BIT_SHIFT_LED1CM 8 1492#define BIT_MASK_LED1CM 0x7 1493#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) 1494#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) 1495 1496#define BIT_LED0DIS BIT(7) 1497 1498/* 2 REG_LED_CFG (Offset 0x004C) */ 1499 1500#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 1501#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 1502#define BIT_AFE_LDO_SWR_CHECK(x) \ 1503 (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) 1504#define BIT_GET_AFE_LDO_SWR_CHECK(x) \ 1505 (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) 1506 1507/* 2 REG_LED_CFG (Offset 0x004C) */ 1508 1509#define BIT_LED0PL BIT(4) 1510#define BIT_LED0SV BIT(3) 1511 1512#define BIT_SHIFT_LED0CM 0 1513#define BIT_MASK_LED0CM 0x7 1514#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) 1515#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) 1516 1517/* 2 REG_FSIMR (Offset 0x0050) */ 1518 1519#define BIT_FS_PDNINT_EN BIT(31) 1520 1521/* 2 REG_FSIMR (Offset 0x0050) */ 1522 1523#define BIT_NFC_INT_PAD_EN BIT(30) 1524 1525/* 2 REG_FSIMR (Offset 0x0050) */ 1526 1527#define BIT_FS_SPS_OCP_INT_EN BIT(29) 1528 1529/* 2 REG_FSIMR (Offset 0x0050) */ 1530 1531#define BIT_FS_PWMERR_INT_EN BIT(28) 1532 1533/* 2 REG_FSIMR (Offset 0x0050) */ 1534 1535#define BIT_FS_GPIOF_INT_EN BIT(27) 1536#define BIT_FS_GPIOE_INT_EN BIT(26) 1537#define BIT_FS_GPIOD_INT_EN BIT(25) 1538#define BIT_FS_GPIOC_INT_EN BIT(24) 1539 1540/* 2 REG_FSIMR (Offset 0x0050) */ 1541 1542#define BIT_FS_GPIOB_INT_EN BIT(23) 1543 1544/* 2 REG_FSIMR (Offset 0x0050) */ 1545 1546#define BIT_FS_GPIOA_INT_EN BIT(22) 1547 1548/* 2 REG_FSIMR (Offset 0x0050) */ 1549 1550#define BIT_FS_GPIO9_INT_EN BIT(21) 1551 1552/* 2 REG_FSIMR (Offset 0x0050) */ 1553 1554#define BIT_FS_GPIO8_INT_EN BIT(20) 1555 1556/* 2 REG_FSIMR (Offset 0x0050) */ 1557 1558#define BIT_FS_GPIO7_INT_EN BIT(19) 1559 1560/* 2 REG_FSIMR (Offset 0x0050) */ 1561 1562#define BIT_FS_GPIO6_INT_EN BIT(18) 1563 1564/* 2 REG_FSIMR (Offset 0x0050) */ 1565 1566#define BIT_FS_GPIO5_INT_EN BIT(17) 1567 1568/* 2 REG_FSIMR (Offset 0x0050) */ 1569 1570#define BIT_FS_GPIO4_INT_EN BIT(16) 1571 1572/* 2 REG_FSIMR (Offset 0x0050) */ 1573 1574#define BIT_FS_GPIO3_INT_EN BIT(15) 1575 1576/* 2 REG_FSIMR (Offset 0x0050) */ 1577 1578#define BIT_FS_GPIO2_INT_EN BIT(14) 1579 1580/* 2 REG_FSIMR (Offset 0x0050) */ 1581 1582#define BIT_FS_GPIO1_INT_EN BIT(13) 1583 1584/* 2 REG_FSIMR (Offset 0x0050) */ 1585 1586#define BIT_FS_GPIO0_INT_EN BIT(12) 1587 1588/* 2 REG_FSIMR (Offset 0x0050) */ 1589 1590#define BIT_FS_HCI_SUS_EN BIT(11) 1591 1592/* 2 REG_FSIMR (Offset 0x0050) */ 1593 1594#define BIT_FS_HCI_RES_EN BIT(10) 1595 1596/* 2 REG_FSIMR (Offset 0x0050) */ 1597 1598#define BIT_FS_HCI_RESET_EN BIT(9) 1599 1600/* 2 REG_FSIMR (Offset 0x0050) */ 1601 1602#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) 1603 1604/* 2 REG_FSIMR (Offset 0x0050) */ 1605 1606#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) 1607 1608/* 2 REG_FSIMR (Offset 0x0050) */ 1609 1610#define BIT_GEN1GEN2_SWITCH BIT(5) 1611 1612/* 2 REG_FSIMR (Offset 0x0050) */ 1613 1614#define BIT_HCI_TXDMA_REQ_HIMR BIT(4) 1615 1616/* 2 REG_FSIMR (Offset 0x0050) */ 1617 1618#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) 1619 1620/* 2 REG_FSIMR (Offset 0x0050) */ 1621 1622#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) 1623 1624/* 2 REG_FSIMR (Offset 0x0050) */ 1625 1626#define BIT_FS_USB_LPMRSM_MSK BIT(1) 1627 1628/* 2 REG_FSIMR (Offset 0x0050) */ 1629 1630#define BIT_FS_USB_LPMINT_MSK BIT(0) 1631 1632/* 2 REG_FSISR (Offset 0x0054) */ 1633 1634#define BIT_FS_PDNINT BIT(31) 1635 1636/* 2 REG_FSISR (Offset 0x0054) */ 1637 1638#define BIT_FS_SPS_OCP_INT BIT(29) 1639 1640/* 2 REG_FSISR (Offset 0x0054) */ 1641 1642#define BIT_FS_PWMERR_INT BIT(28) 1643 1644/* 2 REG_FSISR (Offset 0x0054) */ 1645 1646#define BIT_FS_GPIOF_INT BIT(27) 1647#define BIT_FS_GPIOE_INT BIT(26) 1648#define BIT_FS_GPIOD_INT BIT(25) 1649#define BIT_FS_GPIOC_INT BIT(24) 1650 1651/* 2 REG_FSISR (Offset 0x0054) */ 1652 1653#define BIT_FS_GPIOB_INT BIT(23) 1654 1655/* 2 REG_FSISR (Offset 0x0054) */ 1656 1657#define BIT_FS_GPIOA_INT BIT(22) 1658 1659/* 2 REG_FSISR (Offset 0x0054) */ 1660 1661#define BIT_FS_GPIO9_INT BIT(21) 1662 1663/* 2 REG_FSISR (Offset 0x0054) */ 1664 1665#define BIT_FS_GPIO8_INT BIT(20) 1666 1667/* 2 REG_FSISR (Offset 0x0054) */ 1668 1669#define BIT_FS_GPIO7_INT BIT(19) 1670 1671/* 2 REG_FSISR (Offset 0x0054) */ 1672 1673#define BIT_FS_GPIO6_INT BIT(18) 1674 1675/* 2 REG_FSISR (Offset 0x0054) */ 1676 1677#define BIT_FS_GPIO5_INT BIT(17) 1678 1679/* 2 REG_FSISR (Offset 0x0054) */ 1680 1681#define BIT_FS_GPIO4_INT BIT(16) 1682 1683/* 2 REG_FSISR (Offset 0x0054) */ 1684 1685#define BIT_FS_GPIO3_INT BIT(15) 1686 1687/* 2 REG_FSISR (Offset 0x0054) */ 1688 1689#define BIT_FS_GPIO2_INT BIT(14) 1690 1691/* 2 REG_FSISR (Offset 0x0054) */ 1692 1693#define BIT_FS_GPIO1_INT BIT(13) 1694 1695/* 2 REG_FSISR (Offset 0x0054) */ 1696 1697#define BIT_FS_GPIO0_INT BIT(12) 1698 1699/* 2 REG_FSISR (Offset 0x0054) */ 1700 1701#define BIT_FS_HCI_SUS_INT BIT(11) 1702 1703/* 2 REG_FSISR (Offset 0x0054) */ 1704 1705#define BIT_FS_HCI_RES_INT BIT(10) 1706 1707/* 2 REG_FSISR (Offset 0x0054) */ 1708 1709#define BIT_FS_HCI_RESET_INT BIT(9) 1710 1711/* 2 REG_FSISR (Offset 0x0054) */ 1712 1713#define BIT_ACT2RECOVERY BIT(6) 1714 1715/* 2 REG_FSISR (Offset 0x0054) */ 1716 1717#define BIT_HCI_TXDMA_REQ_HISR BIT(4) 1718 1719/* 2 REG_FSISR (Offset 0x0054) */ 1720 1721#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) 1722 1723/* 2 REG_FSISR (Offset 0x0054) */ 1724 1725#define BIT_FS_32K_ENTER_SETTING_INT BIT(2) 1726 1727/* 2 REG_FSISR (Offset 0x0054) */ 1728 1729#define BIT_FS_USB_LPMRSM_INT BIT(1) 1730 1731/* 2 REG_FSISR (Offset 0x0054) */ 1732 1733#define BIT_FS_USB_LPMINT_INT BIT(0) 1734 1735/* 2 REG_HSIMR (Offset 0x0058) */ 1736 1737#define BIT_GPIOF_INT_EN BIT(31) 1738#define BIT_GPIOE_INT_EN BIT(30) 1739#define BIT_GPIOD_INT_EN BIT(29) 1740#define BIT_GPIOC_INT_EN BIT(28) 1741#define BIT_GPIOB_INT_EN BIT(27) 1742#define BIT_GPIOA_INT_EN BIT(26) 1743#define BIT_GPIO9_INT_EN BIT(25) 1744#define BIT_GPIO8_INT_EN BIT(24) 1745#define BIT_GPIO7_INT_EN BIT(23) 1746#define BIT_GPIO6_INT_EN BIT(22) 1747#define BIT_GPIO5_INT_EN BIT(21) 1748#define BIT_GPIO4_INT_EN BIT(20) 1749#define BIT_GPIO3_INT_EN BIT(19) 1750 1751/* 2 REG_HSIMR (Offset 0x0058) */ 1752 1753#define BIT_GPIO1_INT_EN BIT(17) 1754#define BIT_GPIO0_INT_EN BIT(16) 1755 1756/* 2 REG_HSIMR (Offset 0x0058) */ 1757 1758#define BIT_GPIO2_INT_EN_V1 BIT(16) 1759 1760/* 2 REG_HSIMR (Offset 0x0058) */ 1761 1762#define BIT_PDNINT_EN BIT(7) 1763 1764/* 2 REG_HSIMR (Offset 0x0058) */ 1765 1766#define BIT_RON_INT_EN BIT(6) 1767 1768/* 2 REG_HSIMR (Offset 0x0058) */ 1769 1770#define BIT_SPS_OCP_INT_EN BIT(5) 1771 1772/* 2 REG_HSIMR (Offset 0x0058) */ 1773 1774#define BIT_GPIO15_0_INT_EN BIT(0) 1775 1776/* 2 REG_HSISR (Offset 0x005C) */ 1777 1778#define BIT_GPIOF_INT BIT(31) 1779#define BIT_GPIOE_INT BIT(30) 1780#define BIT_GPIOD_INT BIT(29) 1781#define BIT_GPIOC_INT BIT(28) 1782#define BIT_GPIOB_INT BIT(27) 1783#define BIT_GPIOA_INT BIT(26) 1784#define BIT_GPIO9_INT BIT(25) 1785#define BIT_GPIO8_INT BIT(24) 1786#define BIT_GPIO7_INT BIT(23) 1787 1788/* 2 REG_HSISR (Offset 0x005C) */ 1789 1790#define BIT_GPIO6_INT BIT(22) 1791#define BIT_GPIO5_INT BIT(21) 1792#define BIT_GPIO4_INT BIT(20) 1793#define BIT_GPIO3_INT BIT(19) 1794 1795/* 2 REG_HSISR (Offset 0x005C) */ 1796 1797#define BIT_GPIO1_INT BIT(17) 1798#define BIT_GPIO0_INT BIT(16) 1799 1800/* 2 REG_HSISR (Offset 0x005C) */ 1801 1802#define BIT_GPIO2_INT_V1 BIT(16) 1803 1804/* 2 REG_HSISR (Offset 0x005C) */ 1805 1806#define BIT_PDNINT BIT(7) 1807 1808/* 2 REG_HSISR (Offset 0x005C) */ 1809 1810#define BIT_RON_INT BIT(6) 1811 1812/* 2 REG_HSISR (Offset 0x005C) */ 1813 1814#define BIT_SPS_OCP_INT BIT(5) 1815 1816/* 2 REG_HSISR (Offset 0x005C) */ 1817 1818#define BIT_GPIO15_0_INT BIT(0) 1819#define BIT_MCUFWDL_EN BIT(0) 1820 1821/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ 1822 1823#define BIT_SHIFT_GPIO_MOD_15_TO_8 24 1824#define BIT_MASK_GPIO_MOD_15_TO_8 0xff 1825#define BIT_GPIO_MOD_15_TO_8(x) \ 1826 (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) 1827#define BIT_GET_GPIO_MOD_15_TO_8(x) \ 1828 (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) 1829 1830#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 1831#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff 1832#define BIT_GPIO_IO_SEL_15_TO_8(x) \ 1833 (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) 1834#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ 1835 (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) 1836 1837#define BIT_SHIFT_GPIO_OUT_15_TO_8 8 1838#define BIT_MASK_GPIO_OUT_15_TO_8 0xff 1839#define BIT_GPIO_OUT_15_TO_8(x) \ 1840 (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) 1841#define BIT_GET_GPIO_OUT_15_TO_8(x) \ 1842 (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) 1843 1844#define BIT_SHIFT_GPIO_IN_15_TO_8 0 1845#define BIT_MASK_GPIO_IN_15_TO_8 0xff 1846#define BIT_GPIO_IN_15_TO_8(x) \ 1847 (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) 1848#define BIT_GET_GPIO_IN_15_TO_8(x) \ 1849 (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) 1850 1851/* 2 REG_SDIO_H2C (Offset 0x10250060) */ 1852 1853#define BIT_SHIFT_SDIO_H2C_MSG 0 1854#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL 1855#define BIT_SDIO_H2C_MSG(x) \ 1856 (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) 1857#define BIT_GET_SDIO_H2C_MSG(x) \ 1858 (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) 1859 1860/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1861 1862#define BIT_PAPE_WLBT_SEL BIT(29) 1863#define BIT_LNAON_WLBT_SEL BIT(28) 1864 1865/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1866 1867#define BIT_BTGP_GPG3_FEN BIT(26) 1868#define BIT_BTGP_GPG2_FEN BIT(25) 1869 1870/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1871 1872#define BIT_BTGP_JTAG_EN BIT(24) 1873 1874/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1875 1876#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) 1877 1878/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1879 1880#define BIT_BTGP_UART0_EN BIT(22) 1881 1882/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1883 1884#define BIT_BTGP_UART1_EN BIT(21) 1885 1886/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1887 1888#define BIT_BTGP_SPI_EN BIT(20) 1889 1890/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1891 1892#define BIT_BTGP_GPIO_E2 BIT(19) 1893 1894/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1895 1896#define BIT_BTGP_GPIO_EN BIT(18) 1897 1898/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1899 1900#define BIT_SHIFT_BTGP_GPIO_SL 16 1901#define BIT_MASK_BTGP_GPIO_SL 0x3 1902#define BIT_BTGP_GPIO_SL(x) \ 1903 (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) 1904#define BIT_GET_BTGP_GPIO_SL(x) \ 1905 (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) 1906 1907/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1908 1909#define BIT_PAD_SDIO_SR BIT(14) 1910 1911/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1912 1913#define BIT_GPIO14_OUTPUT_PL BIT(13) 1914 1915/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1916 1917#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) 1918 1919/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1920 1921#define BIT_HOST_WAKE_PAD_SL BIT(11) 1922 1923/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1924 1925#define BIT_PAD_LNAON_SR BIT(10) 1926 1927/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1928 1929#define BIT_PAD_LNAON_E2 BIT(9) 1930 1931/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1932 1933#define BIT_SW_LNAON_G_SEL_DATA BIT(8) 1934 1935/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1936 1937#define BIT_SW_LNAON_A_SEL_DATA BIT(7) 1938 1939/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1940 1941#define BIT_PAD_PAPE_SR BIT(6) 1942 1943/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1944 1945#define BIT_PAD_PAPE_E2 BIT(5) 1946 1947/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1948 1949#define BIT_SW_PAPE_G_SEL_DATA BIT(4) 1950 1951/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1952 1953#define BIT_SW_PAPE_A_SEL_DATA BIT(3) 1954 1955/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1956 1957#define BIT_PAD_DPDT_SR BIT(2) 1958 1959/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1960 1961#define BIT_PAD_DPDT_PAD_E2 BIT(1) 1962 1963/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1964 1965#define BIT_SW_DPDT_SEL_DATA BIT(0) 1966 1967/* 2 REG_SDIO_C2H (Offset 0x10250064) */ 1968 1969#define BIT_SHIFT_SDIO_C2H_MSG 0 1970#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL 1971#define BIT_SDIO_C2H_MSG(x) \ 1972 (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) 1973#define BIT_GET_SDIO_C2H_MSG(x) \ 1974 (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) 1975 1976/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1977 1978#define BIT_ISO_BD2PP BIT(31) 1979#define BIT_LDOV12B_EN BIT(30) 1980#define BIT_CKEN_BTGPS BIT(29) 1981#define BIT_FEN_BTGPS BIT(28) 1982 1983/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1984 1985#define BIT_MULRW BIT(27) 1986 1987/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1988 1989#define BIT_BTCPU_BOOTSEL BIT(27) 1990#define BIT_SPI_SPEEDUP BIT(26) 1991 1992/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1993 1994#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) 1995#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) 1996 1997/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1998 1999#define BIT_EN_CPL_TIMEOUT_PS BIT(22) 2000
2001/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2002 2003#define BIT_ISO_BTPON2PP BIT(22) 2004 2005/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2006 2007#define BIT_REG_TXDMA_FAIL_PS BIT(21) 2008 2009/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2010 2011#define BIT_EN_HWENTR_L1 BIT(19) 2012 2013/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2014 2015#define BIT_BT_HWROF_EN BIT(19) 2016 2017/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2018 2019#define BIT_EN_ADV_CLKGATE BIT(18) 2020 2021/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2022 2023#define BIT_BT_FUNC_EN BIT(18) 2024 2025/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2026 2027#define BIT_BT_HWPDN_SL BIT(17) 2028 2029/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2030 2031#define BIT_BT_DISN_EN BIT(16) 2032 2033/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2034 2035#define BIT_BT_PDN_PULL_EN BIT(15) 2036 2037/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2038 2039#define BIT_WL_PDN_PULL_EN BIT(14) 2040#define BIT_EXTERNAL_REQUEST_PL BIT(13) 2041 2042/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2043 2044#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) 2045 2046/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2047 2048#define BIT_ISO_BA2PP BIT(11) 2049#define BIT_BT_AFE_LDO_EN BIT(10) 2050 2051/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2052 2053#define BIT_BT_AFE_PLL_EN BIT(9) 2054 2055/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2056 2057#define BIT_BT_DIG_CLK_EN BIT(8) 2058 2059/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2060 2061#define BIT_WL_DRV_EXIST_IDX BIT(5) 2062 2063/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2064 2065#define BIT_DOP_EHPAD BIT(4) 2066 2067/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2068 2069#define BIT_WL_HWROF_EN BIT(3) 2070 2071/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2072 2073#define BIT_WL_FUNC_EN BIT(2) 2074 2075/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2076 2077#define BIT_WL_HWPDN_SL BIT(1) 2078#define BIT_WL_HWPDN_EN BIT(0) 2079 2080/* 2 REG_SDM_DEBUG (Offset 0x006C) */ 2081 2082#define BIT_SHIFT_WLCLK_PHASE 0 2083#define BIT_MASK_WLCLK_PHASE 0x1f 2084#define BIT_WLCLK_PHASE(x) \ 2085 (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) 2086#define BIT_GET_WLCLK_PHASE(x) \ 2087 (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) 2088 2089/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2090 2091#define BIT_DBG_GNT_WL_BT BIT(27) 2092 2093/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2094 2095#define BIT_LTE_MUX_CTRL_PATH BIT(26) 2096 2097/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2098 2099#define BIT_LTE_COEX_UART BIT(25) 2100 2101/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2102 2103#define BIT_3W_LTE_WL_GPIO BIT(24) 2104 2105/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2106 2107#define BIT_SDIO_INT_POLARITY BIT(19) 2108#define BIT_SDIO_INT BIT(18) 2109 2110/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2111 2112#define BIT_SDIO_OFF_EN BIT(17) 2113 2114/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2115 2116#define BIT_SDIO_ON_EN BIT(16) 2117 2118/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2119 2120#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) 2121#define BIT_PCIE_WAIT_TIME BIT(9) 2122 2123/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2124 2125#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) 2126 2127/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2128 2129#define BIT_SHIFT_TSFT_SEL 29 2130#define BIT_MASK_TSFT_SEL 0x7 2131#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) 2132#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) 2133 2134/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2135 2136#define BIT_SHIFT_RPWM 24 2137#define BIT_MASK_RPWM 0xff 2138#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) 2139#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) 2140 2141#define BIT_ROM_DLEN BIT(19) 2142 2143#define BIT_SHIFT_ROM_PGE 16 2144#define BIT_MASK_ROM_PGE 0x7 2145#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) 2146#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) 2147 2148/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2149 2150#define BIT_USB_HOST_PWR_OFF_EN BIT(12) 2151 2152/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2153 2154#define BIT_SYM_LPS_BLOCK_EN BIT(11) 2155 2156/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2157 2158#define BIT_USB_LPM_ACT_EN BIT(10) 2159 2160/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2161 2162#define BIT_USB_LPM_NY BIT(9) 2163 2164/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2165 2166#define BIT_USB_SUS_DIS BIT(8) 2167 2168/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2169 2170#define BIT_SHIFT_SDIO_PAD_E 5 2171#define BIT_MASK_SDIO_PAD_E 0x7 2172#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) 2173#define BIT_GET_SDIO_PAD_E(x) \ 2174 (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) 2175 2176/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2177 2178#define BIT_USB_LPPLL_EN BIT(4) 2179 2180/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2181 2182#define BIT_ROP_SW15 BIT(2) 2183 2184/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2185 2186#define BIT_PCI_CKRDY_OPT BIT(1) 2187 2188/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2189 2190#define BIT_PCI_VAUX_EN BIT(0) 2191 2192/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2193 2194#define BIT_ZCD_HW_AUTO_EN BIT(27) 2195#define BIT_ZCD_REGSEL BIT(26) 2196 2197/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2198 2199#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 2200#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f 2201#define BIT_AUTO_ZCD_IN_CODE(x) \ 2202 (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) 2203#define BIT_GET_AUTO_ZCD_IN_CODE(x) \ 2204 (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) 2205 2206/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2207 2208#define BIT_SHIFT_ZCD_CODE_IN_L 16 2209#define BIT_MASK_ZCD_CODE_IN_L 0x1f 2210#define BIT_ZCD_CODE_IN_L(x) \ 2211 (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) 2212#define BIT_GET_ZCD_CODE_IN_L(x) \ 2213 (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) 2214 2215/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2216 2217#define BIT_SHIFT_LDO_HV5_DUMMY 14 2218#define BIT_MASK_LDO_HV5_DUMMY 0x3 2219#define BIT_LDO_HV5_DUMMY(x) \ 2220 (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) 2221#define BIT_GET_LDO_HV5_DUMMY(x) \ 2222 (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) 2223 2224/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2225 2226#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 2227#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 2228#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ 2229 (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ 2230 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) 2231#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ 2232 (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ 2233 BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) 2234 2235/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2236 2237#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 2238#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 2239#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ 2240 (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ 2241 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) 2242#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ 2243 (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ 2244 BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) 2245 2246/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2247 2248#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 2249#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 2250#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ 2251 (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ 2252 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) 2253#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ 2254 (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ 2255 BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) 2256 2257/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2258 2259#define BIT_REG_BYPASS_L BIT(7) 2260 2261/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2262 2263#define BIT_REG_LDOF_L BIT(6) 2264 2265/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2266 2267#define BIT_REG_TYPE_L_V1 BIT(5) 2268 2269/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2270 2271#define BIT_ARENB_L BIT(3) 2272 2273/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2274 2275#define BIT_SHIFT_CFC_L 1 2276#define BIT_MASK_CFC_L 0x3 2277#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) 2278#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) 2279 2280/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2281 2282#define BIT_REG_OCPS_L_V1 BIT(0) 2283 2284/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2285 2286#define BIT_ANA_PORT_EN BIT(22) 2287#define BIT_MAC_PORT_EN BIT(21) 2288#define BIT_BOOT_FSPI_EN BIT(20) 2289#define BIT_FW_INIT_RDY BIT(15) 2290#define BIT_FW_DW_RDY BIT(14) 2291 2292/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2293 2294#define BIT_SHIFT_CPU_CLK_SEL 12 2295#define BIT_MASK_CPU_CLK_SEL 0x3 2296#define BIT_CPU_CLK_SEL(x) \ 2297 (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) 2298#define BIT_GET_CPU_CLK_SEL(x) \ 2299 (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) 2300 2301/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2302 2303#define BIT_CCLK_CHG_MASK BIT(11) 2304 2305/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2306 2307#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) 2308 2309/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2310 2311#define BIT_EMEM_TXBUF_DW_RDY BIT(9) 2312 2313/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2314 2315#define BIT_EMEM_CHKSUM_OK BIT(8) 2316#define BIT_EMEM_DW_OK BIT(7) 2317#define BIT_TOGGLING BIT(7) 2318#define BIT_DMEM_CHKSUM_OK BIT(6) 2319#define BIT_ACK BIT(6) 2320 2321/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2322 2323#define BIT_DMEM_DW_OK BIT(5) 2324 2325/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2326 2327#define BIT_IMEM_CHKSUM_OK BIT(4) 2328 2329/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2330 2331#define BIT_IMEM_DW_OK BIT(3) 2332 2333/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2334 2335#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) 2336 2337/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2338 2339#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) 2340 2341/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ 2342 2343#define BIT_32K_PERMISSION BIT(0) 2344 2345/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ 2346 2347#define BIT_SHIFT_LBKTST 0 2348#define BIT_MASK_LBKTST 0xffff 2349#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) 2350#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) 2351 2352/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ 2353 2354#define BIT_PAD_CLK_XHGE_EN BIT(3) 2355#define BIT_INTER_CLK_EN BIT(2) 2356#define BIT_EN_RPT_TXCRC BIT(1) 2357#define BIT_DIS_RXDMA_STS BIT(0) 2358 2359/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ 2360 2361#define BIT_INTR_CTRL BIT(4) 2362#define BIT_SDIO_VOLTAGE BIT(3) 2363#define BIT_BYPASS_INIT BIT(2) 2364 2365/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ 2366 2367#define BIT_HCI_RESUME_RDY BIT(1) 2368#define BIT_HCI_SUS_REQ BIT(0) 2369 2370/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ 2371 2372#define BIT_SHIFT_HOST_MSG_E1 16 2373#define BIT_MASK_HOST_MSG_E1 0xffff 2374#define BIT_HOST_MSG_E1(x) \ 2375 (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) 2376#define BIT_GET_HOST_MSG_E1(x) \ 2377 (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) 2378 2379#define BIT_SHIFT_HOST_MSG_E0 0 2380#define BIT_MASK_HOST_MSG_E0 0xffff 2381#define BIT_HOST_MSG_E0(x) \ 2382 (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) 2383#define BIT_GET_HOST_MSG_E0(x) \ 2384 (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) 2385 2386/* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ 2387 2388#define BIT_SHIFT_CMDIN_2RESP_TIMER 0 2389#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff 2390#define BIT_CMDIN_2RESP_TIMER(x) \ 2391 (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) 2392#define BIT_GET_CMDIN_2RESP_TIMER(x) \ 2393 (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) 2394 2395/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ 2396 2397#define BIT_SHIFT_SDIO_CMD_CRC_V1 0 2398#define BIT_MASK_SDIO_CMD_CRC_V1 0xff 2399#define BIT_SDIO_CMD_CRC_V1(x) \ 2400 (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) 2401#define BIT_GET_SDIO_CMD_CRC_V1(x) \ 2402 (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) 2403 2404/* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ 2405 2406#define BIT_SHIFT_HOST_MSG_E3 16 2407#define BIT_MASK_HOST_MSG_E3 0xffff 2408#define BIT_HOST_MSG_E3(x) \ 2409 (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) 2410#define BIT_GET_HOST_MSG_E3(x) \ 2411 (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) 2412 2413#define BIT_SHIFT_HOST_MSG_E2 0 2414#define BIT_MASK_HOST_MSG_E2 0xffff 2415#define BIT_HOST_MSG_E2(x) \ 2416 (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) 2417#define BIT_GET_HOST_MSG_E2(x) \ 2418 (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) 2419 2420/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2421 2422#define BIT_WLLPSOP_EABM BIT(31) 2423 2424/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2425 2426#define BIT_WLLPSOP_ACKF BIT(30) 2427 2428/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2429 2430#define BIT_WLLPSOP_DLDM BIT(29) 2431 2432/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2433 2434#define BIT_WLLPSOP_ESWR BIT(28) 2435 2436/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2437 2438#define BIT_WLLPSOP_PWMM BIT(27) 2439#define BIT_WLLPSOP_EECK BIT(26) 2440 2441/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2442 2443#define BIT_WLLPSOP_WLMACOFF BIT(25) 2444 2445/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2446 2447#define BIT_WLLPSOP_EXTAL BIT(24) 2448 2449/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2450 2451#define BIT_WL_SYNPON_VOLTSPDN BIT(23) 2452 2453/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2454 2455#define BIT_WLLPSOP_WLBBOFF BIT(22) 2456 2457/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2458 2459#define BIT_WLLPSOP_WLMEM_DS BIT(21) 2460 2461/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2462 2463#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 2464#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf 2465#define BIT_LPLDH12_VADJ_STEP_DN(x) \ 2466 (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ 2467 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) 2468#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ 2469 (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ 2470 BIT_MASK_LPLDH12_VADJ_STEP_DN) 2471 2472/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2473 2474#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 2475#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 2476#define BIT_V15ADJ_L1_STEP_DN(x) \ 2477 (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) 2478#define BIT_GET_V15ADJ_L1_STEP_DN(x) \ 2479 (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) 2480 2481#define BIT_REGU_32K_CLK_EN BIT(1) 2482#define BIT_DRV_WLAN_INT_CLR BIT(1) 2483 2484/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2485 2486#define BIT_WL_LPS_EN BIT(0) 2487 2488/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ 2489 2490#define BIT_DRV_WLAN_INT BIT(0) 2491 2492/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ 2493 2494#define BIT_HISR_MASK BIT(0) 2495 2496/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2497 2498#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) 2499 2500/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2501 2502#define BIT_ORDER_SDM BIT(30) 2503#define BIT_RFE_SEL_SDM BIT(29) 2504 2505#define BIT_SHIFT_REF_SEL 25 2506#define BIT_MASK_REF_SEL 0xf 2507#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) 2508#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) 2509 2510/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2511 2512#define BIT_SHIFT_F0F_SDM 12 2513#define BIT_MASK_F0F_SDM 0x1fff 2514#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) 2515#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) 2516 2517/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2518 2519#define BIT_SHIFT_F0N_SDM 9 2520#define BIT_MASK_F0N_SDM 0x7 2521#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) 2522#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) 2523 2524/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2525 2526#define BIT_SHIFT_DIVN_SDM 3 2527#define BIT_MASK_DIVN_SDM 0x3f 2528#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) 2529#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) 2530 2531/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ 2532 2533#define BIT_WLGP_DBC1EN BIT(15) 2534 2535#define BIT_SHIFT_WLGP_DBC1 8 2536#define BIT_MASK_WLGP_DBC1 0xf 2537#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) 2538#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) 2539 2540#define BIT_WLGP_DBC0EN BIT(7) 2541 2542#define BIT_SHIFT_WLGP_DBC0 0 2543#define BIT_MASK_WLGP_DBC0 0xf 2544#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) 2545#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) 2546 2547/* 2 REG_RPWM2 (Offset 0x009C) */ 2548 2549#define BIT_SHIFT_RPWM2 16 2550#define BIT_MASK_RPWM2 0xffff 2551#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) 2552#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) 2553 2554/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ 2555 2556#define BIT_SHIFT_FSM_MON_SEL 24 2557#define BIT_MASK_FSM_MON_SEL 0x7 2558#define BIT_FSM_MON_SEL(x) \ 2559 (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) 2560#define BIT_GET_FSM_MON_SEL(x) \ 2561 (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) 2562 2563#define BIT_DOP_ELDO BIT(23) 2564#define BIT_FSM_MON_UPD BIT(15) 2565 2566#define BIT_SHIFT_FSM_PAR 0 2567#define BIT_MASK_FSM_PAR 0x7fff 2568#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) 2569#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) 2570 2571/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ 2572 2573#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 2574#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 2575#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ 2576 (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ 2577 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) 2578#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ 2579 (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ 2580 BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) 2581 2582/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ 2583 2584#define BIT_BT_INT_EN BIT(31) 2585 2586#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 2587#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff 2588#define BIT_RD_WR_WIFI_BT_INFO(x) \ 2589 (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) 2590#define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ 2591 (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) 2592 2593/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ 2594 2595#define BIT_PMC_WR_OVF BIT(8) 2596 2597#define BIT_SHIFT_WLPMC_ERRINT 0 2598#define BIT_MASK_WLPMC_ERRINT 0xff 2599#define BIT_WLPMC_ERRINT(x) \ 2600 (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) 2601#define BIT_GET_WLPMC_ERRINT(x) \ 2602 (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) 2603 2604/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2605 2606#define BIT_SHIFT_SEL_V 30 2607#define BIT_MASK_SEL_V 0x3 2608#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) 2609#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) 2610 2611/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2612 2613#define BIT_TXFIFO_TH_INT BIT(30) 2614 2615/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2616 2617#define BIT_SEL_LDO_PC BIT(29) 2618 2619/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2620 2621#define BIT_SHIFT_CK_MON_SEL 26 2622#define BIT_MASK_CK_MON_SEL 0x7 2623#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) 2624#define BIT_GET_CK_MON_SEL(x) \ 2625 (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) 2626 2627/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2628 2629#define BIT_CK_MON_EN BIT(25) 2630#define BIT_FREF_EDGE BIT(24) 2631#define BIT_CK320M_EN BIT(23) 2632#define BIT_CK_5M_EN BIT(22) 2633#define BIT_TESTEN BIT(21) 2634 2635/* 2 REG_HIMR0 (Offset 0x00B0) */ 2636 2637#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) 2638#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) 2639#define BIT_PSTIMEOUT_MSK BIT(29) 2640#define BIT_GTINT4_MSK BIT(28) 2641#define BIT_GTINT3_MSK BIT(27) 2642#define BIT_TXBCN0ERR_MSK BIT(26) 2643#define BIT_TXBCN0OK_MSK BIT(25) 2644#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) 2645#define BIT_BCNDMAINT0_MSK BIT(20) 2646#define BIT_BCNDERR0_MSK BIT(16) 2647#define BIT_HSISR_IND_ON_INT_MSK BIT(15) 2648 2649/* 2 REG_HIMR0 (Offset 0x00B0) */ 2650 2651#define BIT_BCNDMAINT_E_MSK BIT(14) 2652 2653/* 2 REG_HIMR0 (Offset 0x00B0) */ 2654 2655#define BIT_CTWEND_MSK BIT(12) 2656#define BIT_HISR1_IND_MSK BIT(11) 2657 2658/* 2 REG_HIMR0 (Offset 0x00B0) */ 2659 2660#define BIT_C2HCMD_MSK BIT(10) 2661#define BIT_CPWM2_MSK BIT(9) 2662#define BIT_CPWM_MSK BIT(8) 2663#define BIT_HIGHDOK_MSK BIT(7) 2664#define BIT_MGTDOK_MSK BIT(6) 2665#define BIT_BKDOK_MSK BIT(5) 2666#define BIT_BEDOK_MSK BIT(4) 2667#define BIT_VIDOK_MSK BIT(3) 2668#define BIT_VODOK_MSK BIT(2) 2669#define BIT_RDU_MSK BIT(1) 2670#define BIT_RXOK_MSK BIT(0) 2671 2672/* 2 REG_HISR0 (Offset 0x00B4) */ 2673 2674#define BIT_TIMEOUT_INTERRUPT2 BIT(31) 2675 2676/* 2 REG_HISR0 (Offset 0x00B4) */ 2677 2678#define BIT_TIMEOUT_INTERRUTP1 BIT(30) 2679 2680/* 2 REG_HISR0 (Offset 0x00B4) */ 2681 2682#define BIT_PSTIMEOUT BIT(29) 2683#define BIT_GTINT4 BIT(28) 2684#define BIT_GTINT3 BIT(27) 2685#define BIT_TXBCN0ERR BIT(26) 2686#define BIT_TXBCN0OK BIT(25) 2687#define BIT_TSF_BIT32_TOGGLE BIT(24) 2688#define BIT_BCNDMAINT0 BIT(20) 2689#define BIT_BCNDERR0 BIT(16) 2690#define BIT_HSISR_IND_ON_INT BIT(15) 2691 2692/* 2 REG_HISR0 (Offset 0x00B4) */ 2693 2694#define BIT_BCNDMAINT_E BIT(14) 2695 2696/* 2 REG_HISR0 (Offset 0x00B4) */ 2697 2698#define BIT_CTWEND BIT(12) 2699 2700/* 2 REG_HISR0 (Offset 0x00B4) */ 2701 2702#define BIT_HISR1_IND_INT BIT(11) 2703#define BIT_C2HCMD BIT(10) 2704#define BIT_CPWM2 BIT(9) 2705#define BIT_CPWM BIT(8) 2706#define BIT_HIGHDOK BIT(7) 2707#define BIT_MGTDOK BIT(6) 2708#define BIT_BKDOK BIT(5) 2709#define BIT_BEDOK BIT(4) 2710#define BIT_VIDOK BIT(3) 2711#define BIT_VODOK BIT(2) 2712#define BIT_RDU BIT(1) 2713#define BIT_RXOK BIT(0) 2714 2715/* 2 REG_HIMR1 (Offset 0x00B8) */ 2716 2717#define BIT_BTON_STS_UPDATE_MASK BIT(29) 2718 2719/* 2 REG_HIMR1 (Offset 0x00B8) */ 2720 2721#define BIT_MCU_ERR_MASK BIT(28) 2722 2723/* 2 REG_HIMR1 (Offset 0x00B8) */ 2724 2725#define BIT_BCNDMAINT7__MSK BIT(27) 2726 2727/* 2 REG_HIMR1 (Offset 0x00B8) */ 2728 2729#define BIT_BCNDMAINT6__MSK BIT(26) 2730 2731/* 2 REG_HIMR1 (Offset 0x00B8) */ 2732 2733#define BIT_BCNDMAINT5__MSK BIT(25) 2734 2735/* 2 REG_HIMR1 (Offset 0x00B8) */ 2736 2737#define BIT_BCNDMAINT4__MSK BIT(24) 2738 2739/* 2 REG_HIMR1 (Offset 0x00B8) */ 2740 2741#define BIT_BCNDMAINT3_MSK BIT(23) 2742#define BIT_BCNDMAINT2_MSK BIT(22) 2743#define BIT_BCNDMAINT1_MSK BIT(21) 2744#define BIT_BCNDERR7_MSK BIT(20) 2745#define BIT_BCNDERR6_MSK BIT(19) 2746#define BIT_BCNDERR5_MSK BIT(18) 2747#define BIT_BCNDERR4_MSK BIT(17) 2748#define BIT_BCNDERR3_MSK BIT(16) 2749#define BIT_BCNDERR2_MSK BIT(15) 2750#define BIT_BCNDERR1_MSK BIT(14) 2751 2752/* 2 REG_HIMR1 (Offset 0x00B8) */ 2753 2754#define BIT_ATIMEND_E_MSK BIT(13) 2755 2756/* 2 REG_HIMR1 (Offset 0x00B8) */ 2757 2758#define BIT_ATIMEND__MSK BIT(12) 2759 2760/* 2 REG_HIMR1 (Offset 0x00B8) */ 2761 2762#define BIT_TXERR_MSK BIT(11) 2763#define BIT_RXERR_MSK BIT(10) 2764#define BIT_TXFOVW_MSK BIT(9) 2765#define BIT_FOVW_MSK BIT(8) 2766 2767/* 2 REG_HIMR1 (Offset 0x00B8) */ 2768 2769#define BIT_CPU_MGQ_TXDONE_MSK BIT(5) 2770#define BIT_PS_TIMER_C_MSK BIT(4) 2771#define BIT_PS_TIMER_B_MSK BIT(3) 2772#define BIT_PS_TIMER_A_MSK BIT(2) 2773#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) 2774 2775/* 2 REG_HISR1 (Offset 0x00BC) */ 2776 2777#define BIT_BTON_STS_UPDATE_INT BIT(29) 2778 2779/* 2 REG_HISR1 (Offset 0x00BC) */ 2780 2781#define BIT_MCU_ERR BIT(28) 2782 2783/* 2 REG_HISR1 (Offset 0x00BC) */ 2784 2785#define BIT_BCNDMAINT7 BIT(27) 2786#define BIT_BCNDMAINT6 BIT(26) 2787#define BIT_BCNDMAINT5 BIT(25) 2788#define BIT_BCNDMAINT4 BIT(24) 2789#define BIT_BCNDMAINT3 BIT(23) 2790#define BIT_BCNDMAINT2 BIT(22) 2791#define BIT_BCNDMAINT1 BIT(21) 2792#define BIT_BCNDERR7 BIT(20) 2793#define BIT_BCNDERR6 BIT(19) 2794#define BIT_BCNDERR5 BIT(18) 2795#define BIT_BCNDERR4 BIT(17) 2796#define BIT_BCNDERR3 BIT(16) 2797#define BIT_BCNDERR2 BIT(15) 2798#define BIT_BCNDERR1 BIT(14) 2799 2800/* 2 REG_HISR1 (Offset 0x00BC) */ 2801 2802#define BIT_ATIMEND_E BIT(13) 2803 2804/* 2 REG_HISR1 (Offset 0x00BC) */ 2805 2806#define BIT_ATIMEND BIT(12) 2807#define BIT_TXERR_INT BIT(11) 2808#define BIT_RXERR_INT BIT(10) 2809#define BIT_TXFOVW BIT(9) 2810#define BIT_FOVW BIT(8) 2811 2812/* 2 REG_HISR1 (Offset 0x00BC) */ 2813 2814#define BIT_CPU_MGQ_TXDONE BIT(5) 2815#define BIT_PS_TIMER_C BIT(4) 2816#define BIT_PS_TIMER_B BIT(3) 2817#define BIT_PS_TIMER_A BIT(2) 2818#define BIT_CPUMGQ_TX_TIMER BIT(1) 2819 2820/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ 2821 2822#define BIT_HR_FF_OVF BIT(6) 2823#define BIT_HR_FF_UDN BIT(5) 2824#define BIT_TXDMA_BUSY_ERR BIT(4) 2825#define BIT_TXDMA_VLD_ERR BIT(3) 2826#define BIT_QSEL_UNKNOWN_ERR BIT(2) 2827#define BIT_QSEL_MIS_ERR BIT(1) 2828 2829/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ 2830 2831#define BIT_SHIFT_DEBUG_ST 0 2832#define BIT_MASK_DEBUG_ST 0xffffffffL 2833#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) 2834#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) 2835 2836/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ 2837 2838#define BIT_SDIO_OVERRD_ERR BIT(0) 2839 2840/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */ 2841 2842#define BIT_SHIFT_CMD_CRC_ERR_CNT 0 2843#define BIT_MASK_CMD_CRC_ERR_CNT 0xff 2844#define BIT_CMD_CRC_ERR_CNT(x) \ 2845 (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) 2846#define BIT_GET_CMD_CRC_ERR_CNT(x) \ 2847 (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) 2848 2849/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */ 2850 2851#define BIT_SHIFT_DATA_CRC_ERR_CNT 0 2852#define BIT_MASK_DATA_CRC_ERR_CNT 0xff 2853#define BIT_DATA_CRC_ERR_CNT(x) \ 2854 (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) 2855#define BIT_GET_DATA_CRC_ERR_CNT(x) \ 2856 (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) 2857 2858/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2859 2860#define BIT_USB3_USB2_TRANSITION BIT(20) 2861 2862/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2863 2864#define BIT_SHIFT_USB23_SW_MODE_V1 18 2865#define BIT_MASK_USB23_SW_MODE_V1 0x3 2866#define BIT_USB23_SW_MODE_V1(x) \ 2867 (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) 2868#define BIT_GET_USB23_SW_MODE_V1(x) \ 2869 (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) 2870 2871/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2872 2873#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) 2874 2875/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2876 2877#define BIT_RSM_EN_V1 BIT(16) 2878 2879/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2880 2881#define BIT_LD_B12V_EN BIT(7) 2882 2883/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2884 2885#define BIT_EECS_IOSEL_V1 BIT(6) 2886 2887/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2888 2889#define BIT_EECS_DATA_O_V1 BIT(5) 2890 2891/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2892 2893#define BIT_EECS_DATA_I_V1 BIT(4) 2894 2895/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2896 2897#define BIT_EESK_IOSEL_V1 BIT(2) 2898 2899/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2900 2901#define BIT_EESK_DATA_O_V1 BIT(1) 2902 2903/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2904 2905#define BIT_EESK_DATA_I_V1 BIT(0) 2906 2907/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ 2908 2909#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 2910#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL 2911#define BIT_SDIO_CMD_ERR_CONTENT(x) \ 2912 (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ 2913 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) 2914#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ 2915 (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ 2916 BIT_MASK_SDIO_CMD_ERR_CONTENT) 2917 2918/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ 2919 2920#define BIT_D3_CRC_ERR BIT(4) 2921#define BIT_D2_CRC_ERR BIT(3) 2922#define BIT_D1_CRC_ERR BIT(2) 2923#define BIT_D0_CRC_ERR BIT(1) 2924#define BIT_CMD_CRC_ERR BIT(0) 2925 2926/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ 2927 2928#define BIT_SHIFT_SDIO_DATA_CRC 0 2929#define BIT_MASK_SDIO_DATA_CRC 0xff 2930#define BIT_SDIO_DATA_CRC(x) \ 2931 (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) 2932#define BIT_GET_SDIO_DATA_CRC(x) \ 2933 (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) 2934 2935/* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */ 2936 2937#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 2938#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 2939#define BIT_SDIO_DATA_REPLY_TIME(x) \ 2940 (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ 2941 << BIT_SHIFT_SDIO_DATA_REPLY_TIME) 2942#define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ 2943 (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ 2944 BIT_MASK_SDIO_DATA_REPLY_TIME) 2945 2946/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2947 2948#define BIT_SHIFT_EFUSE_BURN_GNT 24 2949#define BIT_MASK_EFUSE_BURN_GNT 0xff 2950#define BIT_EFUSE_BURN_GNT(x) \ 2951 (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) 2952#define BIT_GET_EFUSE_BURN_GNT(x) \ 2953 (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) 2954 2955/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2956 2957#define BIT_STOP_WL_PMC BIT(9) 2958#define BIT_STOP_SYM_PMC BIT(8) 2959 2960/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2961 2962#define BIT_REG_RST_WLPMC BIT(5) 2963#define BIT_REG_RST_PD12N BIT(4) 2964#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) 2965#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) 2966 2967#define BIT_SHIFT_SYSON_REG_ARB 0 2968#define BIT_MASK_SYSON_REG_ARB 0x3 2969#define BIT_SYSON_REG_ARB(x) \ 2970 (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) 2971#define BIT_GET_SYSON_REG_ARB(x) \ 2972 (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) 2973 2974/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2975 2976#define BIT_BIST_USB_DIS BIT(27) 2977 2978/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2979 2980#define BIT_BIST_PCI_DIS BIT(26) 2981 2982/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2983 2984#define BIT_BIST_BT_DIS BIT(25) 2985 2986/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2987 2988#define BIT_BIST_WL_DIS BIT(24) 2989 2990/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2991 2992#define BIT_SHIFT_BIST_RPT_SEL 16 2993#define BIT_MASK_BIST_RPT_SEL 0xf 2994#define BIT_BIST_RPT_SEL(x) \ 2995 (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) 2996#define BIT_GET_BIST_RPT_SEL(x) \ 2997 (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) 2998 2999/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 3000
3001#define BIT_BIST_RESUME_PS BIT(4) 3002 3003/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 3004 3005#define BIT_BIST_RESUME BIT(3) 3006#define BIT_BIST_NORMAL BIT(2) 3007 3008/* 2 REG_BIST_CTRL (Offset 0x00D0) */ 3009 3010#define BIT_BIST_RSTN BIT(1) 3011#define BIT_BIST_CLK_EN BIT(0) 3012 3013/* 2 REG_BIST_RPT (Offset 0x00D4) */ 3014 3015#define BIT_SHIFT_MBIST_REPORT 0 3016#define BIT_MASK_MBIST_REPORT 0xffffffffL 3017#define BIT_MBIST_REPORT(x) \ 3018 (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) 3019#define BIT_GET_MBIST_REPORT(x) \ 3020 (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) 3021 3022/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3023 3024#define BIT_UMEM_RME BIT(31) 3025 3026/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3027 3028#define BIT_SHIFT_BT_SPRAM 28 3029#define BIT_MASK_BT_SPRAM 0x3 3030#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) 3031#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) 3032 3033/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3034 3035#define BIT_SHIFT_BT_ROM 24 3036#define BIT_MASK_BT_ROM 0xf 3037#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) 3038#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) 3039 3040#define BIT_SHIFT_PCI_DPRAM 10 3041#define BIT_MASK_PCI_DPRAM 0x3 3042#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) 3043#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) 3044 3045/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3046 3047#define BIT_SHIFT_PCI_SPRAM 8 3048#define BIT_MASK_PCI_SPRAM 0x3 3049#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) 3050#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) 3051 3052#define BIT_SHIFT_USB_SPRAM 6 3053#define BIT_MASK_USB_SPRAM 0x3 3054#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) 3055#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) 3056 3057/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3058 3059#define BIT_SHIFT_USB_SPRF 4 3060#define BIT_MASK_USB_SPRF 0x3 3061#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) 3062#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) 3063 3064/* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3065 3066#define BIT_SHIFT_MCU_ROM 0 3067#define BIT_MASK_MCU_ROM 0xf 3068#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) 3069#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) 3070 3071/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3072 3073#define BIT_SYN_AGPIO BIT(20) 3074 3075/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3076 3077#define BIT_XTAL_LP BIT(4) 3078#define BIT_XTAL_GM_SEP BIT(3) 3079 3080/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3081 3082#define BIT_SHIFT_XTAL_SEL_TOK 0 3083#define BIT_MASK_XTAL_SEL_TOK 0x7 3084#define BIT_XTAL_SEL_TOK(x) \ 3085 (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) 3086#define BIT_GET_XTAL_SEL_TOK(x) \ 3087 (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) 3088 3089/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3090 3091#define BIT_RD_SEL BIT(31) 3092 3093/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3094 3095#define BIT_USB_SIE_INTF_WE_V1 BIT(30) 3096#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) 3097#define BIT_USB_SIE_SELECT BIT(28) 3098 3099/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3100 3101#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 3102#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff 3103#define BIT_USB_SIE_INTF_ADDR_V1(x) \ 3104 (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ 3105 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) 3106#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ 3107 (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ 3108 BIT_MASK_USB_SIE_INTF_ADDR_V1) 3109 3110/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3111 3112#define BIT_SHIFT_USB_SIE_INTF_RD 8 3113#define BIT_MASK_USB_SIE_INTF_RD 0xff 3114#define BIT_USB_SIE_INTF_RD(x) \ 3115 (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) 3116#define BIT_GET_USB_SIE_INTF_RD(x) \ 3117 (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) 3118 3119#define BIT_SHIFT_USB_SIE_INTF_WD 0 3120#define BIT_MASK_USB_SIE_INTF_WD 0xff 3121#define BIT_USB_SIE_INTF_WD(x) \ 3122 (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) 3123#define BIT_GET_USB_SIE_INTF_WD(x) \ 3124 (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) 3125 3126/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ 3127 3128#define BIT_PCIE_MIO_BYIOREG BIT(13) 3129#define BIT_PCIE_MIO_RE BIT(12) 3130 3131#define BIT_SHIFT_PCIE_MIO_WE 8 3132#define BIT_MASK_PCIE_MIO_WE 0xf 3133#define BIT_PCIE_MIO_WE(x) \ 3134 (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) 3135#define BIT_GET_PCIE_MIO_WE(x) \ 3136 (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) 3137 3138#define BIT_SHIFT_PCIE_MIO_ADDR 0 3139#define BIT_MASK_PCIE_MIO_ADDR 0xff 3140#define BIT_PCIE_MIO_ADDR(x) \ 3141 (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) 3142#define BIT_GET_PCIE_MIO_ADDR(x) \ 3143 (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) 3144 3145/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ 3146 3147#define BIT_SHIFT_PCIE_MIO_DATA 0 3148#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL 3149#define BIT_PCIE_MIO_DATA(x) \ 3150 (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) 3151#define BIT_GET_PCIE_MIO_DATA(x) \ 3152 (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) 3153 3154/* 2 REG_WLRF1 (Offset 0x00EC) */ 3155 3156#define BIT_SHIFT_WLRF1_CTRL 24 3157#define BIT_MASK_WLRF1_CTRL 0xff 3158#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) 3159#define BIT_GET_WLRF1_CTRL(x) \ 3160 (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) 3161 3162/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3163 3164#define BIT_SHIFT_TRP_ICFG 28 3165#define BIT_MASK_TRP_ICFG 0xf 3166#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) 3167#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) 3168 3169/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3170 3171#define BIT_RF_TYPE_ID BIT(27) 3172#define BIT_BD_HCI_SEL BIT(26) 3173 3174/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3175 3176#define BIT_BD_PKG_SEL BIT(25) 3177 3178/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3179 3180#define BIT_SPSLDO_SEL BIT(24) 3181 3182/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3183 3184#define BIT_RTL_ID BIT(23) 3185#define BIT_PAD_HWPD_IDN BIT(22) 3186 3187/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3188 3189#define BIT_TESTMODE BIT(20) 3190 3191/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3192 3193#define BIT_SHIFT_VENDOR_ID 16 3194#define BIT_MASK_VENDOR_ID 0xf 3195#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 3196#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 3197 3198/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3199 3200#define BIT_SHIFT_CHIP_VER 12 3201#define BIT_MASK_CHIP_VER 0xf 3202#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 3203#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 3204 3205/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3206 3207#define BIT_BD_MAC3 BIT(11) 3208 3209/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3210 3211#define BIT_BD_MAC1 BIT(10) 3212#define BIT_BD_MAC2 BIT(9) 3213#define BIT_SIC_IDLE BIT(8) 3214#define BIT_SW_OFFLOAD_EN BIT(7) 3215 3216/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3217 3218#define BIT_OCP_SHUTDN BIT(6) 3219 3220/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3221 3222#define BIT_V15_VLD BIT(5) 3223 3224/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3225 3226#define BIT_PCIRSTB BIT(4) 3227 3228/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3229 3230#define BIT_PCLK_VLD BIT(3) 3231 3232/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3233 3234#define BIT_UCLK_VLD BIT(2) 3235 3236/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3237 3238#define BIT_ACLK_VLD BIT(1) 3239 3240/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3241 3242#define BIT_XCLK_VLD BIT(0) 3243 3244/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3245 3246#define BIT_SHIFT_RF_RL_ID 28 3247#define BIT_MASK_RF_RL_ID 0xf 3248#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) 3249#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) 3250 3251/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3252 3253#define BIT_HPHY_ICFG BIT(19) 3254 3255/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3256 3257#define BIT_SHIFT_SEL_0XC0 16 3258#define BIT_MASK_SEL_0XC0 0x3 3259#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) 3260#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) 3261 3262/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3263 3264#define BIT_SHIFT_HCI_SEL_V3 12 3265#define BIT_MASK_HCI_SEL_V3 0x7 3266#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) 3267#define BIT_GET_HCI_SEL_V3(x) \ 3268 (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) 3269 3270/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3271 3272#define BIT_USB_OPERATION_MODE BIT(10) 3273#define BIT_BT_PDN BIT(9) 3274#define BIT_AUTO_WLPON BIT(8) 3275 3276/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3277 3278#define BIT_WL_MODE BIT(7) 3279 3280/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3281 3282#define BIT_PKG_SEL_HCI BIT(6) 3283 3284/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3285 3286#define BIT_SHIFT_PAD_HCI_SEL_V1 3 3287#define BIT_MASK_PAD_HCI_SEL_V1 0x7 3288#define BIT_PAD_HCI_SEL_V1(x) \ 3289 (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) 3290#define BIT_GET_PAD_HCI_SEL_V1(x) \ 3291 (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) 3292 3293/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3294 3295#define BIT_SHIFT_EFS_HCI_SEL_V1 0 3296#define BIT_MASK_EFS_HCI_SEL_V1 0x7 3297#define BIT_EFS_HCI_SEL_V1(x) \ 3298 (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) 3299#define BIT_GET_EFS_HCI_SEL_V1(x) \ 3300 (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) 3301 3302/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ 3303 3304#define BIT_SIO_ALDN BIT(19) 3305#define BIT_USB_ALDN BIT(18) 3306#define BIT_PCI_ALDN BIT(17) 3307#define BIT_SYS_ALDN BIT(16) 3308 3309#define BIT_SHIFT_EPVID1 8 3310#define BIT_MASK_EPVID1 0xff 3311#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) 3312#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) 3313 3314#define BIT_SHIFT_EPVID0 0 3315#define BIT_MASK_EPVID0 0xff 3316#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) 3317#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) 3318 3319/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ 3320 3321#define BIT_HCI_SEL_EMBEDDED BIT(8) 3322 3323/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ 3324 3325#define BIT_SHIFT_HW_ID 0 3326#define BIT_MASK_HW_ID 0xff 3327#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) 3328#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) 3329 3330/* 2 REG_CR (Offset 0x0100) */ 3331 3332#define BIT_SHIFT_LBMODE 24 3333#define BIT_MASK_LBMODE 0x1f 3334#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) 3335#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) 3336 3337#define BIT_SHIFT_NETYPE1 18 3338#define BIT_MASK_NETYPE1 0x3 3339#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) 3340#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) 3341 3342#define BIT_SHIFT_NETYPE0 16 3343#define BIT_MASK_NETYPE0 0x3 3344#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) 3345#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) 3346 3347/* 2 REG_CR (Offset 0x0100) */ 3348 3349#define BIT_I2C_MAILBOX_EN BIT(12) 3350#define BIT_SHCUT_EN BIT(11) 3351 3352/* 2 REG_CR (Offset 0x0100) */ 3353 3354#define BIT_32K_CAL_TMR_EN BIT(10) 3355#define BIT_MAC_SEC_EN BIT(9) 3356#define BIT_ENSWBCN BIT(8) 3357#define BIT_MACRXEN BIT(7) 3358#define BIT_MACTXEN BIT(6) 3359#define BIT_SCHEDULE_EN BIT(5) 3360#define BIT_PROTOCOL_EN BIT(4) 3361#define BIT_RXDMA_EN BIT(3) 3362#define BIT_TXDMA_EN BIT(2) 3363#define BIT_HCI_RXDMA_EN BIT(1) 3364#define BIT_HCI_TXDMA_EN BIT(0) 3365 3366/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ 3367 3368#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 3369#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff 3370#define BIT_PKT_BUFF_ACCESS_CTRL(x) \ 3371 (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ 3372 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) 3373#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ 3374 (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ 3375 BIT_MASK_PKT_BUFF_ACCESS_CTRL) 3376 3377/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ 3378 3379#define BIT_TSF_CLK_STABLE BIT(15) 3380 3381#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 3382#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 3383#define BIT_I2C_M_BUS_GNT_FW(x) \ 3384 (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) 3385#define BIT_GET_I2C_M_BUS_GNT_FW(x) \ 3386 (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) 3387 3388#define BIT_I2C_M_GNT_FW BIT(3) 3389 3390#define BIT_SHIFT_I2C_M_SPEED 1 3391#define BIT_MASK_I2C_M_SPEED 0x3 3392#define BIT_I2C_M_SPEED(x) \ 3393 (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) 3394#define BIT_GET_I2C_M_SPEED(x) \ 3395 (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) 3396 3397#define BIT_I2C_M_UNLOCK BIT(0) 3398 3399/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ 3400 3401#define BIT_SHIFT_TXDMA_HIQ_MAP 14 3402#define BIT_MASK_TXDMA_HIQ_MAP 0x3 3403#define BIT_TXDMA_HIQ_MAP(x) \ 3404 (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 3405#define BIT_GET_TXDMA_HIQ_MAP(x) \ 3406 (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) 3407 3408#define BIT_SHIFT_TXDMA_MGQ_MAP 12 3409#define BIT_MASK_TXDMA_MGQ_MAP 0x3 3410#define BIT_TXDMA_MGQ_MAP(x) \ 3411 (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 3412#define BIT_GET_TXDMA_MGQ_MAP(x) \ 3413 (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) 3414 3415#define BIT_SHIFT_TXDMA_BKQ_MAP 10 3416#define BIT_MASK_TXDMA_BKQ_MAP 0x3 3417#define BIT_TXDMA_BKQ_MAP(x) \ 3418 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 3419#define BIT_GET_TXDMA_BKQ_MAP(x) \ 3420 (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) 3421 3422#define BIT_SHIFT_TXDMA_BEQ_MAP 8 3423#define BIT_MASK_TXDMA_BEQ_MAP 0x3 3424#define BIT_TXDMA_BEQ_MAP(x) \ 3425 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 3426#define BIT_GET_TXDMA_BEQ_MAP(x) \ 3427 (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) 3428 3429#define BIT_SHIFT_TXDMA_VIQ_MAP 6 3430#define BIT_MASK_TXDMA_VIQ_MAP 0x3 3431#define BIT_TXDMA_VIQ_MAP(x) \ 3432 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 3433#define BIT_GET_TXDMA_VIQ_MAP(x) \ 3434 (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) 3435 3436#define BIT_SHIFT_TXDMA_VOQ_MAP 4 3437#define BIT_MASK_TXDMA_VOQ_MAP 0x3 3438#define BIT_TXDMA_VOQ_MAP(x) \ 3439 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 3440#define BIT_GET_TXDMA_VOQ_MAP(x) \ 3441 (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) 3442 3443#define BIT_RXDMA_AGG_EN BIT(2) 3444#define BIT_RXSHFT_EN BIT(1) 3445#define BIT_RXDMA_ARBBW_EN BIT(0) 3446 3447/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3448 3449#define BIT_SHIFT_RXFFOVFL_RSV_V2 8 3450#define BIT_MASK_RXFFOVFL_RSV_V2 0xf 3451#define BIT_RXFFOVFL_RSV_V2(x) \ 3452 (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) 3453#define BIT_GET_RXFFOVFL_RSV_V2(x) \ 3454 (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) 3455 3456/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3457 3458#define BIT_SHIFT_TXPKTBUF_PGBNDY 0 3459#define BIT_MASK_TXPKTBUF_PGBNDY 0xff 3460#define BIT_TXPKTBUF_PGBNDY(x) \ 3461 (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) 3462#define BIT_GET_TXPKTBUF_PGBNDY(x) \ 3463 (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) 3464 3465/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3466 3467#define BIT_SHIFT_RXFF0_BNDY_V2 0 3468#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff 3469#define BIT_RXFF0_BNDY_V2(x) \ 3470 (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) 3471#define BIT_GET_RXFF0_BNDY_V2(x) \ 3472 (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) 3473 3474#define BIT_SHIFT_RXFF0_RDPTR_V2 0 3475#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff 3476#define BIT_RXFF0_RDPTR_V2(x) \ 3477 (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) 3478#define BIT_GET_RXFF0_RDPTR_V2(x) \ 3479 (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) 3480 3481#define BIT_SHIFT_RXFF0_WTPTR_V2 0 3482#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff 3483#define BIT_RXFF0_WTPTR_V2(x) \ 3484 (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) 3485#define BIT_GET_RXFF0_WTPTR_V2(x) \ 3486 (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) 3487 3488/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ 3489 3490#define BIT_SHIFT_I2C_M_STATUS 8 3491#define BIT_MASK_I2C_M_STATUS 0xf 3492#define BIT_I2C_M_STATUS(x) \ 3493 (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) 3494#define BIT_GET_I2C_M_STATUS(x) \ 3495 (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) 3496 3497/* 2 REG_FE1IMR (Offset 0x0120) */ 3498 3499#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) 3500#define BIT_FS_RXDONE3_INT_EN BIT(27) 3501#define BIT_FS_RXDONE2_INT_EN BIT(26) 3502#define BIT_FS_RX_BCN_P4_INT_EN BIT(25) 3503#define BIT_FS_RX_BCN_P3_INT_EN BIT(24) 3504#define BIT_FS_RX_BCN_P2_INT_EN BIT(23) 3505#define BIT_FS_RX_BCN_P1_INT_EN BIT(22) 3506#define BIT_FS_RX_BCN_P0_INT_EN BIT(21) 3507#define BIT_FS_RX_UMD0_INT_EN BIT(20) 3508#define BIT_FS_RX_UMD1_INT_EN BIT(19) 3509#define BIT_FS_RX_BMD0_INT_EN BIT(18) 3510#define BIT_FS_RX_BMD1_INT_EN BIT(17) 3511#define BIT_FS_RXDONE_INT_EN BIT(16) 3512#define BIT_FS_WWLAN_INT_EN BIT(15) 3513#define BIT_FS_SOUND_DONE_INT_EN BIT(14) 3514#define BIT_FS_LP_STBY_INT_EN BIT(13) 3515#define BIT_FS_TRL_MTR_INT_EN BIT(12) 3516#define BIT_FS_BF1_PRETO_INT_EN BIT(11) 3517#define BIT_FS_BF0_PRETO_INT_EN BIT(10) 3518#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) 3519 3520/* 2 REG_FE1IMR (Offset 0x0120) */ 3521 3522#define BIT_FS_LTE_COEX_EN BIT(6) 3523 3524/* 2 REG_FE1IMR (Offset 0x0120) */ 3525 3526#define BIT_FS_WLACTOFF_INT_EN BIT(5) 3527#define BIT_FS_WLACTON_INT_EN BIT(4) 3528#define BIT_FS_BTCMD_INT_EN BIT(3) 3529 3530/* 2 REG_FE1IMR (Offset 0x0120) */ 3531 3532#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) 3533 3534/* 2 REG_FE1IMR (Offset 0x0120) */ 3535 3536#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) 3537 3538/* 2 REG_FE1IMR (Offset 0x0120) */ 3539 3540#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) 3541 3542/* 2 REG_FE1ISR (Offset 0x0124) */ 3543 3544#define BIT_FS_RXDMA2_DONE_INT BIT(28) 3545#define BIT_FS_RXDONE3_INT BIT(27) 3546#define BIT_FS_RXDONE2_INT BIT(26) 3547#define BIT_FS_RX_BCN_P4_INT BIT(25) 3548#define BIT_FS_RX_BCN_P3_INT BIT(24) 3549#define BIT_FS_RX_BCN_P2_INT BIT(23) 3550#define BIT_FS_RX_BCN_P1_INT BIT(22) 3551#define BIT_FS_RX_BCN_P0_INT BIT(21) 3552#define BIT_FS_RX_UMD0_INT BIT(20) 3553#define BIT_FS_RX_UMD1_INT BIT(19) 3554#define BIT_FS_RX_BMD0_INT BIT(18) 3555#define BIT_FS_RX_BMD1_INT BIT(17) 3556#define BIT_FS_RXDONE_INT BIT(16) 3557#define BIT_FS_WWLAN_INT BIT(15) 3558#define BIT_FS_SOUND_DONE_INT BIT(14) 3559#define BIT_FS_LP_STBY_INT BIT(13) 3560#define BIT_FS_TRL_MTR_INT BIT(12) 3561#define BIT_FS_BF1_PRETO_INT BIT(11) 3562#define BIT_FS_BF0_PRETO_INT BIT(10) 3563#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) 3564 3565/* 2 REG_FE1ISR (Offset 0x0124) */ 3566 3567#define BIT_FS_LTE_COEX_INT BIT(6) 3568 3569/* 2 REG_FE1ISR (Offset 0x0124) */ 3570 3571#define BIT_FS_WLACTOFF_INT BIT(5) 3572#define BIT_FS_WLACTON_INT BIT(4) 3573#define BIT_FS_BCN_RX_INT_INT BIT(3) 3574 3575/* 2 REG_FE1ISR (Offset 0x0124) */ 3576 3577#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) 3578 3579/* 2 REG_FE1ISR (Offset 0x0124) */ 3580 3581#define BIT_FS_TRPC_TO_INT BIT(1) 3582 3583/* 2 REG_FE1ISR (Offset 0x0124) */ 3584 3585#define BIT_FS_RPC_O_T_INT BIT(0) 3586 3587/* 2 REG_CPWM (Offset 0x012C) */ 3588 3589#define BIT_CPWM_TOGGLING BIT(31) 3590 3591#define BIT_SHIFT_CPWM_MOD 24 3592#define BIT_MASK_CPWM_MOD 0x7f 3593#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) 3594#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) 3595 3596/* 2 REG_FWIMR (Offset 0x0130) */ 3597 3598#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) 3599 3600/* 2 REG_FWIMR (Offset 0x0130) */ 3601 3602#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) 3603 3604/* 2 REG_FWIMR (Offset 0x0130) */ 3605 3606#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) 3607 3608/* 2 REG_FWIMR (Offset 0x0130) */ 3609 3610#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) 3611 3612/* 2 REG_FWIMR (Offset 0x0130) */ 3613 3614#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) 3615 3616/* 2 REG_FWIMR (Offset 0x0130) */ 3617 3618#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) 3619 3620/* 2 REG_FWIMR (Offset 0x0130) */ 3621 3622#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) 3623 3624/* 2 REG_FWIMR (Offset 0x0130) */ 3625 3626#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) 3627 3628/* 2 REG_FWIMR (Offset 0x0130) */ 3629 3630#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) 3631 3632/* 2 REG_FWIMR (Offset 0x0130) */ 3633 3634#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) 3635 3636/* 2 REG_FWIMR (Offset 0x0130) */ 3637 3638#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) 3639 3640/* 2 REG_FWIMR (Offset 0x0130) */ 3641 3642#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) 3643 3644/* 2 REG_FWIMR (Offset 0x0130) */ 3645 3646#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) 3647 3648/* 2 REG_FWIMR (Offset 0x0130) */ 3649 3650#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) 3651 3652/* 2 REG_FWIMR (Offset 0x0130) */ 3653 3654#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) 3655 3656/* 2 REG_FWIMR (Offset 0x0130) */ 3657 3658#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) 3659 3660/* 2 REG_FWIMR (Offset 0x0130) */ 3661 3662#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) 3663 3664/* 2 REG_FWIMR (Offset 0x0130) */ 3665 3666#define BIT_SIFS_OVERSPEC_INT_EN BIT(14) 3667 3668/* 2 REG_FWIMR (Offset 0x0130) */ 3669 3670#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) 3671 3672/* 2 REG_FWIMR (Offset 0x0130) */ 3673 3674#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) 3675 3676/* 2 REG_FWIMR (Offset 0x0130) */ 3677 3678#define BIT_FS_DDMA1_LP_INT_EN BIT(11) 3679 3680/* 2 REG_FWIMR (Offset 0x0130) */ 3681 3682#define BIT_FS_DDMA1_HP_INT_EN BIT(10) 3683 3684/* 2 REG_FWIMR (Offset 0x0130) */ 3685 3686#define BIT_FS_DDMA0_LP_INT_EN BIT(9) 3687 3688/* 2 REG_FWIMR (Offset 0x0130) */ 3689 3690#define BIT_FS_DDMA0_HP_INT_EN BIT(8) 3691 3692/* 2 REG_FWIMR (Offset 0x0130) */ 3693 3694#define BIT_FS_TRXRPT_INT_EN BIT(7) 3695 3696/* 2 REG_FWIMR (Offset 0x0130) */ 3697 3698#define BIT_FS_C2H_W_READY_INT_EN BIT(6) 3699 3700/* 2 REG_FWIMR (Offset 0x0130) */ 3701 3702#define BIT_FS_HRCV_INT_EN BIT(5) 3703 3704/* 2 REG_FWIMR (Offset 0x0130) */ 3705 3706#define BIT_FS_H2CCMD_INT_EN BIT(4) 3707 3708/* 2 REG_FWIMR (Offset 0x0130) */ 3709 3710#define BIT_FS_TXPKTIN_INT_EN BIT(3) 3711 3712/* 2 REG_FWIMR (Offset 0x0130) */ 3713 3714#define BIT_FS_ERRORHDL_INT_EN BIT(2) 3715 3716/* 2 REG_FWIMR (Offset 0x0130) */ 3717 3718#define BIT_FS_TXCCX_INT_EN BIT(1) 3719 3720/* 2 REG_FWIMR (Offset 0x0130) */ 3721 3722#define BIT_FS_TXCLOSE_INT_EN BIT(0) 3723 3724/* 2 REG_FWISR (Offset 0x0134) */ 3725 3726#define BIT_FS_TXBCNOK_MB7_INT BIT(31) 3727 3728/* 2 REG_FWISR (Offset 0x0134) */ 3729 3730#define BIT_FS_TXBCNOK_MB6_INT BIT(30) 3731 3732/* 2 REG_FWISR (Offset 0x0134) */ 3733 3734#define BIT_FS_TXBCNOK_MB5_INT BIT(29) 3735 3736/* 2 REG_FWISR (Offset 0x0134) */ 3737 3738#define BIT_FS_TXBCNOK_MB4_INT BIT(28) 3739 3740/* 2 REG_FWISR (Offset 0x0134) */ 3741 3742#define BIT_FS_TXBCNOK_MB3_INT BIT(27) 3743 3744/* 2 REG_FWISR (Offset 0x0134) */ 3745 3746#define BIT_FS_TXBCNOK_MB2_INT BIT(26) 3747 3748/* 2 REG_FWISR (Offset 0x0134) */ 3749 3750#define BIT_FS_TXBCNOK_MB1_INT BIT(25) 3751 3752/* 2 REG_FWISR (Offset 0x0134) */ 3753 3754#define BIT_FS_TXBCNOK_MB0_INT BIT(24) 3755 3756/* 2 REG_FWISR (Offset 0x0134) */ 3757 3758#define BIT_FS_TXBCNERR_MB7_INT BIT(23) 3759 3760/* 2 REG_FWISR (Offset 0x0134) */ 3761 3762#define BIT_FS_TXBCNERR_MB6_INT BIT(22) 3763 3764/* 2 REG_FWISR (Offset 0x0134) */ 3765 3766#define BIT_FS_TXBCNERR_MB5_INT BIT(21) 3767 3768/* 2 REG_FWISR (Offset 0x0134) */ 3769 3770#define BIT_FS_TXBCNERR_MB4_INT BIT(20) 3771 3772/* 2 REG_FWISR (Offset 0x0134) */ 3773 3774#define BIT_FS_TXBCNERR_MB3_INT BIT(19) 3775 3776/* 2 REG_FWISR (Offset 0x0134) */ 3777 3778#define BIT_FS_TXBCNERR_MB2_INT BIT(18) 3779 3780/* 2 REG_FWISR (Offset 0x0134) */ 3781 3782#define BIT_FS_TXBCNERR_MB1_INT BIT(17) 3783 3784/* 2 REG_FWISR (Offset 0x0134) */ 3785 3786#define BIT_FS_TXBCNERR_MB0_INT BIT(16) 3787 3788/* 2 REG_FWISR (Offset 0x0134) */ 3789 3790#define BIT_CPU_MGQ_TXDONE_INT BIT(15) 3791 3792/* 2 REG_FWISR (Offset 0x0134) */ 3793 3794#define BIT_SIFS_OVERSPEC_INT BIT(14) 3795 3796/* 2 REG_FWISR (Offset 0x0134) */ 3797 3798#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) 3799 3800/* 2 REG_FWISR (Offset 0x0134) */ 3801 3802#define BIT_FS_MGNTQFF_TO_INT BIT(12) 3803 3804/* 2 REG_FWISR (Offset 0x0134) */ 3805 3806#define BIT_FS_DDMA1_LP_INT BIT(11) 3807 3808/* 2 REG_FWISR (Offset 0x0134) */ 3809 3810#define BIT_FS_DDMA1_HP_INT BIT(10) 3811 3812/* 2 REG_FWISR (Offset 0x0134) */ 3813 3814#define BIT_FS_DDMA0_LP_INT BIT(9) 3815 3816/* 2 REG_FWISR (Offset 0x0134) */ 3817 3818#define BIT_FS_DDMA0_HP_INT BIT(8) 3819 3820/* 2 REG_FWISR (Offset 0x0134) */ 3821 3822#define BIT_FS_TRXRPT_INT BIT(7) 3823 3824/* 2 REG_FWISR (Offset 0x0134) */ 3825 3826#define BIT_FS_C2H_W_READY_INT BIT(6) 3827 3828/* 2 REG_FWISR (Offset 0x0134) */ 3829 3830#define BIT_FS_HRCV_INT BIT(5) 3831 3832/* 2 REG_FWISR (Offset 0x0134) */ 3833 3834#define BIT_FS_H2CCMD_INT BIT(4) 3835 3836/* 2 REG_FWISR (Offset 0x0134) */ 3837 3838#define BIT_FS_TXPKTIN_INT BIT(3) 3839 3840/* 2 REG_FWISR (Offset 0x0134) */ 3841 3842#define BIT_FS_ERRORHDL_INT BIT(2) 3843 3844/* 2 REG_FWISR (Offset 0x0134) */ 3845 3846#define BIT_FS_TXCCX_INT BIT(1) 3847 3848/* 2 REG_FWISR (Offset 0x0134) */ 3849 3850#define BIT_FS_TXCLOSE_INT BIT(0) 3851 3852/* 2 REG_FTIMR (Offset 0x0138) */ 3853 3854#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) 3855 3856/* 2 REG_FTIMR (Offset 0x0138) */ 3857 3858#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) 3859 3860/* 2 REG_FTIMR (Offset 0x0138) */ 3861 3862#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) 3863 3864/* 2 REG_FTIMR (Offset 0x0138) */ 3865 3866#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) 3867 3868/* 2 REG_FTIMR (Offset 0x0138) */ 3869 3870#define BIT_PS_TIMER_C_INT_EN BIT(19) 3871 3872/* 2 REG_FTIMR (Offset 0x0138) */ 3873 3874#define BIT_PS_TIMER_B_INT_EN BIT(18) 3875 3876/* 2 REG_FTIMR (Offset 0x0138) */ 3877 3878#define BIT_PS_TIMER_A_INT_EN BIT(17) 3879 3880/* 2 REG_FTIMR (Offset 0x0138) */ 3881 3882#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) 3883 3884/* 2 REG_FTIMR (Offset 0x0138) */ 3885 3886#define BIT_FS_PS_TIMEOUT2_EN BIT(15) 3887 3888/* 2 REG_FTIMR (Offset 0x0138) */ 3889 3890#define BIT_FS_PS_TIMEOUT1_EN BIT(14) 3891 3892/* 2 REG_FTIMR (Offset 0x0138) */ 3893 3894#define BIT_FS_PS_TIMEOUT0_EN BIT(13) 3895 3896/* 2 REG_FTIMR (Offset 0x0138) */ 3897 3898#define BIT_FS_GTINT8_EN BIT(8) 3899 3900/* 2 REG_FTIMR (Offset 0x0138) */ 3901 3902#define BIT_FS_GTINT7_EN BIT(7) 3903 3904/* 2 REG_FTIMR (Offset 0x0138) */ 3905 3906#define BIT_FS_GTINT6_EN BIT(6) 3907 3908/* 2 REG_FTIMR (Offset 0x0138) */ 3909 3910#define BIT_FS_GTINT5_EN BIT(5) 3911 3912/* 2 REG_FTIMR (Offset 0x0138) */ 3913 3914#define BIT_FS_GTINT4_EN BIT(4) 3915 3916/* 2 REG_FTIMR (Offset 0x0138) */ 3917 3918#define BIT_FS_GTINT3_EN BIT(3) 3919 3920/* 2 REG_FTIMR (Offset 0x0138) */ 3921 3922#define BIT_FS_GTINT2_EN BIT(2) 3923 3924/* 2 REG_FTIMR (Offset 0x0138) */ 3925 3926#define BIT_FS_GTINT1_EN BIT(1) 3927 3928/* 2 REG_FTIMR (Offset 0x0138) */ 3929 3930#define BIT_FS_GTINT0_EN BIT(0) 3931 3932/* 2 REG_FTISR (Offset 0x013C) */ 3933 3934#define BIT_PS_TIMER_C_EARLY__INT BIT(23) 3935 3936/* 2 REG_FTISR (Offset 0x013C) */ 3937 3938#define BIT_PS_TIMER_B_EARLY__INT BIT(22) 3939 3940/* 2 REG_FTISR (Offset 0x013C) */ 3941 3942#define BIT_PS_TIMER_A_EARLY__INT BIT(21) 3943 3944/* 2 REG_FTISR (Offset 0x013C) */ 3945 3946#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) 3947 3948/* 2 REG_FTISR (Offset 0x013C) */ 3949 3950#define BIT_PS_TIMER_C_INT BIT(19) 3951 3952/* 2 REG_FTISR (Offset 0x013C) */ 3953 3954#define BIT_PS_TIMER_B_INT BIT(18) 3955 3956/* 2 REG_FTISR (Offset 0x013C) */ 3957 3958#define BIT_PS_TIMER_A_INT BIT(17) 3959 3960/* 2 REG_FTISR (Offset 0x013C) */ 3961 3962#define BIT_CPUMGQ_TX_TIMER_INT BIT(16) 3963 3964/* 2 REG_FTISR (Offset 0x013C) */ 3965 3966#define BIT_FS_PS_TIMEOUT2_INT BIT(15) 3967 3968/* 2 REG_FTISR (Offset 0x013C) */ 3969 3970#define BIT_FS_PS_TIMEOUT1_INT BIT(14) 3971 3972/* 2 REG_FTISR (Offset 0x013C) */ 3973 3974#define BIT_FS_PS_TIMEOUT0_INT BIT(13) 3975 3976/* 2 REG_FTISR (Offset 0x013C) */ 3977 3978#define BIT_FS_GTINT8_INT BIT(8) 3979 3980/* 2 REG_FTISR (Offset 0x013C) */ 3981 3982#define BIT_FS_GTINT7_INT BIT(7) 3983 3984/* 2 REG_FTISR (Offset 0x013C) */ 3985 3986#define BIT_FS_GTINT6_INT BIT(6) 3987 3988/* 2 REG_FTISR (Offset 0x013C) */ 3989 3990#define BIT_FS_GTINT5_INT BIT(5) 3991 3992/* 2 REG_FTISR (Offset 0x013C) */ 3993 3994#define BIT_FS_GTINT4_INT BIT(4) 3995 3996/* 2 REG_FTISR (Offset 0x013C) */ 3997 3998#define BIT_FS_GTINT3_INT BIT(3) 3999 4000/* 2 REG_FTISR (Offset 0x013C) */
4001 4002#define BIT_FS_GTINT2_INT BIT(2) 4003 4004/* 2 REG_FTISR (Offset 0x013C) */ 4005 4006#define BIT_FS_GTINT1_INT BIT(1) 4007 4008/* 2 REG_FTISR (Offset 0x013C) */ 4009 4010#define BIT_FS_GTINT0_INT BIT(0) 4011 4012/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4013 4014#define BIT_SHIFT_PKTBUF_WRITE_EN 24 4015#define BIT_MASK_PKTBUF_WRITE_EN 0xff 4016#define BIT_PKTBUF_WRITE_EN(x) \ 4017 (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) 4018#define BIT_GET_PKTBUF_WRITE_EN(x) \ 4019 (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) 4020 4021/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4022 4023#define BIT_TXRPTBUF_DBG BIT(23) 4024 4025/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4026 4027#define BIT_TXPKTBUF_DBG_V2 BIT(20) 4028 4029/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4030 4031#define BIT_RXPKTBUF_DBG BIT(16) 4032 4033/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4034 4035#define BIT_SHIFT_PKTBUF_DBG_ADDR 0 4036#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff 4037#define BIT_PKTBUF_DBG_ADDR(x) \ 4038 (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) 4039#define BIT_GET_PKTBUF_DBG_ADDR(x) \ 4040 (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) 4041 4042/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ 4043 4044#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 4045#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL 4046#define BIT_PKTBUF_DBG_DATA_L(x) \ 4047 (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) 4048#define BIT_GET_PKTBUF_DBG_DATA_L(x) \ 4049 (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) 4050 4051/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ 4052 4053#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 4054#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL 4055#define BIT_PKTBUF_DBG_DATA_H(x) \ 4056 (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) 4057#define BIT_GET_PKTBUF_DBG_DATA_H(x) \ 4058 (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) 4059 4060/* 2 REG_CPWM2 (Offset 0x014C) */ 4061 4062#define BIT_SHIFT_L0S_TO_RCVY_NUM 16 4063#define BIT_MASK_L0S_TO_RCVY_NUM 0xff 4064#define BIT_L0S_TO_RCVY_NUM(x) \ 4065 (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) 4066#define BIT_GET_L0S_TO_RCVY_NUM(x) \ 4067 (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) 4068 4069#define BIT_CPWM2_TOGGLING BIT(15) 4070 4071#define BIT_SHIFT_CPWM2_MOD 0 4072#define BIT_MASK_CPWM2_MOD 0x7fff 4073#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) 4074#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) 4075 4076/* 2 REG_TC0_CTRL (Offset 0x0150) */ 4077 4078#define BIT_TC0INT_EN BIT(26) 4079#define BIT_TC0MODE BIT(25) 4080#define BIT_TC0EN BIT(24) 4081 4082#define BIT_SHIFT_TC0DATA 0 4083#define BIT_MASK_TC0DATA 0xffffff 4084#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) 4085#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) 4086 4087/* 2 REG_TC1_CTRL (Offset 0x0154) */ 4088 4089#define BIT_TC1INT_EN BIT(26) 4090#define BIT_TC1MODE BIT(25) 4091#define BIT_TC1EN BIT(24) 4092 4093#define BIT_SHIFT_TC1DATA 0 4094#define BIT_MASK_TC1DATA 0xffffff 4095#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) 4096#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) 4097 4098/* 2 REG_TC2_CTRL (Offset 0x0158) */ 4099 4100#define BIT_TC2INT_EN BIT(26) 4101#define BIT_TC2MODE BIT(25) 4102#define BIT_TC2EN BIT(24) 4103 4104#define BIT_SHIFT_TC2DATA 0 4105#define BIT_MASK_TC2DATA 0xffffff 4106#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) 4107#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) 4108 4109/* 2 REG_TC3_CTRL (Offset 0x015C) */ 4110 4111#define BIT_TC3INT_EN BIT(26) 4112#define BIT_TC3MODE BIT(25) 4113#define BIT_TC3EN BIT(24) 4114 4115#define BIT_SHIFT_TC3DATA 0 4116#define BIT_MASK_TC3DATA 0xffffff 4117#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) 4118#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) 4119 4120/* 2 REG_TC4_CTRL (Offset 0x0160) */ 4121 4122#define BIT_TC4INT_EN BIT(26) 4123#define BIT_TC4MODE BIT(25) 4124#define BIT_TC4EN BIT(24) 4125 4126#define BIT_SHIFT_TC4DATA 0 4127#define BIT_MASK_TC4DATA 0xffffff 4128#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) 4129#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) 4130 4131/* 2 REG_TCUNIT_BASE (Offset 0x0164) */ 4132 4133#define BIT_SHIFT_TCUNIT_BASE 0 4134#define BIT_MASK_TCUNIT_BASE 0x3fff 4135#define BIT_TCUNIT_BASE(x) \ 4136 (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) 4137#define BIT_GET_TCUNIT_BASE(x) \ 4138 (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) 4139 4140/* 2 REG_TC5_CTRL (Offset 0x0168) */ 4141 4142#define BIT_TC5INT_EN BIT(26) 4143 4144/* 2 REG_TC5_CTRL (Offset 0x0168) */ 4145 4146#define BIT_TC5MODE BIT(25) 4147#define BIT_TC5EN BIT(24) 4148 4149#define BIT_SHIFT_TC5DATA 0 4150#define BIT_MASK_TC5DATA 0xffffff 4151#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) 4152#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) 4153 4154/* 2 REG_TC6_CTRL (Offset 0x016C) */ 4155 4156#define BIT_TC6INT_EN BIT(26) 4157 4158/* 2 REG_TC6_CTRL (Offset 0x016C) */ 4159 4160#define BIT_TC6MODE BIT(25) 4161#define BIT_TC6EN BIT(24) 4162 4163#define BIT_SHIFT_TC6DATA 0 4164#define BIT_MASK_TC6DATA 0xffffff 4165#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) 4166#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) 4167 4168/* 2 REG_MBIST_FAIL (Offset 0x0170) */ 4169 4170#define BIT_SHIFT_8051_MBIST_FAIL 26 4171#define BIT_MASK_8051_MBIST_FAIL 0x7 4172#define BIT_8051_MBIST_FAIL(x) \ 4173 (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) 4174#define BIT_GET_8051_MBIST_FAIL(x) \ 4175 (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) 4176 4177#define BIT_SHIFT_USB_MBIST_FAIL 24 4178#define BIT_MASK_USB_MBIST_FAIL 0x3 4179#define BIT_USB_MBIST_FAIL(x) \ 4180 (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) 4181#define BIT_GET_USB_MBIST_FAIL(x) \ 4182 (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) 4183 4184#define BIT_SHIFT_PCIE_MBIST_FAIL 16 4185#define BIT_MASK_PCIE_MBIST_FAIL 0x3f 4186#define BIT_PCIE_MBIST_FAIL(x) \ 4187 (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) 4188#define BIT_GET_PCIE_MBIST_FAIL(x) \ 4189 (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) 4190 4191/* 2 REG_MBIST_FAIL (Offset 0x0170) */ 4192 4193#define BIT_SHIFT_MAC_MBIST_FAIL 0 4194#define BIT_MASK_MAC_MBIST_FAIL 0xfff 4195#define BIT_MAC_MBIST_FAIL(x) \ 4196 (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) 4197#define BIT_GET_MAC_MBIST_FAIL(x) \ 4198 (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) 4199 4200/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ 4201 4202#define BIT_SHIFT_8051_MBIST_START_PAUSE 26 4203#define BIT_MASK_8051_MBIST_START_PAUSE 0x7 4204#define BIT_8051_MBIST_START_PAUSE(x) \ 4205 (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \ 4206 << BIT_SHIFT_8051_MBIST_START_PAUSE) 4207#define BIT_GET_8051_MBIST_START_PAUSE(x) \ 4208 (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \ 4209 BIT_MASK_8051_MBIST_START_PAUSE) 4210 4211#define BIT_SHIFT_USB_MBIST_START_PAUSE 24 4212#define BIT_MASK_USB_MBIST_START_PAUSE 0x3 4213#define BIT_USB_MBIST_START_PAUSE(x) \ 4214 (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \ 4215 << BIT_SHIFT_USB_MBIST_START_PAUSE) 4216#define BIT_GET_USB_MBIST_START_PAUSE(x) \ 4217 (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \ 4218 BIT_MASK_USB_MBIST_START_PAUSE) 4219 4220#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 4221#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f 4222#define BIT_PCIE_MBIST_START_PAUSE(x) \ 4223 (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \ 4224 << BIT_SHIFT_PCIE_MBIST_START_PAUSE) 4225#define BIT_GET_PCIE_MBIST_START_PAUSE(x) \ 4226 (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \ 4227 BIT_MASK_PCIE_MBIST_START_PAUSE) 4228 4229/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ 4230 4231#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 4232#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff 4233#define BIT_MAC_MBIST_START_PAUSE(x) \ 4234 (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \ 4235 << BIT_SHIFT_MAC_MBIST_START_PAUSE) 4236#define BIT_GET_MAC_MBIST_START_PAUSE(x) \ 4237 (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \ 4238 BIT_MASK_MAC_MBIST_START_PAUSE) 4239 4240/* 2 REG_MBIST_DONE (Offset 0x0178) */ 4241 4242#define BIT_SHIFT_8051_MBIST_DONE 26 4243#define BIT_MASK_8051_MBIST_DONE 0x7 4244#define BIT_8051_MBIST_DONE(x) \ 4245 (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) 4246#define BIT_GET_8051_MBIST_DONE(x) \ 4247 (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) 4248 4249#define BIT_SHIFT_USB_MBIST_DONE 24 4250#define BIT_MASK_USB_MBIST_DONE 0x3 4251#define BIT_USB_MBIST_DONE(x) \ 4252 (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) 4253#define BIT_GET_USB_MBIST_DONE(x) \ 4254 (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) 4255 4256#define BIT_SHIFT_PCIE_MBIST_DONE 16 4257#define BIT_MASK_PCIE_MBIST_DONE 0x3f 4258#define BIT_PCIE_MBIST_DONE(x) \ 4259 (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) 4260#define BIT_GET_PCIE_MBIST_DONE(x) \ 4261 (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) 4262 4263/* 2 REG_MBIST_DONE (Offset 0x0178) */ 4264 4265#define BIT_SHIFT_MAC_MBIST_DONE 0 4266#define BIT_MASK_MAC_MBIST_DONE 0xfff 4267#define BIT_MAC_MBIST_DONE(x) \ 4268 (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) 4269#define BIT_GET_MAC_MBIST_DONE(x) \ 4270 (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) 4271 4272/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ 4273 4274#define BIT_SHIFT_MBIST_FAIL_NRML 0 4275#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL 4276#define BIT_MBIST_FAIL_NRML(x) \ 4277 (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) 4278#define BIT_GET_MBIST_FAIL_NRML(x) \ 4279 (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) 4280 4281/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ 4282 4283#define BIT_SHIFT_IPS_CFG_ADDR 0 4284#define BIT_MASK_IPS_CFG_ADDR 0xff 4285#define BIT_IPS_CFG_ADDR(x) \ 4286 (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) 4287#define BIT_GET_IPS_CFG_ADDR(x) \ 4288 (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) 4289 4290/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ 4291 4292#define BIT_SHIFT_IPS_CFG_DATA 0 4293#define BIT_MASK_IPS_CFG_DATA 0xffffffffL 4294#define BIT_IPS_CFG_DATA(x) \ 4295 (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) 4296#define BIT_GET_IPS_CFG_DATA(x) \ 4297 (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) 4298 4299/* 2 REG_TMETER (Offset 0x0190) */ 4300 4301#define BIT_TEMP_VALID BIT(31) 4302 4303#define BIT_SHIFT_TEMP_VALUE 24 4304#define BIT_MASK_TEMP_VALUE 0x3f 4305#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) 4306#define BIT_GET_TEMP_VALUE(x) \ 4307 (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) 4308 4309#define BIT_SHIFT_REG_TMETER_TIMER 8 4310#define BIT_MASK_REG_TMETER_TIMER 0xfff 4311#define BIT_REG_TMETER_TIMER(x) \ 4312 (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) 4313#define BIT_GET_REG_TMETER_TIMER(x) \ 4314 (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) 4315 4316#define BIT_SHIFT_REG_TEMP_DELTA 2 4317#define BIT_MASK_REG_TEMP_DELTA 0x3f 4318#define BIT_REG_TEMP_DELTA(x) \ 4319 (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) 4320#define BIT_GET_REG_TEMP_DELTA(x) \ 4321 (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) 4322 4323#define BIT_REG_TMETER_EN BIT(0) 4324 4325/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4326 4327#define BIT_SHIFT_OSC_32K_CLKGEN_0 16 4328#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff 4329#define BIT_OSC_32K_CLKGEN_0(x) \ 4330 (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) 4331#define BIT_GET_OSC_32K_CLKGEN_0(x) \ 4332 (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) 4333 4334/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4335 4336#define BIT_SHIFT_OSC_32K_RES_COMP 4 4337#define BIT_MASK_OSC_32K_RES_COMP 0x3 4338#define BIT_OSC_32K_RES_COMP(x) \ 4339 (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) 4340#define BIT_GET_OSC_32K_RES_COMP(x) \ 4341 (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) 4342 4343#define BIT_OSC_32K_OUT_SEL BIT(3) 4344 4345/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4346 4347#define BIT_ISO_WL_2_OSC_32K BIT(1) 4348 4349/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4350 4351#define BIT_POW_CKGEN BIT(0) 4352 4353/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ 4354 4355#define BIT_CAL_32K_REG_WR BIT(31) 4356#define BIT_CAL_32K_DBG_SEL BIT(22) 4357 4358#define BIT_SHIFT_CAL_32K_REG_ADDR 16 4359#define BIT_MASK_CAL_32K_REG_ADDR 0x3f 4360#define BIT_CAL_32K_REG_ADDR(x) \ 4361 (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) 4362#define BIT_GET_CAL_32K_REG_ADDR(x) \ 4363 (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) 4364 4365/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ 4366 4367#define BIT_SHIFT_CAL_32K_REG_DATA 0 4368#define BIT_MASK_CAL_32K_REG_DATA 0xffff 4369#define BIT_CAL_32K_REG_DATA(x) \ 4370 (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) 4371#define BIT_GET_CAL_32K_REG_DATA(x) \ 4372 (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) 4373 4374/* 2 REG_C2HEVT (Offset 0x01A0) */ 4375 4376#define BIT_SHIFT_C2HEVT_MSG 0 4377#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL 4378#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) 4379#define BIT_GET_C2HEVT_MSG(x) \ 4380 (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) 4381 4382/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ 4383 4384#define BIT_SHIFT_SW_DEFINED_PAGE1 0 4385#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL 4386#define BIT_SW_DEFINED_PAGE1(x) \ 4387 (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) 4388#define BIT_GET_SW_DEFINED_PAGE1(x) \ 4389 (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) 4390 4391/* 2 REG_MCUTST_I (Offset 0x01C0) */ 4392 4393#define BIT_SHIFT_MCUDMSG_I 0 4394#define BIT_MASK_MCUDMSG_I 0xffffffffL 4395#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) 4396#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) 4397 4398/* 2 REG_MCUTST_II (Offset 0x01C4) */ 4399 4400#define BIT_SHIFT_MCUDMSG_II 0 4401#define BIT_MASK_MCUDMSG_II 0xffffffffL 4402#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) 4403#define BIT_GET_MCUDMSG_II(x) \ 4404 (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) 4405 4406/* 2 REG_FMETHR (Offset 0x01C8) */ 4407 4408#define BIT_FMSG_INT BIT(31) 4409 4410#define BIT_SHIFT_FW_MSG 0 4411#define BIT_MASK_FW_MSG 0xffffffffL 4412#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) 4413#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) 4414 4415/* 2 REG_HMETFR (Offset 0x01CC) */ 4416 4417#define BIT_SHIFT_HRCV_MSG 24 4418#define BIT_MASK_HRCV_MSG 0xff 4419#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) 4420#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) 4421 4422#define BIT_INT_BOX3 BIT(3) 4423#define BIT_INT_BOX2 BIT(2) 4424#define BIT_INT_BOX1 BIT(1) 4425#define BIT_INT_BOX0 BIT(0) 4426 4427/* 2 REG_HMEBOX0 (Offset 0x01D0) */ 4428 4429#define BIT_SHIFT_HOST_MSG_0 0 4430#define BIT_MASK_HOST_MSG_0 0xffffffffL 4431#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) 4432#define BIT_GET_HOST_MSG_0(x) \ 4433 (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) 4434 4435/* 2 REG_HMEBOX1 (Offset 0x01D4) */ 4436 4437#define BIT_SHIFT_HOST_MSG_1 0 4438#define BIT_MASK_HOST_MSG_1 0xffffffffL 4439#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) 4440#define BIT_GET_HOST_MSG_1(x) \ 4441 (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) 4442 4443/* 2 REG_HMEBOX2 (Offset 0x01D8) */ 4444 4445#define BIT_SHIFT_HOST_MSG_2 0 4446#define BIT_MASK_HOST_MSG_2 0xffffffffL 4447#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) 4448#define BIT_GET_HOST_MSG_2(x) \ 4449 (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) 4450 4451/* 2 REG_HMEBOX3 (Offset 0x01DC) */ 4452 4453#define BIT_SHIFT_HOST_MSG_3 0 4454#define BIT_MASK_HOST_MSG_3 0xffffffffL 4455#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) 4456#define BIT_GET_HOST_MSG_3(x) \ 4457 (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) 4458 4459/* 2 REG_LLT_INIT (Offset 0x01E0) */ 4460 4461#define BIT_SHIFT_LLTE_RWM 30 4462#define BIT_MASK_LLTE_RWM 0x3 4463#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) 4464#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) 4465 4466/* 2 REG_LLT_INIT (Offset 0x01E0) */ 4467 4468#define BIT_SHIFT_LLTINI_PDATA_V1 16 4469#define BIT_MASK_LLTINI_PDATA_V1 0xfff 4470#define BIT_LLTINI_PDATA_V1(x) \ 4471 (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) 4472#define BIT_GET_LLTINI_PDATA_V1(x) \ 4473 (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) 4474 4475/* 2 REG_LLT_INIT (Offset 0x01E0) */ 4476 4477#define BIT_SHIFT_LLTINI_HDATA_V1 0 4478#define BIT_MASK_LLTINI_HDATA_V1 0xfff 4479#define BIT_LLTINI_HDATA_V1(x) \ 4480 (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) 4481#define BIT_GET_LLTINI_HDATA_V1(x) \ 4482 (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) 4483 4484/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ 4485 4486#define BIT_SHIFT_LLTINI_ADDR_V1 0 4487#define BIT_MASK_LLTINI_ADDR_V1 0xfff 4488#define BIT_LLTINI_ADDR_V1(x) \ 4489 (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) 4490#define BIT_GET_LLTINI_ADDR_V1(x) \ 4491 (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) 4492 4493/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4494 4495#define BIT_SHIFT_BB_WRITE_READ 30 4496#define BIT_MASK_BB_WRITE_READ 0x3 4497#define BIT_BB_WRITE_READ(x) \ 4498 (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) 4499#define BIT_GET_BB_WRITE_READ(x) \ 4500 (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) 4501 4502/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4503 4504#define BIT_SHIFT_BB_WRITE_EN 12 4505#define BIT_MASK_BB_WRITE_EN 0xf 4506#define BIT_BB_WRITE_EN(x) \ 4507 (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) 4508#define BIT_GET_BB_WRITE_EN(x) \ 4509 (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) 4510 4511#define BIT_SHIFT_BB_ADDR 2 4512#define BIT_MASK_BB_ADDR 0x1ff 4513#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) 4514#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) 4515 4516/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4517 4518#define BIT_BB_ERRACC BIT(0) 4519 4520/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ 4521 4522#define BIT_SHIFT_BB_DATA 0 4523#define BIT_MASK_BB_DATA 0xffffffffL 4524#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) 4525#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) 4526 4527/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ 4528 4529#define BIT_SHIFT_HMEBOX_E0 0 4530#define BIT_MASK_HMEBOX_E0 0xffffffffL 4531#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) 4532#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) 4533 4534/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ 4535 4536#define BIT_SHIFT_HMEBOX_E1 0 4537#define BIT_MASK_HMEBOX_E1 0xffffffffL 4538#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) 4539#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) 4540 4541/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ 4542 4543#define BIT_SHIFT_HMEBOX_E2 0 4544#define BIT_MASK_HMEBOX_E2 0xffffffffL 4545#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) 4546#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) 4547 4548/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ 4549 4550#define BIT_LD_RQPN BIT(31) 4551 4552#define BIT_SHIFT_HMEBOX_E3 0 4553#define BIT_MASK_HMEBOX_E3 0xffffffffL 4554#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) 4555#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) 4556 4557/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ 4558 4559#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 4560#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff 4561#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \ 4562 (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \ 4563 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) 4564#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \ 4565 (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \ 4566 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) 4567 4568/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ 4569 4570#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 4571#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff 4572#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \ 4573 (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \ 4574 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) 4575#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \ 4576 (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \ 4577 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) 4578 4579/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4580 4581#define BIT_BCN_VALID_1_V1 BIT(31) 4582 4583/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4584 4585#define BIT_SHIFT_BCN_HEAD_1_V1 16 4586#define BIT_MASK_BCN_HEAD_1_V1 0xfff 4587#define BIT_BCN_HEAD_1_V1(x) \ 4588 (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) 4589#define BIT_GET_BCN_HEAD_1_V1(x) \ 4590 (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) 4591 4592#define BIT_BCN_VALID_V1 BIT(15) 4593 4594/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4595 4596#define BIT_SHIFT_BCN_HEAD_V1 0 4597#define BIT_MASK_BCN_HEAD_V1 0xfff 4598#define BIT_BCN_HEAD_V1(x) \ 4599 (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) 4600#define BIT_GET_BCN_HEAD_V1(x) \ 4601 (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) 4602 4603/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4604 4605#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 4606#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff 4607#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ 4608 (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \ 4609 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) 4610#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ 4611 (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \ 4612 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) 4613 4614/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4615 4616#define BIT_SHIFT_LLT_FREE_PAGE_V1 8 4617#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff 4618#define BIT_LLT_FREE_PAGE_V1(x) \ 4619 (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) 4620#define BIT_GET_LLT_FREE_PAGE_V1(x) \ 4621 (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) 4622 4623/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ 4624 4625#define BIT_SHIFT_BLK_DESC_NUM 4 4626#define BIT_MASK_BLK_DESC_NUM 0xf 4627#define BIT_BLK_DESC_NUM(x) \ 4628 (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) 4629#define BIT_GET_BLK_DESC_NUM(x) \ 4630 (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) 4631 4632/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4633 4634#define BIT_R_BCN_HEAD_SEL BIT(3) 4635#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) 4636#define BIT_LLT_DBG_SEL BIT(1) 4637#define BIT_AUTO_INIT_LLT_V1 BIT(0) 4638 4639/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4640 4641#define BIT_EM_CHKSUM_FIN BIT(31) 4642#define BIT_EMN_PCIE_DMA_MOD BIT(30) 4643 4644/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4645 4646#define BIT_EN_TXQUE_CLR BIT(29) 4647#define BIT_EN_PCIE_FIFO_MODE BIT(28) 4648 4649/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4650 4651#define BIT_SHIFT_PG_UNDER_TH_V1 16 4652#define BIT_MASK_PG_UNDER_TH_V1 0xfff 4653#define BIT_PG_UNDER_TH_V1(x) \ 4654 (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) 4655#define BIT_GET_PG_UNDER_TH_V1(x) \ 4656 (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) 4657 4658/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4659 4660#define BIT_RESTORE_H2C_ADDRESS BIT(15) 4661 4662/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4663 4664#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) 4665#define BIT_RST_RDPTR BIT(12) 4666#define BIT_RST_WRPTR BIT(11) 4667#define BIT_CHK_PG_TH_EN BIT(10) 4668#define BIT_DROP_DATA_EN BIT(9) 4669#define BIT_CHECK_OFFSET_EN BIT(8) 4670 4671#define BIT_SHIFT_CHECK_OFFSET 0 4672#define BIT_MASK_CHECK_OFFSET 0xff 4673#define BIT_CHECK_OFFSET(x) \ 4674 (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) 4675#define BIT_GET_CHECK_OFFSET(x) \ 4676 (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) 4677 4678/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ 4679 4680#define BIT_HI_OQT_UDN BIT(17) 4681#define BIT_HI_OQT_OVF BIT(16) 4682#define BIT_PAYLOAD_CHKSUM_ERR BIT(15) 4683#define BIT_PAYLOAD_UDN BIT(14) 4684#define BIT_PAYLOAD_OVF BIT(13) 4685#define BIT_DSC_CHKSUM_FAIL BIT(12) 4686#define BIT_UNKNOWN_QSEL BIT(11) 4687#define BIT_EP_QSEL_DIFF BIT(10) 4688#define BIT_TX_OFFS_UNMATCH BIT(9) 4689#define BIT_TXOQT_UDN BIT(8) 4690#define BIT_TXOQT_OVF BIT(7) 4691#define BIT_TXDMA_SFF_UDN BIT(6) 4692#define BIT_TXDMA_SFF_OVF BIT(5) 4693#define BIT_LLT_NULL_PG BIT(4) 4694#define BIT_PAGE_UDN BIT(3) 4695#define BIT_PAGE_OVF BIT(2) 4696#define BIT_TXFF_PG_UDN BIT(1) 4697#define BIT_TXFF_PG_OVF BIT(0) 4698 4699/* 2 REG_TQPNT1 (Offset 0x0218) */ 4700 4701#define BIT_SHIFT_HPQ_HIGH_TH_V1 16 4702#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff 4703#define BIT_HPQ_HIGH_TH_V1(x) \ 4704 (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) 4705#define BIT_GET_HPQ_HIGH_TH_V1(x) \ 4706 (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) 4707 4708/* 2 REG_TQPNT1 (Offset 0x0218) */ 4709 4710#define BIT_SHIFT_HPQ_LOW_TH_V1 0 4711#define BIT_MASK_HPQ_LOW_TH_V1 0xfff 4712#define BIT_HPQ_LOW_TH_V1(x) \ 4713 (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) 4714#define BIT_GET_HPQ_LOW_TH_V1(x) \ 4715 (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) 4716 4717/* 2 REG_TQPNT2 (Offset 0x021C) */ 4718 4719#define BIT_SHIFT_NPQ_HIGH_TH_V1 16 4720#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff 4721#define BIT_NPQ_HIGH_TH_V1(x) \ 4722 (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) 4723#define BIT_GET_NPQ_HIGH_TH_V1(x) \ 4724 (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) 4725 4726/* 2 REG_TQPNT2 (Offset 0x021C) */ 4727 4728#define BIT_SHIFT_NPQ_LOW_TH_V1 0 4729#define BIT_MASK_NPQ_LOW_TH_V1 0xfff 4730#define BIT_NPQ_LOW_TH_V1(x) \ 4731 (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) 4732#define BIT_GET_NPQ_LOW_TH_V1(x) \ 4733 (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) 4734 4735/* 2 REG_TQPNT3 (Offset 0x0220) */ 4736 4737#define BIT_SHIFT_LPQ_HIGH_TH_V1 16 4738#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff 4739#define BIT_LPQ_HIGH_TH_V1(x) \ 4740 (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) 4741#define BIT_GET_LPQ_HIGH_TH_V1(x) \ 4742 (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) 4743 4744/* 2 REG_TQPNT3 (Offset 0x0220) */ 4745 4746#define BIT_SHIFT_LPQ_LOW_TH_V1 0 4747#define BIT_MASK_LPQ_LOW_TH_V1 0xfff 4748#define BIT_LPQ_LOW_TH_V1(x) \ 4749 (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) 4750#define BIT_GET_LPQ_LOW_TH_V1(x) \ 4751 (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) 4752 4753/* 2 REG_TQPNT4 (Offset 0x0224) */ 4754 4755#define BIT_SHIFT_EXQ_HIGH_TH_V1 16 4756#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff 4757#define BIT_EXQ_HIGH_TH_V1(x) \ 4758 (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) 4759#define BIT_GET_EXQ_HIGH_TH_V1(x) \ 4760 (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) 4761 4762/* 2 REG_TQPNT4 (Offset 0x0224) */ 4763 4764#define BIT_SHIFT_EXQ_LOW_TH_V1 0 4765#define BIT_MASK_EXQ_LOW_TH_V1 0xfff 4766#define BIT_EXQ_LOW_TH_V1(x) \ 4767 (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) 4768#define BIT_GET_EXQ_LOW_TH_V1(x) \ 4769 (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) 4770 4771/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ 4772 4773#define BIT_SHIFT_TXPKTNUM_H 16 4774#define BIT_MASK_TXPKTNUM_H 0xffff 4775#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) 4776#define BIT_GET_TXPKTNUM_H(x) \ 4777 (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) 4778 4779/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ 4780 4781#define BIT_SHIFT_TXPKTNUM_V2 0 4782#define BIT_MASK_TXPKTNUM_V2 0xffff 4783#define BIT_TXPKTNUM_V2(x) \ 4784 (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) 4785#define BIT_GET_TXPKTNUM_V2(x) \ 4786 (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) 4787 4788/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ 4789 4790#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) 4791#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) 4792#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) 4793#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) 4794 4795/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ 4796 4797#define BIT_SHIFT_HPQ_AVAL_PG_V1 16 4798#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff 4799#define BIT_HPQ_AVAL_PG_V1(x) \ 4800 (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) 4801#define BIT_GET_HPQ_AVAL_PG_V1(x) \ 4802 (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) 4803 4804#define BIT_SHIFT_HPQ_V1 0 4805#define BIT_MASK_HPQ_V1 0xfff 4806#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) 4807#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) 4808 4809/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ 4810 4811#define BIT_SHIFT_LPQ_AVAL_PG_V1 16 4812#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff 4813#define BIT_LPQ_AVAL_PG_V1(x) \ 4814 (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) 4815#define BIT_GET_LPQ_AVAL_PG_V1(x) \ 4816 (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) 4817 4818#define BIT_SHIFT_LPQ_V1 0 4819#define BIT_MASK_LPQ_V1 0xfff 4820#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) 4821#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) 4822 4823/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ 4824 4825#define BIT_SHIFT_NPQ_AVAL_PG_V1 16 4826#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff 4827#define BIT_NPQ_AVAL_PG_V1(x) \ 4828 (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) 4829#define BIT_GET_NPQ_AVAL_PG_V1(x) \ 4830 (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) 4831 4832/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ 4833 4834#define BIT_SHIFT_NPQ_V1 0 4835#define BIT_MASK_NPQ_V1 0xfff 4836#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) 4837#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) 4838 4839/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ 4840 4841#define BIT_SHIFT_EXQ_AVAL_PG_V1 16 4842#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff 4843#define BIT_EXQ_AVAL_PG_V1(x) \ 4844 (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) 4845#define BIT_GET_EXQ_AVAL_PG_V1(x) \ 4846 (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) 4847 4848#define BIT_SHIFT_EXQ_V1 0 4849#define BIT_MASK_EXQ_V1 0xfff 4850#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) 4851#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) 4852 4853/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ 4854 4855#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 4856#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff 4857#define BIT_PUBQ_AVAL_PG_V1(x) \ 4858 (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) 4859#define BIT_GET_PUBQ_AVAL_PG_V1(x) \ 4860 (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) 4861 4862#define BIT_SHIFT_PUBQ_V1 0 4863#define BIT_MASK_PUBQ_V1 0xfff 4864#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) 4865#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) 4866 4867/* 2 REG_H2C_HEAD (Offset 0x0244) */ 4868 4869#define BIT_SHIFT_H2C_HEAD 0 4870#define BIT_MASK_H2C_HEAD 0x3ffff 4871#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) 4872#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) 4873 4874/* 2 REG_H2C_TAIL (Offset 0x0248) */ 4875 4876#define BIT_SHIFT_H2C_TAIL 0 4877#define BIT_MASK_H2C_TAIL 0x3ffff 4878#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) 4879#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) 4880 4881/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ 4882 4883#define BIT_SHIFT_H2C_READ_ADDR 0 4884#define BIT_MASK_H2C_READ_ADDR 0x3ffff 4885#define BIT_H2C_READ_ADDR(x) \ 4886 (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) 4887#define BIT_GET_H2C_READ_ADDR(x) \ 4888 (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) 4889 4890/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ 4891 4892#define BIT_SHIFT_H2C_WR_ADDR 0 4893#define BIT_MASK_H2C_WR_ADDR 0x3ffff 4894#define BIT_H2C_WR_ADDR(x) \ 4895 (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) 4896#define BIT_GET_H2C_WR_ADDR(x) \ 4897 (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) 4898 4899/* 2 REG_H2C_INFO (Offset 0x0254) */ 4900 4901#define BIT_H2C_SPACE_VLD BIT(3) 4902#define BIT_H2C_WR_ADDR_RST BIT(2) 4903 4904#define BIT_SHIFT_H2C_LEN_SEL 0 4905#define BIT_MASK_H2C_LEN_SEL 0x3 4906#define BIT_H2C_LEN_SEL(x) \ 4907 (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) 4908#define BIT_GET_H2C_LEN_SEL(x) \ 4909 (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) 4910 4911/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4912 4913#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 4914#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff 4915#define BIT_RXDMA_AGG_OLD_MOD(x) \ 4916 (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) 4917#define BIT_GET_RXDMA_AGG_OLD_MOD(x) \ 4918 (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) 4919 4920/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4921 4922#define BIT_SHIFT_PKT_NUM_WOL 16 4923#define BIT_MASK_PKT_NUM_WOL 0xff 4924#define BIT_PKT_NUM_WOL(x) \ 4925 (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) 4926#define BIT_GET_PKT_NUM_WOL(x) \ 4927 (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) 4928 4929/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4930 4931#define BIT_SHIFT_DMA_AGG_TO 8 4932#define BIT_MASK_DMA_AGG_TO 0xf 4933#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) 4934#define BIT_GET_DMA_AGG_TO(x) \ 4935 (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) 4936 4937/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4938 4939#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 4940#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf 4941#define BIT_RXDMA_AGG_PG_TH_V1(x) \ 4942 (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) 4943#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \ 4944 (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) 4945 4946/* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4947 4948#define BIT_SHIFT_RXPKT_NUM 24 4949#define BIT_MASK_RXPKT_NUM 0xff 4950#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) 4951#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) 4952 4953/* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4954 4955#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 4956#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf 4957#define BIT_FW_UPD_RDPTR19_TO_16(x) \ 4958 (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \ 4959 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) 4960#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \ 4961 (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \ 4962 BIT_MASK_FW_UPD_RDPTR19_TO_16) 4963 4964/* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4965 4966#define BIT_RXDMA_REQ BIT(19) 4967#define BIT_RW_RELEASE_EN BIT(18) 4968#define BIT_RXDMA_IDLE BIT(17) 4969#define BIT_RXPKT_RELEASE_POLL BIT(16) 4970 4971#define BIT_SHIFT_FW_UPD_RDPTR 0 4972#define BIT_MASK_FW_UPD_RDPTR 0xffff 4973#define BIT_FW_UPD_RDPTR(x) \ 4974 (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) 4975#define BIT_GET_FW_UPD_RDPTR(x) \ 4976 (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) 4977 4978/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4979 4980#define BIT_C2H_PKT_OVF BIT(7) 4981 4982/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4983 4984#define BIT_AGG_CONFGI_ISSUE BIT(6) 4985 4986/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4987 4988#define BIT_FW_POLL_ISSUE BIT(5) 4989#define BIT_RX_DATA_UDN BIT(4) 4990#define BIT_RX_SFF_UDN BIT(3) 4991#define BIT_RX_SFF_OVF BIT(2) 4992 4993/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4994 4995#define BIT_RXPKT_OVF BIT(0) 4996 4997/* 2 REG_RXDMA_DPR (Offset 0x028C) */ 4998 4999#define BIT_SHIFT_RDE_DEBUG 0 5000#define BIT_MASK_RDE_DEBUG 0xffffffffL
5001#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) 5002#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) 5003 5004/* 2 REG_RXDMA_MODE (Offset 0x0290) */ 5005 5006#define BIT_SHIFT_PKTNUM_TH_V2 24 5007#define BIT_MASK_PKTNUM_TH_V2 0x1f 5008#define BIT_PKTNUM_TH_V2(x) \ 5009 (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) 5010#define BIT_GET_PKTNUM_TH_V2(x) \ 5011 (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) 5012 5013#define BIT_TXBA_BREAK_USBAGG BIT(23) 5014 5015#define BIT_SHIFT_PKTLEN_PARA 16 5016#define BIT_MASK_PKTLEN_PARA 0x7 5017#define BIT_PKTLEN_PARA(x) \ 5018 (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) 5019#define BIT_GET_PKTLEN_PARA(x) \ 5020 (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) 5021 5022/* 2 REG_RXDMA_MODE (Offset 0x0290) */ 5023 5024#define BIT_SHIFT_BURST_SIZE 4 5025#define BIT_MASK_BURST_SIZE 0x3 5026#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) 5027#define BIT_GET_BURST_SIZE(x) \ 5028 (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) 5029 5030#define BIT_SHIFT_BURST_CNT 2 5031#define BIT_MASK_BURST_CNT 0x3 5032#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) 5033#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) 5034 5035/* 2 REG_RXDMA_MODE (Offset 0x0290) */ 5036 5037#define BIT_DMA_MODE BIT(1) 5038 5039/* 2 REG_C2H_PKT (Offset 0x0294) */ 5040 5041#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 5042#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf 5043#define BIT_R_C2H_STR_ADDR_16_TO_19(x) \ 5044 (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \ 5045 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) 5046#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \ 5047 (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \ 5048 BIT_MASK_R_C2H_STR_ADDR_16_TO_19) 5049 5050#define BIT_SHIFT_MDIO_PHY_ADDR 24 5051#define BIT_MASK_MDIO_PHY_ADDR 0x1f 5052#define BIT_MDIO_PHY_ADDR(x) \ 5053 (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) 5054#define BIT_GET_MDIO_PHY_ADDR(x) \ 5055 (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) 5056 5057/* 2 REG_C2H_PKT (Offset 0x0294) */ 5058 5059#define BIT_R_C2H_PKT_REQ BIT(16) 5060#define BIT_RX_CLOSE_EN BIT(15) 5061#define BIT_STOP_BCNQ BIT(14) 5062#define BIT_STOP_MGQ BIT(13) 5063#define BIT_STOP_VOQ BIT(12) 5064#define BIT_STOP_VIQ BIT(11) 5065#define BIT_STOP_BEQ BIT(10) 5066#define BIT_STOP_BKQ BIT(9) 5067#define BIT_STOP_RXQ BIT(8) 5068#define BIT_STOP_HI7Q BIT(7) 5069#define BIT_STOP_HI6Q BIT(6) 5070#define BIT_STOP_HI5Q BIT(5) 5071#define BIT_STOP_HI4Q BIT(4) 5072#define BIT_STOP_HI3Q BIT(3) 5073#define BIT_STOP_HI2Q BIT(2) 5074#define BIT_STOP_HI1Q BIT(1) 5075 5076#define BIT_SHIFT_R_C2H_STR_ADDR 0 5077#define BIT_MASK_R_C2H_STR_ADDR 0xffff 5078#define BIT_R_C2H_STR_ADDR(x) \ 5079 (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) 5080#define BIT_GET_R_C2H_STR_ADDR(x) \ 5081 (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) 5082 5083#define BIT_STOP_HI0Q BIT(0) 5084 5085/* 2 REG_FWFF_C2H (Offset 0x0298) */ 5086 5087#define BIT_SHIFT_C2H_DMA_ADDR 0 5088#define BIT_MASK_C2H_DMA_ADDR 0x3ffff 5089#define BIT_C2H_DMA_ADDR(x) \ 5090 (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) 5091#define BIT_GET_C2H_DMA_ADDR(x) \ 5092 (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) 5093 5094/* 2 REG_FWFF_CTRL (Offset 0x029C) */ 5095 5096#define BIT_FWFF_DMAPKT_REQ BIT(31) 5097 5098#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 5099#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff 5100#define BIT_FWFF_DMA_PKT_NUM(x) \ 5101 (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) 5102#define BIT_GET_FWFF_DMA_PKT_NUM(x) \ 5103 (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) 5104 5105#define BIT_SHIFT_FWFF_STR_ADDR 0 5106#define BIT_MASK_FWFF_STR_ADDR 0xffff 5107#define BIT_FWFF_STR_ADDR(x) \ 5108 (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) 5109#define BIT_GET_FWFF_STR_ADDR(x) \ 5110 (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) 5111 5112/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ 5113 5114#define BIT_SHIFT_FWFF_PKT_QUEUED 16 5115#define BIT_MASK_FWFF_PKT_QUEUED 0xff 5116#define BIT_FWFF_PKT_QUEUED(x) \ 5117 (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) 5118#define BIT_GET_FWFF_PKT_QUEUED(x) \ 5119 (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) 5120 5121/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ 5122 5123#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 5124#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff 5125#define BIT_FWFF_PKT_STR_ADDR(x) \ 5126 (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) 5127#define BIT_GET_FWFF_PKT_STR_ADDR(x) \ 5128 (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) 5129 5130/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5131 5132#define BIT_PCIEIO_PERSTB_SEL BIT(31) 5133 5134/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5135 5136#define BIT_SHIFT_PCIE_MAX_RXDMA 28 5137#define BIT_MASK_PCIE_MAX_RXDMA 0x7 5138#define BIT_PCIE_MAX_RXDMA(x) \ 5139 (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) 5140#define BIT_GET_PCIE_MAX_RXDMA(x) \ 5141 (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) 5142 5143/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5144 5145#define BIT_SHIFT_PCIE_MAX_TXDMA 24 5146#define BIT_MASK_PCIE_MAX_TXDMA 0x7 5147#define BIT_PCIE_MAX_TXDMA(x) \ 5148 (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) 5149#define BIT_GET_PCIE_MAX_TXDMA(x) \ 5150 (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) 5151 5152/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5153 5154#define BIT_PCIE_RST_TRXDMA_INTF BIT(20) 5155 5156/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5157 5158#define BIT_PCIE_EN_SWENT_L23 BIT(17) 5159 5160/* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5161 5162#define BIT_PCIE_EN_HWEXT_L1 BIT(16) 5163 5164/* 2 REG_INT_MIG (Offset 0x0304) */ 5165 5166#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 5167#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf 5168#define BIT_TXTTIMER_MATCH_NUM(x) \ 5169 (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) 5170#define BIT_GET_TXTTIMER_MATCH_NUM(x) \ 5171 (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) 5172 5173#define BIT_SHIFT_TXPKT_NUM_MATCH 24 5174#define BIT_MASK_TXPKT_NUM_MATCH 0xf 5175#define BIT_TXPKT_NUM_MATCH(x) \ 5176 (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) 5177#define BIT_GET_TXPKT_NUM_MATCH(x) \ 5178 (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) 5179 5180#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 5181#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf 5182#define BIT_RXTTIMER_MATCH_NUM(x) \ 5183 (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) 5184#define BIT_GET_RXTTIMER_MATCH_NUM(x) \ 5185 (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) 5186 5187#define BIT_SHIFT_RXPKT_NUM_MATCH 16 5188#define BIT_MASK_RXPKT_NUM_MATCH 0xf 5189#define BIT_RXPKT_NUM_MATCH(x) \ 5190 (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) 5191#define BIT_GET_RXPKT_NUM_MATCH(x) \ 5192 (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) 5193 5194#define BIT_SHIFT_MIGRATE_TIMER 0 5195#define BIT_MASK_MIGRATE_TIMER 0xffff 5196#define BIT_MIGRATE_TIMER(x) \ 5197 (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) 5198#define BIT_GET_MIGRATE_TIMER(x) \ 5199 (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) 5200 5201/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ 5202 5203#define BIT_SHIFT_BCNQ_TXBD_DESA 0 5204#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL 5205#define BIT_BCNQ_TXBD_DESA(x) \ 5206 (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) 5207#define BIT_GET_BCNQ_TXBD_DESA(x) \ 5208 (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) 5209 5210/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ 5211 5212#define BIT_SHIFT_MGQ_TXBD_DESA 0 5213#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL 5214#define BIT_MGQ_TXBD_DESA(x) \ 5215 (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) 5216#define BIT_GET_MGQ_TXBD_DESA(x) \ 5217 (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) 5218 5219/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ 5220 5221#define BIT_SHIFT_VOQ_TXBD_DESA 0 5222#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL 5223#define BIT_VOQ_TXBD_DESA(x) \ 5224 (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) 5225#define BIT_GET_VOQ_TXBD_DESA(x) \ 5226 (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) 5227 5228/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ 5229 5230#define BIT_SHIFT_VIQ_TXBD_DESA 0 5231#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL 5232#define BIT_VIQ_TXBD_DESA(x) \ 5233 (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) 5234#define BIT_GET_VIQ_TXBD_DESA(x) \ 5235 (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) 5236 5237/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ 5238 5239#define BIT_SHIFT_BEQ_TXBD_DESA 0 5240#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL 5241#define BIT_BEQ_TXBD_DESA(x) \ 5242 (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) 5243#define BIT_GET_BEQ_TXBD_DESA(x) \ 5244 (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) 5245 5246/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ 5247 5248#define BIT_SHIFT_BKQ_TXBD_DESA 0 5249#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL 5250#define BIT_BKQ_TXBD_DESA(x) \ 5251 (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) 5252#define BIT_GET_BKQ_TXBD_DESA(x) \ 5253 (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) 5254 5255/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ 5256 5257#define BIT_SHIFT_RXQ_RXBD_DESA 0 5258#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL 5259#define BIT_RXQ_RXBD_DESA(x) \ 5260 (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) 5261#define BIT_GET_RXQ_RXBD_DESA(x) \ 5262 (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) 5263 5264/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ 5265 5266#define BIT_SHIFT_HI0Q_TXBD_DESA 0 5267#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL 5268#define BIT_HI0Q_TXBD_DESA(x) \ 5269 (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) 5270#define BIT_GET_HI0Q_TXBD_DESA(x) \ 5271 (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) 5272 5273/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ 5274 5275#define BIT_SHIFT_HI1Q_TXBD_DESA 0 5276#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL 5277#define BIT_HI1Q_TXBD_DESA(x) \ 5278 (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) 5279#define BIT_GET_HI1Q_TXBD_DESA(x) \ 5280 (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) 5281 5282/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ 5283 5284#define BIT_SHIFT_HI2Q_TXBD_DESA 0 5285#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL 5286#define BIT_HI2Q_TXBD_DESA(x) \ 5287 (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) 5288#define BIT_GET_HI2Q_TXBD_DESA(x) \ 5289 (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) 5290 5291/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ 5292 5293#define BIT_SHIFT_HI3Q_TXBD_DESA 0 5294#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL 5295#define BIT_HI3Q_TXBD_DESA(x) \ 5296 (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) 5297#define BIT_GET_HI3Q_TXBD_DESA(x) \ 5298 (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) 5299 5300/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ 5301 5302#define BIT_SHIFT_HI4Q_TXBD_DESA 0 5303#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL 5304#define BIT_HI4Q_TXBD_DESA(x) \ 5305 (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) 5306#define BIT_GET_HI4Q_TXBD_DESA(x) \ 5307 (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) 5308 5309/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ 5310 5311#define BIT_SHIFT_HI5Q_TXBD_DESA 0 5312#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL 5313#define BIT_HI5Q_TXBD_DESA(x) \ 5314 (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) 5315#define BIT_GET_HI5Q_TXBD_DESA(x) \ 5316 (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) 5317 5318/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ 5319 5320#define BIT_SHIFT_HI6Q_TXBD_DESA 0 5321#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL 5322#define BIT_HI6Q_TXBD_DESA(x) \ 5323 (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) 5324#define BIT_GET_HI6Q_TXBD_DESA(x) \ 5325 (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) 5326 5327/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ 5328 5329#define BIT_SHIFT_HI7Q_TXBD_DESA 0 5330#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL 5331#define BIT_HI7Q_TXBD_DESA(x) \ 5332 (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) 5333#define BIT_GET_HI7Q_TXBD_DESA(x) \ 5334 (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) 5335 5336/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ 5337 5338#define BIT_PCIE_MGQ_FLAG BIT(14) 5339 5340/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ 5341 5342#define BIT_SHIFT_MGQ_DESC_MODE 12 5343#define BIT_MASK_MGQ_DESC_MODE 0x3 5344#define BIT_MGQ_DESC_MODE(x) \ 5345 (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) 5346#define BIT_GET_MGQ_DESC_MODE(x) \ 5347 (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) 5348 5349#define BIT_SHIFT_MGQ_DESC_NUM 0 5350#define BIT_MASK_MGQ_DESC_NUM 0xfff 5351#define BIT_MGQ_DESC_NUM(x) \ 5352 (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) 5353#define BIT_GET_MGQ_DESC_NUM(x) \ 5354 (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) 5355 5356/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5357 5358#define BIT_SYS_32_64 BIT(15) 5359 5360#define BIT_SHIFT_BCNQ_DESC_MODE 13 5361#define BIT_MASK_BCNQ_DESC_MODE 0x3 5362#define BIT_BCNQ_DESC_MODE(x) \ 5363 (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) 5364#define BIT_GET_BCNQ_DESC_MODE(x) \ 5365 (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) 5366 5367/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5368 5369#define BIT_PCIE_BCNQ_FLAG BIT(12) 5370 5371/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5372 5373#define BIT_SHIFT_RXQ_DESC_NUM 0 5374#define BIT_MASK_RXQ_DESC_NUM 0xfff 5375#define BIT_RXQ_DESC_NUM(x) \ 5376 (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) 5377#define BIT_GET_RXQ_DESC_NUM(x) \ 5378 (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) 5379 5380/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ 5381 5382#define BIT_PCIE_VOQ_FLAG BIT(14) 5383 5384/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ 5385 5386#define BIT_SHIFT_VOQ_DESC_MODE 12 5387#define BIT_MASK_VOQ_DESC_MODE 0x3 5388#define BIT_VOQ_DESC_MODE(x) \ 5389 (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) 5390#define BIT_GET_VOQ_DESC_MODE(x) \ 5391 (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) 5392 5393#define BIT_SHIFT_VOQ_DESC_NUM 0 5394#define BIT_MASK_VOQ_DESC_NUM 0xfff 5395#define BIT_VOQ_DESC_NUM(x) \ 5396 (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) 5397#define BIT_GET_VOQ_DESC_NUM(x) \ 5398 (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) 5399 5400/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ 5401 5402#define BIT_PCIE_VIQ_FLAG BIT(14) 5403 5404/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ 5405 5406#define BIT_SHIFT_VIQ_DESC_MODE 12 5407#define BIT_MASK_VIQ_DESC_MODE 0x3 5408#define BIT_VIQ_DESC_MODE(x) \ 5409 (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) 5410#define BIT_GET_VIQ_DESC_MODE(x) \ 5411 (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) 5412 5413#define BIT_SHIFT_VIQ_DESC_NUM 0 5414#define BIT_MASK_VIQ_DESC_NUM 0xfff 5415#define BIT_VIQ_DESC_NUM(x) \ 5416 (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) 5417#define BIT_GET_VIQ_DESC_NUM(x) \ 5418 (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) 5419 5420/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ 5421 5422#define BIT_PCIE_BEQ_FLAG BIT(14) 5423 5424/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ 5425 5426#define BIT_SHIFT_BEQ_DESC_MODE 12 5427#define BIT_MASK_BEQ_DESC_MODE 0x3 5428#define BIT_BEQ_DESC_MODE(x) \ 5429 (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) 5430#define BIT_GET_BEQ_DESC_MODE(x) \ 5431 (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) 5432 5433#define BIT_SHIFT_BEQ_DESC_NUM 0 5434#define BIT_MASK_BEQ_DESC_NUM 0xfff 5435#define BIT_BEQ_DESC_NUM(x) \ 5436 (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) 5437#define BIT_GET_BEQ_DESC_NUM(x) \ 5438 (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) 5439 5440/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ 5441 5442#define BIT_PCIE_BKQ_FLAG BIT(14) 5443 5444/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ 5445 5446#define BIT_SHIFT_BKQ_DESC_MODE 12 5447#define BIT_MASK_BKQ_DESC_MODE 0x3 5448#define BIT_BKQ_DESC_MODE(x) \ 5449 (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) 5450#define BIT_GET_BKQ_DESC_MODE(x) \ 5451 (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) 5452 5453#define BIT_SHIFT_BKQ_DESC_NUM 0 5454#define BIT_MASK_BKQ_DESC_NUM 0xfff 5455#define BIT_BKQ_DESC_NUM(x) \ 5456 (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) 5457#define BIT_GET_BKQ_DESC_NUM(x) \ 5458 (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) 5459 5460/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ 5461 5462#define BIT_HI0Q_FLAG BIT(14) 5463 5464#define BIT_SHIFT_HI0Q_DESC_MODE 12 5465#define BIT_MASK_HI0Q_DESC_MODE 0x3 5466#define BIT_HI0Q_DESC_MODE(x) \ 5467 (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) 5468#define BIT_GET_HI0Q_DESC_MODE(x) \ 5469 (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) 5470 5471#define BIT_SHIFT_HI0Q_DESC_NUM 0 5472#define BIT_MASK_HI0Q_DESC_NUM 0xfff 5473#define BIT_HI0Q_DESC_NUM(x) \ 5474 (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) 5475#define BIT_GET_HI0Q_DESC_NUM(x) \ 5476 (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) 5477 5478/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ 5479 5480#define BIT_HI1Q_FLAG BIT(14) 5481 5482#define BIT_SHIFT_HI1Q_DESC_MODE 12 5483#define BIT_MASK_HI1Q_DESC_MODE 0x3 5484#define BIT_HI1Q_DESC_MODE(x) \ 5485 (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) 5486#define BIT_GET_HI1Q_DESC_MODE(x) \ 5487 (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) 5488 5489#define BIT_SHIFT_HI1Q_DESC_NUM 0 5490#define BIT_MASK_HI1Q_DESC_NUM 0xfff 5491#define BIT_HI1Q_DESC_NUM(x) \ 5492 (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) 5493#define BIT_GET_HI1Q_DESC_NUM(x) \ 5494 (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) 5495 5496/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ 5497 5498#define BIT_HI2Q_FLAG BIT(14) 5499 5500#define BIT_SHIFT_HI2Q_DESC_MODE 12 5501#define BIT_MASK_HI2Q_DESC_MODE 0x3 5502#define BIT_HI2Q_DESC_MODE(x) \ 5503 (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) 5504#define BIT_GET_HI2Q_DESC_MODE(x) \ 5505 (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) 5506 5507#define BIT_SHIFT_HI2Q_DESC_NUM 0 5508#define BIT_MASK_HI2Q_DESC_NUM 0xfff 5509#define BIT_HI2Q_DESC_NUM(x) \ 5510 (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) 5511#define BIT_GET_HI2Q_DESC_NUM(x) \ 5512 (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) 5513 5514/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ 5515 5516#define BIT_HI3Q_FLAG BIT(14) 5517 5518#define BIT_SHIFT_HI3Q_DESC_MODE 12 5519#define BIT_MASK_HI3Q_DESC_MODE 0x3 5520#define BIT_HI3Q_DESC_MODE(x) \ 5521 (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) 5522#define BIT_GET_HI3Q_DESC_MODE(x) \ 5523 (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) 5524 5525#define BIT_SHIFT_HI3Q_DESC_NUM 0 5526#define BIT_MASK_HI3Q_DESC_NUM 0xfff 5527#define BIT_HI3Q_DESC_NUM(x) \ 5528 (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) 5529#define BIT_GET_HI3Q_DESC_NUM(x) \ 5530 (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) 5531 5532/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ 5533 5534#define BIT_HI4Q_FLAG BIT(14) 5535 5536#define BIT_SHIFT_HI4Q_DESC_MODE 12 5537#define BIT_MASK_HI4Q_DESC_MODE 0x3 5538#define BIT_HI4Q_DESC_MODE(x) \ 5539 (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) 5540#define BIT_GET_HI4Q_DESC_MODE(x) \ 5541 (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) 5542 5543#define BIT_SHIFT_HI4Q_DESC_NUM 0 5544#define BIT_MASK_HI4Q_DESC_NUM 0xfff 5545#define BIT_HI4Q_DESC_NUM(x) \ 5546 (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) 5547#define BIT_GET_HI4Q_DESC_NUM(x) \ 5548 (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) 5549 5550/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ 5551 5552#define BIT_HI5Q_FLAG BIT(14) 5553 5554#define BIT_SHIFT_HI5Q_DESC_MODE 12 5555#define BIT_MASK_HI5Q_DESC_MODE 0x3 5556#define BIT_HI5Q_DESC_MODE(x) \ 5557 (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) 5558#define BIT_GET_HI5Q_DESC_MODE(x) \ 5559 (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) 5560 5561#define BIT_SHIFT_HI5Q_DESC_NUM 0 5562#define BIT_MASK_HI5Q_DESC_NUM 0xfff 5563#define BIT_HI5Q_DESC_NUM(x) \ 5564 (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) 5565#define BIT_GET_HI5Q_DESC_NUM(x) \ 5566 (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) 5567 5568/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ 5569 5570#define BIT_HI6Q_FLAG BIT(14) 5571 5572#define BIT_SHIFT_HI6Q_DESC_MODE 12 5573#define BIT_MASK_HI6Q_DESC_MODE 0x3 5574#define BIT_HI6Q_DESC_MODE(x) \ 5575 (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) 5576#define BIT_GET_HI6Q_DESC_MODE(x) \ 5577 (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) 5578 5579#define BIT_SHIFT_HI6Q_DESC_NUM 0 5580#define BIT_MASK_HI6Q_DESC_NUM 0xfff 5581#define BIT_HI6Q_DESC_NUM(x) \ 5582 (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) 5583#define BIT_GET_HI6Q_DESC_NUM(x) \ 5584 (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) 5585 5586/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ 5587 5588#define BIT_HI7Q_FLAG BIT(14) 5589 5590#define BIT_SHIFT_HI7Q_DESC_MODE 12 5591#define BIT_MASK_HI7Q_DESC_MODE 0x3 5592#define BIT_HI7Q_DESC_MODE(x) \ 5593 (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) 5594#define BIT_GET_HI7Q_DESC_MODE(x) \ 5595 (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) 5596 5597#define BIT_SHIFT_HI7Q_DESC_NUM 0 5598#define BIT_MASK_HI7Q_DESC_NUM 0xfff 5599#define BIT_HI7Q_DESC_NUM(x) \ 5600 (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) 5601#define BIT_GET_HI7Q_DESC_NUM(x) \ 5602 (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) 5603 5604/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5605 5606#define BIT_CLR_HI7Q_HW_IDX BIT(29) 5607#define BIT_CLR_HI6Q_HW_IDX BIT(28) 5608#define BIT_CLR_HI5Q_HW_IDX BIT(27) 5609#define BIT_CLR_HI4Q_HW_IDX BIT(26) 5610#define BIT_CLR_HI3Q_HW_IDX BIT(25) 5611#define BIT_CLR_HI2Q_HW_IDX BIT(24) 5612#define BIT_CLR_HI1Q_HW_IDX BIT(23) 5613 5614/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5615 5616#define BIT_CLR_HI0Q_HW_IDX BIT(22) 5617 5618/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5619 5620#define BIT_CLR_BKQ_HW_IDX BIT(21) 5621 5622/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5623 5624#define BIT_CLR_BEQ_HW_IDX BIT(20) 5625 5626/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5627 5628#define BIT_CLR_VIQ_HW_IDX BIT(19) 5629 5630/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5631 5632#define BIT_CLR_VOQ_HW_IDX BIT(18) 5633 5634/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5635 5636#define BIT_CLR_MGQ_HW_IDX BIT(17) 5637 5638/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ 5639 5640#define BIT_SHIFT_TSFT2_HCI 16 5641#define BIT_MASK_TSFT2_HCI 0xffff 5642#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) 5643#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) 5644 5645#define BIT_CLR_RXQ_HW_IDX BIT(16) 5646 5647/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5648 5649#define BIT_CLR_HI7Q_HOST_IDX BIT(13) 5650 5651/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5652 5653#define BIT_CLR_HI6Q_HOST_IDX BIT(12) 5654 5655/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5656 5657#define BIT_CLR_HI5Q_HOST_IDX BIT(11) 5658 5659/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5660 5661#define BIT_CLR_HI4Q_HOST_IDX BIT(10) 5662 5663/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5664 5665#define BIT_CLR_HI3Q_HOST_IDX BIT(9) 5666 5667/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5668 5669#define BIT_CLR_HI2Q_HOST_IDX BIT(8) 5670 5671/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5672 5673#define BIT_CLR_HI1Q_HOST_IDX BIT(7) 5674#define BIT_CLR_HI0Q_HOST_IDX BIT(6) 5675 5676/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5677 5678#define BIT_CLR_BKQ_HOST_IDX BIT(5) 5679 5680/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5681 5682#define BIT_CLR_BEQ_HOST_IDX BIT(4) 5683 5684/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5685 5686#define BIT_CLR_VIQ_HOST_IDX BIT(3) 5687 5688/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5689 5690#define BIT_CLR_VOQ_HOST_IDX BIT(2) 5691 5692/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5693 5694#define BIT_CLR_MGQ_HOST_IDX BIT(1) 5695 5696/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ 5697 5698#define BIT_SHIFT_TSFT1_HCI 0 5699#define BIT_MASK_TSFT1_HCI 0xffff 5700#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) 5701#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) 5702 5703#define BIT_CLR_RXQ_HOST_IDX BIT(0) 5704 5705/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ 5706 5707#define BIT_SHIFT_VOQ_HW_IDX 16 5708#define BIT_MASK_VOQ_HW_IDX 0xfff 5709#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) 5710#define BIT_GET_VOQ_HW_IDX(x) \ 5711 (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) 5712 5713#define BIT_SHIFT_VOQ_HOST_IDX 0 5714#define BIT_MASK_VOQ_HOST_IDX 0xfff 5715#define BIT_VOQ_HOST_IDX(x) \ 5716 (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) 5717#define BIT_GET_VOQ_HOST_IDX(x) \ 5718 (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) 5719 5720/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ 5721 5722#define BIT_SHIFT_VIQ_HW_IDX 16 5723#define BIT_MASK_VIQ_HW_IDX 0xfff 5724#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) 5725#define BIT_GET_VIQ_HW_IDX(x) \ 5726 (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) 5727 5728#define BIT_SHIFT_VIQ_HOST_IDX 0 5729#define BIT_MASK_VIQ_HOST_IDX 0xfff 5730#define BIT_VIQ_HOST_IDX(x) \ 5731 (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) 5732#define BIT_GET_VIQ_HOST_IDX(x) \ 5733 (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) 5734 5735/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ 5736 5737#define BIT_SHIFT_BEQ_HW_IDX 16 5738#define BIT_MASK_BEQ_HW_IDX 0xfff 5739#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) 5740#define BIT_GET_BEQ_HW_IDX(x) \ 5741 (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) 5742 5743#define BIT_SHIFT_BEQ_HOST_IDX 0 5744#define BIT_MASK_BEQ_HOST_IDX 0xfff 5745#define BIT_BEQ_HOST_IDX(x) \ 5746 (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) 5747#define BIT_GET_BEQ_HOST_IDX(x) \ 5748 (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) 5749 5750/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ 5751 5752#define BIT_SHIFT_BKQ_HW_IDX 16 5753#define BIT_MASK_BKQ_HW_IDX 0xfff 5754#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) 5755#define BIT_GET_BKQ_HW_IDX(x) \ 5756 (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) 5757 5758#define BIT_SHIFT_BKQ_HOST_IDX 0 5759#define BIT_MASK_BKQ_HOST_IDX 0xfff 5760#define BIT_BKQ_HOST_IDX(x) \ 5761 (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) 5762#define BIT_GET_BKQ_HOST_IDX(x) \ 5763 (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) 5764 5765/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ 5766 5767#define BIT_SHIFT_MGQ_HW_IDX 16 5768#define BIT_MASK_MGQ_HW_IDX 0xfff 5769#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) 5770#define BIT_GET_MGQ_HW_IDX(x) \ 5771 (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) 5772 5773#define BIT_SHIFT_MGQ_HOST_IDX 0 5774#define BIT_MASK_MGQ_HOST_IDX 0xfff 5775#define BIT_MGQ_HOST_IDX(x) \ 5776 (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) 5777#define BIT_GET_MGQ_HOST_IDX(x) \ 5778 (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) 5779 5780/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ 5781 5782#define BIT_SHIFT_RXQ_HW_IDX 16 5783#define BIT_MASK_RXQ_HW_IDX 0xfff 5784#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) 5785#define BIT_GET_RXQ_HW_IDX(x) \ 5786 (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) 5787 5788#define BIT_SHIFT_RXQ_HOST_IDX 0 5789#define BIT_MASK_RXQ_HOST_IDX 0xfff 5790#define BIT_RXQ_HOST_IDX(x) \ 5791 (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) 5792#define BIT_GET_RXQ_HOST_IDX(x) \ 5793 (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) 5794 5795/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ 5796 5797#define BIT_SHIFT_HI0Q_HW_IDX 16 5798#define BIT_MASK_HI0Q_HW_IDX 0xfff 5799#define BIT_HI0Q_HW_IDX(x) \ 5800 (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) 5801#define BIT_GET_HI0Q_HW_IDX(x) \ 5802 (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) 5803 5804#define BIT_SHIFT_HI0Q_HOST_IDX 0 5805#define BIT_MASK_HI0Q_HOST_IDX 0xfff 5806#define BIT_HI0Q_HOST_IDX(x) \ 5807 (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) 5808#define BIT_GET_HI0Q_HOST_IDX(x) \ 5809 (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) 5810 5811/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ 5812 5813#define BIT_SHIFT_HI1Q_HW_IDX 16 5814#define BIT_MASK_HI1Q_HW_IDX 0xfff 5815#define BIT_HI1Q_HW_IDX(x) \ 5816 (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) 5817#define BIT_GET_HI1Q_HW_IDX(x) \ 5818 (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) 5819 5820#define BIT_SHIFT_HI1Q_HOST_IDX 0 5821#define BIT_MASK_HI1Q_HOST_IDX 0xfff 5822#define BIT_HI1Q_HOST_IDX(x) \ 5823 (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) 5824#define BIT_GET_HI1Q_HOST_IDX(x) \ 5825 (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) 5826 5827/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ 5828 5829#define BIT_SHIFT_HI2Q_HW_IDX 16 5830#define BIT_MASK_HI2Q_HW_IDX 0xfff 5831#define BIT_HI2Q_HW_IDX(x) \ 5832 (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) 5833#define BIT_GET_HI2Q_HW_IDX(x) \ 5834 (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) 5835 5836#define BIT_SHIFT_HI2Q_HOST_IDX 0 5837#define BIT_MASK_HI2Q_HOST_IDX 0xfff 5838#define BIT_HI2Q_HOST_IDX(x) \ 5839 (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) 5840#define BIT_GET_HI2Q_HOST_IDX(x) \ 5841 (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) 5842 5843/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ 5844 5845#define BIT_SHIFT_HI3Q_HW_IDX 16 5846#define BIT_MASK_HI3Q_HW_IDX 0xfff 5847#define BIT_HI3Q_HW_IDX(x) \ 5848 (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) 5849#define BIT_GET_HI3Q_HW_IDX(x) \ 5850 (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) 5851 5852#define BIT_SHIFT_HI3Q_HOST_IDX 0 5853#define BIT_MASK_HI3Q_HOST_IDX 0xfff 5854#define BIT_HI3Q_HOST_IDX(x) \ 5855 (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) 5856#define BIT_GET_HI3Q_HOST_IDX(x) \ 5857 (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) 5858 5859/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ 5860 5861#define BIT_SHIFT_HI4Q_HW_IDX 16 5862#define BIT_MASK_HI4Q_HW_IDX 0xfff 5863#define BIT_HI4Q_HW_IDX(x) \ 5864 (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) 5865#define BIT_GET_HI4Q_HW_IDX(x) \ 5866 (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) 5867 5868#define BIT_SHIFT_HI4Q_HOST_IDX 0 5869#define BIT_MASK_HI4Q_HOST_IDX 0xfff 5870#define BIT_HI4Q_HOST_IDX(x) \ 5871 (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) 5872#define BIT_GET_HI4Q_HOST_IDX(x) \ 5873 (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) 5874 5875/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ 5876 5877#define BIT_SHIFT_HI5Q_HW_IDX 16 5878#define BIT_MASK_HI5Q_HW_IDX 0xfff 5879#define BIT_HI5Q_HW_IDX(x) \ 5880 (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) 5881#define BIT_GET_HI5Q_HW_IDX(x) \ 5882 (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) 5883 5884#define BIT_SHIFT_HI5Q_HOST_IDX 0 5885#define BIT_MASK_HI5Q_HOST_IDX 0xfff 5886#define BIT_HI5Q_HOST_IDX(x) \ 5887 (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) 5888#define BIT_GET_HI5Q_HOST_IDX(x) \ 5889 (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) 5890 5891/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ 5892 5893#define BIT_SHIFT_HI6Q_HW_IDX 16 5894#define BIT_MASK_HI6Q_HW_IDX 0xfff 5895#define BIT_HI6Q_HW_IDX(x) \ 5896 (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) 5897#define BIT_GET_HI6Q_HW_IDX(x) \ 5898 (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) 5899 5900#define BIT_SHIFT_HI6Q_HOST_IDX 0 5901#define BIT_MASK_HI6Q_HOST_IDX 0xfff 5902#define BIT_HI6Q_HOST_IDX(x) \ 5903 (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) 5904#define BIT_GET_HI6Q_HOST_IDX(x) \ 5905 (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) 5906 5907/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ 5908 5909#define BIT_SHIFT_HI7Q_HW_IDX 16 5910#define BIT_MASK_HI7Q_HW_IDX 0xfff 5911#define BIT_HI7Q_HW_IDX(x) \ 5912 (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) 5913#define BIT_GET_HI7Q_HW_IDX(x) \ 5914 (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) 5915 5916#define BIT_SHIFT_HI7Q_HOST_IDX 0 5917#define BIT_MASK_HI7Q_HOST_IDX 0xfff 5918#define BIT_HI7Q_HOST_IDX(x) \ 5919 (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) 5920#define BIT_GET_HI7Q_HOST_IDX(x) \ 5921 (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) 5922 5923/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ 5924 5925#define BIT_DIS_TXDMA_PRE BIT(7) 5926#define BIT_DIS_RXDMA_PRE BIT(6) 5927#define BIT_TXFLAG_EXIT_L1_EN BIT(2) 5928 5929#define BIT_SHIFT_DBG_SEL 0 5930#define BIT_MASK_DBG_SEL 0xff 5931#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) 5932#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) 5933 5934/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ 5935 5936#define BIT_SHIFT_PCIE_HRPWM 0 5937#define BIT_MASK_PCIE_HRPWM 0xff 5938#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) 5939#define BIT_GET_PCIE_HRPWM(x) \ 5940 (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) 5941 5942/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ 5943 5944#define BIT_SHIFT_PCIE_HCPWM 0 5945#define BIT_MASK_PCIE_HCPWM 0xff 5946#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) 5947#define BIT_GET_PCIE_HCPWM(x) \ 5948 (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) 5949 5950/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5951 5952#define BIT_SHIFT_HPS_CLKR_PCIE 4 5953#define BIT_MASK_HPS_CLKR_PCIE 0x3 5954#define BIT_HPS_CLKR_PCIE(x) \ 5955 (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) 5956#define BIT_GET_HPS_CLKR_PCIE(x) \ 5957 (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) 5958 5959/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5960 5961#define BIT_PCIE_INT BIT(3) 5962 5963/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5964 5965#define BIT_EN_RXDMA_ALIGN BIT(1) 5966#define BIT_EN_TXDMA_ALIGN BIT(0) 5967 5968/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ 5969 5970#define BIT_SHIFT_PCIE_HRPWM2 0 5971#define BIT_MASK_PCIE_HRPWM2 0xffff 5972#define BIT_PCIE_HRPWM2(x) \ 5973 (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) 5974#define BIT_GET_PCIE_HRPWM2(x) \ 5975 (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) 5976 5977/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ 5978 5979#define BIT_SHIFT_PCIE_HCPWM2 0 5980#define BIT_MASK_PCIE_HCPWM2 0xffff 5981#define BIT_PCIE_HCPWM2(x) \ 5982 (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) 5983#define BIT_GET_PCIE_HCPWM2(x) \ 5984 (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) 5985 5986/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ 5987 5988#define BIT_SHIFT_DRV2FW_INFO 0 5989#define BIT_MASK_DRV2FW_INFO 0xffffffffL 5990#define BIT_DRV2FW_INFO(x) \ 5991 (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) 5992#define BIT_GET_DRV2FW_INFO(x) \ 5993 (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) 5994 5995/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ 5996 5997#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 5998#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL 5999#define BIT_HCI_PCIE_C2H_MSG(x) \ 6000 (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)
6001#define BIT_GET_HCI_PCIE_C2H_MSG(x) \ 6002 (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) 6003 6004/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ 6005 6006#define BIT_SHIFT_DBI_WDATA 0 6007#define BIT_MASK_DBI_WDATA 0xffffffffL 6008#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) 6009#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) 6010 6011/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ 6012 6013#define BIT_SHIFT_DBI_RDATA 0 6014#define BIT_MASK_DBI_RDATA 0xffffffffL 6015#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) 6016#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) 6017 6018/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ 6019 6020#define BIT_EN_STUCK_DBG BIT(26) 6021#define BIT_RX_STUCK BIT(25) 6022#define BIT_TX_STUCK BIT(24) 6023#define BIT_DBI_RFLAG BIT(17) 6024#define BIT_DBI_WFLAG BIT(16) 6025 6026#define BIT_SHIFT_DBI_WREN 12 6027#define BIT_MASK_DBI_WREN 0xf 6028#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) 6029#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) 6030 6031#define BIT_SHIFT_DBI_ADDR 0 6032#define BIT_MASK_DBI_ADDR 0xfff 6033#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) 6034#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) 6035 6036/* 2 REG_MDIO_V1 (Offset 0x03F4) */ 6037 6038#define BIT_SHIFT_MDIO_RDATA 16 6039#define BIT_MASK_MDIO_RDATA 0xffff 6040#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) 6041#define BIT_GET_MDIO_RDATA(x) \ 6042 (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) 6043 6044#define BIT_SHIFT_MDIO_WDATA 0 6045#define BIT_MASK_MDIO_WDATA 0xffff 6046#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) 6047#define BIT_GET_MDIO_WDATA(x) \ 6048 (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) 6049 6050/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ 6051 6052#define BIT_EN_WATCH_DOG BIT(8) 6053 6054/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ 6055 6056#define BIT_SHIFT_MDIO_REG_ADDR_V1 0 6057#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f 6058#define BIT_MDIO_REG_ADDR_V1(x) \ 6059 (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) 6060#define BIT_GET_MDIO_REG_ADDR_V1(x) \ 6061 (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) 6062 6063/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ 6064 6065#define BIT_HOST_GEN2_SUPPORT BIT(20) 6066 6067#define BIT_SHIFT_TXDMA_ERR_FLAG 16 6068#define BIT_MASK_TXDMA_ERR_FLAG 0xf 6069#define BIT_TXDMA_ERR_FLAG(x) \ 6070 (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) 6071#define BIT_GET_TXDMA_ERR_FLAG(x) \ 6072 (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) 6073 6074#define BIT_SHIFT_EARLY_MODE_SEL 12 6075#define BIT_MASK_EARLY_MODE_SEL 0xf 6076#define BIT_EARLY_MODE_SEL(x) \ 6077 (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) 6078#define BIT_GET_EARLY_MODE_SEL(x) \ 6079 (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) 6080 6081#define BIT_EPHY_RX50_EN BIT(11) 6082 6083#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 6084#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 6085#define BIT_MSI_TIMEOUT_ID_V1(x) \ 6086 (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) 6087#define BIT_GET_MSI_TIMEOUT_ID_V1(x) \ 6088 (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) 6089 6090#define BIT_RADDR_RD BIT(7) 6091#define BIT_EN_MUL_TAG BIT(6) 6092#define BIT_EN_EARLY_MODE BIT(5) 6093#define BIT_L0S_LINK_OFF BIT(4) 6094#define BIT_ACT_LINK_OFF BIT(3) 6095 6096/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ 6097 6098#define BIT_EN_SLOW_MAC_TX BIT(2) 6099#define BIT_EN_SLOW_MAC_RX BIT(1) 6100 6101/* 2 REG_Q0_INFO (Offset 0x0400) */ 6102 6103#define BIT_SHIFT_QUEUEMACID_Q0_V1 25 6104#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f 6105#define BIT_QUEUEMACID_Q0_V1(x) \ 6106 (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) 6107#define BIT_GET_QUEUEMACID_Q0_V1(x) \ 6108 (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) 6109 6110#define BIT_SHIFT_QUEUEAC_Q0_V1 23 6111#define BIT_MASK_QUEUEAC_Q0_V1 0x3 6112#define BIT_QUEUEAC_Q0_V1(x) \ 6113 (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) 6114#define BIT_GET_QUEUEAC_Q0_V1(x) \ 6115 (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) 6116 6117/* 2 REG_Q0_INFO (Offset 0x0400) */ 6118 6119#define BIT_TIDEMPTY_Q0_V1 BIT(22) 6120 6121/* 2 REG_Q0_INFO (Offset 0x0400) */ 6122 6123#define BIT_SHIFT_TAIL_PKT_Q0_V2 11 6124#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff 6125#define BIT_TAIL_PKT_Q0_V2(x) \ 6126 (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) 6127#define BIT_GET_TAIL_PKT_Q0_V2(x) \ 6128 (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) 6129 6130/* 2 REG_Q0_INFO (Offset 0x0400) */ 6131 6132#define BIT_SHIFT_HEAD_PKT_Q0_V1 0 6133#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff 6134#define BIT_HEAD_PKT_Q0_V1(x) \ 6135 (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) 6136#define BIT_GET_HEAD_PKT_Q0_V1(x) \ 6137 (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) 6138 6139/* 2 REG_Q1_INFO (Offset 0x0404) */ 6140 6141#define BIT_SHIFT_QUEUEMACID_Q1_V1 25 6142#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f 6143#define BIT_QUEUEMACID_Q1_V1(x) \ 6144 (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) 6145#define BIT_GET_QUEUEMACID_Q1_V1(x) \ 6146 (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) 6147 6148#define BIT_SHIFT_QUEUEAC_Q1_V1 23 6149#define BIT_MASK_QUEUEAC_Q1_V1 0x3 6150#define BIT_QUEUEAC_Q1_V1(x) \ 6151 (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) 6152#define BIT_GET_QUEUEAC_Q1_V1(x) \ 6153 (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) 6154 6155/* 2 REG_Q1_INFO (Offset 0x0404) */ 6156 6157#define BIT_TIDEMPTY_Q1_V1 BIT(22) 6158 6159/* 2 REG_Q1_INFO (Offset 0x0404) */ 6160 6161#define BIT_SHIFT_TAIL_PKT_Q1_V2 11 6162#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff 6163#define BIT_TAIL_PKT_Q1_V2(x) \ 6164 (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) 6165#define BIT_GET_TAIL_PKT_Q1_V2(x) \ 6166 (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) 6167 6168/* 2 REG_Q1_INFO (Offset 0x0404) */ 6169 6170#define BIT_SHIFT_HEAD_PKT_Q1_V1 0 6171#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff 6172#define BIT_HEAD_PKT_Q1_V1(x) \ 6173 (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) 6174#define BIT_GET_HEAD_PKT_Q1_V1(x) \ 6175 (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) 6176 6177/* 2 REG_Q2_INFO (Offset 0x0408) */ 6178 6179#define BIT_SHIFT_QUEUEMACID_Q2_V1 25 6180#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f 6181#define BIT_QUEUEMACID_Q2_V1(x) \ 6182 (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) 6183#define BIT_GET_QUEUEMACID_Q2_V1(x) \ 6184 (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) 6185 6186#define BIT_SHIFT_QUEUEAC_Q2_V1 23 6187#define BIT_MASK_QUEUEAC_Q2_V1 0x3 6188#define BIT_QUEUEAC_Q2_V1(x) \ 6189 (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) 6190#define BIT_GET_QUEUEAC_Q2_V1(x) \ 6191 (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) 6192 6193/* 2 REG_Q2_INFO (Offset 0x0408) */ 6194 6195#define BIT_TIDEMPTY_Q2_V1 BIT(22) 6196 6197/* 2 REG_Q2_INFO (Offset 0x0408) */ 6198 6199#define BIT_SHIFT_TAIL_PKT_Q2_V2 11 6200#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff 6201#define BIT_TAIL_PKT_Q2_V2(x) \ 6202 (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) 6203#define BIT_GET_TAIL_PKT_Q2_V2(x) \ 6204 (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) 6205 6206/* 2 REG_Q2_INFO (Offset 0x0408) */ 6207 6208#define BIT_SHIFT_HEAD_PKT_Q2_V1 0 6209#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff 6210#define BIT_HEAD_PKT_Q2_V1(x) \ 6211 (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) 6212#define BIT_GET_HEAD_PKT_Q2_V1(x) \ 6213 (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) 6214 6215/* 2 REG_Q3_INFO (Offset 0x040C) */ 6216 6217#define BIT_SHIFT_QUEUEMACID_Q3_V1 25 6218#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f 6219#define BIT_QUEUEMACID_Q3_V1(x) \ 6220 (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) 6221#define BIT_GET_QUEUEMACID_Q3_V1(x) \ 6222 (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) 6223 6224#define BIT_SHIFT_QUEUEAC_Q3_V1 23 6225#define BIT_MASK_QUEUEAC_Q3_V1 0x3 6226#define BIT_QUEUEAC_Q3_V1(x) \ 6227 (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) 6228#define BIT_GET_QUEUEAC_Q3_V1(x) \ 6229 (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) 6230 6231/* 2 REG_Q3_INFO (Offset 0x040C) */ 6232 6233#define BIT_TIDEMPTY_Q3_V1 BIT(22) 6234 6235/* 2 REG_Q3_INFO (Offset 0x040C) */ 6236 6237#define BIT_SHIFT_TAIL_PKT_Q3_V2 11 6238#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff 6239#define BIT_TAIL_PKT_Q3_V2(x) \ 6240 (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) 6241#define BIT_GET_TAIL_PKT_Q3_V2(x) \ 6242 (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) 6243 6244/* 2 REG_Q3_INFO (Offset 0x040C) */ 6245 6246#define BIT_SHIFT_HEAD_PKT_Q3_V1 0 6247#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff 6248#define BIT_HEAD_PKT_Q3_V1(x) \ 6249 (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) 6250#define BIT_GET_HEAD_PKT_Q3_V1(x) \ 6251 (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) 6252 6253/* 2 REG_MGQ_INFO (Offset 0x0410) */ 6254 6255#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 6256#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f 6257#define BIT_QUEUEMACID_MGQ_V1(x) \ 6258 (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) 6259#define BIT_GET_QUEUEMACID_MGQ_V1(x) \ 6260 (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) 6261 6262#define BIT_SHIFT_QUEUEAC_MGQ_V1 23 6263#define BIT_MASK_QUEUEAC_MGQ_V1 0x3 6264#define BIT_QUEUEAC_MGQ_V1(x) \ 6265 (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) 6266#define BIT_GET_QUEUEAC_MGQ_V1(x) \ 6267 (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) 6268 6269/* 2 REG_MGQ_INFO (Offset 0x0410) */ 6270 6271#define BIT_TIDEMPTY_MGQ_V1 BIT(22) 6272 6273/* 2 REG_MGQ_INFO (Offset 0x0410) */ 6274 6275#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 6276#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff 6277#define BIT_TAIL_PKT_MGQ_V2(x) \ 6278 (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) 6279#define BIT_GET_TAIL_PKT_MGQ_V2(x) \ 6280 (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) 6281 6282/* 2 REG_MGQ_INFO (Offset 0x0410) */ 6283 6284#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 6285#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff 6286#define BIT_HEAD_PKT_MGQ_V1(x) \ 6287 (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) 6288#define BIT_GET_HEAD_PKT_MGQ_V1(x) \ 6289 (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) 6290 6291/* 2 REG_HIQ_INFO (Offset 0x0414) */ 6292 6293#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 6294#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f 6295#define BIT_QUEUEMACID_HIQ_V1(x) \ 6296 (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) 6297#define BIT_GET_QUEUEMACID_HIQ_V1(x) \ 6298 (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) 6299 6300#define BIT_SHIFT_QUEUEAC_HIQ_V1 23 6301#define BIT_MASK_QUEUEAC_HIQ_V1 0x3 6302#define BIT_QUEUEAC_HIQ_V1(x) \ 6303 (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) 6304#define BIT_GET_QUEUEAC_HIQ_V1(x) \ 6305 (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) 6306 6307/* 2 REG_HIQ_INFO (Offset 0x0414) */ 6308 6309#define BIT_TIDEMPTY_HIQ_V1 BIT(22) 6310 6311/* 2 REG_HIQ_INFO (Offset 0x0414) */ 6312 6313#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 6314#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff 6315#define BIT_TAIL_PKT_HIQ_V2(x) \ 6316 (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) 6317#define BIT_GET_TAIL_PKT_HIQ_V2(x) \ 6318 (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) 6319 6320/* 2 REG_HIQ_INFO (Offset 0x0414) */ 6321 6322#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 6323#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff 6324#define BIT_HEAD_PKT_HIQ_V1(x) \ 6325 (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) 6326#define BIT_GET_HEAD_PKT_HIQ_V1(x) \ 6327 (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) 6328 6329/* 2 REG_BCNQ_INFO (Offset 0x0418) */ 6330 6331#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 6332#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff 6333#define BIT_BCNQ_HEAD_PG_V1(x) \ 6334 (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) 6335#define BIT_GET_BCNQ_HEAD_PG_V1(x) \ 6336 (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) 6337 6338/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ 6339 6340#define BIT_BCNQ_EMPTY BIT(11) 6341#define BIT_HQQ_EMPTY BIT(10) 6342#define BIT_MQQ_EMPTY BIT(9) 6343#define BIT_MGQ_CPU_EMPTY BIT(8) 6344#define BIT_AC7Q_EMPTY BIT(7) 6345#define BIT_AC6Q_EMPTY BIT(6) 6346#define BIT_AC5Q_EMPTY BIT(5) 6347#define BIT_AC4Q_EMPTY BIT(4) 6348#define BIT_AC3Q_EMPTY BIT(3) 6349#define BIT_AC2Q_EMPTY BIT(2) 6350#define BIT_AC1Q_EMPTY BIT(1) 6351#define BIT_AC0Q_EMPTY BIT(0) 6352 6353/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6354 6355#define BIT_BCN1_POLL BIT(30) 6356 6357/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6358 6359#define BIT_CPUMGT_POLL BIT(29) 6360#define BIT_BCN_POLL BIT(28) 6361 6362/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6363 6364#define BIT_CPUMGQ_FW_NUM_V1 BIT(12) 6365 6366/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6367 6368#define BIT_SHIFT_FW_FREE_TAIL_V1 0 6369#define BIT_MASK_FW_FREE_TAIL_V1 0xfff 6370#define BIT_FW_FREE_TAIL_V1(x) \ 6371 (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) 6372#define BIT_GET_FW_FREE_TAIL_V1(x) \ 6373 (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) 6374 6375/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6376 6377#define BIT_RTS_LIMIT_IN_OFDM BIT(23) 6378#define BIT_EN_BCNQ_DL BIT(22) 6379#define BIT_EN_RD_RESP_NAV_BK BIT(21) 6380#define BIT_EN_WR_FREE_TAIL BIT(20) 6381 6382#define BIT_SHIFT_EN_QUEUE_RPT 8 6383#define BIT_MASK_EN_QUEUE_RPT 0xff 6384#define BIT_EN_QUEUE_RPT(x) \ 6385 (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) 6386#define BIT_GET_EN_QUEUE_RPT(x) \ 6387 (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) 6388 6389#define BIT_EN_RTY_BK BIT(7) 6390#define BIT_EN_USE_INI_RAT BIT(6) 6391#define BIT_EN_RTS_NAV_BK BIT(5) 6392#define BIT_DIS_SSN_CHECK BIT(4) 6393#define BIT_MACID_MATCH_RTS BIT(3) 6394 6395/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6396 6397#define BIT_EN_BCN_TRXRPT_V1 BIT(2) 6398 6399/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6400 6401#define BIT_EN_FTMACKRPT BIT(1) 6402 6403/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6404 6405#define BIT_EN_FTMRPT BIT(0) 6406 6407/* 2 REG_DATAFB_SEL (Offset 0x0423) */ 6408 6409#define BIT__R_EN_RTY_BK_COD BIT(2) 6410 6411/* 2 REG_DATAFB_SEL (Offset 0x0423) */ 6412 6413#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 6414#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 6415#define BIT__R_DATA_FALLBACK_SEL(x) \ 6416 (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \ 6417 << BIT_SHIFT__R_DATA_FALLBACK_SEL) 6418#define BIT_GET__R_DATA_FALLBACK_SEL(x) \ 6419 (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \ 6420 BIT_MASK__R_DATA_FALLBACK_SEL) 6421 6422/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ 6423 6424#define BIT_SHIFT_BCNQ_PGBNDY_V1 0 6425#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff 6426#define BIT_BCNQ_PGBNDY_V1(x) \ 6427 (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) 6428#define BIT_GET_BCNQ_PGBNDY_V1(x) \ 6429 (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) 6430 6431/* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6432 6433#define BIT_BT_INT_CPU BIT(7) 6434#define BIT_BT_INT_PTA BIT(6) 6435 6436/* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6437 6438#define BIT_EN_CTRL_RTYBIT BIT(4) 6439 6440/* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6441 6442#define BIT_LIFETIME_BK_EN BIT(3) 6443#define BIT_LIFETIME_BE_EN BIT(2) 6444#define BIT_LIFETIME_VI_EN BIT(1) 6445#define BIT_LIFETIME_VO_EN BIT(0) 6446 6447/* 2 REG_SPEC_SIFS (Offset 0x0428) */ 6448 6449#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 6450#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff 6451#define BIT_SPEC_SIFS_OFDM_PTCL(x) \ 6452 (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) 6453#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \ 6454 (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) 6455 6456#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 6457#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff 6458#define BIT_SPEC_SIFS_CCK_PTCL(x) \ 6459 (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) 6460#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \ 6461 (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) 6462 6463/* 2 REG_RETRY_LIMIT (Offset 0x042A) */ 6464 6465#define BIT_SHIFT_SRL 8 6466#define BIT_MASK_SRL 0x3f 6467#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) 6468#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) 6469 6470#define BIT_SHIFT_LRL 0 6471#define BIT_MASK_LRL 0x3f 6472#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) 6473#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) 6474 6475/* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6476 6477#define BIT_R_ENABLE_NDPA BIT(31) 6478#define BIT_USE_NDPA_PARAMETER BIT(30) 6479#define BIT_R_PROP_TXBF BIT(29) 6480#define BIT_R_EN_NDPA_INT BIT(28) 6481#define BIT_R_TXBF1_80M BIT(27) 6482#define BIT_R_TXBF1_40M BIT(26) 6483#define BIT_R_TXBF1_20M BIT(25) 6484 6485#define BIT_SHIFT_R_TXBF1_AID 16 6486#define BIT_MASK_R_TXBF1_AID 0x1ff 6487#define BIT_R_TXBF1_AID(x) \ 6488 (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) 6489#define BIT_GET_R_TXBF1_AID(x) \ 6490 (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) 6491 6492/* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6493 6494#define BIT_DIS_NDP_BFEN BIT(15) 6495 6496/* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6497 6498#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) 6499 6500/* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6501 6502#define BIT_R_TXBF0_80M BIT(11) 6503#define BIT_R_TXBF0_40M BIT(10) 6504#define BIT_R_TXBF0_20M BIT(9) 6505 6506#define BIT_SHIFT_R_TXBF0_AID 0 6507#define BIT_MASK_R_TXBF0_AID 0x1ff 6508#define BIT_R_TXBF0_AID(x) \ 6509 (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) 6510#define BIT_GET_R_TXBF0_AID(x) \ 6511 (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) 6512 6513/* 2 REG_DARFRC (Offset 0x0430) */ 6514 6515#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) 6516#define BIT_MASK_DARF_RC8 0x1f 6517#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) 6518#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) 6519 6520#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) 6521#define BIT_MASK_DARF_RC7 0x1f 6522#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) 6523#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) 6524 6525#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) 6526#define BIT_MASK_DARF_RC6 0x1f 6527#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) 6528#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) 6529 6530#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) 6531#define BIT_MASK_DARF_RC5 0x1f 6532#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) 6533#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) 6534 6535#define BIT_SHIFT_DARF_RC4 24 6536#define BIT_MASK_DARF_RC4 0x1f 6537#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) 6538#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) 6539 6540#define BIT_SHIFT_DARF_RC3 16 6541#define BIT_MASK_DARF_RC3 0x1f 6542#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) 6543#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) 6544 6545#define BIT_SHIFT_DARF_RC2 8 6546#define BIT_MASK_DARF_RC2 0x1f 6547#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) 6548#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) 6549 6550#define BIT_SHIFT_DARF_RC1 0 6551#define BIT_MASK_DARF_RC1 0x1f 6552#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) 6553#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) 6554 6555/* 2 REG_RARFRC (Offset 0x0438) */ 6556 6557#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) 6558#define BIT_MASK_RARF_RC8 0x1f 6559#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) 6560#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) 6561 6562#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) 6563#define BIT_MASK_RARF_RC7 0x1f 6564#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) 6565#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) 6566 6567#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) 6568#define BIT_MASK_RARF_RC6 0x1f 6569#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) 6570#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) 6571 6572#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) 6573#define BIT_MASK_RARF_RC5 0x1f 6574#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) 6575#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) 6576 6577#define BIT_SHIFT_RARF_RC4 24 6578#define BIT_MASK_RARF_RC4 0x1f 6579#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) 6580#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) 6581 6582#define BIT_SHIFT_RARF_RC3 16 6583#define BIT_MASK_RARF_RC3 0x1f 6584#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) 6585#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) 6586 6587#define BIT_SHIFT_RARF_RC2 8 6588#define BIT_MASK_RARF_RC2 0x1f 6589#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) 6590#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) 6591 6592#define BIT_SHIFT_RARF_RC1 0 6593#define BIT_MASK_RARF_RC1 0x1f 6594#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) 6595#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) 6596 6597/* 2 REG_RRSR (Offset 0x0440) */ 6598 6599#define BIT_SHIFT_RRSR_RSC 21 6600#define BIT_MASK_RRSR_RSC 0x3 6601#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) 6602#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) 6603 6604#define BIT_RRSR_BW BIT(20) 6605 6606#define BIT_SHIFT_RRSC_BITMAP 0 6607#define BIT_MASK_RRSC_BITMAP 0xfffff 6608#define BIT_RRSC_BITMAP(x) \ 6609 (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) 6610#define BIT_GET_RRSC_BITMAP(x) \ 6611 (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) 6612 6613/* 2 REG_ARFR0 (Offset 0x0444) */ 6614 6615#define BIT_SHIFT_ARFR0_V1 0 6616#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL 6617#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) 6618#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) 6619 6620/* 2 REG_ARFR1_V1 (Offset 0x044C) */ 6621 6622#define BIT_SHIFT_ARFR1_V1 0 6623#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL 6624#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) 6625#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) 6626 6627/* 2 REG_CCK_CHECK (Offset 0x0454) */ 6628 6629#define BIT_CHECK_CCK_EN BIT(7) 6630#define BIT_EN_BCN_PKT_REL BIT(6) 6631#define BIT_BCN_PORT_SEL BIT(5) 6632#define BIT_MOREDATA_BYPASS BIT(4) 6633#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) 6634 6635/* 2 REG_CCK_CHECK (Offset 0x0454) */ 6636 6637#define BIT_R_EN_SET_MOREDATA BIT(2) 6638#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) 6639#define BIT__R_MACID_RELEASE_EN BIT(0) 6640 6641/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ 6642 6643#define BIT_SHIFT_AMPDU_MAX_TIME 0 6644#define BIT_MASK_AMPDU_MAX_TIME 0xff 6645#define BIT_AMPDU_MAX_TIME(x) \ 6646 (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) 6647#define BIT_GET_AMPDU_MAX_TIME(x) \ 6648 (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) 6649 6650/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ 6651 6652#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 6653#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff 6654#define BIT_BCNQ1_PGBNDY_V1(x) \ 6655 (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) 6656#define BIT_GET_BCNQ1_PGBNDY_V1(x) \ 6657 (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) 6658 6659/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ 6660 6661#define BIT_SHIFT_AMPDU_MAX_LENGTH 0 6662#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL 6663#define BIT_AMPDU_MAX_LENGTH(x) \ 6664 (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) 6665#define BIT_GET_AMPDU_MAX_LENGTH(x) \ 6666 (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) 6667 6668/* 2 REG_ACQ_STOP (Offset 0x045C) */ 6669 6670#define BIT_AC7Q_STOP BIT(7) 6671#define BIT_AC6Q_STOP BIT(6) 6672#define BIT_AC5Q_STOP BIT(5) 6673#define BIT_AC4Q_STOP BIT(4) 6674#define BIT_AC3Q_STOP BIT(3) 6675#define BIT_AC2Q_STOP BIT(2) 6676#define BIT_AC1Q_STOP BIT(1) 6677#define BIT_AC0Q_STOP BIT(0) 6678 6679/* 2 REG_NDPA_RATE (Offset 0x045D) */ 6680 6681#define BIT_SHIFT_R_NDPA_RATE_V1 0 6682#define BIT_MASK_R_NDPA_RATE_V1 0xff 6683#define BIT_R_NDPA_RATE_V1(x) \ 6684 (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) 6685#define BIT_GET_R_NDPA_RATE_V1(x) \ 6686 (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) 6687 6688/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6689 6690#define BIT_R_EN_GNT_BT_AWAKE BIT(3) 6691 6692/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6693 6694#define BIT_EN_EOF_V1 BIT(2) 6695 6696/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6697 6698#define BIT_DIS_OQT_BLOCK BIT(1) 6699#define BIT_SEARCH_QUEUE_EN BIT(0) 6700 6701/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6702 6703#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) 6704 6705/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6706 6707#define BIT_SHIFT_BW_SIGTA 3 6708#define BIT_MASK_BW_SIGTA 0x3 6709#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) 6710#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) 6711 6712/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6713 6714#define BIT_EN_BAR_SIGTA BIT(2) 6715 6716/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6717 6718#define BIT_SHIFT_R_NDPA_BW 0 6719#define BIT_MASK_R_NDPA_BW 0x3 6720#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) 6721#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) 6722 6723/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ 6724 6725#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 6726#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f 6727#define BIT_RD_RESP_PKT_TH_V1(x) \ 6728 (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) 6729#define BIT_GET_RD_RESP_PKT_TH_V1(x) \ 6730 (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) 6731 6732/* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6733 6734#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 6735#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f 6736#define BIT_QUEUEMACID_CMDQ_V1(x) \ 6737 (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) 6738#define BIT_GET_QUEUEMACID_CMDQ_V1(x) \ 6739 (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) 6740 6741/* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6742 6743#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 6744#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 6745#define BIT_QUEUEAC_CMDQ_V1(x) \ 6746 (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) 6747#define BIT_GET_QUEUEAC_CMDQ_V1(x) \ 6748 (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) 6749 6750/* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6751 6752#define BIT_TIDEMPTY_CMDQ_V1 BIT(22) 6753 6754/* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6755 6756#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 6757#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff 6758#define BIT_TAIL_PKT_CMDQ_V2(x) \ 6759 (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) 6760#define BIT_GET_TAIL_PKT_CMDQ_V2(x) \ 6761 (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) 6762 6763/* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6764 6765#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 6766#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff 6767#define BIT_HEAD_PKT_CMDQ_V1(x) \ 6768 (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) 6769#define BIT_GET_HEAD_PKT_CMDQ_V1(x) \ 6770 (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) 6771 6772/* 2 REG_Q4_INFO (Offset 0x0468) */ 6773 6774#define BIT_SHIFT_QUEUEMACID_Q4_V1 25 6775#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f 6776#define BIT_QUEUEMACID_Q4_V1(x) \ 6777 (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) 6778#define BIT_GET_QUEUEMACID_Q4_V1(x) \ 6779 (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) 6780 6781#define BIT_SHIFT_QUEUEAC_Q4_V1 23 6782#define BIT_MASK_QUEUEAC_Q4_V1 0x3 6783#define BIT_QUEUEAC_Q4_V1(x) \ 6784 (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) 6785#define BIT_GET_QUEUEAC_Q4_V1(x) \ 6786 (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) 6787 6788/* 2 REG_Q4_INFO (Offset 0x0468) */ 6789 6790#define BIT_TIDEMPTY_Q4_V1 BIT(22) 6791 6792/* 2 REG_Q4_INFO (Offset 0x0468) */ 6793 6794#define BIT_SHIFT_TAIL_PKT_Q4_V2 11 6795#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff 6796#define BIT_TAIL_PKT_Q4_V2(x) \ 6797 (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) 6798#define BIT_GET_TAIL_PKT_Q4_V2(x) \ 6799 (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) 6800 6801/* 2 REG_Q4_INFO (Offset 0x0468) */ 6802 6803#define BIT_SHIFT_HEAD_PKT_Q4_V1 0 6804#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff 6805#define BIT_HEAD_PKT_Q4_V1(x) \ 6806 (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) 6807#define BIT_GET_HEAD_PKT_Q4_V1(x) \ 6808 (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) 6809 6810/* 2 REG_Q5_INFO (Offset 0x046C) */ 6811 6812#define BIT_SHIFT_QUEUEMACID_Q5_V1 25 6813#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f 6814#define BIT_QUEUEMACID_Q5_V1(x) \ 6815 (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) 6816#define BIT_GET_QUEUEMACID_Q5_V1(x) \ 6817 (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) 6818 6819#define BIT_SHIFT_QUEUEAC_Q5_V1 23 6820#define BIT_MASK_QUEUEAC_Q5_V1 0x3 6821#define BIT_QUEUEAC_Q5_V1(x) \ 6822 (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) 6823#define BIT_GET_QUEUEAC_Q5_V1(x) \ 6824 (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) 6825 6826/* 2 REG_Q5_INFO (Offset 0x046C) */ 6827 6828#define BIT_TIDEMPTY_Q5_V1 BIT(22) 6829 6830/* 2 REG_Q5_INFO (Offset 0x046C) */ 6831 6832#define BIT_SHIFT_TAIL_PKT_Q5_V2 11 6833#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff 6834#define BIT_TAIL_PKT_Q5_V2(x) \ 6835 (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) 6836#define BIT_GET_TAIL_PKT_Q5_V2(x) \ 6837 (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) 6838 6839/* 2 REG_Q5_INFO (Offset 0x046C) */ 6840 6841#define BIT_SHIFT_HEAD_PKT_Q5_V1 0 6842#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff 6843#define BIT_HEAD_PKT_Q5_V1(x) \ 6844 (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) 6845#define BIT_GET_HEAD_PKT_Q5_V1(x) \ 6846 (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) 6847 6848/* 2 REG_Q6_INFO (Offset 0x0470) */ 6849 6850#define BIT_SHIFT_QUEUEMACID_Q6_V1 25 6851#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f 6852#define BIT_QUEUEMACID_Q6_V1(x) \ 6853 (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) 6854#define BIT_GET_QUEUEMACID_Q6_V1(x) \ 6855 (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) 6856 6857#define BIT_SHIFT_QUEUEAC_Q6_V1 23 6858#define BIT_MASK_QUEUEAC_Q6_V1 0x3 6859#define BIT_QUEUEAC_Q6_V1(x) \ 6860 (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) 6861#define BIT_GET_QUEUEAC_Q6_V1(x) \ 6862 (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) 6863 6864/* 2 REG_Q6_INFO (Offset 0x0470) */ 6865 6866#define BIT_TIDEMPTY_Q6_V1 BIT(22) 6867 6868/* 2 REG_Q6_INFO (Offset 0x0470) */ 6869 6870#define BIT_SHIFT_TAIL_PKT_Q6_V2 11 6871#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff 6872#define BIT_TAIL_PKT_Q6_V2(x) \ 6873 (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) 6874#define BIT_GET_TAIL_PKT_Q6_V2(x) \ 6875 (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) 6876 6877/* 2 REG_Q6_INFO (Offset 0x0470) */ 6878 6879#define BIT_SHIFT_HEAD_PKT_Q6_V1 0 6880#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff 6881#define BIT_HEAD_PKT_Q6_V1(x) \ 6882 (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) 6883#define BIT_GET_HEAD_PKT_Q6_V1(x) \ 6884 (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) 6885 6886/* 2 REG_Q7_INFO (Offset 0x0474) */ 6887 6888#define BIT_SHIFT_QUEUEMACID_Q7_V1 25 6889#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f 6890#define BIT_QUEUEMACID_Q7_V1(x) \ 6891 (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) 6892#define BIT_GET_QUEUEMACID_Q7_V1(x) \ 6893 (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) 6894 6895#define BIT_SHIFT_QUEUEAC_Q7_V1 23 6896#define BIT_MASK_QUEUEAC_Q7_V1 0x3 6897#define BIT_QUEUEAC_Q7_V1(x) \ 6898 (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) 6899#define BIT_GET_QUEUEAC_Q7_V1(x) \ 6900 (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) 6901 6902/* 2 REG_Q7_INFO (Offset 0x0474) */ 6903 6904#define BIT_TIDEMPTY_Q7_V1 BIT(22) 6905 6906/* 2 REG_Q7_INFO (Offset 0x0474) */ 6907 6908#define BIT_SHIFT_TAIL_PKT_Q7_V2 11 6909#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff 6910#define BIT_TAIL_PKT_Q7_V2(x) \ 6911 (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) 6912#define BIT_GET_TAIL_PKT_Q7_V2(x) \ 6913 (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) 6914 6915/* 2 REG_Q7_INFO (Offset 0x0474) */ 6916 6917#define BIT_SHIFT_HEAD_PKT_Q7_V1 0 6918#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff 6919#define BIT_HEAD_PKT_Q7_V1(x) \ 6920 (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) 6921#define BIT_GET_HEAD_PKT_Q7_V1(x) \ 6922 (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) 6923 6924/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ 6925 6926#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 6927#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff 6928#define BIT_WMAC_LBK_BUF_HEAD_V1(x) \ 6929 (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \ 6930 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) 6931#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \ 6932 (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \ 6933 BIT_MASK_WMAC_LBK_BUF_HEAD_V1) 6934 6935/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ 6936 6937#define BIT_SHIFT_MGQ_PGBNDY_V1 0 6938#define BIT_MASK_MGQ_PGBNDY_V1 0xfff 6939#define BIT_MGQ_PGBNDY_V1(x) \ 6940 (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) 6941#define BIT_GET_MGQ_PGBNDY_V1(x) \ 6942 (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) 6943 6944/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6945 6946#define BIT_SHIFT_TRXRPT_TIMER_TH 24 6947#define BIT_MASK_TRXRPT_TIMER_TH 0xff 6948#define BIT_TRXRPT_TIMER_TH(x) \ 6949 (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) 6950#define BIT_GET_TRXRPT_TIMER_TH(x) \ 6951 (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) 6952 6953/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6954 6955#define BIT_SHIFT_TRXRPT_LEN_TH 16 6956#define BIT_MASK_TRXRPT_LEN_TH 0xff 6957#define BIT_TRXRPT_LEN_TH(x) \ 6958 (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) 6959#define BIT_GET_TRXRPT_LEN_TH(x) \ 6960 (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) 6961 6962/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6963 6964#define BIT_SHIFT_TRXRPT_READ_PTR 8 6965#define BIT_MASK_TRXRPT_READ_PTR 0xff 6966#define BIT_TRXRPT_READ_PTR(x) \ 6967 (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) 6968#define BIT_GET_TRXRPT_READ_PTR(x) \ 6969 (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) 6970 6971/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6972 6973#define BIT_SHIFT_TRXRPT_WRITE_PTR 0 6974#define BIT_MASK_TRXRPT_WRITE_PTR 0xff 6975#define BIT_TRXRPT_WRITE_PTR(x) \ 6976 (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) 6977#define BIT_GET_TRXRPT_WRITE_PTR(x) \ 6978 (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) 6979 6980/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ 6981 6982#define BIT_LEAG_RTS_BW_DUP BIT(5) 6983 6984/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ 6985 6986#define BIT_SHIFT_BASIC_CFEND_RATE 0 6987#define BIT_MASK_BASIC_CFEND_RATE 0x1f 6988#define BIT_BASIC_CFEND_RATE(x) \ 6989 (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) 6990#define BIT_GET_BASIC_CFEND_RATE(x) \ 6991 (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) 6992 6993/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ 6994 6995#define BIT_SHIFT_STBC_CFEND_RATE 0 6996#define BIT_MASK_STBC_CFEND_RATE 0x1f 6997#define BIT_STBC_CFEND_RATE(x) \ 6998 (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) 6999#define BIT_GET_STBC_CFEND_RATE(x) \ 7000 (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
7001 7002/* 2 REG_DATA_SC (Offset 0x0483) */ 7003 7004#define BIT_SHIFT_TXSC_40M 4 7005#define BIT_MASK_TXSC_40M 0xf 7006#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 7007#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) 7008 7009#define BIT_SHIFT_TXSC_20M 0 7010#define BIT_MASK_TXSC_20M 0xf 7011#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 7012#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) 7013 7014/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ 7015 7016#define BIT_SHIFT_MACID127_96_PKTSLEEP 0 7017#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL 7018#define BIT_MACID127_96_PKTSLEEP(x) \ 7019 (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \ 7020 << BIT_SHIFT_MACID127_96_PKTSLEEP) 7021#define BIT_GET_MACID127_96_PKTSLEEP(x) \ 7022 (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \ 7023 BIT_MASK_MACID127_96_PKTSLEEP) 7024 7025/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ 7026 7027#define BIT_SHIFT_MACID63_32_PKTSLEEP 0 7028#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL 7029#define BIT_MACID63_32_PKTSLEEP(x) \ 7030 (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) 7031#define BIT_GET_MACID63_32_PKTSLEEP(x) \ 7032 (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) 7033 7034/* 2 REG_ARFR2_V1 (Offset 0x048C) */ 7035 7036#define BIT_SHIFT_ARFR2_V1 0 7037#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL 7038#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) 7039#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) 7040 7041/* 2 REG_ARFR3_V1 (Offset 0x0494) */ 7042 7043#define BIT_SHIFT_ARFR3_V1 0 7044#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL 7045#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) 7046#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) 7047 7048/* 2 REG_ARFR4 (Offset 0x049C) */ 7049 7050#define BIT_SHIFT_ARFR4 0 7051#define BIT_MASK_ARFR4 0xffffffffffffffffL 7052#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) 7053#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) 7054 7055/* 2 REG_ARFR5 (Offset 0x04A4) */ 7056 7057#define BIT_SHIFT_ARFR5 0 7058#define BIT_MASK_ARFR5 0xffffffffffffffffL 7059#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) 7060#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) 7061 7062/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7063 7064#define BIT_SHIFT_MACID_MURATE_OFFSET 24 7065#define BIT_MASK_MACID_MURATE_OFFSET 0xff 7066#define BIT_MACID_MURATE_OFFSET(x) \ 7067 (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) 7068#define BIT_GET_MACID_MURATE_OFFSET(x) \ 7069 (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) 7070 7071/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7072 7073#define BIT_RPTFIFO_SIZE_OPT BIT(16) 7074 7075/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7076 7077#define BIT_SHIFT_MACID_CTRL_OFFSET 8 7078#define BIT_MASK_MACID_CTRL_OFFSET 0xff 7079#define BIT_MACID_CTRL_OFFSET(x) \ 7080 (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) 7081#define BIT_GET_MACID_CTRL_OFFSET(x) \ 7082 (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) 7083 7084/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7085 7086#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 7087#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff 7088#define BIT_AMPDU_TXRPT_OFFSET(x) \ 7089 (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) 7090#define BIT_GET_AMPDU_TXRPT_OFFSET(x) \ 7091 (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) 7092 7093/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ 7094 7095#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) 7096#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) 7097#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) 7098#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) 7099#define BIT_PTA_WL_PRI_MASK_BK BIT(27) 7100#define BIT_PTA_WL_PRI_MASK_BE BIT(26) 7101#define BIT_PTA_WL_PRI_MASK_VI BIT(25) 7102#define BIT_PTA_WL_PRI_MASK_VO BIT(24) 7103 7104/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ 7105 7106#define BIT_SHIFT_POWER_STAGE1 0 7107#define BIT_MASK_POWER_STAGE1 0xffffff 7108#define BIT_POWER_STAGE1(x) \ 7109 (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) 7110#define BIT_GET_POWER_STAGE1(x) \ 7111 (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) 7112 7113/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ 7114 7115#define BIT__R_CTRL_PKT_POW_ADJ BIT(24) 7116 7117/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ 7118 7119#define BIT_SHIFT_POWER_STAGE2 0 7120#define BIT_MASK_POWER_STAGE2 0xffffff 7121#define BIT_POWER_STAGE2(x) \ 7122 (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) 7123#define BIT_GET_POWER_STAGE2(x) \ 7124 (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) 7125 7126/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7127 7128#define BIT_SHIFT_PAD_NUM_THRES 24 7129#define BIT_MASK_PAD_NUM_THRES 0x3f 7130#define BIT_PAD_NUM_THRES(x) \ 7131 (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) 7132#define BIT_GET_PAD_NUM_THRES(x) \ 7133 (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) 7134 7135/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7136 7137#define BIT_R_DMA_THIS_QUEUE_BK BIT(23) 7138#define BIT_R_DMA_THIS_QUEUE_BE BIT(22) 7139#define BIT_R_DMA_THIS_QUEUE_VI BIT(21) 7140#define BIT_R_DMA_THIS_QUEUE_VO BIT(20) 7141 7142#define BIT_SHIFT_R_TOTAL_LEN_TH 8 7143#define BIT_MASK_R_TOTAL_LEN_TH 0xfff 7144#define BIT_R_TOTAL_LEN_TH(x) \ 7145 (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) 7146#define BIT_GET_R_TOTAL_LEN_TH(x) \ 7147 (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) 7148 7149/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7150 7151#define BIT_EN_NEW_EARLY BIT(7) 7152 7153/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7154 7155#define BIT_PRE_TX_CMD BIT(6) 7156 7157#define BIT_SHIFT_NUM_SCL_EN 4 7158#define BIT_MASK_NUM_SCL_EN 0x3 7159#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) 7160#define BIT_GET_NUM_SCL_EN(x) \ 7161 (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) 7162 7163#define BIT_BK_EN BIT(3) 7164#define BIT_BE_EN BIT(2) 7165#define BIT_VI_EN BIT(1) 7166#define BIT_VO_EN BIT(0) 7167 7168/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ 7169 7170#define BIT_SHIFT_PKT_LIFTIME_BEBK 16 7171#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff 7172#define BIT_PKT_LIFTIME_BEBK(x) \ 7173 (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) 7174#define BIT_GET_PKT_LIFTIME_BEBK(x) \ 7175 (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) 7176 7177#define BIT_SHIFT_PKT_LIFTIME_VOVI 0 7178#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff 7179#define BIT_PKT_LIFTIME_VOVI(x) \ 7180 (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) 7181#define BIT_GET_PKT_LIFTIME_VOVI(x) \ 7182 (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) 7183 7184/* 2 REG_STBC_SETTING (Offset 0x04C4) */ 7185 7186#define BIT_SHIFT_CDEND_TXTIME_L 4 7187#define BIT_MASK_CDEND_TXTIME_L 0xf 7188#define BIT_CDEND_TXTIME_L(x) \ 7189 (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) 7190#define BIT_GET_CDEND_TXTIME_L(x) \ 7191 (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) 7192 7193#define BIT_SHIFT_NESS 2 7194#define BIT_MASK_NESS 0x3 7195#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) 7196#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) 7197 7198#define BIT_SHIFT_STBC_CFEND 0 7199#define BIT_MASK_STBC_CFEND 0x3 7200#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) 7201#define BIT_GET_STBC_CFEND(x) \ 7202 (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) 7203 7204/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ 7205 7206#define BIT_SHIFT_CDEND_TXTIME_H 0 7207#define BIT_MASK_CDEND_TXTIME_H 0x1f 7208#define BIT_CDEND_TXTIME_H(x) \ 7209 (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) 7210#define BIT_GET_CDEND_TXTIME_H(x) \ 7211 (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) 7212 7213/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ 7214 7215#define BIT_PTA_EDCCA_EN BIT(5) 7216#define BIT_PTA_WL_TX_EN BIT(4) 7217 7218/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ 7219 7220#define BIT_R_USE_DATA_BW BIT(3) 7221#define BIT_TRI_PKT_INT_MODE1 BIT(2) 7222#define BIT_TRI_PKT_INT_MODE0 BIT(1) 7223#define BIT_ACQ_MODE_SEL BIT(0) 7224 7225/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ 7226 7227#define BIT_EN_SINGLE_APMDU BIT(7) 7228 7229/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ 7230 7231#define BIT_SHIFT_RTS_MAX_AGG_NUM 24 7232#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f 7233#define BIT_RTS_MAX_AGG_NUM(x) \ 7234 (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) 7235#define BIT_GET_RTS_MAX_AGG_NUM(x) \ 7236 (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) 7237 7238#define BIT_SHIFT_MAX_AGG_NUM 16 7239#define BIT_MASK_MAX_AGG_NUM 0x3f 7240#define BIT_MAX_AGG_NUM(x) \ 7241 (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) 7242#define BIT_GET_MAX_AGG_NUM(x) \ 7243 (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) 7244 7245#define BIT_SHIFT_RTS_TXTIME_TH 8 7246#define BIT_MASK_RTS_TXTIME_TH 0xff 7247#define BIT_RTS_TXTIME_TH(x) \ 7248 (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) 7249#define BIT_GET_RTS_TXTIME_TH(x) \ 7250 (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) 7251 7252#define BIT_SHIFT_RTS_LEN_TH 0 7253#define BIT_MASK_RTS_LEN_TH 0xff 7254#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) 7255#define BIT_GET_RTS_LEN_TH(x) \ 7256 (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) 7257 7258/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ 7259 7260#define BIT_SHIFT_BAR_RTY_LMT 16 7261#define BIT_MASK_BAR_RTY_LMT 0x3 7262#define BIT_BAR_RTY_LMT(x) \ 7263 (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) 7264#define BIT_GET_BAR_RTY_LMT(x) \ 7265 (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) 7266 7267#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 7268#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff 7269#define BIT_BAR_PKT_TXTIME_TH(x) \ 7270 (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) 7271#define BIT_GET_BAR_PKT_TXTIME_TH(x) \ 7272 (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) 7273 7274#define BIT_BAR_EN_V1 BIT(6) 7275 7276#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 7277#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f 7278#define BIT_BAR_PKTNUM_TH_V1(x) \ 7279 (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) 7280#define BIT_GET_BAR_PKTNUM_TH_V1(x) \ 7281 (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) 7282 7283/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ 7284 7285#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 7286#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f 7287#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \ 7288 (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \ 7289 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) 7290#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \ 7291 (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \ 7292 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) 7293 7294/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ 7295 7296#define BIT_SHIFT_MACID95_64PKTSLEEP 0 7297#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL 7298#define BIT_MACID95_64PKTSLEEP(x) \ 7299 (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) 7300#define BIT_GET_MACID95_64PKTSLEEP(x) \ 7301 (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) 7302 7303/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ 7304 7305#define BIT_SHIFT_MACID31_0_PKTSLEEP 0 7306#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL 7307#define BIT_MACID31_0_PKTSLEEP(x) \ 7308 (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) 7309#define BIT_GET_MACID31_0_PKTSLEEP(x) \ 7310 (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) 7311 7312/* 2 REG_HW_SEQ0 (Offset 0x04D8) */ 7313 7314#define BIT_SHIFT_HW_SSN_SEQ0 0 7315#define BIT_MASK_HW_SSN_SEQ0 0xfff 7316#define BIT_HW_SSN_SEQ0(x) \ 7317 (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) 7318#define BIT_GET_HW_SSN_SEQ0(x) \ 7319 (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) 7320 7321/* 2 REG_HW_SEQ1 (Offset 0x04DA) */ 7322 7323#define BIT_SHIFT_HW_SSN_SEQ1 0 7324#define BIT_MASK_HW_SSN_SEQ1 0xfff 7325#define BIT_HW_SSN_SEQ1(x) \ 7326 (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) 7327#define BIT_GET_HW_SSN_SEQ1(x) \ 7328 (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) 7329 7330/* 2 REG_HW_SEQ2 (Offset 0x04DC) */ 7331 7332#define BIT_SHIFT_HW_SSN_SEQ2 0 7333#define BIT_MASK_HW_SSN_SEQ2 0xfff 7334#define BIT_HW_SSN_SEQ2(x) \ 7335 (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) 7336#define BIT_GET_HW_SSN_SEQ2(x) \ 7337 (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) 7338 7339/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ 7340 7341#define BIT_SHIFT_HW_SSN_SEQ3 0 7342#define BIT_MASK_HW_SSN_SEQ3 0xfff 7343#define BIT_HW_SSN_SEQ3(x) \ 7344 (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) 7345#define BIT_GET_HW_SSN_SEQ3(x) \ 7346 (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) 7347 7348/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ 7349 7350#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 7351#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff 7352#define BIT_PTCL_TOTAL_PG_V2(x) \ 7353 (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) 7354#define BIT_GET_PTCL_TOTAL_PG_V2(x) \ 7355 (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) 7356 7357/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ 7358 7359#define BIT_TX_NULL_1 BIT(1) 7360#define BIT_TX_NULL_0 BIT(0) 7361 7362/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ 7363 7364#define BIT_PTCL_RATE_TABLE_INVALID BIT(7) 7365#define BIT_FTM_T2R_ERROR BIT(6) 7366 7367/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ 7368 7369#define BIT_PTCL_ERR0 BIT(5) 7370#define BIT_PTCL_ERR1 BIT(4) 7371#define BIT_PTCL_ERR2 BIT(3) 7372#define BIT_PTCL_ERR3 BIT(2) 7373#define BIT_PTCL_ERR4 BIT(1) 7374#define BIT_PTCL_ERR5 BIT(0) 7375 7376/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ 7377 7378#define BIT_CLI3_TX_NULL_1 BIT(7) 7379#define BIT_CLI3_TX_NULL_0 BIT(6) 7380#define BIT_CLI2_TX_NULL_1 BIT(5) 7381#define BIT_CLI2_TX_NULL_0 BIT(4) 7382#define BIT_CLI1_TX_NULL_1 BIT(3) 7383#define BIT_CLI1_TX_NULL_0 BIT(2) 7384#define BIT_CLI0_TX_NULL_1 BIT(1) 7385 7386/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ 7387 7388#define BIT_CLI0_TX_NULL_0 BIT(0) 7389 7390/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ 7391 7392#define BIT_VIDEO_JUST_DROP BIT(1) 7393#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) 7394 7395/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ 7396 7397#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 7398#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff 7399#define BIT_BT_POLLUTE_PKT_CNT(x) \ 7400 (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) 7401#define BIT_GET_BT_POLLUTE_PKT_CNT(x) \ 7402 (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) 7403 7404/* 2 REG_PTCL_DBG (Offset 0x04EC) */ 7405 7406#define BIT_SHIFT_PTCL_DBG 0 7407#define BIT_MASK_PTCL_DBG 0xffffffffL 7408#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) 7409#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) 7410 7411/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ 7412 7413#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) 7414 7415#define BIT_SHIFT_GTAB_ID 28 7416#define BIT_MASK_GTAB_ID 0x7 7417#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) 7418#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) 7419 7420#define BIT_SHIFT_TRI_HEAD_ADDR 16 7421#define BIT_MASK_TRI_HEAD_ADDR 0xfff 7422#define BIT_TRI_HEAD_ADDR(x) \ 7423 (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) 7424#define BIT_GET_TRI_HEAD_ADDR(x) \ 7425 (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) 7426 7427#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) 7428 7429#define BIT_SHIFT_GTAB_ID_V1 12 7430#define BIT_MASK_GTAB_ID_V1 0x7 7431#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) 7432#define BIT_GET_GTAB_ID_V1(x) \ 7433 (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) 7434 7435#define BIT_DROP_TH_EN BIT(8) 7436 7437#define BIT_SHIFT_DROP_TH 0 7438#define BIT_MASK_DROP_TH 0xff 7439#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) 7440#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) 7441 7442/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ 7443 7444#define BIT_BCN_EN_EXTHWSEQ BIT(1) 7445#define BIT_BCN_EN_HWSEQ BIT(0) 7446 7447/* 2 REG_MOREDATA (Offset 0x04FE) */ 7448 7449#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) 7450#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) 7451#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) 7452 7453/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ 7454 7455#define BIT_SHIFT_TXOPLIMIT 16 7456#define BIT_MASK_TXOPLIMIT 0x7ff 7457#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) 7458#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) 7459 7460#define BIT_SHIFT_CW 8 7461#define BIT_MASK_CW 0xff 7462#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) 7463#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) 7464 7465#define BIT_SHIFT_AIFS 0 7466#define BIT_MASK_AIFS 0xff 7467#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) 7468#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) 7469 7470/* 2 REG_BCNTCFG (Offset 0x0510) */ 7471 7472#define BIT_SHIFT_BCNCW_MAX 12 7473#define BIT_MASK_BCNCW_MAX 0xf 7474#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) 7475#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) 7476 7477#define BIT_SHIFT_BCNCW_MIN 8 7478#define BIT_MASK_BCNCW_MIN 0xf 7479#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) 7480#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) 7481 7482#define BIT_SHIFT_BCNIFS 0 7483#define BIT_MASK_BCNIFS 0xff 7484#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) 7485#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) 7486 7487/* 2 REG_PIFS (Offset 0x0512) */ 7488 7489#define BIT_SHIFT_PIFS 0 7490#define BIT_MASK_PIFS 0xff 7491#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) 7492#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) 7493 7494/* 2 REG_RDG_PIFS (Offset 0x0513) */ 7495 7496#define BIT_SHIFT_RDG_PIFS 0 7497#define BIT_MASK_RDG_PIFS 0xff 7498#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) 7499#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) 7500 7501/* 2 REG_SIFS (Offset 0x0514) */ 7502 7503#define BIT_SHIFT_SIFS_OFDM_TRX 24 7504#define BIT_MASK_SIFS_OFDM_TRX 0xff 7505#define BIT_SIFS_OFDM_TRX(x) \ 7506 (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) 7507#define BIT_GET_SIFS_OFDM_TRX(x) \ 7508 (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) 7509 7510#define BIT_SHIFT_SIFS_CCK_TRX 16 7511#define BIT_MASK_SIFS_CCK_TRX 0xff 7512#define BIT_SIFS_CCK_TRX(x) \ 7513 (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) 7514#define BIT_GET_SIFS_CCK_TRX(x) \ 7515 (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) 7516 7517#define BIT_SHIFT_SIFS_OFDM_CTX 8 7518#define BIT_MASK_SIFS_OFDM_CTX 0xff 7519#define BIT_SIFS_OFDM_CTX(x) \ 7520 (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) 7521#define BIT_GET_SIFS_OFDM_CTX(x) \ 7522 (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) 7523 7524#define BIT_SHIFT_SIFS_CCK_CTX 0 7525#define BIT_MASK_SIFS_CCK_CTX 0xff 7526#define BIT_SIFS_CCK_CTX(x) \ 7527 (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) 7528#define BIT_GET_SIFS_CCK_CTX(x) \ 7529 (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) 7530 7531/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ 7532 7533#define BIT_SHIFT_TSFTR_SNC_OFFSET 0 7534#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff 7535#define BIT_TSFTR_SNC_OFFSET(x) \ 7536 (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) 7537#define BIT_GET_TSFTR_SNC_OFFSET(x) \ 7538 (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) 7539 7540/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ 7541 7542#define BIT_SHIFT_AGGR_BK_TIME 0 7543#define BIT_MASK_AGGR_BK_TIME 0xff 7544#define BIT_AGGR_BK_TIME(x) \ 7545 (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) 7546#define BIT_GET_AGGR_BK_TIME(x) \ 7547 (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) 7548 7549/* 2 REG_SLOT (Offset 0x051B) */ 7550 7551#define BIT_SHIFT_SLOT 0 7552#define BIT_MASK_SLOT 0xff 7553#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) 7554#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) 7555 7556/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ 7557 7558#define BIT_DIS_EDCCA BIT(15) 7559#define BIT_DIS_CCA BIT(14) 7560#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) 7561#define BIT_SIFS_BK_EN BIT(12) 7562 7563#define BIT_SHIFT_TXQ_NAV_MSK 8 7564#define BIT_MASK_TXQ_NAV_MSK 0xf 7565#define BIT_TXQ_NAV_MSK(x) \ 7566 (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) 7567#define BIT_GET_TXQ_NAV_MSK(x) \ 7568 (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) 7569 7570#define BIT_DIS_CW BIT(7) 7571#define BIT_NAV_END_TXOP BIT(6) 7572#define BIT_RDG_END_TXOP BIT(5) 7573#define BIT_AC_INBCN_HOLD BIT(4) 7574#define BIT_MGTQ_TXOP_EN BIT(3) 7575#define BIT_MGTQ_RTSMF_EN BIT(2) 7576#define BIT_HIQ_RTSMF_EN BIT(1) 7577#define BIT_BCN_RTSMF_EN BIT(0) 7578 7579/* 2 REG_TXPAUSE (Offset 0x0522) */ 7580 7581#define BIT_STOP_BCN_HI_MGT BIT(7) 7582#define BIT_MAC_STOPBCNQ BIT(6) 7583#define BIT_MAC_STOPHIQ BIT(5) 7584#define BIT_MAC_STOPMGQ BIT(4) 7585#define BIT_MAC_STOPBK BIT(3) 7586#define BIT_MAC_STOPBE BIT(2) 7587#define BIT_MAC_STOPVI BIT(1) 7588#define BIT_MAC_STOPVO BIT(0) 7589 7590/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ 7591 7592#define BIT_DIS_BT_CCA BIT(7) 7593 7594/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ 7595 7596#define BIT_DIS_TXREQ_CLR_HI BIT(5) 7597#define BIT_DIS_TXREQ_CLR_MGQ BIT(4) 7598#define BIT_DIS_TXREQ_CLR_VO BIT(3) 7599#define BIT_DIS_TXREQ_CLR_VI BIT(2) 7600#define BIT_DIS_TXREQ_CLR_BE BIT(1) 7601#define BIT_DIS_TXREQ_CLR_BK BIT(0) 7602 7603/* 2 REG_RD_CTRL (Offset 0x0524) */ 7604 7605#define BIT_EN_CLR_TXREQ_INCCA BIT(15) 7606#define BIT_DIS_TX_OVER_BCNQ BIT(14) 7607 7608/* 2 REG_RD_CTRL (Offset 0x0524) */ 7609 7610#define BIT_EN_BCNERR_INCCCA BIT(13) 7611 7612/* 2 REG_RD_CTRL (Offset 0x0524) */ 7613 7614#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) 7615#define BIT_DIS_TXOP_CFE BIT(10) 7616#define BIT_DIS_LSIG_CFE BIT(9) 7617#define BIT_DIS_STBC_CFE BIT(8) 7618#define BIT_BKQ_RD_INIT_EN BIT(7) 7619#define BIT_BEQ_RD_INIT_EN BIT(6) 7620#define BIT_VIQ_RD_INIT_EN BIT(5) 7621#define BIT_VOQ_RD_INIT_EN BIT(4) 7622#define BIT_BKQ_RD_RESP_EN BIT(3) 7623#define BIT_BEQ_RD_RESP_EN BIT(2) 7624#define BIT_VIQ_RD_RESP_EN BIT(1) 7625#define BIT_VOQ_RD_RESP_EN BIT(0) 7626 7627/* 2 REG_MBSSID_CTRL (Offset 0x0526) */ 7628 7629#define BIT_MBID_BCNQ7_EN BIT(7) 7630#define BIT_MBID_BCNQ6_EN BIT(6) 7631#define BIT_MBID_BCNQ5_EN BIT(5) 7632#define BIT_MBID_BCNQ4_EN BIT(4) 7633#define BIT_MBID_BCNQ3_EN BIT(3) 7634#define BIT_MBID_BCNQ2_EN BIT(2) 7635#define BIT_MBID_BCNQ1_EN BIT(1) 7636#define BIT_MBID_BCNQ0_EN BIT(0) 7637 7638/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ 7639 7640#define BIT_P2P_CTW_ALLSTASLEEP BIT(7) 7641#define BIT_P2P_OFF_DISTX_EN BIT(6) 7642#define BIT_PWR_MGT_EN BIT(5) 7643 7644/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ 7645 7646#define BIT_P2P_NOA1_EN BIT(2) 7647#define BIT_P2P_NOA0_EN BIT(1) 7648 7649/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ 7650 7651#define BIT_EN_P2P_CTWND1 BIT(23) 7652 7653/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ 7654 7655#define BIT_EN_BKF_CLR_TXREQ BIT(22) 7656#define BIT_EN_TSFBIT32_RST_P2P BIT(21) 7657#define BIT_EN_BCN_TX_BTCCA BIT(20) 7658#define BIT_DIS_PKT_TX_ATIM BIT(19) 7659#define BIT_DIS_BCN_DIS_CTN BIT(18) 7660#define BIT_EN_NAVEND_RST_TXOP BIT(17) 7661#define BIT_EN_FILTER_CCA BIT(16) 7662 7663#define BIT_SHIFT_CCA_FILTER_THRS 8 7664#define BIT_MASK_CCA_FILTER_THRS 0xff 7665#define BIT_CCA_FILTER_THRS(x) \ 7666 (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) 7667#define BIT_GET_CCA_FILTER_THRS(x) \ 7668 (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) 7669 7670#define BIT_SHIFT_EDCCA_THRS 0 7671#define BIT_MASK_EDCCA_THRS 0xff 7672#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) 7673#define BIT_GET_EDCCA_THRS(x) \ 7674 (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) 7675 7676/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ 7677 7678#define BIT_SPEC_POWER_STATE BIT(7) 7679#define BIT_SPEC_CTWINDOW_ON BIT(6) 7680#define BIT_SPEC_BEACON_AREA_ON BIT(5) 7681#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) 7682#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) 7683#define BIT_SPEC_FORCE_DOZE1 BIT(2) 7684#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) 7685#define BIT_SPEC_FORCE_DOZE0 BIT(0) 7686 7687/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ 7688 7689#define BIT_SHIFT_BK_QUEUE_THR 24 7690#define BIT_MASK_BK_QUEUE_THR 0xff 7691#define BIT_BK_QUEUE_THR(x) \ 7692 (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) 7693#define BIT_GET_BK_QUEUE_THR(x) \ 7694 (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) 7695 7696#define BIT_SHIFT_BE_QUEUE_THR 16 7697#define BIT_MASK_BE_QUEUE_THR 0xff 7698#define BIT_BE_QUEUE_THR(x) \ 7699 (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) 7700#define BIT_GET_BE_QUEUE_THR(x) \ 7701 (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) 7702 7703#define BIT_SHIFT_VI_QUEUE_THR 8 7704#define BIT_MASK_VI_QUEUE_THR 0xff 7705#define BIT_VI_QUEUE_THR(x) \ 7706 (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) 7707#define BIT_GET_VI_QUEUE_THR(x) \ 7708 (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) 7709 7710#define BIT_SHIFT_VO_QUEUE_THR 0 7711#define BIT_MASK_VO_QUEUE_THR 0xff 7712#define BIT_VO_QUEUE_THR(x) \ 7713 (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) 7714#define BIT_GET_VO_QUEUE_THR(x) \ 7715 (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) 7716 7717/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7718 7719#define BIT_QUEUE_INCOL_EN BIT(16) 7720 7721/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7722 7723#define BIT_SHIFT_BE_TRIGGER_NUM 12 7724#define BIT_MASK_BE_TRIGGER_NUM 0xf 7725#define BIT_BE_TRIGGER_NUM(x) \ 7726 (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) 7727#define BIT_GET_BE_TRIGGER_NUM(x) \ 7728 (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) 7729 7730/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7731 7732#define BIT_SHIFT_BK_TRIGGER_NUM 8 7733#define BIT_MASK_BK_TRIGGER_NUM 0xf 7734#define BIT_BK_TRIGGER_NUM(x) \ 7735 (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) 7736#define BIT_GET_BK_TRIGGER_NUM(x) \ 7737 (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) 7738 7739/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7740 7741#define BIT_SHIFT_VI_TRIGGER_NUM 4 7742#define BIT_MASK_VI_TRIGGER_NUM 0xf 7743#define BIT_VI_TRIGGER_NUM(x) \ 7744 (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) 7745#define BIT_GET_VI_TRIGGER_NUM(x) \ 7746 (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) 7747 7748#define BIT_SHIFT_VO_TRIGGER_NUM 0 7749#define BIT_MASK_VO_TRIGGER_NUM 0xf 7750#define BIT_VO_TRIGGER_NUM(x) \ 7751 (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) 7752#define BIT_GET_VO_TRIGGER_NUM(x) \ 7753 (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) 7754 7755/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ 7756 7757#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 7758#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff 7759#define BIT_TBTT_HOLD_TIME_AP(x) \ 7760 (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) 7761#define BIT_GET_TBTT_HOLD_TIME_AP(x) \ 7762 (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) 7763 7764/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ 7765 7766#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 7767#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf 7768#define BIT_TBTT_PROHIBIT_SETUP(x) \ 7769 (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) 7770#define BIT_GET_TBTT_PROHIBIT_SETUP(x) \ 7771 (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) 7772 7773/* 2 REG_P2PPS_STATE (Offset 0x0543) */ 7774 7775#define BIT_POWER_STATE BIT(7) 7776#define BIT_CTWINDOW_ON BIT(6) 7777#define BIT_BEACON_AREA_ON BIT(5) 7778#define BIT_CTWIN_EARLY_DISTX BIT(4) 7779#define BIT_NOA1_OFF_PERIOD BIT(3) 7780#define BIT_FORCE_DOZE1 BIT(2) 7781#define BIT_NOA0_OFF_PERIOD BIT(1) 7782#define BIT_FORCE_DOZE0 BIT(0) 7783 7784/* 2 REG_RD_NAV_NXT (Offset 0x0544) */ 7785 7786#define BIT_SHIFT_RD_NAV_PROT_NXT 0 7787#define BIT_MASK_RD_NAV_PROT_NXT 0xffff 7788#define BIT_RD_NAV_PROT_NXT(x) \ 7789 (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) 7790#define BIT_GET_RD_NAV_PROT_NXT(x) \ 7791 (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) 7792 7793/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ 7794 7795#define BIT_SHIFT_NAV_PROT_LEN 0 7796#define BIT_MASK_NAV_PROT_LEN 0xffff 7797#define BIT_NAV_PROT_LEN(x) \ 7798 (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) 7799#define BIT_GET_NAV_PROT_LEN(x) \ 7800 (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) 7801 7802/* 2 REG_BCN_CTRL (Offset 0x0550) */ 7803 7804#define BIT_DIS_RX_BSSID_FIT BIT(6) 7805 7806/* 2 REG_BCN_CTRL (Offset 0x0550) */ 7807 7808#define BIT_P0_EN_TXBCN_RPT BIT(5) 7809 7810/* 2 REG_BCN_CTRL (Offset 0x0550) */ 7811 7812#define BIT_DIS_TSF_UDT BIT(4) 7813#define BIT_EN_BCN_FUNCTION BIT(3) 7814 7815/* 2 REG_BCN_CTRL (Offset 0x0550) */ 7816 7817#define BIT_P0_EN_RXBCN_RPT BIT(2) 7818 7819/* 2 REG_BCN_CTRL (Offset 0x0550) */ 7820 7821#define BIT_EN_P2P_CTWINDOW BIT(1) 7822#define BIT_EN_P2P_BCNQ_AREA BIT(0) 7823 7824/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7825 7826#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) 7827 7828/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7829 7830#define BIT_CLI0_DIS_TSF_UDT BIT(4) 7831 7832/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7833 7834#define BIT_CLI0_EN_BCN_FUNCTION BIT(3) 7835 7836/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7837 7838#define BIT_CLI0_EN_RXBCN_RPT BIT(2) 7839 7840/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7841 7842#define BIT_CLI0_ENP2P_CTWINDOW BIT(1) 7843#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) 7844 7845/* 2 REG_MBID_NUM (Offset 0x0552) */ 7846 7847#define BIT_EN_PRE_DL_BEACON BIT(3) 7848 7849#define BIT_SHIFT_MBID_BCN_NUM 0 7850#define BIT_MASK_MBID_BCN_NUM 0x7 7851#define BIT_MBID_BCN_NUM(x) \ 7852 (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) 7853#define BIT_GET_MBID_BCN_NUM(x) \ 7854 (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) 7855 7856/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7857 7858#define BIT_FREECNT_RST BIT(5) 7859 7860/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7861 7862#define BIT_TSFTR_CLI3_RST BIT(4) 7863 7864/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7865 7866#define BIT_TSFTR_CLI2_RST BIT(3) 7867 7868/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7869 7870#define BIT_TSFTR_CLI1_RST BIT(2) 7871 7872/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7873 7874#define BIT_TSFTR_CLI0_RST BIT(1) 7875 7876/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7877 7878#define BIT_TSFTR_RST BIT(0) 7879 7880/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7881 7882#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 7883#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 7884#define BIT_BCN_TIMER_SEL_FWRD(x) \ 7885 (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) 7886#define BIT_GET_BCN_TIMER_SEL_FWRD(x) \ 7887 (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) 7888 7889/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7890 7891#define BIT_SHIFT_BCN_SPACE_CLINT0 16 7892#define BIT_MASK_BCN_SPACE_CLINT0 0xfff 7893#define BIT_BCN_SPACE_CLINT0(x) \ 7894 (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) 7895#define BIT_GET_BCN_SPACE_CLINT0(x) \ 7896 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) 7897 7898/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7899 7900#define BIT_SHIFT_BCN_SPACE0 0 7901#define BIT_MASK_BCN_SPACE0 0xffff 7902#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) 7903#define BIT_GET_BCN_SPACE0(x) \ 7904 (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) 7905 7906/* 2 REG_DRVERLYINT (Offset 0x0558) */ 7907 7908#define BIT_SHIFT_DRVERLYITV 0 7909#define BIT_MASK_DRVERLYITV 0xff 7910#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) 7911#define BIT_GET_DRVERLYITV(x) \ 7912 (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) 7913 7914/* 2 REG_BCNDMATIM (Offset 0x0559) */ 7915 7916#define BIT_SHIFT_BCNDMATIM 0 7917#define BIT_MASK_BCNDMATIM 0xff 7918#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) 7919#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) 7920 7921/* 2 REG_ATIMWND (Offset 0x055A) */ 7922 7923#define BIT_SHIFT_ATIMWND0 0 7924#define BIT_MASK_ATIMWND0 0xffff 7925#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) 7926#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) 7927 7928/* 2 REG_USTIME_TSF (Offset 0x055C) */ 7929 7930#define BIT_SHIFT_USTIME_TSF_V1 0 7931#define BIT_MASK_USTIME_TSF_V1 0xff 7932#define BIT_USTIME_TSF_V1(x) \ 7933 (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) 7934#define BIT_GET_USTIME_TSF_V1(x) \ 7935 (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) 7936 7937/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ 7938 7939#define BIT_SHIFT_BCN_MAX_ERR 0 7940#define BIT_MASK_BCN_MAX_ERR 0xff 7941#define BIT_BCN_MAX_ERR(x) \ 7942 (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) 7943#define BIT_GET_BCN_MAX_ERR(x) \ 7944 (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) 7945 7946/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ 7947 7948#define BIT_SHIFT_CCK_RXTSF_OFFSET 0 7949#define BIT_MASK_CCK_RXTSF_OFFSET 0xff 7950#define BIT_CCK_RXTSF_OFFSET(x) \ 7951 (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) 7952#define BIT_GET_CCK_RXTSF_OFFSET(x) \ 7953 (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) 7954 7955/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ 7956 7957#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 7958#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff 7959#define BIT_OFDM_RXTSF_OFFSET(x) \ 7960 (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) 7961#define BIT_GET_OFDM_RXTSF_OFFSET(x) \ 7962 (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) 7963 7964/* 2 REG_TSFTR (Offset 0x0560) */ 7965 7966#define BIT_SHIFT_TSF_TIMER 0 7967#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL 7968#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) 7969#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) 7970 7971/* 2 REG_FREERUN_CNT (Offset 0x0568) */ 7972 7973#define BIT_SHIFT_FREERUN_CNT 0 7974#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL 7975#define BIT_FREERUN_CNT(x) \ 7976 (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) 7977#define BIT_GET_FREERUN_CNT(x) \ 7978 (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) 7979 7980/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ 7981 7982#define BIT_SHIFT_ATIMWND1_V1 0 7983#define BIT_MASK_ATIMWND1_V1 0xff 7984#define BIT_ATIMWND1_V1(x) \ 7985 (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) 7986#define BIT_GET_ATIMWND1_V1(x) \ 7987 (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) 7988 7989/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ 7990 7991#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 7992#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff 7993#define BIT_TBTT_PROHIBIT_INFRA(x) \ 7994 (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) 7995#define BIT_GET_TBTT_PROHIBIT_INFRA(x) \ 7996 (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) 7997 7998/* 2 REG_CTWND (Offset 0x0572) */ 7999 8000#define BIT_SHIFT_CTWND 0
8001#define BIT_MASK_CTWND 0xff 8002#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) 8003#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) 8004 8005/* 2 REG_BCNIVLCUNT (Offset 0x0573) */ 8006 8007#define BIT_SHIFT_BCNIVLCUNT 0 8008#define BIT_MASK_BCNIVLCUNT 0x7f 8009#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) 8010#define BIT_GET_BCNIVLCUNT(x) \ 8011 (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) 8012 8013/* 2 REG_BCNDROPCTRL (Offset 0x0574) */ 8014 8015#define BIT_BEACON_DROP_EN BIT(7) 8016 8017#define BIT_SHIFT_BEACON_DROP_IVL 0 8018#define BIT_MASK_BEACON_DROP_IVL 0x7f 8019#define BIT_BEACON_DROP_IVL(x) \ 8020 (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) 8021#define BIT_GET_BEACON_DROP_IVL(x) \ 8022 (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) 8023 8024/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ 8025 8026#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 8027#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff 8028#define BIT_HGQ_TIMEOUT_PERIOD(x) \ 8029 (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) 8030#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \ 8031 (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) 8032 8033/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ 8034 8035#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 8036#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff 8037#define BIT_TXCMD_TIMEOUT_PERIOD(x) \ 8038 (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \ 8039 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) 8040#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \ 8041 (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \ 8042 BIT_MASK_TXCMD_TIMEOUT_PERIOD) 8043 8044/* 2 REG_MISC_CTRL (Offset 0x0577) */ 8045 8046#define BIT_DIS_TRX_CAL_BCN BIT(5) 8047#define BIT_DIS_TX_CAL_TBTT BIT(4) 8048#define BIT_EN_FREECNT BIT(3) 8049#define BIT_BCN_AGGRESSION BIT(2) 8050 8051#define BIT_SHIFT_DIS_SECONDARY_CCA 0 8052#define BIT_MASK_DIS_SECONDARY_CCA 0x3 8053#define BIT_DIS_SECONDARY_CCA(x) \ 8054 (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) 8055#define BIT_GET_DIS_SECONDARY_CCA(x) \ 8056 (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) 8057 8058/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8059 8060#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) 8061#define BIT_CLI1_DIS_TSF_UDT BIT(4) 8062#define BIT_CLI1_EN_BCN_FUNCTION BIT(3) 8063 8064/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8065 8066#define BIT_CLI1_EN_RXBCN_RPT BIT(2) 8067 8068/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8069 8070#define BIT_CLI1_ENP2P_CTWINDOW BIT(1) 8071#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) 8072 8073/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8074 8075#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) 8076#define BIT_CLI2_DIS_TSF_UDT BIT(4) 8077#define BIT_CLI2_EN_BCN_FUNCTION BIT(3) 8078 8079/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8080 8081#define BIT_CLI2_EN_RXBCN_RPT BIT(2) 8082 8083/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8084 8085#define BIT_CLI2_ENP2P_CTWINDOW BIT(1) 8086#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) 8087 8088/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8089 8090#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) 8091#define BIT_CLI3_DIS_TSF_UDT BIT(4) 8092#define BIT_CLI3_EN_BCN_FUNCTION BIT(3) 8093 8094/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8095 8096#define BIT_CLI3_EN_RXBCN_RPT BIT(2) 8097 8098/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8099 8100#define BIT_CLI3_ENP2P_CTWINDOW BIT(1) 8101#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) 8102 8103/* 2 REG_EXTEND_CTRL (Offset 0x057B) */ 8104 8105#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) 8106#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) 8107 8108#define BIT_SHIFT_PORT_SEL 0 8109#define BIT_MASK_PORT_SEL 0x7 8110#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) 8111#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) 8112 8113/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ 8114 8115#define BIT_P2P1_SPEC_POWER_STATE BIT(7) 8116#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) 8117#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) 8118#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) 8119#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) 8120#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) 8121#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) 8122#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) 8123 8124/* 2 REG_P2PPS1_STATE (Offset 0x057D) */ 8125 8126#define BIT_P2P1_POWER_STATE BIT(7) 8127#define BIT_P2P1_CTWINDOW_ON BIT(6) 8128#define BIT_P2P1_BEACON_AREA_ON BIT(5) 8129#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) 8130#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) 8131#define BIT_P2P1_FORCE_DOZE1 BIT(2) 8132#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) 8133#define BIT_P2P1_FORCE_DOZE0 BIT(0) 8134 8135/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ 8136 8137#define BIT_P2P2_SPEC_POWER_STATE BIT(7) 8138#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) 8139#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) 8140#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) 8141#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) 8142#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) 8143#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) 8144#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) 8145 8146/* 2 REG_P2PPS2_STATE (Offset 0x057F) */ 8147 8148#define BIT_P2P2_POWER_STATE BIT(7) 8149#define BIT_P2P2_CTWINDOW_ON BIT(6) 8150#define BIT_P2P2_BEACON_AREA_ON BIT(5) 8151#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) 8152#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) 8153#define BIT_P2P2_FORCE_DOZE1 BIT(2) 8154#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) 8155#define BIT_P2P2_FORCE_DOZE0 BIT(0) 8156 8157/* 2 REG_PS_TIMER0 (Offset 0x0580) */ 8158 8159#define BIT_SHIFT_PSTIMER0_INT 5 8160#define BIT_MASK_PSTIMER0_INT 0x7ffffff 8161#define BIT_PSTIMER0_INT(x) \ 8162 (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) 8163#define BIT_GET_PSTIMER0_INT(x) \ 8164 (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) 8165 8166/* 2 REG_PS_TIMER1 (Offset 0x0584) */ 8167 8168#define BIT_SHIFT_PSTIMER1_INT 5 8169#define BIT_MASK_PSTIMER1_INT 0x7ffffff 8170#define BIT_PSTIMER1_INT(x) \ 8171 (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) 8172#define BIT_GET_PSTIMER1_INT(x) \ 8173 (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) 8174 8175/* 2 REG_PS_TIMER2 (Offset 0x0588) */ 8176 8177#define BIT_SHIFT_PSTIMER2_INT 5 8178#define BIT_MASK_PSTIMER2_INT 0x7ffffff 8179#define BIT_PSTIMER2_INT(x) \ 8180 (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) 8181#define BIT_GET_PSTIMER2_INT(x) \ 8182 (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) 8183 8184/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ 8185 8186#define BIT_SHIFT_TBTT_CTN_AREA 0 8187#define BIT_MASK_TBTT_CTN_AREA 0xff 8188#define BIT_TBTT_CTN_AREA(x) \ 8189 (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) 8190#define BIT_GET_TBTT_CTN_AREA(x) \ 8191 (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) 8192 8193/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ 8194 8195#define BIT_SHIFT_FORCE_BCN_IFS 0 8196#define BIT_MASK_FORCE_BCN_IFS 0xff 8197#define BIT_FORCE_BCN_IFS(x) \ 8198 (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) 8199#define BIT_GET_FORCE_BCN_IFS(x) \ 8200 (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) 8201 8202/* 2 REG_TXOP_MIN (Offset 0x0590) */ 8203 8204#define BIT_SHIFT_TXOP_MIN 0 8205#define BIT_MASK_TXOP_MIN 0x3fff 8206#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) 8207#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) 8208 8209/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ 8210 8211#define BIT_SHIFT_PRE_BKF_TIME 0 8212#define BIT_MASK_PRE_BKF_TIME 0xff 8213#define BIT_PRE_BKF_TIME(x) \ 8214 (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) 8215#define BIT_GET_PRE_BKF_TIME(x) \ 8216 (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) 8217 8218/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ 8219 8220#define BIT_DTIM_BYPASS BIT(2) 8221#define BIT_RTS_NAV_TXOP BIT(1) 8222#define BIT_NOT_CROSS_TXOP BIT(0) 8223 8224/* 2 REG_ATIMWND2 (Offset 0x05A0) */ 8225 8226#define BIT_SHIFT_ATIMWND2 0 8227#define BIT_MASK_ATIMWND2 0xff 8228#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) 8229#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) 8230 8231/* 2 REG_ATIMWND3 (Offset 0x05A1) */ 8232 8233#define BIT_SHIFT_ATIMWND3 0 8234#define BIT_MASK_ATIMWND3 0xff 8235#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) 8236#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) 8237 8238/* 2 REG_ATIMWND4 (Offset 0x05A2) */ 8239 8240#define BIT_SHIFT_ATIMWND4 0 8241#define BIT_MASK_ATIMWND4 0xff 8242#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) 8243#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) 8244 8245/* 2 REG_ATIMWND5 (Offset 0x05A3) */ 8246 8247#define BIT_SHIFT_ATIMWND5 0 8248#define BIT_MASK_ATIMWND5 0xff 8249#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) 8250#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) 8251 8252/* 2 REG_ATIMWND6 (Offset 0x05A4) */ 8253 8254#define BIT_SHIFT_ATIMWND6 0 8255#define BIT_MASK_ATIMWND6 0xff 8256#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) 8257#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) 8258 8259/* 2 REG_ATIMWND7 (Offset 0x05A5) */ 8260 8261#define BIT_SHIFT_ATIMWND7 0 8262#define BIT_MASK_ATIMWND7 0xff 8263#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) 8264#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) 8265 8266/* 2 REG_ATIMUGT (Offset 0x05A6) */ 8267 8268#define BIT_SHIFT_ATIM_URGENT 0 8269#define BIT_MASK_ATIM_URGENT 0xff 8270#define BIT_ATIM_URGENT(x) \ 8271 (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) 8272#define BIT_GET_ATIM_URGENT(x) \ 8273 (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) 8274 8275/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ 8276 8277#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) 8278#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) 8279#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) 8280#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) 8281#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) 8282#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) 8283#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) 8284#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) 8285 8286/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ 8287 8288#define BIT_SHIFT_DTIM_COUNT_ROOT 0 8289#define BIT_MASK_DTIM_COUNT_ROOT 0xff 8290#define BIT_DTIM_COUNT_ROOT(x) \ 8291 (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) 8292#define BIT_GET_DTIM_COUNT_ROOT(x) \ 8293 (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) 8294 8295/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ 8296 8297#define BIT_SHIFT_DTIM_COUNT_VAP1 0 8298#define BIT_MASK_DTIM_COUNT_VAP1 0xff 8299#define BIT_DTIM_COUNT_VAP1(x) \ 8300 (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) 8301#define BIT_GET_DTIM_COUNT_VAP1(x) \ 8302 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) 8303 8304/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ 8305 8306#define BIT_SHIFT_DTIM_COUNT_VAP2 0 8307#define BIT_MASK_DTIM_COUNT_VAP2 0xff 8308#define BIT_DTIM_COUNT_VAP2(x) \ 8309 (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) 8310#define BIT_GET_DTIM_COUNT_VAP2(x) \ 8311 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) 8312 8313/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ 8314 8315#define BIT_SHIFT_DTIM_COUNT_VAP3 0 8316#define BIT_MASK_DTIM_COUNT_VAP3 0xff 8317#define BIT_DTIM_COUNT_VAP3(x) \ 8318 (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) 8319#define BIT_GET_DTIM_COUNT_VAP3(x) \ 8320 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) 8321 8322/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ 8323 8324#define BIT_SHIFT_DTIM_COUNT_VAP4 0 8325#define BIT_MASK_DTIM_COUNT_VAP4 0xff 8326#define BIT_DTIM_COUNT_VAP4(x) \ 8327 (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) 8328#define BIT_GET_DTIM_COUNT_VAP4(x) \ 8329 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) 8330 8331/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ 8332 8333#define BIT_SHIFT_DTIM_COUNT_VAP5 0 8334#define BIT_MASK_DTIM_COUNT_VAP5 0xff 8335#define BIT_DTIM_COUNT_VAP5(x) \ 8336 (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) 8337#define BIT_GET_DTIM_COUNT_VAP5(x) \ 8338 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) 8339 8340/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ 8341 8342#define BIT_SHIFT_DTIM_COUNT_VAP6 0 8343#define BIT_MASK_DTIM_COUNT_VAP6 0xff 8344#define BIT_DTIM_COUNT_VAP6(x) \ 8345 (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) 8346#define BIT_GET_DTIM_COUNT_VAP6(x) \ 8347 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) 8348 8349/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ 8350 8351#define BIT_SHIFT_DTIM_COUNT_VAP7 0 8352#define BIT_MASK_DTIM_COUNT_VAP7 0xff 8353#define BIT_DTIM_COUNT_VAP7(x) \ 8354 (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) 8355#define BIT_GET_DTIM_COUNT_VAP7(x) \ 8356 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) 8357 8358/* 2 REG_DIS_ATIM (Offset 0x05B0) */ 8359 8360#define BIT_DIS_ATIM_VAP7 BIT(7) 8361#define BIT_DIS_ATIM_VAP6 BIT(6) 8362#define BIT_DIS_ATIM_VAP5 BIT(5) 8363#define BIT_DIS_ATIM_VAP4 BIT(4) 8364#define BIT_DIS_ATIM_VAP3 BIT(3) 8365#define BIT_DIS_ATIM_VAP2 BIT(2) 8366#define BIT_DIS_ATIM_VAP1 BIT(1) 8367#define BIT_DIS_ATIM_ROOT BIT(0) 8368 8369/* 2 REG_EARLY_128US (Offset 0x05B1) */ 8370 8371#define BIT_SHIFT_TSFT_SEL_TIMER1 3 8372#define BIT_MASK_TSFT_SEL_TIMER1 0x7 8373#define BIT_TSFT_SEL_TIMER1(x) \ 8374 (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) 8375#define BIT_GET_TSFT_SEL_TIMER1(x) \ 8376 (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) 8377 8378#define BIT_SHIFT_EARLY_128US 0 8379#define BIT_MASK_EARLY_128US 0x7 8380#define BIT_EARLY_128US(x) \ 8381 (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) 8382#define BIT_GET_EARLY_128US(x) \ 8383 (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) 8384 8385/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ 8386 8387#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) 8388#define BIT_P2P1_OFF_DISTX_EN BIT(6) 8389#define BIT_P2P1_PWR_MGT_EN BIT(5) 8390#define BIT_P2P1_NOA1_EN BIT(2) 8391#define BIT_P2P1_NOA0_EN BIT(1) 8392 8393/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ 8394 8395#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) 8396#define BIT_P2P2_OFF_DISTX_EN BIT(6) 8397#define BIT_P2P2_PWR_MGT_EN BIT(5) 8398#define BIT_P2P2_NOA1_EN BIT(2) 8399#define BIT_P2P2_NOA0_EN BIT(1) 8400 8401/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ 8402 8403#define BIT_SHIFT_SYNC_CLI_SEL 4 8404#define BIT_MASK_SYNC_CLI_SEL 0x7 8405#define BIT_SYNC_CLI_SEL(x) \ 8406 (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) 8407#define BIT_GET_SYNC_CLI_SEL(x) \ 8408 (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) 8409 8410#define BIT_SHIFT_TSFT_SEL_TIMER0 0 8411#define BIT_MASK_TSFT_SEL_TIMER0 0x7 8412#define BIT_TSFT_SEL_TIMER0(x) \ 8413 (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) 8414#define BIT_GET_TSFT_SEL_TIMER0(x) \ 8415 (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) 8416 8417/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ 8418 8419#define BIT_SHIFT_NOA_UNIT2_SEL 8 8420#define BIT_MASK_NOA_UNIT2_SEL 0x7 8421#define BIT_NOA_UNIT2_SEL(x) \ 8422 (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) 8423#define BIT_GET_NOA_UNIT2_SEL(x) \ 8424 (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) 8425 8426#define BIT_SHIFT_NOA_UNIT1_SEL 4 8427#define BIT_MASK_NOA_UNIT1_SEL 0x7 8428#define BIT_NOA_UNIT1_SEL(x) \ 8429 (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) 8430#define BIT_GET_NOA_UNIT1_SEL(x) \ 8431 (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) 8432 8433#define BIT_SHIFT_NOA_UNIT0_SEL 0 8434#define BIT_MASK_NOA_UNIT0_SEL 0x7 8435#define BIT_NOA_UNIT0_SEL(x) \ 8436 (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) 8437#define BIT_GET_NOA_UNIT0_SEL(x) \ 8438 (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) 8439 8440/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ 8441 8442#define BIT_SHIFT_P2POFF_DIS_TXTIME 0 8443#define BIT_MASK_P2POFF_DIS_TXTIME 0xff 8444#define BIT_P2POFF_DIS_TXTIME(x) \ 8445 (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) 8446#define BIT_GET_P2POFF_DIS_TXTIME(x) \ 8447 (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) 8448 8449/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ 8450 8451#define BIT_SHIFT_BCN_SPACE_CLINT2 16 8452#define BIT_MASK_BCN_SPACE_CLINT2 0xfff 8453#define BIT_BCN_SPACE_CLINT2(x) \ 8454 (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) 8455#define BIT_GET_BCN_SPACE_CLINT2(x) \ 8456 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) 8457 8458#define BIT_SHIFT_BCN_SPACE_CLINT1 0 8459#define BIT_MASK_BCN_SPACE_CLINT1 0xfff 8460#define BIT_BCN_SPACE_CLINT1(x) \ 8461 (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) 8462#define BIT_GET_BCN_SPACE_CLINT1(x) \ 8463 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) 8464 8465/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ 8466 8467#define BIT_SHIFT_SUB_BCN_SPACE 16 8468#define BIT_MASK_SUB_BCN_SPACE 0xff 8469#define BIT_SUB_BCN_SPACE(x) \ 8470 (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) 8471#define BIT_GET_SUB_BCN_SPACE(x) \ 8472 (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) 8473 8474/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ 8475 8476#define BIT_SHIFT_BCN_SPACE_CLINT3 0 8477#define BIT_MASK_BCN_SPACE_CLINT3 0xfff 8478#define BIT_BCN_SPACE_CLINT3(x) \ 8479 (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) 8480#define BIT_GET_BCN_SPACE_CLINT3(x) \ 8481 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) 8482 8483/* 2 REG_ACMHWCTRL (Offset 0x05C0) */ 8484 8485#define BIT_BEQ_ACM_STATUS BIT(7) 8486#define BIT_VIQ_ACM_STATUS BIT(6) 8487#define BIT_VOQ_ACM_STATUS BIT(5) 8488#define BIT_BEQ_ACM_EN BIT(3) 8489#define BIT_VIQ_ACM_EN BIT(2) 8490#define BIT_VOQ_ACM_EN BIT(1) 8491#define BIT_ACMHWEN BIT(0) 8492 8493/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ 8494 8495#define BIT_BE_ACM_RESET_USED_TIME BIT(2) 8496#define BIT_VI_ACM_RESET_USED_TIME BIT(1) 8497#define BIT_VO_ACM_RESET_USED_TIME BIT(0) 8498 8499/* 2 REG_ACMAVG (Offset 0x05C2) */ 8500 8501#define BIT_SHIFT_AVGPERIOD 0 8502#define BIT_MASK_AVGPERIOD 0xffff 8503#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) 8504#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) 8505 8506/* 2 REG_VO_ADMTIME (Offset 0x05C4) */ 8507 8508#define BIT_SHIFT_VO_ADMITTED_TIME 0 8509#define BIT_MASK_VO_ADMITTED_TIME 0xffff 8510#define BIT_VO_ADMITTED_TIME(x) \ 8511 (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) 8512#define BIT_GET_VO_ADMITTED_TIME(x) \ 8513 (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) 8514 8515/* 2 REG_VI_ADMTIME (Offset 0x05C6) */ 8516 8517#define BIT_SHIFT_VI_ADMITTED_TIME 0 8518#define BIT_MASK_VI_ADMITTED_TIME 0xffff 8519#define BIT_VI_ADMITTED_TIME(x) \ 8520 (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) 8521#define BIT_GET_VI_ADMITTED_TIME(x) \ 8522 (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) 8523 8524/* 2 REG_BE_ADMTIME (Offset 0x05C8) */ 8525 8526#define BIT_SHIFT_BE_ADMITTED_TIME 0 8527#define BIT_MASK_BE_ADMITTED_TIME 0xffff 8528#define BIT_BE_ADMITTED_TIME(x) \ 8529 (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) 8530#define BIT_GET_BE_ADMITTED_TIME(x) \ 8531 (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) 8532 8533/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ 8534 8535#define BIT_SHIFT_RANDOM_GEN 0 8536#define BIT_MASK_RANDOM_GEN 0xffffff 8537#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) 8538#define BIT_GET_RANDOM_GEN(x) \ 8539 (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) 8540 8541/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ 8542 8543#define BIT_SHIFT_NOA_SEL 4 8544#define BIT_MASK_NOA_SEL 0x7 8545#define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL) 8546#define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL) 8547 8548/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ 8549 8550#define BIT_SHIFT_TXCMD_SEG_SEL 0 8551#define BIT_MASK_TXCMD_SEG_SEL 0xf 8552#define BIT_TXCMD_SEG_SEL(x) \ 8553 (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) 8554#define BIT_GET_TXCMD_SEG_SEL(x) \ 8555 (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) 8556 8557/* 2 REG_NOA_PARAM (Offset 0x05E0) */ 8558 8559#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) 8560#define BIT_MASK_NOA_COUNT 0xff 8561#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) 8562#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) 8563 8564#define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH) 8565#define BIT_MASK_NOA_START_TIME 0xffffffffL 8566#define BIT_NOA_START_TIME(x) \ 8567 (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME) 8568#define BIT_GET_NOA_START_TIME(x) \ 8569 (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME) 8570 8571#define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH) 8572#define BIT_MASK_NOA_INTERVAL 0xffffffffL 8573#define BIT_NOA_INTERVAL(x) \ 8574 (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL) 8575#define BIT_GET_NOA_INTERVAL(x) \ 8576 (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL) 8577 8578#define BIT_SHIFT_NOA_DURATION 0 8579#define BIT_MASK_NOA_DURATION 0xffffffffL 8580#define BIT_NOA_DURATION(x) \ 8581 (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) 8582#define BIT_GET_NOA_DURATION(x) \ 8583 (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) 8584 8585/* 2 REG_P2P_RST (Offset 0x05F0) */ 8586 8587#define BIT_P2P2_PWR_RST1 BIT(5) 8588#define BIT_P2P2_PWR_RST0 BIT(4) 8589#define BIT_P2P1_PWR_RST1 BIT(3) 8590#define BIT_P2P1_PWR_RST0 BIT(2) 8591#define BIT_P2P_PWR_RST1_V1 BIT(1) 8592#define BIT_P2P_PWR_RST0_V1 BIT(0) 8593 8594/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ 8595 8596#define BIT_SYNC_CLI BIT(1) 8597#define BIT_SCHEDULER_RST_V1 BIT(0) 8598 8599/* 2 REG_SCH_TXCMD (Offset 0x05F8) */ 8600 8601#define BIT_SHIFT_SCH_TXCMD 0 8602#define BIT_MASK_SCH_TXCMD 0xffffffffL 8603#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) 8604#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) 8605 8606/* 2 REG_WMAC_CR (Offset 0x0600) */ 8607 8608#define BIT_IC_MACPHY_M BIT(0) 8609 8610/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8611 8612#define BIT_FWEN BIT(7) 8613 8614/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8615 8616#define BIT_PHYSTS_PKT_CTRL BIT(6) 8617 8618/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8619 8620#define BIT_APPHDR_MIDSRCH_FAIL BIT(4) 8621#define BIT_FWPARSING_EN BIT(3) 8622 8623#define BIT_SHIFT_APPEND_MHDR_LEN 0 8624#define BIT_MASK_APPEND_MHDR_LEN 0x7 8625#define BIT_APPEND_MHDR_LEN(x) \ 8626 (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) 8627#define BIT_GET_APPEND_MHDR_LEN(x) \ 8628 (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) 8629 8630/* 2 REG_TCR (Offset 0x0604) */ 8631 8632#define BIT_WMAC_EN_RTS_ADDR BIT(31) 8633#define BIT_WMAC_DISABLE_CCK BIT(30) 8634#define BIT_WMAC_RAW_LEN BIT(29) 8635#define BIT_WMAC_NOTX_IN_RXNDP BIT(28) 8636#define BIT_WMAC_EN_EOF BIT(27) 8637#define BIT_WMAC_BF_SEL BIT(26) 8638#define BIT_WMAC_ANTMODE_SEL BIT(25) 8639 8640/* 2 REG_TCR (Offset 0x0604) */ 8641 8642#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) 8643 8644/* 2 REG_TCR (Offset 0x0604) */ 8645 8646#define BIT_WMAC_SMOOTH_VAL BIT(23) 8647 8648/* 2 REG_TCR (Offset 0x0604) */ 8649 8650#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) 8651 8652/* 2 REG_TCR (Offset 0x0604) */ 8653 8654#define BIT_WMAC_TCR_EN_20MST BIT(19) 8655#define BIT_WMAC_DIS_SIGTA BIT(18) 8656#define BIT_WMAC_DIS_A2B0 BIT(17) 8657#define BIT_WMAC_MSK_SIGBCRC BIT(16) 8658 8659/* 2 REG_TCR (Offset 0x0604) */ 8660 8661#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) 8662#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) 8663#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) 8664#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) 8665#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) 8666#define BIT_ICV BIT(10) 8667#define BIT_CFEND_FORMAT BIT(9) 8668#define BIT_CRC BIT(8) 8669#define BIT_PWRBIT_OW_EN BIT(7) 8670#define BIT_PWR_ST BIT(6) 8671#define BIT_WMAC_TCR_UPD_TIMIE BIT(5) 8672#define BIT_WMAC_TCR_UPD_HGQMD BIT(4) 8673 8674/* 2 REG_TCR (Offset 0x0604) */ 8675 8676#define BIT_VHTSIGA1_TXPS BIT(3) 8677 8678/* 2 REG_TCR (Offset 0x0604) */ 8679 8680#define BIT_PAD_SEL BIT(2) 8681#define BIT_DIS_GCLK BIT(1) 8682 8683/* 2 REG_RCR (Offset 0x0608) */ 8684 8685#define BIT_APP_FCS BIT(31) 8686#define BIT_APP_MIC BIT(30) 8687#define BIT_APP_ICV BIT(29) 8688#define BIT_APP_PHYSTS BIT(28) 8689#define BIT_APP_BASSN BIT(27) 8690 8691/* 2 REG_RCR (Offset 0x0608) */ 8692 8693#define BIT_VHT_DACK BIT(26) 8694 8695/* 2 REG_RCR (Offset 0x0608) */ 8696 8697#define BIT_TCPOFLD_EN BIT(25) 8698#define BIT_ENMBID BIT(24) 8699#define BIT_LSIGEN BIT(23) 8700#define BIT_MFBEN BIT(22) 8701#define BIT_DISCHKPPDLLEN BIT(21) 8702#define BIT_PKTCTL_DLEN BIT(20) 8703#define BIT_TIM_PARSER_EN BIT(18) 8704#define BIT_BC_MD_EN BIT(17) 8705#define BIT_UC_MD_EN BIT(16) 8706#define BIT_RXSK_PERPKT BIT(15) 8707#define BIT_HTC_LOC_CTRL BIT(14) 8708 8709/* 2 REG_RCR (Offset 0x0608) */ 8710 8711#define BIT_RPFM_CAM_ENABLE BIT(12) 8712 8713/* 2 REG_RCR (Offset 0x0608) */ 8714 8715#define BIT_TA_BCN BIT(11) 8716 8717/* 2 REG_RCR (Offset 0x0608) */ 8718 8719#define BIT_DISDECMYPKT BIT(10) 8720#define BIT_AICV BIT(9) 8721#define BIT_ACRC32 BIT(8) 8722#define BIT_CBSSID_BCN BIT(7) 8723#define BIT_CBSSID_DATA BIT(6) 8724#define BIT_APWRMGT BIT(5) 8725#define BIT_ADD3 BIT(4) 8726#define BIT_AB BIT(3) 8727#define BIT_AM BIT(2) 8728#define BIT_APM BIT(1) 8729#define BIT_AAP BIT(0) 8730 8731/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ 8732 8733#define BIT_SHIFT_RXPKTLMT 0 8734#define BIT_MASK_RXPKTLMT 0x3f 8735#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) 8736#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) 8737 8738/* 2 REG_RX_DLK_TIME (Offset 0x060D) */ 8739 8740#define BIT_SHIFT_RX_DLK_TIME 0 8741#define BIT_MASK_RX_DLK_TIME 0xff 8742#define BIT_RX_DLK_TIME(x) \ 8743 (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) 8744#define BIT_GET_RX_DLK_TIME(x) \ 8745 (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) 8746 8747/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8748 8749#define BIT_DATA_RPFM15EN BIT(15) 8750#define BIT_DATA_RPFM14EN BIT(14) 8751#define BIT_DATA_RPFM13EN BIT(13) 8752#define BIT_DATA_RPFM12EN BIT(12) 8753#define BIT_DATA_RPFM11EN BIT(11) 8754#define BIT_DATA_RPFM10EN BIT(10) 8755#define BIT_DATA_RPFM9EN BIT(9) 8756#define BIT_DATA_RPFM8EN BIT(8) 8757 8758/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8759 8760#define BIT_PHYSTS_PER_PKT_MODE BIT(7) 8761#define BIT_DATA_RPFM7EN BIT(7) 8762 8763/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8764 8765#define BIT_DATA_RPFM6EN BIT(6) 8766 8767/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8768 8769#define BIT_DATA_RPFM5EN BIT(5) 8770#define BIT_DATA_RPFM4EN BIT(4) 8771#define BIT_DATA_RPFM3EN BIT(3) 8772#define BIT_DATA_RPFM2EN BIT(2) 8773#define BIT_DATA_RPFM1EN BIT(1) 8774 8775/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8776 8777#define BIT_SHIFT_DRVINFO_SZ_V1 0 8778#define BIT_MASK_DRVINFO_SZ_V1 0xf 8779#define BIT_DRVINFO_SZ_V1(x) \ 8780 (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) 8781#define BIT_GET_DRVINFO_SZ_V1(x) \ 8782 (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) 8783 8784/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8785 8786#define BIT_DATA_RPFM0EN BIT(0) 8787 8788/* 2 REG_MACID (Offset 0x0610) */ 8789 8790#define BIT_SHIFT_MACID 0 8791#define BIT_MASK_MACID 0xffffffffffffL 8792#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) 8793#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) 8794 8795/* 2 REG_BSSID (Offset 0x0618) */ 8796 8797#define BIT_SHIFT_BSSID 0 8798#define BIT_MASK_BSSID 0xffffffffffffL 8799#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) 8800#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) 8801 8802/* 2 REG_MAR (Offset 0x0620) */ 8803 8804#define BIT_SHIFT_MAR 0 8805#define BIT_MASK_MAR 0xffffffffffffffffL 8806#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) 8807#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) 8808 8809/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ 8810 8811#define BIT_SHIFT_MBIDCAM_RWDATA_L 0 8812#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL 8813#define BIT_MBIDCAM_RWDATA_L(x) \ 8814 (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) 8815#define BIT_GET_MBIDCAM_RWDATA_L(x) \ 8816 (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) 8817 8818/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8819 8820#define BIT_MBIDCAM_POLL BIT(31) 8821#define BIT_MBIDCAM_WT_EN BIT(30) 8822 8823#define BIT_SHIFT_MBIDCAM_ADDR 24 8824#define BIT_MASK_MBIDCAM_ADDR 0x1f 8825#define BIT_MBIDCAM_ADDR(x) \ 8826 (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) 8827#define BIT_GET_MBIDCAM_ADDR(x) \ 8828 (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) 8829 8830#define BIT_MBIDCAM_VALID BIT(23) 8831#define BIT_LSIC_TXOP_EN BIT(17) 8832 8833/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8834 8835#define BIT_CTS_EN BIT(16) 8836 8837/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8838 8839#define BIT_SHIFT_MBIDCAM_RWDATA_H 0 8840#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff 8841#define BIT_MBIDCAM_RWDATA_H(x) \ 8842 (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) 8843#define BIT_GET_MBIDCAM_RWDATA_H(x) \ 8844 (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) 8845 8846/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ 8847 8848#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 8849#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff 8850#define BIT_WMAC_TCR_TSFT_OFS(x) \ 8851 (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) 8852#define BIT_GET_WMAC_TCR_TSFT_OFS(x) \ 8853 (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) 8854 8855/* 2 REG_UDF_THSD (Offset 0x0632) */ 8856 8857#define BIT_SHIFT_UDF_THSD 0 8858#define BIT_MASK_UDF_THSD 0xff 8859#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) 8860#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) 8861 8862/* 2 REG_ZLD_NUM (Offset 0x0633) */ 8863 8864#define BIT_SHIFT_ZLD_NUM 0 8865#define BIT_MASK_ZLD_NUM 0xff 8866#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) 8867#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) 8868 8869/* 2 REG_STMP_THSD (Offset 0x0634) */ 8870 8871#define BIT_SHIFT_STMP_THSD 0 8872#define BIT_MASK_STMP_THSD 0xff 8873#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) 8874#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) 8875 8876/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ 8877 8878#define BIT_SHIFT_WMAC_TXTIMEOUT 0 8879#define BIT_MASK_WMAC_TXTIMEOUT 0xff 8880#define BIT_WMAC_TXTIMEOUT(x) \ 8881 (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) 8882#define BIT_GET_WMAC_TXTIMEOUT(x) \ 8883 (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) 8884 8885/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ 8886 8887#define BIT_SHIFT_MCU_RSVD_2_V1 0 8888#define BIT_MASK_MCU_RSVD_2_V1 0xffff 8889#define BIT_MCU_RSVD_2_V1(x) \ 8890 (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) 8891#define BIT_GET_MCU_RSVD_2_V1(x) \ 8892 (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) 8893 8894/* 2 REG_USTIME_EDCA (Offset 0x0638) */ 8895 8896#define BIT_SHIFT_USTIME_EDCA_V1 0 8897#define BIT_MASK_USTIME_EDCA_V1 0x1ff 8898#define BIT_USTIME_EDCA_V1(x) \ 8899 (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) 8900#define BIT_GET_USTIME_EDCA_V1(x) \ 8901 (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) 8902 8903/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ 8904 8905#define BIT_SHIFT_SPEC_SIFS_OFDM 8 8906#define BIT_MASK_SPEC_SIFS_OFDM 0xff 8907#define BIT_SPEC_SIFS_OFDM(x) \ 8908 (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) 8909#define BIT_GET_SPEC_SIFS_OFDM(x) \ 8910 (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) 8911 8912#define BIT_SHIFT_SPEC_SIFS_CCK 0 8913#define BIT_MASK_SPEC_SIFS_CCK 0xff 8914#define BIT_SPEC_SIFS_CCK(x) \ 8915 (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) 8916#define BIT_GET_SPEC_SIFS_CCK(x) \ 8917 (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) 8918 8919/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ 8920 8921#define BIT_SHIFT_SIFS_R2T_CCK 8 8922#define BIT_MASK_SIFS_R2T_CCK 0xff 8923#define BIT_SIFS_R2T_CCK(x) \ 8924 (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) 8925#define BIT_GET_SIFS_R2T_CCK(x) \ 8926 (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) 8927 8928#define BIT_SHIFT_SIFS_T2T_CCK 0 8929#define BIT_MASK_SIFS_T2T_CCK 0xff 8930#define BIT_SIFS_T2T_CCK(x) \ 8931 (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) 8932#define BIT_GET_SIFS_T2T_CCK(x) \ 8933 (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) 8934 8935/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ 8936 8937#define BIT_SHIFT_SIFS_R2T_OFDM 8 8938#define BIT_MASK_SIFS_R2T_OFDM 0xff 8939#define BIT_SIFS_R2T_OFDM(x) \ 8940 (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) 8941#define BIT_GET_SIFS_R2T_OFDM(x) \ 8942 (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) 8943 8944#define BIT_SHIFT_SIFS_T2T_OFDM 0 8945#define BIT_MASK_SIFS_T2T_OFDM 0xff 8946#define BIT_SIFS_T2T_OFDM(x) \ 8947 (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) 8948#define BIT_GET_SIFS_T2T_OFDM(x) \ 8949 (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) 8950 8951/* 2 REG_ACKTO (Offset 0x0640) */ 8952 8953#define BIT_SHIFT_ACKTO 0 8954#define BIT_MASK_ACKTO 0xff 8955#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) 8956#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) 8957 8958/* 2 REG_CTS2TO (Offset 0x0641) */ 8959 8960#define BIT_SHIFT_CTS2TO 0 8961#define BIT_MASK_CTS2TO 0xff 8962#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) 8963#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) 8964 8965/* 2 REG_EIFS (Offset 0x0642) */ 8966 8967#define BIT_SHIFT_EIFS 0 8968#define BIT_MASK_EIFS 0xffff 8969#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) 8970#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) 8971 8972/* 2 REG_NAV_CTRL (Offset 0x0650) */ 8973 8974#define BIT_SHIFT_NAV_UPPER 16 8975#define BIT_MASK_NAV_UPPER 0xff 8976#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) 8977#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) 8978 8979#define BIT_SHIFT_RXMYRTS_NAV 8 8980#define BIT_MASK_RXMYRTS_NAV 0xf 8981#define BIT_RXMYRTS_NAV(x) \ 8982 (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) 8983#define BIT_GET_RXMYRTS_NAV(x) \ 8984 (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) 8985 8986#define BIT_SHIFT_RTSRST 0 8987#define BIT_MASK_RTSRST 0xff 8988#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) 8989#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) 8990 8991/* 2 REG_BACAMCMD (Offset 0x0654) */ 8992 8993#define BIT_BACAM_POLL BIT(31) 8994#define BIT_BACAM_RST BIT(17) 8995#define BIT_BACAM_RW BIT(16) 8996 8997#define BIT_SHIFT_TXSBM 14 8998#define BIT_MASK_TXSBM 0x3 8999#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) 9000#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)
9001 9002#define BIT_SHIFT_BACAM_ADDR 0 9003#define BIT_MASK_BACAM_ADDR 0x3f 9004#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) 9005#define BIT_GET_BACAM_ADDR(x) \ 9006 (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) 9007 9008/* 2 REG_BACAMCONTENT (Offset 0x0658) */ 9009 9010#define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH) 9011#define BIT_MASK_BA_CONTENT_H 0xffffffffL 9012#define BIT_BA_CONTENT_H(x) \ 9013 (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H) 9014#define BIT_GET_BA_CONTENT_H(x) \ 9015 (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H) 9016 9017#define BIT_SHIFT_BA_CONTENT_L 0 9018#define BIT_MASK_BA_CONTENT_L 0xffffffffL 9019#define BIT_BA_CONTENT_L(x) \ 9020 (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) 9021#define BIT_GET_BA_CONTENT_L(x) \ 9022 (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) 9023 9024/* 2 REG_LBDLY (Offset 0x0660) */ 9025 9026#define BIT_SHIFT_LBDLY 0 9027#define BIT_MASK_LBDLY 0x1f 9028#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) 9029#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) 9030 9031/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ 9032 9033#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 9034#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f 9035#define BIT_BITMAP_SSNBK_COUNTER(x) \ 9036 (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \ 9037 << BIT_SHIFT_BITMAP_SSNBK_COUNTER) 9038#define BIT_GET_BITMAP_SSNBK_COUNTER(x) \ 9039 (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \ 9040 BIT_MASK_BITMAP_SSNBK_COUNTER) 9041 9042#define BIT_BITMAP_EN BIT(1) 9043 9044/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ 9045 9046#define BIT_WMAC_BACAM_RPMEN BIT(0) 9047 9048/* 2 REG_TX_RX (Offset 0x0662) */ 9049 9050#define BIT_SHIFT_RXPKT_TYPE 2 9051#define BIT_MASK_RXPKT_TYPE 0x3f 9052#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) 9053#define BIT_GET_RXPKT_TYPE(x) \ 9054 (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) 9055 9056#define BIT_TXACT_IND BIT(1) 9057#define BIT_RXACT_IND BIT(0) 9058 9059/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ 9060 9061#define BIT_BITMAP_VO BIT(7) 9062#define BIT_BITMAP_VI BIT(6) 9063#define BIT_BITMAP_BE BIT(5) 9064#define BIT_BITMAP_BK BIT(4) 9065 9066#define BIT_SHIFT_BITMAP_CONDITION 2 9067#define BIT_MASK_BITMAP_CONDITION 0x3 9068#define BIT_BITMAP_CONDITION(x) \ 9069 (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) 9070#define BIT_GET_BITMAP_CONDITION(x) \ 9071 (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) 9072 9073#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) 9074#define BIT_BITMAP_FORCE BIT(0) 9075 9076/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9077 9078#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 9079#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf 9080#define BIT_RXERR_RPT_SEL_V1_3_0(x) \ 9081 (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \ 9082 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) 9083#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \ 9084 (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \ 9085 BIT_MASK_RXERR_RPT_SEL_V1_3_0) 9086 9087/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9088 9089#define BIT_RXERR_RPT_RST BIT(27) 9090 9091/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9092 9093#define BIT_RXERR_RPT_SEL_V1_4 BIT(26) 9094 9095/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9096 9097#define BIT_W1S BIT(23) 9098 9099/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9100 9101#define BIT_UD_SELECT_BSSID BIT(22) 9102 9103/* 2 REG_RXERR_RPT (Offset 0x0664) */ 9104 9105#define BIT_SHIFT_UD_SUB_TYPE 18 9106#define BIT_MASK_UD_SUB_TYPE 0xf 9107#define BIT_UD_SUB_TYPE(x) \ 9108 (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) 9109#define BIT_GET_UD_SUB_TYPE(x) \ 9110 (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) 9111 9112#define BIT_SHIFT_UD_TYPE 16 9113#define BIT_MASK_UD_TYPE 0x3 9114#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) 9115#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) 9116 9117#define BIT_SHIFT_RPT_COUNTER 0 9118#define BIT_MASK_RPT_COUNTER 0xffff 9119#define BIT_RPT_COUNTER(x) \ 9120 (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) 9121#define BIT_GET_RPT_COUNTER(x) \ 9122 (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) 9123 9124/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9125 9126#define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH) 9127#define BIT_MASK_ACKBA_TYPSEL 0xf 9128#define BIT_ACKBA_TYPSEL(x) \ 9129 (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL) 9130#define BIT_GET_ACKBA_TYPSEL(x) \ 9131 (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL) 9132 9133#define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH) 9134#define BIT_MASK_ACKBA_ACKPCHK 0xf 9135#define BIT_ACKBA_ACKPCHK(x) \ 9136 (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK) 9137#define BIT_GET_ACKBA_ACKPCHK(x) \ 9138 (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK) 9139 9140#define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH) 9141#define BIT_MASK_ACKBAR_TYPESEL 0xff 9142#define BIT_ACKBAR_TYPESEL(x) \ 9143 (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL) 9144#define BIT_GET_ACKBAR_TYPESEL(x) \ 9145 (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL) 9146 9147#define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH) 9148#define BIT_MASK_ACKBAR_ACKPCHK 0xf 9149#define BIT_ACKBAR_ACKPCHK(x) \ 9150 (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK) 9151#define BIT_GET_ACKBAR_ACKPCHK(x) \ 9152 (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK) 9153 9154/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9155 9156#define BIT_RXBA_IGNOREA2 BIT(42) 9157#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) 9158#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) 9159 9160/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9161 9162#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) 9163#define BIT_DIS_TXBA_RXBARINFULL BIT(38) 9164#define BIT_DIS_TXCFE_INFULL BIT(37) 9165#define BIT_DIS_TXCTS_INFULL BIT(36) 9166#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) 9167#define BIT_EN_TXACKBA_IN_TXOP BIT(34) 9168#define BIT_EN_TXCTS_IN_RXNAV BIT(33) 9169#define BIT_EN_TXCTS_INTXOP BIT(32) 9170#define BIT_BLK_EDCA_BBSLP BIT(31) 9171#define BIT_BLK_EDCA_BBSBY BIT(30) 9172#define BIT_ACKTO_BLOCK_SCH_EN BIT(27) 9173#define BIT_EIFS_BLOCK_SCH_EN BIT(26) 9174#define BIT_PLCPCHK_RST_EIFS BIT(25) 9175#define BIT_CCA_RST_EIFS BIT(24) 9176#define BIT_DIS_UPD_MYRXPKTNAV BIT(23) 9177#define BIT_EARLY_TXBA BIT(22) 9178 9179#define BIT_SHIFT_RESP_CHNBUSY 20 9180#define BIT_MASK_RESP_CHNBUSY 0x3 9181#define BIT_RESP_CHNBUSY(x) \ 9182 (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) 9183#define BIT_GET_RESP_CHNBUSY(x) \ 9184 (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) 9185 9186#define BIT_RESP_DCTS_EN BIT(19) 9187#define BIT_RESP_DCFE_EN BIT(18) 9188#define BIT_RESP_SPLCPEN BIT(17) 9189#define BIT_RESP_SGIEN BIT(16) 9190 9191/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9192 9193#define BIT_RESP_LDPC_EN BIT(15) 9194#define BIT_DIS_RESP_ACKINCCA BIT(14) 9195#define BIT_DIS_RESP_CTSINCCA BIT(13) 9196 9197/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9198 9199#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 9200#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 9201#define BIT_R_WMAC_SECOND_CCA_TIMER(x) \ 9202 (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \ 9203 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) 9204#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \ 9205 (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \ 9206 BIT_MASK_R_WMAC_SECOND_CCA_TIMER) 9207 9208/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9209 9210#define BIT_SHIFT_RFMOD 7 9211#define BIT_MASK_RFMOD 0x3 9212#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) 9213#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) 9214 9215/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9216 9217#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 9218#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 9219#define BIT_RESP_CTS_DYNBW_SEL(x) \ 9220 (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) 9221#define BIT_GET_RESP_CTS_DYNBW_SEL(x) \ 9222 (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) 9223 9224/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9225 9226#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) 9227 9228/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9229 9230#define BIT_TXRESP_BY_RXANTSEL BIT(3) 9231 9232/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9233 9234#define BIT_SHIFT_ORIG_DCTS_CHK 0 9235#define BIT_MASK_ORIG_DCTS_CHK 0x3 9236#define BIT_ORIG_DCTS_CHK(x) \ 9237 (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) 9238#define BIT_GET_ORIG_DCTS_CHK(x) \ 9239 (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) 9240 9241/* 2 REG_CAMCMD (Offset 0x0670) */ 9242 9243#define BIT_SECCAM_POLLING BIT(31) 9244#define BIT_SECCAM_CLR BIT(30) 9245#define BIT_MFBCAM_CLR BIT(29) 9246 9247/* 2 REG_CAMCMD (Offset 0x0670) */ 9248 9249#define BIT_SECCAM_WE BIT(16) 9250 9251/* 2 REG_CAMCMD (Offset 0x0670) */ 9252 9253#define BIT_SHIFT_SECCAM_ADDR_V2 0 9254#define BIT_MASK_SECCAM_ADDR_V2 0x3ff 9255#define BIT_SECCAM_ADDR_V2(x) \ 9256 (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) 9257#define BIT_GET_SECCAM_ADDR_V2(x) \ 9258 (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) 9259 9260/* 2 REG_CAMWRITE (Offset 0x0674) */ 9261 9262#define BIT_SHIFT_CAMW_DATA 0 9263#define BIT_MASK_CAMW_DATA 0xffffffffL 9264#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) 9265#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) 9266 9267/* 2 REG_CAMREAD (Offset 0x0678) */ 9268 9269#define BIT_SHIFT_CAMR_DATA 0 9270#define BIT_MASK_CAMR_DATA 0xffffffffL 9271#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) 9272#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) 9273 9274/* 2 REG_CAMDBG (Offset 0x067C) */ 9275 9276#define BIT_SECCAM_INFO BIT(31) 9277#define BIT_SEC_KEYFOUND BIT(15) 9278 9279#define BIT_SHIFT_CAMDBG_SEC_TYPE 12 9280#define BIT_MASK_CAMDBG_SEC_TYPE 0x7 9281#define BIT_CAMDBG_SEC_TYPE(x) \ 9282 (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) 9283#define BIT_GET_CAMDBG_SEC_TYPE(x) \ 9284 (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) 9285 9286/* 2 REG_CAMDBG (Offset 0x067C) */ 9287 9288#define BIT_CAMDBG_EXT_SECTYPE BIT(11) 9289 9290/* 2 REG_CAMDBG (Offset 0x067C) */ 9291 9292#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 9293#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f 9294#define BIT_CAMDBG_MIC_KEY_IDX(x) \ 9295 (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) 9296#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \ 9297 (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) 9298 9299#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 9300#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f 9301#define BIT_CAMDBG_SEC_KEY_IDX(x) \ 9302 (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) 9303#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \ 9304 (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) 9305 9306/* 2 REG_SECCFG (Offset 0x0680) */ 9307 9308#define BIT_DIS_GCLK_WAPI BIT(15) 9309#define BIT_DIS_GCLK_AES BIT(14) 9310#define BIT_DIS_GCLK_TKIP BIT(13) 9311 9312/* 2 REG_SECCFG (Offset 0x0680) */ 9313 9314#define BIT_AES_SEL_QC_1 BIT(12) 9315#define BIT_AES_SEL_QC_0 BIT(11) 9316 9317/* 2 REG_SECCFG (Offset 0x0680) */ 9318 9319#define BIT_CHK_BMC BIT(9) 9320 9321/* 2 REG_SECCFG (Offset 0x0680) */ 9322 9323#define BIT_CHK_KEYID BIT(8) 9324#define BIT_RXBCUSEDK BIT(7) 9325#define BIT_TXBCUSEDK BIT(6) 9326#define BIT_NOSKMC BIT(5) 9327#define BIT_SKBYA2 BIT(4) 9328#define BIT_RXDEC BIT(3) 9329#define BIT_TXENC BIT(2) 9330#define BIT_RXUHUSEDK BIT(1) 9331#define BIT_TXUHUSEDK BIT(0) 9332 9333/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ 9334 9335#define BIT_SHIFT_RXFILTER_CATEGORY_1 0 9336#define BIT_MASK_RXFILTER_CATEGORY_1 0xff 9337#define BIT_RXFILTER_CATEGORY_1(x) \ 9338 (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) 9339#define BIT_GET_RXFILTER_CATEGORY_1(x) \ 9340 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) 9341 9342/* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ 9343 9344#define BIT_SHIFT_RXFILTER_ACTION_1 0 9345#define BIT_MASK_RXFILTER_ACTION_1 0xff 9346#define BIT_RXFILTER_ACTION_1(x) \ 9347 (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) 9348#define BIT_GET_RXFILTER_ACTION_1(x) \ 9349 (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) 9350 9351/* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ 9352 9353#define BIT_SHIFT_RXFILTER_CATEGORY_2 0 9354#define BIT_MASK_RXFILTER_CATEGORY_2 0xff 9355#define BIT_RXFILTER_CATEGORY_2(x) \ 9356 (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) 9357#define BIT_GET_RXFILTER_CATEGORY_2(x) \ 9358 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) 9359 9360/* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ 9361 9362#define BIT_SHIFT_RXFILTER_ACTION_2 0 9363#define BIT_MASK_RXFILTER_ACTION_2 0xff 9364#define BIT_RXFILTER_ACTION_2(x) \ 9365 (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) 9366#define BIT_GET_RXFILTER_ACTION_2(x) \ 9367 (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) 9368 9369/* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ 9370 9371#define BIT_SHIFT_RXFILTER_CATEGORY_3 0 9372#define BIT_MASK_RXFILTER_CATEGORY_3 0xff 9373#define BIT_RXFILTER_CATEGORY_3(x) \ 9374 (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) 9375#define BIT_GET_RXFILTER_CATEGORY_3(x) \ 9376 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) 9377 9378/* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ 9379 9380#define BIT_SHIFT_RXFILTER_ACTION_3 0 9381#define BIT_MASK_RXFILTER_ACTION_3 0xff 9382#define BIT_RXFILTER_ACTION_3(x) \ 9383 (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) 9384#define BIT_GET_RXFILTER_ACTION_3(x) \ 9385 (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) 9386 9387/* 2 REG_RXFLTMAP3 (Offset 0x0688) */ 9388 9389#define BIT_MGTFLT15EN_FW BIT(15) 9390#define BIT_MGTFLT14EN_FW BIT(14) 9391#define BIT_MGTFLT13EN_FW BIT(13) 9392#define BIT_MGTFLT12EN_FW BIT(12) 9393#define BIT_MGTFLT11EN_FW BIT(11) 9394#define BIT_MGTFLT10EN_FW BIT(10) 9395#define BIT_MGTFLT9EN_FW BIT(9) 9396#define BIT_MGTFLT8EN_FW BIT(8) 9397#define BIT_MGTFLT7EN_FW BIT(7) 9398#define BIT_MGTFLT6EN_FW BIT(6) 9399#define BIT_MGTFLT5EN_FW BIT(5) 9400#define BIT_MGTFLT4EN_FW BIT(4) 9401#define BIT_MGTFLT3EN_FW BIT(3) 9402#define BIT_MGTFLT2EN_FW BIT(2) 9403#define BIT_MGTFLT1EN_FW BIT(1) 9404#define BIT_MGTFLT0EN_FW BIT(0) 9405 9406/* 2 REG_RXFLTMAP4 (Offset 0x068A) */ 9407 9408#define BIT_CTRLFLT15EN_FW BIT(15) 9409#define BIT_CTRLFLT14EN_FW BIT(14) 9410#define BIT_CTRLFLT13EN_FW BIT(13) 9411#define BIT_CTRLFLT12EN_FW BIT(12) 9412#define BIT_CTRLFLT11EN_FW BIT(11) 9413#define BIT_CTRLFLT10EN_FW BIT(10) 9414#define BIT_CTRLFLT9EN_FW BIT(9) 9415#define BIT_CTRLFLT8EN_FW BIT(8) 9416#define BIT_CTRLFLT7EN_FW BIT(7) 9417#define BIT_CTRLFLT6EN_FW BIT(6) 9418#define BIT_CTRLFLT5EN_FW BIT(5) 9419#define BIT_CTRLFLT4EN_FW BIT(4) 9420#define BIT_CTRLFLT3EN_FW BIT(3) 9421#define BIT_CTRLFLT2EN_FW BIT(2) 9422#define BIT_CTRLFLT1EN_FW BIT(1) 9423#define BIT_CTRLFLT0EN_FW BIT(0) 9424 9425/* 2 REG_RXFLTMAP5 (Offset 0x068C) */ 9426 9427#define BIT_DATAFLT15EN_FW BIT(15) 9428#define BIT_DATAFLT14EN_FW BIT(14) 9429#define BIT_DATAFLT13EN_FW BIT(13) 9430#define BIT_DATAFLT12EN_FW BIT(12) 9431#define BIT_DATAFLT11EN_FW BIT(11) 9432#define BIT_DATAFLT10EN_FW BIT(10) 9433#define BIT_DATAFLT9EN_FW BIT(9) 9434#define BIT_DATAFLT8EN_FW BIT(8) 9435#define BIT_DATAFLT7EN_FW BIT(7) 9436#define BIT_DATAFLT6EN_FW BIT(6) 9437#define BIT_DATAFLT5EN_FW BIT(5) 9438#define BIT_DATAFLT4EN_FW BIT(4) 9439#define BIT_DATAFLT3EN_FW BIT(3) 9440#define BIT_DATAFLT2EN_FW BIT(2) 9441#define BIT_DATAFLT1EN_FW BIT(1) 9442#define BIT_DATAFLT0EN_FW BIT(0) 9443 9444/* 2 REG_RXFLTMAP6 (Offset 0x068E) */ 9445 9446#define BIT_ACTIONFLT15EN_FW BIT(15) 9447#define BIT_ACTIONFLT14EN_FW BIT(14) 9448#define BIT_ACTIONFLT13EN_FW BIT(13) 9449#define BIT_ACTIONFLT12EN_FW BIT(12) 9450#define BIT_ACTIONFLT11EN_FW BIT(11) 9451#define BIT_ACTIONFLT10EN_FW BIT(10) 9452#define BIT_ACTIONFLT9EN_FW BIT(9) 9453#define BIT_ACTIONFLT8EN_FW BIT(8) 9454#define BIT_ACTIONFLT7EN_FW BIT(7) 9455#define BIT_ACTIONFLT6EN_FW BIT(6) 9456#define BIT_ACTIONFLT5EN_FW BIT(5) 9457#define BIT_ACTIONFLT4EN_FW BIT(4) 9458#define BIT_ACTIONFLT3EN_FW BIT(3) 9459#define BIT_ACTIONFLT2EN_FW BIT(2) 9460#define BIT_ACTIONFLT1EN_FW BIT(1) 9461#define BIT_ACTIONFLT0EN_FW BIT(0) 9462 9463/* 2 REG_WOW_CTRL (Offset 0x0690) */ 9464 9465#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 9466#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 9467#define BIT_PSF_BSSIDSEL_B2B1(x) \ 9468 (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) 9469#define BIT_GET_PSF_BSSIDSEL_B2B1(x) \ 9470 (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) 9471 9472/* 2 REG_WOW_CTRL (Offset 0x0690) */ 9473 9474#define BIT_WOWHCI BIT(5) 9475 9476/* 2 REG_WOW_CTRL (Offset 0x0690) */ 9477 9478#define BIT_PSF_BSSIDSEL_B0 BIT(4) 9479 9480/* 2 REG_WOW_CTRL (Offset 0x0690) */ 9481 9482#define BIT_UWF BIT(3) 9483#define BIT_MAGIC BIT(2) 9484#define BIT_WOWEN BIT(1) 9485#define BIT_FORCE_WAKEUP BIT(0) 9486 9487/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ 9488 9489#define BIT_CHK_TSF_TA BIT(2) 9490#define BIT_CHK_TSF_CBSSID BIT(1) 9491#define BIT_CHK_TSF_EN BIT(0) 9492 9493/* 2 REG_PS_RX_INFO (Offset 0x0692) */ 9494 9495#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 9496#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 9497#define BIT_PORTSEL__PS_RX_INFO(x) \ 9498 (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) 9499#define BIT_GET_PORTSEL__PS_RX_INFO(x) \ 9500 (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) 9501 9502/* 2 REG_PS_RX_INFO (Offset 0x0692) */ 9503 9504#define BIT_RXCTRLIN0 BIT(4) 9505#define BIT_RXMGTIN0 BIT(3) 9506#define BIT_RXDATAIN2 BIT(2) 9507#define BIT_RXDATAIN1 BIT(1) 9508#define BIT_RXDATAIN0 BIT(0) 9509 9510/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ 9511 9512#define BIT_WMMPS_UAPSD_TID7 BIT(7) 9513#define BIT_WMMPS_UAPSD_TID6 BIT(6) 9514#define BIT_WMMPS_UAPSD_TID5 BIT(5) 9515#define BIT_WMMPS_UAPSD_TID4 BIT(4) 9516#define BIT_WMMPS_UAPSD_TID3 BIT(3) 9517#define BIT_WMMPS_UAPSD_TID2 BIT(2) 9518#define BIT_WMMPS_UAPSD_TID1 BIT(1) 9519#define BIT_WMMPS_UAPSD_TID0 BIT(0) 9520 9521/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ 9522 9523#define BIT_LPNAV_EN BIT(31) 9524 9525#define BIT_SHIFT_LPNAV_EARLY 16 9526#define BIT_MASK_LPNAV_EARLY 0x7fff 9527#define BIT_LPNAV_EARLY(x) \ 9528 (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) 9529#define BIT_GET_LPNAV_EARLY(x) \ 9530 (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) 9531 9532#define BIT_SHIFT_LPNAV_TH 0 9533#define BIT_MASK_LPNAV_TH 0xffff 9534#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) 9535#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) 9536 9537/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9538 9539#define BIT_WKFCAM_POLLING_V1 BIT(31) 9540#define BIT_WKFCAM_CLR_V1 BIT(30) 9541 9542/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9543 9544#define BIT_WKFCAM_WE BIT(16) 9545 9546/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9547 9548#define BIT_SHIFT_WKFCAM_ADDR_V2 8 9549#define BIT_MASK_WKFCAM_ADDR_V2 0xff 9550#define BIT_WKFCAM_ADDR_V2(x) \ 9551 (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) 9552#define BIT_GET_WKFCAM_ADDR_V2(x) \ 9553 (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) 9554 9555#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 9556#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff 9557#define BIT_WKFCAM_CAM_NUM_V1(x) \ 9558 (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) 9559#define BIT_GET_WKFCAM_CAM_NUM_V1(x) \ 9560 (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) 9561 9562/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ 9563 9564#define BIT_SHIFT_WKFMCAM_RWD 0 9565#define BIT_MASK_WKFMCAM_RWD 0xffffffffL 9566#define BIT_WKFMCAM_RWD(x) \ 9567 (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) 9568#define BIT_GET_WKFMCAM_RWD(x) \ 9569 (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) 9570 9571/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9572 9573#define BIT_MGTFLT15EN BIT(15) 9574#define BIT_MGTFLT14EN BIT(14) 9575 9576/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9577 9578#define BIT_MGTFLT13EN BIT(13) 9579#define BIT_MGTFLT12EN BIT(12) 9580#define BIT_MGTFLT11EN BIT(11) 9581#define BIT_MGTFLT10EN BIT(10) 9582#define BIT_MGTFLT9EN BIT(9) 9583#define BIT_MGTFLT8EN BIT(8) 9584 9585/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9586 9587#define BIT_MGTFLT7EN BIT(7) 9588#define BIT_MGTFLT6EN BIT(6) 9589 9590/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9591 9592#define BIT_MGTFLT5EN BIT(5) 9593#define BIT_MGTFLT4EN BIT(4) 9594#define BIT_MGTFLT3EN BIT(3) 9595#define BIT_MGTFLT2EN BIT(2) 9596#define BIT_MGTFLT1EN BIT(1) 9597#define BIT_MGTFLT0EN BIT(0) 9598 9599/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ 9600 9601#define BIT_CTRLFLT15EN BIT(15) 9602#define BIT_CTRLFLT14EN BIT(14) 9603#define BIT_CTRLFLT13EN BIT(13) 9604#define BIT_CTRLFLT12EN BIT(12) 9605#define BIT_CTRLFLT11EN BIT(11) 9606#define BIT_CTRLFLT10EN BIT(10) 9607#define BIT_CTRLFLT9EN BIT(9) 9608#define BIT_CTRLFLT8EN BIT(8) 9609#define BIT_CTRLFLT7EN BIT(7) 9610#define BIT_CTRLFLT6EN BIT(6) 9611 9612/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ 9613 9614#define BIT_CTRLFLT5EN BIT(5) 9615#define BIT_CTRLFLT4EN BIT(4) 9616#define BIT_CTRLFLT3EN BIT(3) 9617#define BIT_CTRLFLT2EN BIT(2) 9618#define BIT_CTRLFLT1EN BIT(1) 9619#define BIT_CTRLFLT0EN BIT(0) 9620 9621/* 2 REG_RXFLTMAP (Offset 0x06A4) */ 9622 9623#define BIT_DATAFLT15EN BIT(15) 9624#define BIT_DATAFLT14EN BIT(14) 9625#define BIT_DATAFLT13EN BIT(13) 9626#define BIT_DATAFLT12EN BIT(12) 9627#define BIT_DATAFLT11EN BIT(11) 9628#define BIT_DATAFLT10EN BIT(10) 9629#define BIT_DATAFLT9EN BIT(9) 9630#define BIT_DATAFLT8EN BIT(8) 9631#define BIT_DATAFLT7EN BIT(7) 9632#define BIT_DATAFLT6EN BIT(6) 9633#define BIT_DATAFLT5EN BIT(5) 9634#define BIT_DATAFLT4EN BIT(4) 9635#define BIT_DATAFLT3EN BIT(3) 9636#define BIT_DATAFLT2EN BIT(2) 9637#define BIT_DATAFLT1EN BIT(1) 9638#define BIT_DATAFLT0EN BIT(0) 9639 9640/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ 9641 9642#define BIT_SHIFT_DTIM_CNT 24 9643#define BIT_MASK_DTIM_CNT 0xff 9644#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) 9645#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) 9646 9647#define BIT_SHIFT_DTIM_PERIOD 16 9648#define BIT_MASK_DTIM_PERIOD 0xff 9649#define BIT_DTIM_PERIOD(x) \ 9650 (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) 9651#define BIT_GET_DTIM_PERIOD(x) \ 9652 (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) 9653 9654#define BIT_DTIM BIT(15) 9655#define BIT_TIM BIT(14) 9656 9657#define BIT_SHIFT_PS_AID_0 0 9658#define BIT_MASK_PS_AID_0 0x7ff 9659#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) 9660#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) 9661 9662/* 2 REG_FLC_RPC (Offset 0x06AC) */ 9663 9664#define BIT_SHIFT_FLC_RPC 0 9665#define BIT_MASK_FLC_RPC 0xff 9666#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) 9667#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) 9668 9669/* 2 REG_FLC_RPCT (Offset 0x06AD) */ 9670 9671#define BIT_SHIFT_FLC_RPCT 0 9672#define BIT_MASK_FLC_RPCT 0xff 9673#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) 9674#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) 9675 9676/* 2 REG_FLC_PTS (Offset 0x06AE) */ 9677 9678#define BIT_CMF BIT(2) 9679#define BIT_CCF BIT(1) 9680#define BIT_CDF BIT(0) 9681 9682/* 2 REG_FLC_TRPC (Offset 0x06AF) */ 9683 9684#define BIT_FLC_RPCT_V1 BIT(7) 9685#define BIT_MODE BIT(6) 9686 9687#define BIT_SHIFT_TRPCD 0 9688#define BIT_MASK_TRPCD 0x3f 9689#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) 9690#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) 9691 9692/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ 9693 9694#define BIT_SHIFT_RXBKQPKT_SEQ 20 9695#define BIT_MASK_RXBKQPKT_SEQ 0xf 9696#define BIT_RXBKQPKT_SEQ(x) \ 9697 (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) 9698#define BIT_GET_RXBKQPKT_SEQ(x) \ 9699 (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) 9700 9701#define BIT_SHIFT_RXBEQPKT_SEQ 16 9702#define BIT_MASK_RXBEQPKT_SEQ 0xf 9703#define BIT_RXBEQPKT_SEQ(x) \ 9704 (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) 9705#define BIT_GET_RXBEQPKT_SEQ(x) \ 9706 (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) 9707 9708#define BIT_SHIFT_RXVIQPKT_SEQ 12 9709#define BIT_MASK_RXVIQPKT_SEQ 0xf 9710#define BIT_RXVIQPKT_SEQ(x) \ 9711 (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) 9712#define BIT_GET_RXVIQPKT_SEQ(x) \ 9713 (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) 9714 9715#define BIT_SHIFT_RXVOQPKT_SEQ 8 9716#define BIT_MASK_RXVOQPKT_SEQ 0xf 9717#define BIT_RXVOQPKT_SEQ(x) \ 9718 (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) 9719#define BIT_GET_RXVOQPKT_SEQ(x) \ 9720 (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) 9721 9722#define BIT_RXBKQPKT_ERR BIT(7) 9723#define BIT_RXBEQPKT_ERR BIT(6) 9724#define BIT_RXVIQPKT_ERR BIT(5) 9725#define BIT_RXVOQPKT_ERR BIT(4) 9726#define BIT_RXDMA_MON_EN BIT(2) 9727#define BIT_RXPKT_MON_RST BIT(1) 9728#define BIT_RXPKT_MON_EN BIT(0) 9729 9730/* 2 REG_STATE_MON (Offset 0x06B4) */ 9731 9732#define BIT_SHIFT_STATE_SEL 24 9733#define BIT_MASK_STATE_SEL 0x1f 9734#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) 9735#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) 9736 9737#define BIT_SHIFT_STATE_INFO 8 9738#define BIT_MASK_STATE_INFO 0xff 9739#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) 9740#define BIT_GET_STATE_INFO(x) \ 9741 (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) 9742 9743#define BIT_UPD_NXT_STATE BIT(7) 9744 9745/* 2 REG_STATE_MON (Offset 0x06B4) */ 9746 9747#define BIT_SHIFT_CUR_STATE 0 9748#define BIT_MASK_CUR_STATE 0x7f 9749#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) 9750#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) 9751 9752/* 2 REG_ERROR_MON (Offset 0x06B8) */ 9753 9754#define BIT_MACRX_ERR_1 BIT(17) 9755#define BIT_MACRX_ERR_0 BIT(16) 9756#define BIT_MACTX_ERR_3 BIT(3) 9757#define BIT_MACTX_ERR_2 BIT(2) 9758#define BIT_MACTX_ERR_1 BIT(1) 9759#define BIT_MACTX_ERR_0 BIT(0) 9760 9761/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9762 9763#define BIT_EN_TXRPTBUF_CLK BIT(31) 9764 9765#define BIT_SHIFT_INFO_INDEX_OFFSET 16 9766#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff 9767#define BIT_INFO_INDEX_OFFSET(x) \ 9768 (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) 9769#define BIT_GET_INFO_INDEX_OFFSET(x) \ 9770 (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) 9771 9772/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9773 9774#define BIT_WMAC_SRCH_FIFOFULL BIT(15) 9775 9776/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9777 9778#define BIT_DIS_INFOSRCH BIT(14) 9779#define BIT_DISABLE_B0 BIT(13) 9780 9781#define BIT_SHIFT_INFO_ADDR_OFFSET 0 9782#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff 9783#define BIT_INFO_ADDR_OFFSET(x) \ 9784 (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) 9785#define BIT_GET_INFO_ADDR_OFFSET(x) \ 9786 (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) 9787 9788/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ 9789 9790#define BIT_PRI_MASK_RX_RESP BIT(126) 9791#define BIT_PRI_MASK_RXOFDM BIT(125) 9792#define BIT_PRI_MASK_RXCCK BIT(124) 9793 9794#define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH) 9795#define BIT_MASK_PRI_MASK_TXAC 0x7f 9796#define BIT_PRI_MASK_TXAC(x) \ 9797 (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC) 9798#define BIT_GET_PRI_MASK_TXAC(x) \ 9799 (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC) 9800 9801#define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH) 9802#define BIT_MASK_PRI_MASK_NAV 0xff 9803#define BIT_PRI_MASK_NAV(x) \ 9804 (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV) 9805#define BIT_GET_PRI_MASK_NAV(x) \ 9806 (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV) 9807 9808#define BIT_PRI_MASK_CCK BIT(108) 9809#define BIT_PRI_MASK_OFDM BIT(107) 9810#define BIT_PRI_MASK_RTY BIT(106) 9811 9812#define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH) 9813#define BIT_MASK_PRI_MASK_NUM 0xf 9814#define BIT_PRI_MASK_NUM(x) \ 9815 (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM) 9816#define BIT_GET_PRI_MASK_NUM(x) \ 9817 (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM) 9818 9819#define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH) 9820#define BIT_MASK_PRI_MASK_TYPE 0xf 9821#define BIT_PRI_MASK_TYPE(x) \ 9822 (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE) 9823#define BIT_GET_PRI_MASK_TYPE(x) \ 9824 (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE) 9825 9826#define BIT_OOB BIT(97) 9827#define BIT_ANT_SEL BIT(96) 9828 9829#define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH) 9830#define BIT_MASK_BREAK_TABLE_2 0xffff 9831#define BIT_BREAK_TABLE_2(x) \ 9832 (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2) 9833#define BIT_GET_BREAK_TABLE_2(x) \ 9834 (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2) 9835 9836#define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH) 9837#define BIT_MASK_BREAK_TABLE_1 0xffff 9838#define BIT_BREAK_TABLE_1(x) \ 9839 (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1) 9840#define BIT_GET_BREAK_TABLE_1(x) \ 9841 (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1) 9842 9843#define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH) 9844#define BIT_MASK_COEX_TABLE_2 0xffffffffL 9845#define BIT_COEX_TABLE_2(x) \ 9846 (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2) 9847#define BIT_GET_COEX_TABLE_2(x) \ 9848 (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2) 9849 9850#define BIT_SHIFT_COEX_TABLE_1 0 9851#define BIT_MASK_COEX_TABLE_1 0xffffffffL 9852#define BIT_COEX_TABLE_1(x) \ 9853 (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) 9854#define BIT_GET_COEX_TABLE_1(x) \ 9855 (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) 9856 9857/* 2 REG_RXCMD_0 (Offset 0x06D0) */ 9858 9859#define BIT_RXCMD_EN BIT(31) 9860 9861#define BIT_SHIFT_RXCMD_INFO 0 9862#define BIT_MASK_RXCMD_INFO 0x7fffffffL 9863#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) 9864#define BIT_GET_RXCMD_INFO(x) \ 9865 (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) 9866 9867/* 2 REG_RXCMD_1 (Offset 0x06D4) */ 9868 9869#define BIT_SHIFT_RXCMD_PRD 0 9870#define BIT_MASK_RXCMD_PRD 0xffff 9871#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) 9872#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) 9873 9874/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9875 9876#define BIT_SHIFT_WMAC_RESP_MFB 25 9877#define BIT_MASK_WMAC_RESP_MFB 0x7f 9878#define BIT_WMAC_RESP_MFB(x) \ 9879 (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) 9880#define BIT_GET_WMAC_RESP_MFB(x) \ 9881 (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) 9882 9883#define BIT_SHIFT_WMAC_ANTINF_SEL 23 9884#define BIT_MASK_WMAC_ANTINF_SEL 0x3 9885#define BIT_WMAC_ANTINF_SEL(x) \ 9886 (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) 9887#define BIT_GET_WMAC_ANTINF_SEL(x) \ 9888 (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) 9889 9890#define BIT_SHIFT_WMAC_ANTSEL_SEL 21 9891#define BIT_MASK_WMAC_ANTSEL_SEL 0x3 9892#define BIT_WMAC_ANTSEL_SEL(x) \ 9893 (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) 9894#define BIT_GET_WMAC_ANTSEL_SEL(x) \ 9895 (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) 9896 9897/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9898 9899#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 9900#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 9901#define BIT_R_WMAC_RESP_TXPOWER(x) \ 9902 (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) 9903#define BIT_GET_R_WMAC_RESP_TXPOWER(x) \ 9904 (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) 9905 9906/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9907 9908#define BIT_SHIFT_WMAC_RESP_TXANT 0 9909#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff 9910#define BIT_WMAC_RESP_TXANT(x) \ 9911 (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) 9912#define BIT_GET_WMAC_RESP_TXANT(x) \ 9913 (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) 9914 9915/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9916 9917#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) 9918 9919/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9920 9921#define BIT_WMAC_USE_NDPARATE BIT(30) 9922 9923#define BIT_SHIFT_WMAC_CSI_RATE 24 9924#define BIT_MASK_WMAC_CSI_RATE 0x3f 9925#define BIT_WMAC_CSI_RATE(x) \ 9926 (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) 9927#define BIT_GET_WMAC_CSI_RATE(x) \ 9928 (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) 9929 9930#define BIT_SHIFT_WMAC_RESP_TXRATE 16 9931#define BIT_MASK_WMAC_RESP_TXRATE 0xff 9932#define BIT_WMAC_RESP_TXRATE(x) \ 9933 (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) 9934#define BIT_GET_WMAC_RESP_TXRATE(x) \ 9935 (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) 9936 9937/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9938 9939#define BIT_BBPSF_MPDUCHKEN BIT(5) 9940 9941/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9942 9943#define BIT_BBPSF_MHCHKEN BIT(4) 9944#define BIT_BBPSF_ERRCHKEN BIT(3) 9945 9946#define BIT_SHIFT_BBPSF_ERRTHR 0 9947#define BIT_MASK_BBPSF_ERRTHR 0x7 9948#define BIT_BBPSF_ERRTHR(x) \ 9949 (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) 9950#define BIT_GET_BBPSF_ERRTHR(x) \ 9951 (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) 9952 9953/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9954 9955#define BIT_NOA_PARSER_EN BIT(15) 9956 9957/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9958 9959#define BIT_BSSID_SEL BIT(14) 9960 9961/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9962 9963#define BIT_SHIFT_P2P_OUI_TYPE 0 9964#define BIT_MASK_P2P_OUI_TYPE 0xff 9965#define BIT_P2P_OUI_TYPE(x) \ 9966 (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) 9967#define BIT_GET_P2P_OUI_TYPE(x) \ 9968 (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) 9969 9970/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ 9971 9972#define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH) 9973#define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff 9974#define BIT_R_WMAC_TXCSI_AID0(x) \ 9975 (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0) 9976#define BIT_GET_R_WMAC_TXCSI_AID0(x) \ 9977 (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0) 9978 9979#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 9980#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL 9981#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \ 9982 (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \ 9983 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) 9984#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \ 9985 (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \ 9986 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) 9987 9988/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ 9989 9990#define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH) 9991#define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff 9992#define BIT_R_WMAC_TXCSI_AID1(x) \ 9993 (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1) 9994#define BIT_GET_R_WMAC_TXCSI_AID1(x) \ 9995 (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1) 9996 9997#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 9998#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL 9999#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \ 10000 (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \
10001 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) 10002#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \ 10003 (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \ 10004 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) 10005 10006/* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */ 10007 10008#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 10009#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff 10010#define BIT_R_WMAC_BFINFO_20M_1(x) \ 10011 (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) 10012#define BIT_GET_R_WMAC_BFINFO_20M_1(x) \ 10013 (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) 10014 10015#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 10016#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff 10017#define BIT_R_WMAC_BFINFO_20M_0(x) \ 10018 (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) 10019#define BIT_GET_R_WMAC_BFINFO_20M_0(x) \ 10020 (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) 10021 10022/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ 10023 10024#define BIT_SHIFT_WMAC_RESP_ANTCD 0 10025#define BIT_MASK_WMAC_RESP_ANTCD 0xf 10026#define BIT_WMAC_RESP_ANTCD(x) \ 10027 (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) 10028#define BIT_GET_WMAC_RESP_ANTCD(x) \ 10029 (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) 10030 10031/* 2 REG_MACID1 (Offset 0x0700) */ 10032 10033#define BIT_SHIFT_MACID1 0 10034#define BIT_MASK_MACID1 0xffffffffffffL 10035#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) 10036#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) 10037 10038/* 2 REG_BSSID1 (Offset 0x0708) */ 10039 10040#define BIT_SHIFT_BSSID1 0 10041#define BIT_MASK_BSSID1 0xffffffffffffL 10042#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) 10043#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) 10044 10045/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ 10046 10047#define BIT_SHIFT_DTIM_CNT1 24 10048#define BIT_MASK_DTIM_CNT1 0xff 10049#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) 10050#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) 10051 10052#define BIT_SHIFT_DTIM_PERIOD1 16 10053#define BIT_MASK_DTIM_PERIOD1 0xff 10054#define BIT_DTIM_PERIOD1(x) \ 10055 (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) 10056#define BIT_GET_DTIM_PERIOD1(x) \ 10057 (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) 10058 10059#define BIT_DTIM1 BIT(15) 10060#define BIT_TIM1 BIT(14) 10061 10062#define BIT_SHIFT_PS_AID_1 0 10063#define BIT_MASK_PS_AID_1 0x7ff 10064#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) 10065#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) 10066 10067/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ 10068 10069#define BIT_TXUSER_ID1 BIT(25) 10070 10071#define BIT_SHIFT_AID1 16 10072#define BIT_MASK_AID1 0x1ff 10073#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) 10074#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) 10075 10076#define BIT_TXUSER_ID0 BIT(9) 10077 10078#define BIT_SHIFT_AID0 0 10079#define BIT_MASK_AID0 0x1ff 10080#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) 10081#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) 10082 10083/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10084 10085#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 10086#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff 10087#define BIT_NDP_RX_STANDBY_TIMER(x) \ 10088 (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \ 10089 << BIT_SHIFT_NDP_RX_STANDBY_TIMER) 10090#define BIT_GET_NDP_RX_STANDBY_TIMER(x) \ 10091 (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \ 10092 BIT_MASK_NDP_RX_STANDBY_TIMER) 10093 10094#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 10095#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff 10096#define BIT_CSI_RPT_OFFSET_HT(x) \ 10097 (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) 10098#define BIT_GET_CSI_RPT_OFFSET_HT(x) \ 10099 (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) 10100 10101/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10102 10103#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 10104#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff 10105#define BIT_R_WMAC_VHT_CATEGORY(x) \ 10106 (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) 10107#define BIT_GET_R_WMAC_VHT_CATEGORY(x) \ 10108 (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) 10109 10110/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10111 10112#define BIT_R_WMAC_USE_NSTS BIT(7) 10113#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) 10114#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) 10115#define BIT_R_WMAC_BFPARAM_SEL BIT(4) 10116#define BIT_R_WMAC_CSISEQ_SEL BIT(3) 10117#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) 10118#define BIT_R_WMAC_HT_NDPA_EN BIT(1) 10119#define BIT_R_WMAC_VHT_NDPA_EN BIT(0) 10120 10121/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ 10122 10123#define BIT_R_WMAC_NSARP_RSPEN BIT(15) 10124#define BIT_R_WMAC_NSARP_RARP BIT(9) 10125#define BIT_R_WMAC_NSARP_RIPV6 BIT(8) 10126 10127#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 10128#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 10129#define BIT_R_WMAC_NSARP_MODEN(x) \ 10130 (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) 10131#define BIT_GET_R_WMAC_NSARP_MODEN(x) \ 10132 (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) 10133 10134#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 10135#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 10136#define BIT_R_WMAC_NSARP_RSPFTP(x) \ 10137 (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) 10138#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \ 10139 (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) 10140 10141#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 10142#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf 10143#define BIT_R_WMAC_NSARP_RSPSEC(x) \ 10144 (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) 10145#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \ 10146 (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) 10147 10148/* 2 REG_NS_ARP_INFO (Offset 0x0724) */ 10149 10150#define BIT_REQ_IS_MCNS BIT(23) 10151#define BIT_REQ_IS_UCNS BIT(22) 10152#define BIT_REQ_IS_USNS BIT(21) 10153#define BIT_REQ_IS_ARP BIT(20) 10154#define BIT_EXPRSP_MH_WITHQC BIT(19) 10155 10156#define BIT_SHIFT_EXPRSP_SECTYPE 16 10157#define BIT_MASK_EXPRSP_SECTYPE 0x7 10158#define BIT_EXPRSP_SECTYPE(x) \ 10159 (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) 10160#define BIT_GET_EXPRSP_SECTYPE(x) \ 10161 (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) 10162 10163#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 10164#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff 10165#define BIT_EXPRSP_CHKSM_7_TO_0(x) \ 10166 (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) 10167#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \ 10168 (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) 10169 10170#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 10171#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff 10172#define BIT_EXPRSP_CHKSM_15_TO_8(x) \ 10173 (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \ 10174 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) 10175#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \ 10176 (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \ 10177 BIT_MASK_EXPRSP_CHKSM_15_TO_8) 10178 10179/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ 10180 10181#define BIT_SHIFT_WMAC_ARPIP 0 10182#define BIT_MASK_WMAC_ARPIP 0xffffffffL 10183#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) 10184#define BIT_GET_WMAC_ARPIP(x) \ 10185 (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) 10186 10187/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ 10188 10189#define BIT_SHIFT_BEAMFORMING_INFO 0 10190#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL 10191#define BIT_BEAMFORMING_INFO(x) \ 10192 (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) 10193#define BIT_GET_BEAMFORMING_INFO(x) \ 10194 (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) 10195 10196/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ 10197 10198#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 10199#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf 10200#define BIT_R_WMAC_CTX_SUBTYPE(x) \ 10201 (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) 10202#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \ 10203 (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) 10204 10205#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 10206#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf 10207#define BIT_R_WMAC_RTX_SUBTYPE(x) \ 10208 (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) 10209#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \ 10210 (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) 10211 10212/* 2 REG_BT_COEX_V2 (Offset 0x0762) */ 10213 10214#define BIT_GNT_BT_POLARITY BIT(12) 10215#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) 10216 10217#define BIT_SHIFT_TIMER 0 10218#define BIT_MASK_TIMER 0xff 10219#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) 10220#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) 10221 10222/* 2 REG_BT_COEX (Offset 0x0764) */ 10223 10224#define BIT_R_GNT_BT_RFC_SW BIT(12) 10225#define BIT_R_GNT_BT_RFC_SW_EN BIT(11) 10226#define BIT_R_GNT_BT_BB_SW BIT(10) 10227#define BIT_R_GNT_BT_BB_SW_EN BIT(9) 10228#define BIT_R_BT_CNT_THREN BIT(8) 10229 10230#define BIT_SHIFT_R_BT_CNT_THR 0 10231#define BIT_MASK_R_BT_CNT_THR 0xff 10232#define BIT_R_BT_CNT_THR(x) \ 10233 (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) 10234#define BIT_GET_R_BT_CNT_THR(x) \ 10235 (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) 10236 10237/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10238 10239#define BIT_WLRX_TER_BY_CTL BIT(43) 10240#define BIT_WLRX_TER_BY_AD BIT(42) 10241#define BIT_ANT_DIVERSITY_SEL BIT(41) 10242#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) 10243#define BIT_WLACT_LOW_GNTWL_EN BIT(34) 10244#define BIT_WLACT_HIGH_GNTBT_EN BIT(33) 10245 10246/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10247 10248#define BIT_NAV_UPPER_V1 BIT(32) 10249 10250/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10251 10252#define BIT_SHIFT_RXMYRTS_NAV_V1 8 10253#define BIT_MASK_RXMYRTS_NAV_V1 0xff 10254#define BIT_RXMYRTS_NAV_V1(x) \ 10255 (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) 10256#define BIT_GET_RXMYRTS_NAV_V1(x) \ 10257 (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) 10258 10259#define BIT_SHIFT_RTSRST_V1 0 10260#define BIT_MASK_RTSRST_V1 0xff 10261#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) 10262#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) 10263 10264/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ 10265 10266#define BIT_SHIFT_BT_STAT_DELAY 12 10267#define BIT_MASK_BT_STAT_DELAY 0xf 10268#define BIT_BT_STAT_DELAY(x) \ 10269 (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) 10270#define BIT_GET_BT_STAT_DELAY(x) \ 10271 (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) 10272 10273#define BIT_SHIFT_BT_TRX_INIT_DETECT 8 10274#define BIT_MASK_BT_TRX_INIT_DETECT 0xf 10275#define BIT_BT_TRX_INIT_DETECT(x) \ 10276 (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) 10277#define BIT_GET_BT_TRX_INIT_DETECT(x) \ 10278 (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) 10279 10280#define BIT_SHIFT_BT_PRI_DETECT_TO 4 10281#define BIT_MASK_BT_PRI_DETECT_TO 0xf 10282#define BIT_BT_PRI_DETECT_TO(x) \ 10283 (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) 10284#define BIT_GET_BT_PRI_DETECT_TO(x) \ 10285 (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) 10286 10287#define BIT_R_GRANTALL_WLMASK BIT(3) 10288#define BIT_STATIS_BT_EN BIT(2) 10289#define BIT_WL_ACT_MASK_ENABLE BIT(1) 10290#define BIT_ENHANCED_BT BIT(0) 10291 10292/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ 10293 10294#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) 10295#define BIT_MASK_STATIS_BT_LO_RX 0xffff 10296#define BIT_STATIS_BT_LO_RX(x) \ 10297 (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) 10298#define BIT_GET_STATIS_BT_LO_RX(x) \ 10299 (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) 10300 10301#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) 10302#define BIT_MASK_STATIS_BT_LO_TX 0xffff 10303#define BIT_STATIS_BT_LO_TX(x) \ 10304 (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) 10305#define BIT_GET_STATIS_BT_LO_TX(x) \ 10306 (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) 10307 10308/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ 10309 10310#define BIT_SHIFT_STATIS_BT_HI_RX 16 10311#define BIT_MASK_STATIS_BT_HI_RX 0xffff 10312#define BIT_STATIS_BT_HI_RX(x) \ 10313 (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) 10314#define BIT_GET_STATIS_BT_HI_RX(x) \ 10315 (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) 10316 10317#define BIT_SHIFT_STATIS_BT_HI_TX 0 10318#define BIT_MASK_STATIS_BT_HI_TX 0xffff 10319#define BIT_STATIS_BT_HI_TX(x) \ 10320 (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) 10321#define BIT_GET_STATIS_BT_HI_TX(x) \ 10322 (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) 10323 10324/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ 10325 10326#define BIT_SHIFT_R_BT_CMD_RPT 16 10327#define BIT_MASK_R_BT_CMD_RPT 0xffff 10328#define BIT_R_BT_CMD_RPT(x) \ 10329 (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) 10330#define BIT_GET_R_BT_CMD_RPT(x) \ 10331 (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) 10332 10333#define BIT_SHIFT_R_RPT_FROM_BT 8 10334#define BIT_MASK_R_RPT_FROM_BT 0xff 10335#define BIT_R_RPT_FROM_BT(x) \ 10336 (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) 10337#define BIT_GET_R_RPT_FROM_BT(x) \ 10338 (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) 10339 10340#define BIT_SHIFT_BT_HID_ISR_SET 6 10341#define BIT_MASK_BT_HID_ISR_SET 0x3 10342#define BIT_BT_HID_ISR_SET(x) \ 10343 (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) 10344#define BIT_GET_BT_HID_ISR_SET(x) \ 10345 (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) 10346 10347#define BIT_TDMA_BT_START_NOTIFY BIT(5) 10348#define BIT_ENABLE_TDMA_FW_MODE BIT(4) 10349#define BIT_ENABLE_PTA_TDMA_MODE BIT(3) 10350#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) 10351#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) 10352#define BIT_RTK_BT_ENABLE BIT(0) 10353 10354/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ 10355 10356#define BIT_SHIFT_BT_PROFILE 24 10357#define BIT_MASK_BT_PROFILE 0xff 10358#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) 10359#define BIT_GET_BT_PROFILE(x) \ 10360 (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) 10361 10362#define BIT_SHIFT_BT_POWER 16 10363#define BIT_MASK_BT_POWER 0xff 10364#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) 10365#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) 10366 10367#define BIT_SHIFT_BT_PREDECT_STATUS 8 10368#define BIT_MASK_BT_PREDECT_STATUS 0xff 10369#define BIT_BT_PREDECT_STATUS(x) \ 10370 (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) 10371#define BIT_GET_BT_PREDECT_STATUS(x) \ 10372 (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) 10373 10374#define BIT_SHIFT_BT_CMD_INFO 0 10375#define BIT_MASK_BT_CMD_INFO 0xff 10376#define BIT_BT_CMD_INFO(x) \ 10377 (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) 10378#define BIT_GET_BT_CMD_INFO(x) \ 10379 (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) 10380 10381/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ 10382 10383#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) 10384#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) 10385#define BIT_EN_BT_STSTUS_RPT BIT(29) 10386#define BIT_EN_BT_POWER BIT(28) 10387#define BIT_EN_BT_CHANNEL BIT(27) 10388#define BIT_EN_BT_SLOT_CHANGE BIT(26) 10389#define BIT_EN_BT_PROFILE_OR_HID BIT(25) 10390#define BIT_WLAN_RPT_NOTIFY BIT(24) 10391 10392#define BIT_SHIFT_WLAN_RPT_DATA 16 10393#define BIT_MASK_WLAN_RPT_DATA 0xff 10394#define BIT_WLAN_RPT_DATA(x) \ 10395 (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) 10396#define BIT_GET_WLAN_RPT_DATA(x) \ 10397 (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) 10398 10399#define BIT_SHIFT_CMD_ID 8 10400#define BIT_MASK_CMD_ID 0xff 10401#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) 10402#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) 10403 10404#define BIT_SHIFT_BT_DATA 0 10405#define BIT_MASK_BT_DATA 0xff 10406#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) 10407#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) 10408 10409/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ 10410 10411#define BIT_SHIFT_WLAN_RPT_TO 0 10412#define BIT_MASK_WLAN_RPT_TO 0xff 10413#define BIT_WLAN_RPT_TO(x) \ 10414 (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) 10415#define BIT_GET_WLAN_RPT_TO(x) \ 10416 (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) 10417 10418/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ 10419 10420#define BIT_SHIFT_ISOLATION_CHK 1 10421#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL 10422#define BIT_ISOLATION_CHK(x) \ 10423 (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) 10424#define BIT_GET_ISOLATION_CHK(x) \ 10425 (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) 10426 10427/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ 10428 10429#define BIT_ISOLATION_EN BIT(0) 10430 10431/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ 10432 10433#define BIT_BT_HID_ISR BIT(7) 10434#define BIT_BT_QUERY_ISR BIT(6) 10435#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) 10436#define BIT_WLAN_RPT_ISR BIT(4) 10437#define BIT_BT_POWER_ISR BIT(3) 10438#define BIT_BT_CHANNEL_ISR BIT(2) 10439#define BIT_BT_SLOT_CHANGE_ISR BIT(1) 10440#define BIT_BT_PROFILE_ISR BIT(0) 10441 10442/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ 10443 10444#define BIT_SHIFT_BT_TIME 6 10445#define BIT_MASK_BT_TIME 0x3ffffff 10446#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) 10447#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) 10448 10449#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 10450#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f 10451#define BIT_BT_RPT_SAMPLE_RATE(x) \ 10452 (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) 10453#define BIT_GET_BT_RPT_SAMPLE_RATE(x) \ 10454 (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) 10455 10456/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ 10457 10458#define BIT_SHIFT_BT_EISR_EN 16 10459#define BIT_MASK_BT_EISR_EN 0xff 10460#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) 10461#define BIT_GET_BT_EISR_EN(x) \ 10462 (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) 10463 10464#define BIT_BT_ACT_FALLING_ISR BIT(10) 10465#define BIT_BT_ACT_RISING_ISR BIT(9) 10466#define BIT_TDMA_TO_ISR BIT(8) 10467 10468#define BIT_SHIFT_BT_CH 0 10469#define BIT_MASK_BT_CH 0xff 10470#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) 10471#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) 10472 10473/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ 10474 10475#define BIT_OBFF_EN_V1 BIT(31) 10476 10477#define BIT_SHIFT_OBFF_STATE_V1 28 10478#define BIT_MASK_OBFF_STATE_V1 0x3 10479#define BIT_OBFF_STATE_V1(x) \ 10480 (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) 10481#define BIT_GET_OBFF_STATE_V1(x) \ 10482 (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) 10483 10484#define BIT_OBFF_ACT_RXDMA_EN BIT(27) 10485#define BIT_OBFF_BLOCK_INT_EN BIT(26) 10486#define BIT_OBFF_AUTOACT_EN BIT(25) 10487#define BIT_OBFF_AUTOIDLE_EN BIT(24) 10488 10489#define BIT_SHIFT_WAKE_MAX_PLS 20 10490#define BIT_MASK_WAKE_MAX_PLS 0x7 10491#define BIT_WAKE_MAX_PLS(x) \ 10492 (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) 10493#define BIT_GET_WAKE_MAX_PLS(x) \ 10494 (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) 10495 10496#define BIT_SHIFT_WAKE_MIN_PLS 16 10497#define BIT_MASK_WAKE_MIN_PLS 0x7 10498#define BIT_WAKE_MIN_PLS(x) \ 10499 (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) 10500#define BIT_GET_WAKE_MIN_PLS(x) \ 10501 (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) 10502 10503#define BIT_SHIFT_WAKE_MAX_F2F 12 10504#define BIT_MASK_WAKE_MAX_F2F 0x7 10505#define BIT_WAKE_MAX_F2F(x) \ 10506 (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) 10507#define BIT_GET_WAKE_MAX_F2F(x) \ 10508 (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) 10509 10510#define BIT_SHIFT_WAKE_MIN_F2F 8 10511#define BIT_MASK_WAKE_MIN_F2F 0x7 10512#define BIT_WAKE_MIN_F2F(x) \ 10513 (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) 10514#define BIT_GET_WAKE_MIN_F2F(x) \ 10515 (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) 10516 10517#define BIT_APP_CPU_ACT_V1 BIT(3) 10518#define BIT_APP_OBFF_V1 BIT(2) 10519#define BIT_APP_IDLE_V1 BIT(1) 10520#define BIT_APP_INIT_V1 BIT(0) 10521 10522/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ 10523 10524#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 10525#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 10526#define BIT_RX_HIGH_TIMER_IDX(x) \ 10527 (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) 10528#define BIT_GET_RX_HIGH_TIMER_IDX(x) \ 10529 (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) 10530 10531#define BIT_SHIFT_RX_MED_TIMER_IDX 16 10532#define BIT_MASK_RX_MED_TIMER_IDX 0x7 10533#define BIT_RX_MED_TIMER_IDX(x) \ 10534 (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) 10535#define BIT_GET_RX_MED_TIMER_IDX(x) \ 10536 (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) 10537 10538#define BIT_SHIFT_RX_LOW_TIMER_IDX 8 10539#define BIT_MASK_RX_LOW_TIMER_IDX 0x7 10540#define BIT_RX_LOW_TIMER_IDX(x) \ 10541 (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) 10542#define BIT_GET_RX_LOW_TIMER_IDX(x) \ 10543 (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) 10544 10545#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 10546#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 10547#define BIT_OBFF_INT_TIMER_IDX(x) \ 10548 (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) 10549#define BIT_GET_OBFF_INT_TIMER_IDX(x) \ 10550 (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) 10551 10552/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ 10553 10554#define BIT_LTR_EN_V1 BIT(31) 10555#define BIT_LTR_HW_EN_V1 BIT(30) 10556#define BIT_LRT_ACT_CTS_EN BIT(29) 10557#define BIT_LTR_ACT_RXPKT_EN BIT(28) 10558#define BIT_LTR_ACT_RXDMA_EN BIT(27) 10559#define BIT_LTR_IDLE_NO_SNOOP BIT(26) 10560#define BIT_SPDUP_MGTPKT BIT(25) 10561#define BIT_RX_AGG_EN BIT(24) 10562#define BIT_APP_LTR_ACT BIT(23) 10563#define BIT_APP_LTR_IDLE BIT(22) 10564 10565#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 10566#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 10567#define BIT_HIGH_RATE_TRIG_SEL(x) \ 10568 (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) 10569#define BIT_GET_HIGH_RATE_TRIG_SEL(x) \ 10570 (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) 10571 10572#define BIT_SHIFT_MED_RATE_TRIG_SEL 18 10573#define BIT_MASK_MED_RATE_TRIG_SEL 0x3 10574#define BIT_MED_RATE_TRIG_SEL(x) \ 10575 (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) 10576#define BIT_GET_MED_RATE_TRIG_SEL(x) \ 10577 (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) 10578 10579#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 10580#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 10581#define BIT_LOW_RATE_TRIG_SEL(x) \ 10582 (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) 10583#define BIT_GET_LOW_RATE_TRIG_SEL(x) \ 10584 (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) 10585 10586#define BIT_SHIFT_HIGH_RATE_BD_IDX 8 10587#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f 10588#define BIT_HIGH_RATE_BD_IDX(x) \ 10589 (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) 10590#define BIT_GET_HIGH_RATE_BD_IDX(x) \ 10591 (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) 10592 10593#define BIT_SHIFT_LOW_RATE_BD_IDX 0 10594#define BIT_MASK_LOW_RATE_BD_IDX 0x7f 10595#define BIT_LOW_RATE_BD_IDX(x) \ 10596 (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) 10597#define BIT_GET_LOW_RATE_BD_IDX(x) \ 10598 (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) 10599 10600/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ 10601 10602#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 10603#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 10604#define BIT_RX_EMPTY_TIMER_IDX(x) \ 10605 (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) 10606#define BIT_GET_RX_EMPTY_TIMER_IDX(x) \ 10607 (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) 10608 10609#define BIT_SHIFT_RX_AFULL_TH_IDX 20 10610#define BIT_MASK_RX_AFULL_TH_IDX 0x7 10611#define BIT_RX_AFULL_TH_IDX(x) \ 10612 (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) 10613#define BIT_GET_RX_AFULL_TH_IDX(x) \ 10614 (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) 10615 10616#define BIT_SHIFT_RX_HIGH_TH_IDX 16 10617#define BIT_MASK_RX_HIGH_TH_IDX 0x7 10618#define BIT_RX_HIGH_TH_IDX(x) \ 10619 (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) 10620#define BIT_GET_RX_HIGH_TH_IDX(x) \ 10621 (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) 10622 10623#define BIT_SHIFT_RX_MED_TH_IDX 12 10624#define BIT_MASK_RX_MED_TH_IDX 0x7 10625#define BIT_RX_MED_TH_IDX(x) \ 10626 (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) 10627#define BIT_GET_RX_MED_TH_IDX(x) \ 10628 (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) 10629 10630#define BIT_SHIFT_RX_LOW_TH_IDX 8 10631#define BIT_MASK_RX_LOW_TH_IDX 0x7 10632#define BIT_RX_LOW_TH_IDX(x) \ 10633 (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) 10634#define BIT_GET_RX_LOW_TH_IDX(x) \ 10635 (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) 10636 10637#define BIT_SHIFT_LTR_SPACE_IDX 4 10638#define BIT_MASK_LTR_SPACE_IDX 0x3 10639#define BIT_LTR_SPACE_IDX(x) \ 10640 (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) 10641#define BIT_GET_LTR_SPACE_IDX(x) \ 10642 (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) 10643 10644#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 10645#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 10646#define BIT_LTR_IDLE_TIMER_IDX(x) \ 10647 (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) 10648#define BIT_GET_LTR_IDLE_TIMER_IDX(x) \ 10649 (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) 10650 10651/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ 10652 10653#define BIT_SHIFT_LTR_IDLE_L 0 10654#define BIT_MASK_LTR_IDLE_L 0xffffffffL 10655#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) 10656#define BIT_GET_LTR_IDLE_L(x) \ 10657 (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) 10658 10659/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ 10660 10661#define BIT_SHIFT_LTR_ACT_L 0 10662#define BIT_MASK_LTR_ACT_L 0xffffffffL 10663#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) 10664#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) 10665 10666/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ 10667 10668#define BIT_APPEND_MACID_IN_RESP_EN BIT(50) 10669#define BIT_ADDR2_MATCH_EN BIT(49) 10670#define BIT_ANTTRN_EN BIT(48) 10671 10672#define BIT_SHIFT_TRAIN_STA_ADDR 0 10673#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL 10674#define BIT_TRAIN_STA_ADDR(x) \ 10675 (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) 10676#define BIT_GET_TRAIN_STA_ADDR(x) \ 10677 (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) 10678 10679/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ 10680 10681#define BIT_SHIFT_PKTCNT_BSSIDMAP 4 10682#define BIT_MASK_PKTCNT_BSSIDMAP 0xf 10683#define BIT_PKTCNT_BSSIDMAP(x) \ 10684 (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) 10685#define BIT_GET_PKTCNT_BSSIDMAP(x) \ 10686 (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) 10687 10688#define BIT_PKTCNT_CNTRST BIT(1) 10689#define BIT_PKTCNT_CNTEN BIT(0) 10690 10691/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ 10692 10693#define BIT_WMAC_PKTCNT_TRST BIT(9) 10694#define BIT_WMAC_PKTCNT_FEN BIT(8) 10695 10696#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 10697#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff 10698#define BIT_WMAC_PKTCNT_CFGAD(x) \ 10699 (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) 10700#define BIT_GET_WMAC_PKTCNT_CFGAD(x) \ 10701 (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) 10702 10703/* 2 REG_IQ_DUMP (Offset 0x07C0) */ 10704 10705#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) 10706#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL 10707#define BIT_R_WMAC_MATCH_REF_MAC(x) \ 10708 (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \ 10709 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) 10710#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \ 10711 (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \ 10712 BIT_MASK_R_WMAC_MATCH_REF_MAC) 10713 10714#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) 10715#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff 10716#define BIT_R_WMAC_RX_FIL_LEN(x) \ 10717 (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) 10718#define BIT_GET_R_WMAC_RX_FIL_LEN(x) \ 10719 (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) 10720 10721#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) 10722#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff 10723#define BIT_R_WMAC_RXFIFO_FULL_TH(x) \ 10724 (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \ 10725 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) 10726#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \ 10727 (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \ 10728 BIT_MASK_R_WMAC_RXFIFO_FULL_TH) 10729 10730#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) 10731#define BIT_R_WMAC_NDP_RST BIT(50) 10732#define BIT_R_WMAC_POWINT_EN BIT(49) 10733#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) 10734#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) 10735#define BIT_R_WMAC_PFIN_TOEN BIT(46) 10736#define BIT_R_WMAC_FIL_SECERR BIT(45) 10737#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) 10738#define BIT_R_WMAC_FIL_FCTYPE BIT(43) 10739#define BIT_R_WMAC_FIL_FCPROVER BIT(42) 10740#define BIT_R_WMAC_PHYSTS_SNIF BIT(41) 10741#define BIT_R_WMAC_PHYSTS_PLCP BIT(40) 10742#define BIT_R_MAC_TCR_VBONF_RD BIT(39) 10743#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) 10744#define BIT_R_WMAC_NDP_FILTER BIT(37) 10745#define BIT_R_WMAC_RXLEN_SEL BIT(36) 10746#define BIT_R_WMAC_RXLEN_SEL1 BIT(35) 10747#define BIT_R_OFDM_FILTER BIT(34) 10748#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) 10749 10750#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) 10751#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL 10752#define BIT_R_WMAC_MASK_LA_MAC(x) \ 10753 (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) 10754#define BIT_GET_R_WMAC_MASK_LA_MAC(x) \ 10755 (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) 10756 10757#define BIT_R_WMAC_CHK_CCK_LEN BIT(32) 10758 10759/* 2 REG_IQ_DUMP (Offset 0x07C0) */ 10760 10761#define BIT_SHIFT_R_OFDM_LEN 26 10762#define BIT_MASK_R_OFDM_LEN 0x3f 10763#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) 10764#define BIT_GET_R_OFDM_LEN(x) \ 10765 (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) 10766 10767#define BIT_SHIFT_DUMP_OK_ADDR 15 10768#define BIT_MASK_DUMP_OK_ADDR 0x1ffff 10769#define BIT_DUMP_OK_ADDR(x) \ 10770 (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) 10771#define BIT_GET_DUMP_OK_ADDR(x) \ 10772 (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) 10773 10774#define BIT_SHIFT_R_TRIG_TIME_SEL 8 10775#define BIT_MASK_R_TRIG_TIME_SEL 0x7f 10776#define BIT_R_TRIG_TIME_SEL(x) \ 10777 (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) 10778#define BIT_GET_R_TRIG_TIME_SEL(x) \ 10779 (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) 10780 10781#define BIT_SHIFT_R_MAC_TRIG_SEL 6 10782#define BIT_MASK_R_MAC_TRIG_SEL 0x3 10783#define BIT_R_MAC_TRIG_SEL(x) \ 10784 (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) 10785#define BIT_GET_R_MAC_TRIG_SEL(x) \ 10786 (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) 10787 10788#define BIT_MAC_TRIG_REG BIT(5) 10789 10790#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 10791#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 10792#define BIT_R_LEVEL_PULSE_SEL(x) \ 10793 (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) 10794#define BIT_GET_R_LEVEL_PULSE_SEL(x) \ 10795 (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) 10796 10797#define BIT_EN_LA_MAC BIT(2) 10798#define BIT_R_EN_IQDUMP BIT(1) 10799#define BIT_R_IQDATA_DUMP BIT(0) 10800 10801#define BIT_SHIFT_R_CCK_LEN 0 10802#define BIT_MASK_R_CCK_LEN 0xffff 10803#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) 10804#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) 10805 10806/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ 10807 10808#define BIT_RXFTM_TXACK_SC BIT(6) 10809#define BIT_RXFTM_TXACK_BW BIT(5) 10810#define BIT_RXFTM_EN BIT(3) 10811#define BIT_RXFTMREQ_BYDRV BIT(2) 10812#define BIT_RXFTMREQ_EN BIT(1) 10813#define BIT_FTM_EN BIT(0) 10814 10815/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10816 10817#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) 10818 10819/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10820 10821#define BIT_R_WMAC_MHRDDY_CLR BIT(13) 10822 10823/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10824 10825#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) 10826 10827/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10828 10829#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) 10830 10831/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10832 10833#define BIT_R_CHK_DELIMIT_LEN BIT(10) 10834#define BIT_R_REAPTER_ADDR_MATCH BIT(9) 10835#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) 10836#define BIT_R_LATCH_MACHRDY BIT(7) 10837#define BIT_R_WMAC_RXFIL_REND BIT(6) 10838#define BIT_R_WMAC_MPDURDY_CLR BIT(5) 10839#define BIT_R_WMAC_CLRRXSEC BIT(4) 10840#define BIT_R_WMAC_RXFIL_RDEL BIT(3) 10841#define BIT_R_WMAC_RXFIL_FCSE BIT(2) 10842#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) 10843#define BIT_R_WMAC_RXFIL_MASKM BIT(0) 10844 10845/* 2 REG_NDP_SIG (Offset 0x07E0) */ 10846 10847#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 10848#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff 10849#define BIT_R_WMAC_TXNDP_SIGB(x) \ 10850 (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) 10851#define BIT_GET_R_WMAC_TXNDP_SIGB(x) \ 10852 (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) 10853 10854/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ 10855 10856#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) 10857#define BIT_MASK_R_MAC_DEBUG 0xffffffffL 10858#define BIT_R_MAC_DEBUG(x) \ 10859 (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) 10860#define BIT_GET_R_MAC_DEBUG(x) \ 10861 (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) 10862 10863/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ 10864 10865#define BIT_SHIFT_R_MAC_DBG_SHIFT 8 10866#define BIT_MASK_R_MAC_DBG_SHIFT 0x7 10867#define BIT_R_MAC_DBG_SHIFT(x) \ 10868 (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) 10869#define BIT_GET_R_MAC_DBG_SHIFT(x) \ 10870 (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) 10871 10872#define BIT_SHIFT_R_MAC_DBG_SEL 0 10873#define BIT_MASK_R_MAC_DBG_SEL 0x3 10874#define BIT_R_MAC_DBG_SEL(x) \ 10875 (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) 10876#define BIT_GET_R_MAC_DBG_SEL(x) \ 10877 (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) 10878 10879/* 2 REG_SYS_CFG3 (Offset 0x1000) */ 10880 10881#define BIT_PWC_MA33V BIT(15) 10882 10883/* 2 REG_SYS_CFG3 (Offset 0x1000) */ 10884 10885#define BIT_PWC_MA12V BIT(14) 10886#define BIT_PWC_MD12V BIT(13) 10887#define BIT_PWC_PD12V BIT(12) 10888#define BIT_PWC_UD12V BIT(11) 10889#define BIT_ISO_MA2MD BIT(1) 10890 10891/* 2 REG_SYS_CFG5 (Offset 0x1070) */ 10892 10893#define BIT_LPS_STATUS BIT(3) 10894#define BIT_HCI_TXDMA_BUSY BIT(2) 10895#define BIT_HCI_TXDMA_ALLOW BIT(1) 10896#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) 10897 10898/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10899 10900#define BIT_WDT_OPT_IOWRAPPER BIT(19) 10901 10902/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10903 10904#define BIT_ANA_PORT_IDLE BIT(18) 10905#define BIT_MAC_PORT_IDLE BIT(17) 10906#define BIT_WL_PLATFORM_RST BIT(16) 10907#define BIT_WL_SECURITY_CLK BIT(15) 10908 10909/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10910 10911#define BIT_SHIFT_CPU_DMEM_CON 0 10912#define BIT_MASK_CPU_DMEM_CON 0xff 10913#define BIT_CPU_DMEM_CON(x) \ 10914 (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) 10915#define BIT_GET_CPU_DMEM_CON(x) \ 10916 (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) 10917 10918/* 2 REG_BOOT_REASON (Offset 0x1088) */ 10919 10920#define BIT_SHIFT_BOOT_REASON 0 10921#define BIT_MASK_BOOT_REASON 0x7 10922#define BIT_BOOT_REASON(x) \ 10923 (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON) 10924#define BIT_GET_BOOT_REASON(x) \ 10925 (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON) 10926 10927/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ 10928 10929#define BIT_PAD_SHUTDW BIT(18) 10930#define BIT_SYSON_NFC_PAD BIT(17) 10931#define BIT_NFC_INT_PAD_CTRL BIT(16) 10932#define BIT_NFC_RFDIS_PAD_CTRL BIT(15) 10933#define BIT_NFC_CLK_PAD_CTRL BIT(14) 10934#define BIT_NFC_DATA_PAD_CTRL BIT(13) 10935#define BIT_NFC_PAD_PULL_CTRL BIT(12) 10936 10937#define BIT_SHIFT_NFCPAD_IO_SEL 8 10938#define BIT_MASK_NFCPAD_IO_SEL 0xf 10939#define BIT_NFCPAD_IO_SEL(x) \ 10940 (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) 10941#define BIT_GET_NFCPAD_IO_SEL(x) \ 10942 (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) 10943 10944#define BIT_SHIFT_NFCPAD_OUT 4 10945#define BIT_MASK_NFCPAD_OUT 0xf 10946#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) 10947#define BIT_GET_NFCPAD_OUT(x) \ 10948 (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) 10949 10950#define BIT_SHIFT_NFCPAD_IN 0 10951#define BIT_MASK_NFCPAD_IN 0xf 10952#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) 10953#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) 10954 10955/* 2 REG_HIMR2 (Offset 0x10B0) */ 10956 10957#define BIT_BCNDMAINT_P4_MSK BIT(31) 10958#define BIT_BCNDMAINT_P3_MSK BIT(30) 10959#define BIT_BCNDMAINT_P2_MSK BIT(29) 10960#define BIT_BCNDMAINT_P1_MSK BIT(28) 10961#define BIT_ATIMEND7_MSK BIT(22) 10962#define BIT_ATIMEND6_MSK BIT(21) 10963#define BIT_ATIMEND5_MSK BIT(20) 10964#define BIT_ATIMEND4_MSK BIT(19) 10965#define BIT_ATIMEND3_MSK BIT(18) 10966#define BIT_ATIMEND2_MSK BIT(17) 10967#define BIT_ATIMEND1_MSK BIT(16) 10968#define BIT_TXBCN7OK_MSK BIT(14) 10969#define BIT_TXBCN6OK_MSK BIT(13) 10970#define BIT_TXBCN5OK_MSK BIT(12) 10971#define BIT_TXBCN4OK_MSK BIT(11) 10972#define BIT_TXBCN3OK_MSK BIT(10) 10973#define BIT_TXBCN2OK_MSK BIT(9) 10974#define BIT_TXBCN1OK_MSK_V1 BIT(8) 10975#define BIT_TXBCN7ERR_MSK BIT(6) 10976#define BIT_TXBCN6ERR_MSK BIT(5) 10977#define BIT_TXBCN5ERR_MSK BIT(4) 10978#define BIT_TXBCN4ERR_MSK BIT(3) 10979#define BIT_TXBCN3ERR_MSK BIT(2) 10980#define BIT_TXBCN2ERR_MSK BIT(1) 10981#define BIT_TXBCN1ERR_MSK_V1 BIT(0) 10982 10983/* 2 REG_HISR2 (Offset 0x10B4) */ 10984 10985#define BIT_BCNDMAINT_P4 BIT(31) 10986#define BIT_BCNDMAINT_P3 BIT(30) 10987#define BIT_BCNDMAINT_P2 BIT(29) 10988#define BIT_BCNDMAINT_P1 BIT(28) 10989#define BIT_ATIMEND7 BIT(22) 10990#define BIT_ATIMEND6 BIT(21) 10991#define BIT_ATIMEND5 BIT(20) 10992#define BIT_ATIMEND4 BIT(19) 10993#define BIT_ATIMEND3 BIT(18) 10994#define BIT_ATIMEND2 BIT(17) 10995#define BIT_ATIMEND1 BIT(16) 10996#define BIT_TXBCN7OK BIT(14) 10997#define BIT_TXBCN6OK BIT(13) 10998#define BIT_TXBCN5OK BIT(12) 10999#define BIT_TXBCN4OK BIT(11) 11000#define BIT_TXBCN3OK BIT(10)
11001#define BIT_TXBCN2OK BIT(9) 11002#define BIT_TXBCN1OK BIT(8) 11003#define BIT_TXBCN7ERR BIT(6) 11004#define BIT_TXBCN6ERR BIT(5) 11005#define BIT_TXBCN5ERR BIT(4) 11006#define BIT_TXBCN4ERR BIT(3) 11007#define BIT_TXBCN3ERR BIT(2) 11008#define BIT_TXBCN2ERR BIT(1) 11009#define BIT_TXBCN1ERR BIT(0) 11010 11011/* 2 REG_HIMR3 (Offset 0x10B8) */ 11012 11013#define BIT_WDT_PLATFORM_INT_MSK BIT(18) 11014#define BIT_WDT_CPU_INT_MSK BIT(17) 11015 11016/* 2 REG_HIMR3 (Offset 0x10B8) */ 11017 11018#define BIT_SETH2CDOK_MASK BIT(16) 11019#define BIT_H2C_CMD_FULL_MASK BIT(15) 11020#define BIT_PWR_INT_127_MASK BIT(14) 11021#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) 11022#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) 11023#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) 11024#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) 11025#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) 11026#define BIT_PWR_INT_127_MASK_V1 BIT(8) 11027#define BIT_PWR_INT_126TO96_MASK BIT(7) 11028#define BIT_PWR_INT_95TO64_MASK BIT(6) 11029#define BIT_PWR_INT_63TO32_MASK BIT(5) 11030#define BIT_PWR_INT_31TO0_MASK BIT(4) 11031#define BIT_DDMA0_LP_INT_MSK BIT(1) 11032#define BIT_DDMA0_HP_INT_MSK BIT(0) 11033 11034/* 2 REG_HISR3 (Offset 0x10BC) */ 11035 11036#define BIT_WDT_PLATFORM_INT BIT(18) 11037#define BIT_WDT_CPU_INT BIT(17) 11038 11039/* 2 REG_HISR3 (Offset 0x10BC) */ 11040 11041#define BIT_SETH2CDOK BIT(16) 11042#define BIT_H2C_CMD_FULL BIT(15) 11043#define BIT_PWR_INT_127 BIT(14) 11044#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) 11045#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) 11046#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) 11047#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) 11048#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) 11049#define BIT_PWR_INT_127_V1 BIT(8) 11050#define BIT_PWR_INT_126TO96 BIT(7) 11051#define BIT_PWR_INT_95TO64 BIT(6) 11052#define BIT_PWR_INT_63TO32 BIT(5) 11053#define BIT_PWR_INT_31TO0 BIT(4) 11054#define BIT_DDMA0_LP_INT BIT(1) 11055#define BIT_DDMA0_HP_INT BIT(0) 11056 11057/* 2 REG_SW_MDIO (Offset 0x10C0) */ 11058 11059#define BIT_DIS_TIMEOUT_IO BIT(24) 11060 11061/* 2 REG_SW_FLUSH (Offset 0x10C4) */ 11062 11063#define BIT_FLUSH_HOLDN_EN BIT(25) 11064#define BIT_FLUSH_WR_EN BIT(24) 11065#define BIT_SW_FLASH_CONTROL BIT(23) 11066#define BIT_SW_FLASH_WEN_E BIT(19) 11067#define BIT_SW_FLASH_HOLDN_E BIT(18) 11068#define BIT_SW_FLASH_SO_E BIT(17) 11069#define BIT_SW_FLASH_SI_E BIT(16) 11070#define BIT_SW_FLASH_SK_O BIT(13) 11071#define BIT_SW_FLASH_CEN_O BIT(12) 11072#define BIT_SW_FLASH_WEN_O BIT(11) 11073#define BIT_SW_FLASH_HOLDN_O BIT(10) 11074#define BIT_SW_FLASH_SO_O BIT(9) 11075#define BIT_SW_FLASH_SI_O BIT(8) 11076#define BIT_SW_FLASH_WEN_I BIT(3) 11077#define BIT_SW_FLASH_HOLDN_I BIT(2) 11078#define BIT_SW_FLASH_SO_I BIT(1) 11079#define BIT_SW_FLASH_SI_I BIT(0) 11080 11081/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ 11082 11083#define BIT_SHIFT_H2C_PKT_READADDR 0 11084#define BIT_MASK_H2C_PKT_READADDR 0x3ffff 11085#define BIT_H2C_PKT_READADDR(x) \ 11086 (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) 11087#define BIT_GET_H2C_PKT_READADDR(x) \ 11088 (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) 11089 11090/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ 11091 11092#define BIT_SHIFT_H2C_PKT_WRITEADDR 0 11093#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff 11094#define BIT_H2C_PKT_WRITEADDR(x) \ 11095 (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) 11096#define BIT_GET_H2C_PKT_WRITEADDR(x) \ 11097 (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) 11098 11099/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ 11100 11101#define BIT_MEM_BB_SD BIT(17) 11102#define BIT_MEM_BB_DS BIT(16) 11103#define BIT_MEM_BT_DS BIT(10) 11104#define BIT_MEM_SDIO_LS BIT(9) 11105#define BIT_MEM_SDIO_DS BIT(8) 11106#define BIT_MEM_USB_LS BIT(7) 11107#define BIT_MEM_USB_DS BIT(6) 11108#define BIT_MEM_PCI_LS BIT(5) 11109#define BIT_MEM_PCI_DS BIT(4) 11110#define BIT_MEM_WLMAC_LS BIT(3) 11111#define BIT_MEM_WLMAC_DS BIT(2) 11112#define BIT_MEM_WLMCU_LS BIT(1) 11113 11114/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ 11115 11116#define BIT_MEM_WLMCU_DS BIT(0) 11117 11118/* 2 REG_FW_DBG0 (Offset 0x10E0) */ 11119 11120#define BIT_SHIFT_FW_DBG0 0 11121#define BIT_MASK_FW_DBG0 0xffffffffL 11122#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) 11123#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) 11124 11125/* 2 REG_FW_DBG1 (Offset 0x10E4) */ 11126 11127#define BIT_SHIFT_FW_DBG1 0 11128#define BIT_MASK_FW_DBG1 0xffffffffL 11129#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) 11130#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) 11131 11132/* 2 REG_FW_DBG2 (Offset 0x10E8) */ 11133 11134#define BIT_SHIFT_FW_DBG2 0 11135#define BIT_MASK_FW_DBG2 0xffffffffL 11136#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) 11137#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) 11138 11139/* 2 REG_FW_DBG3 (Offset 0x10EC) */ 11140 11141#define BIT_SHIFT_FW_DBG3 0 11142#define BIT_MASK_FW_DBG3 0xffffffffL 11143#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) 11144#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) 11145 11146/* 2 REG_FW_DBG4 (Offset 0x10F0) */ 11147 11148#define BIT_SHIFT_FW_DBG4 0 11149#define BIT_MASK_FW_DBG4 0xffffffffL 11150#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) 11151#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) 11152 11153/* 2 REG_FW_DBG5 (Offset 0x10F4) */ 11154 11155#define BIT_SHIFT_FW_DBG5 0 11156#define BIT_MASK_FW_DBG5 0xffffffffL 11157#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) 11158#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) 11159 11160/* 2 REG_FW_DBG6 (Offset 0x10F8) */ 11161 11162#define BIT_SHIFT_FW_DBG6 0 11163#define BIT_MASK_FW_DBG6 0xffffffffL 11164#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) 11165#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) 11166 11167/* 2 REG_FW_DBG7 (Offset 0x10FC) */ 11168 11169#define BIT_SHIFT_FW_DBG7 0 11170#define BIT_MASK_FW_DBG7 0xffffffffL 11171#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) 11172#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) 11173 11174/* 2 REG_CR_EXT (Offset 0x1100) */ 11175 11176#define BIT_SHIFT_PHY_REQ_DELAY 24 11177#define BIT_MASK_PHY_REQ_DELAY 0xf 11178#define BIT_PHY_REQ_DELAY(x) \ 11179 (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) 11180#define BIT_GET_PHY_REQ_DELAY(x) \ 11181 (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) 11182 11183#define BIT_SPD_DOWN BIT(16) 11184 11185#define BIT_SHIFT_NETYPE4 4 11186#define BIT_MASK_NETYPE4 0x3 11187#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) 11188#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) 11189 11190#define BIT_SHIFT_NETYPE3 2 11191#define BIT_MASK_NETYPE3 0x3 11192#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) 11193#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) 11194 11195#define BIT_SHIFT_NETYPE2 0 11196#define BIT_MASK_NETYPE2 0x3 11197#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) 11198#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) 11199 11200/* 2 REG_FWFF (Offset 0x1114) */ 11201 11202#define BIT_SHIFT_PKTNUM_TH_V1 24 11203#define BIT_MASK_PKTNUM_TH_V1 0xff 11204#define BIT_PKTNUM_TH_V1(x) \ 11205 (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) 11206#define BIT_GET_PKTNUM_TH_V1(x) \ 11207 (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) 11208 11209/* 2 REG_FWFF (Offset 0x1114) */ 11210 11211#define BIT_SHIFT_TIMER_TH 16 11212#define BIT_MASK_TIMER_TH 0xff 11213#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) 11214#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) 11215 11216/* 2 REG_FWFF (Offset 0x1114) */ 11217 11218#define BIT_SHIFT_RXPKT1ENADDR 0 11219#define BIT_MASK_RXPKT1ENADDR 0xffff 11220#define BIT_RXPKT1ENADDR(x) \ 11221 (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) 11222#define BIT_GET_RXPKT1ENADDR(x) \ 11223 (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) 11224 11225/* 2 REG_FE2IMR (Offset 0x1120) */ 11226 11227#define BIT__FE4ISR__IND_MSK BIT(29) 11228 11229/* 2 REG_FE2IMR (Offset 0x1120) */ 11230 11231#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) 11232#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) 11233#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) 11234#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) 11235#define BIT_FS_TXSC_VODONE_INT_EN BIT(24) 11236 11237/* 2 REG_FE2IMR (Offset 0x1120) */ 11238 11239#define BIT_FS_ATIM_MB7_INT_EN BIT(23) 11240#define BIT_FS_ATIM_MB6_INT_EN BIT(22) 11241#define BIT_FS_ATIM_MB5_INT_EN BIT(21) 11242#define BIT_FS_ATIM_MB4_INT_EN BIT(20) 11243#define BIT_FS_ATIM_MB3_INT_EN BIT(19) 11244#define BIT_FS_ATIM_MB2_INT_EN BIT(18) 11245#define BIT_FS_ATIM_MB1_INT_EN BIT(17) 11246#define BIT_FS_ATIM_MB0_INT_EN BIT(16) 11247#define BIT_FS_TBTT4INT_EN BIT(11) 11248#define BIT_FS_TBTT3INT_EN BIT(10) 11249#define BIT_FS_TBTT2INT_EN BIT(9) 11250#define BIT_FS_TBTT1INT_EN BIT(8) 11251#define BIT_FS_TBTT0_MB7INT_EN BIT(7) 11252#define BIT_FS_TBTT0_MB6INT_EN BIT(6) 11253#define BIT_FS_TBTT0_MB5INT_EN BIT(5) 11254#define BIT_FS_TBTT0_MB4INT_EN BIT(4) 11255#define BIT_FS_TBTT0_MB3INT_EN BIT(3) 11256#define BIT_FS_TBTT0_MB2INT_EN BIT(2) 11257#define BIT_FS_TBTT0_MB1INT_EN BIT(1) 11258#define BIT_FS_TBTT0_INT_EN BIT(0) 11259 11260/* 2 REG_FE2ISR (Offset 0x1124) */ 11261 11262#define BIT__FE4ISR__IND_INT BIT(29) 11263 11264/* 2 REG_FE2ISR (Offset 0x1124) */ 11265 11266#define BIT_FS_TXSC_DESC_DONE_INT BIT(28) 11267#define BIT_FS_TXSC_BKDONE_INT BIT(27) 11268#define BIT_FS_TXSC_BEDONE_INT BIT(26) 11269#define BIT_FS_TXSC_VIDONE_INT BIT(25) 11270#define BIT_FS_TXSC_VODONE_INT BIT(24) 11271 11272/* 2 REG_FE2ISR (Offset 0x1124) */ 11273 11274#define BIT_FS_ATIM_MB7_INT BIT(23) 11275#define BIT_FS_ATIM_MB6_INT BIT(22) 11276#define BIT_FS_ATIM_MB5_INT BIT(21) 11277#define BIT_FS_ATIM_MB4_INT BIT(20) 11278#define BIT_FS_ATIM_MB3_INT BIT(19) 11279#define BIT_FS_ATIM_MB2_INT BIT(18) 11280#define BIT_FS_ATIM_MB1_INT BIT(17) 11281#define BIT_FS_ATIM_MB0_INT BIT(16) 11282#define BIT_FS_TBTT4INT BIT(11) 11283#define BIT_FS_TBTT3INT BIT(10) 11284#define BIT_FS_TBTT2INT BIT(9) 11285#define BIT_FS_TBTT1INT BIT(8) 11286#define BIT_FS_TBTT0_MB7INT BIT(7) 11287#define BIT_FS_TBTT0_MB6INT BIT(6) 11288#define BIT_FS_TBTT0_MB5INT BIT(5) 11289#define BIT_FS_TBTT0_MB4INT BIT(4) 11290#define BIT_FS_TBTT0_MB3INT BIT(3) 11291#define BIT_FS_TBTT0_MB2INT BIT(2) 11292#define BIT_FS_TBTT0_MB1INT BIT(1) 11293#define BIT_FS_TBTT0_INT BIT(0) 11294 11295/* 2 REG_FE3IMR (Offset 0x1128) */ 11296 11297#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) 11298 11299/* 2 REG_FE3IMR (Offset 0x1128) */ 11300 11301#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) 11302 11303/* 2 REG_FE3IMR (Offset 0x1128) */ 11304 11305#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) 11306 11307/* 2 REG_FE3IMR (Offset 0x1128) */ 11308 11309#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) 11310 11311/* 2 REG_FE3IMR (Offset 0x1128) */ 11312 11313#define BIT_FS_BCNDMA4_INT_EN BIT(27) 11314#define BIT_FS_BCNDMA3_INT_EN BIT(26) 11315#define BIT_FS_BCNDMA2_INT_EN BIT(25) 11316#define BIT_FS_BCNDMA1_INT_EN BIT(24) 11317#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) 11318#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) 11319#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) 11320#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) 11321#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) 11322#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) 11323#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) 11324#define BIT_FS_BCNDMA0_INT_EN BIT(16) 11325#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) 11326#define BIT_FS_BCNERLY4_INT_EN BIT(11) 11327#define BIT_FS_BCNERLY3_INT_EN BIT(10) 11328#define BIT_FS_BCNERLY2_INT_EN BIT(9) 11329#define BIT_FS_BCNERLY1_INT_EN BIT(8) 11330#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) 11331#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) 11332#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) 11333#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) 11334#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) 11335#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) 11336#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) 11337#define BIT_FS_BCNERLY0_INT_EN BIT(0) 11338 11339/* 2 REG_FE3ISR (Offset 0x112C) */ 11340 11341#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) 11342 11343/* 2 REG_FE3ISR (Offset 0x112C) */ 11344 11345#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) 11346 11347/* 2 REG_FE3ISR (Offset 0x112C) */ 11348 11349#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) 11350 11351/* 2 REG_FE3ISR (Offset 0x112C) */ 11352 11353#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) 11354 11355/* 2 REG_FE3ISR (Offset 0x112C) */ 11356 11357#define BIT_FS_BCNDMA4_INT BIT(27) 11358#define BIT_FS_BCNDMA3_INT BIT(26) 11359#define BIT_FS_BCNDMA2_INT BIT(25) 11360#define BIT_FS_BCNDMA1_INT BIT(24) 11361#define BIT_FS_BCNDMA0_MB7_INT BIT(23) 11362#define BIT_FS_BCNDMA0_MB6_INT BIT(22) 11363#define BIT_FS_BCNDMA0_MB5_INT BIT(21) 11364#define BIT_FS_BCNDMA0_MB4_INT BIT(20) 11365#define BIT_FS_BCNDMA0_MB3_INT BIT(19) 11366#define BIT_FS_BCNDMA0_MB2_INT BIT(18) 11367#define BIT_FS_BCNDMA0_MB1_INT BIT(17) 11368#define BIT_FS_BCNDMA0_INT BIT(16) 11369#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) 11370#define BIT_FS_BCNERLY4_INT BIT(11) 11371#define BIT_FS_BCNERLY3_INT BIT(10) 11372#define BIT_FS_BCNERLY2_INT BIT(9) 11373#define BIT_FS_BCNERLY1_INT BIT(8) 11374#define BIT_FS_BCNERLY0_MB7INT BIT(7) 11375#define BIT_FS_BCNERLY0_MB6INT BIT(6) 11376#define BIT_FS_BCNERLY0_MB5INT BIT(5) 11377#define BIT_FS_BCNERLY0_MB4INT BIT(4) 11378#define BIT_FS_BCNERLY0_MB3INT BIT(3) 11379#define BIT_FS_BCNERLY0_MB2INT BIT(2) 11380#define BIT_FS_BCNERLY0_MB1INT BIT(1) 11381#define BIT_FS_BCNERLY0_INT BIT(0) 11382 11383/* 2 REG_FE4IMR (Offset 0x1130) */ 11384 11385#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) 11386 11387/* 2 REG_FE4IMR (Offset 0x1130) */ 11388 11389#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) 11390 11391/* 2 REG_FE4IMR (Offset 0x1130) */ 11392 11393#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) 11394 11395/* 2 REG_FE4IMR (Offset 0x1130) */ 11396 11397#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) 11398 11399/* 2 REG_FE4IMR (Offset 0x1130) */ 11400 11401#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) 11402 11403/* 2 REG_FE4IMR (Offset 0x1130) */ 11404 11405#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) 11406 11407/* 2 REG_FE4IMR (Offset 0x1130) */ 11408 11409#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) 11410 11411/* 2 REG_FE4IMR (Offset 0x1130) */ 11412 11413#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) 11414 11415/* 2 REG_FE4IMR (Offset 0x1130) */ 11416 11417#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) 11418 11419/* 2 REG_FE4IMR (Offset 0x1130) */ 11420 11421#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) 11422 11423/* 2 REG_FE4IMR (Offset 0x1130) */ 11424 11425#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) 11426 11427/* 2 REG_FE4IMR (Offset 0x1130) */ 11428 11429#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) 11430 11431/* 2 REG_FE4IMR (Offset 0x1130) */ 11432 11433#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) 11434 11435/* 2 REG_FE4IMR (Offset 0x1130) */ 11436 11437#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) 11438 11439/* 2 REG_FE4IMR (Offset 0x1130) */ 11440 11441#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) 11442 11443/* 2 REG_FE4IMR (Offset 0x1130) */ 11444 11445#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) 11446 11447/* 2 REG_FE4IMR (Offset 0x1130) */ 11448 11449#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) 11450 11451/* 2 REG_FE4IMR (Offset 0x1130) */ 11452 11453#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) 11454 11455/* 2 REG_FE4IMR (Offset 0x1130) */ 11456 11457#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) 11458 11459/* 2 REG_FE4IMR (Offset 0x1130) */ 11460 11461#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) 11462 11463/* 2 REG_FE4ISR (Offset 0x1134) */ 11464 11465#define BIT_FS_CLI3_TXPKTIN_INT BIT(19) 11466 11467/* 2 REG_FE4ISR (Offset 0x1134) */ 11468 11469#define BIT_FS_CLI2_TXPKTIN_INT BIT(18) 11470 11471/* 2 REG_FE4ISR (Offset 0x1134) */ 11472 11473#define BIT_FS_CLI1_TXPKTIN_INT BIT(17) 11474 11475/* 2 REG_FE4ISR (Offset 0x1134) */ 11476 11477#define BIT_FS_CLI0_TXPKTIN_INT BIT(16) 11478 11479/* 2 REG_FE4ISR (Offset 0x1134) */ 11480 11481#define BIT_FS_CLI3_RX_UMD0_INT BIT(15) 11482 11483/* 2 REG_FE4ISR (Offset 0x1134) */ 11484 11485#define BIT_FS_CLI3_RX_UMD1_INT BIT(14) 11486 11487/* 2 REG_FE4ISR (Offset 0x1134) */ 11488 11489#define BIT_FS_CLI3_RX_BMD0_INT BIT(13) 11490 11491/* 2 REG_FE4ISR (Offset 0x1134) */ 11492 11493#define BIT_FS_CLI3_RX_BMD1_INT BIT(12) 11494 11495/* 2 REG_FE4ISR (Offset 0x1134) */ 11496 11497#define BIT_FS_CLI2_RX_UMD0_INT BIT(11) 11498 11499/* 2 REG_FE4ISR (Offset 0x1134) */ 11500 11501#define BIT_FS_CLI2_RX_UMD1_INT BIT(10) 11502 11503/* 2 REG_FE4ISR (Offset 0x1134) */ 11504 11505#define BIT_FS_CLI2_RX_BMD0_INT BIT(9) 11506 11507/* 2 REG_FE4ISR (Offset 0x1134) */ 11508 11509#define BIT_FS_CLI2_RX_BMD1_INT BIT(8) 11510 11511/* 2 REG_FE4ISR (Offset 0x1134) */ 11512 11513#define BIT_FS_CLI1_RX_UMD0_INT BIT(7) 11514 11515/* 2 REG_FE4ISR (Offset 0x1134) */ 11516 11517#define BIT_FS_CLI1_RX_UMD1_INT BIT(6) 11518 11519/* 2 REG_FE4ISR (Offset 0x1134) */ 11520 11521#define BIT_FS_CLI1_RX_BMD0_INT BIT(5) 11522 11523/* 2 REG_FE4ISR (Offset 0x1134) */ 11524 11525#define BIT_FS_CLI1_RX_BMD1_INT BIT(4) 11526 11527/* 2 REG_FE4ISR (Offset 0x1134) */ 11528 11529#define BIT_FS_CLI0_RX_UMD0_INT BIT(3) 11530 11531/* 2 REG_FE4ISR (Offset 0x1134) */ 11532 11533#define BIT_FS_CLI0_RX_UMD1_INT BIT(2) 11534 11535/* 2 REG_FE4ISR (Offset 0x1134) */ 11536 11537#define BIT_FS_CLI0_RX_BMD0_INT BIT(1) 11538 11539/* 2 REG_FE4ISR (Offset 0x1134) */ 11540 11541#define BIT_FS_CLI0_RX_BMD1_INT BIT(0) 11542 11543/* 2 REG_FT1IMR (Offset 0x1138) */ 11544 11545#define BIT__FT2ISR__IND_MSK BIT(30) 11546#define BIT_FTM_PTT_INT_EN BIT(29) 11547#define BIT_RXFTMREQ_INT_EN BIT(28) 11548#define BIT_RXFTM_INT_EN BIT(27) 11549#define BIT_TXFTM_INT_EN BIT(26) 11550 11551/* 2 REG_FT1IMR (Offset 0x1138) */ 11552 11553#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) 11554#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) 11555 11556/* 2 REG_FT1IMR (Offset 0x1138) */ 11557 11558#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) 11559#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) 11560#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) 11561#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) 11562#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) 11563#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) 11564#define BIT_FS_CTWEND2_INT_EN BIT(17) 11565#define BIT_FS_CTWEND1_INT_EN BIT(16) 11566#define BIT_FS_CTWEND0_INT_EN BIT(15) 11567#define BIT_FS_TX_NULL1_INT_EN BIT(14) 11568#define BIT_FS_TX_NULL0_INT_EN BIT(13) 11569#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) 11570#define BIT_FS_P2P_RFON2_INT_EN BIT(11) 11571#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) 11572#define BIT_FS_P2P_RFON1_INT_EN BIT(9) 11573#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) 11574#define BIT_FS_P2P_RFON0_INT_EN BIT(7) 11575#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) 11576#define BIT_FS_RX_UAPSDMD1_EN BIT(5) 11577#define BIT_FS_RX_UAPSDMD0_EN BIT(4) 11578#define BIT_FS_TRIGGER_PKT_EN BIT(3) 11579#define BIT_FS_EOSP_INT_EN BIT(2) 11580#define BIT_FS_RPWM2_INT_EN BIT(1) 11581#define BIT_FS_RPWM_INT_EN BIT(0) 11582 11583/* 2 REG_FT1ISR (Offset 0x113C) */ 11584 11585#define BIT__FT2ISR__IND_INT BIT(30) 11586#define BIT_FTM_PTT_INT BIT(29) 11587#define BIT_RXFTMREQ_INT BIT(28) 11588#define BIT_RXFTM_INT BIT(27) 11589#define BIT_TXFTM_INT BIT(26) 11590 11591/* 2 REG_FT1ISR (Offset 0x113C) */ 11592 11593#define BIT_FS_H2C_CMD_OK_INT BIT(25) 11594#define BIT_FS_H2C_CMD_FULL_INT BIT(24) 11595 11596/* 2 REG_FT1ISR (Offset 0x113C) */ 11597 11598#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) 11599#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) 11600#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) 11601#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) 11602#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) 11603#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) 11604#define BIT_FS_CTWEND2_INT BIT(17) 11605#define BIT_FS_CTWEND1_INT BIT(16) 11606#define BIT_FS_CTWEND0_INT BIT(15) 11607#define BIT_FS_TX_NULL1_INT BIT(14) 11608#define BIT_FS_TX_NULL0_INT BIT(13) 11609#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) 11610#define BIT_FS_P2P_RFON2_INT BIT(11) 11611#define BIT_FS_P2P_RFOFF2_INT BIT(10) 11612#define BIT_FS_P2P_RFON1_INT BIT(9) 11613#define BIT_FS_P2P_RFOFF1_INT BIT(8) 11614#define BIT_FS_P2P_RFON0_INT BIT(7) 11615#define BIT_FS_P2P_RFOFF0_INT BIT(6) 11616#define BIT_FS_RX_UAPSDMD1_INT BIT(5) 11617#define BIT_FS_RX_UAPSDMD0_INT BIT(4) 11618#define BIT_FS_TRIGGER_PKT_INT BIT(3) 11619#define BIT_FS_EOSP_INT BIT(2) 11620#define BIT_FS_RPWM2_INT BIT(1) 11621#define BIT_FS_RPWM_INT BIT(0) 11622 11623/* 2 REG_SPWR0 (Offset 0x1140) */ 11624 11625#define BIT_SHIFT_MID_31TO0 0 11626#define BIT_MASK_MID_31TO0 0xffffffffL 11627#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) 11628#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) 11629 11630/* 2 REG_SPWR1 (Offset 0x1144) */ 11631 11632#define BIT_SHIFT_MID_63TO32 0 11633#define BIT_MASK_MID_63TO32 0xffffffffL 11634#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) 11635#define BIT_GET_MID_63TO32(x) \ 11636 (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) 11637 11638/* 2 REG_SPWR2 (Offset 0x1148) */ 11639 11640#define BIT_SHIFT_MID_95O64 0 11641#define BIT_MASK_MID_95O64 0xffffffffL 11642#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) 11643#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) 11644 11645/* 2 REG_SPWR3 (Offset 0x114C) */ 11646 11647#define BIT_SHIFT_MID_127TO96 0 11648#define BIT_MASK_MID_127TO96 0xffffffffL 11649#define BIT_MID_127TO96(x) \ 11650 (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) 11651#define BIT_GET_MID_127TO96(x) \ 11652 (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) 11653 11654/* 2 REG_POWSEQ (Offset 0x1150) */ 11655 11656#define BIT_SHIFT_SEQNUM_MID 16 11657#define BIT_MASK_SEQNUM_MID 0xffff 11658#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) 11659#define BIT_GET_SEQNUM_MID(x) \ 11660 (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) 11661 11662#define BIT_SHIFT_REF_MID 0 11663#define BIT_MASK_REF_MID 0x7f 11664#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) 11665#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) 11666 11667/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */ 11668 11669#define BIT_TC7INT_EN BIT(26) 11670#define BIT_TC7MODE BIT(25) 11671#define BIT_TC7EN BIT(24) 11672 11673#define BIT_SHIFT_TC7DATA 0 11674#define BIT_MASK_TC7DATA 0xffffff 11675#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) 11676#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) 11677 11678/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */ 11679 11680#define BIT_TC8INT_EN BIT(26) 11681#define BIT_TC8MODE BIT(25) 11682#define BIT_TC8EN BIT(24) 11683 11684#define BIT_SHIFT_TC8DATA 0 11685#define BIT_MASK_TC8DATA 0xffffff 11686#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) 11687#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) 11688 11689/* 2 REG_FT2IMR (Offset 0x11E0) */ 11690 11691#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) 11692 11693/* 2 REG_FT2IMR (Offset 0x11E0) */ 11694 11695#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) 11696 11697/* 2 REG_FT2IMR (Offset 0x11E0) */ 11698 11699#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) 11700 11701/* 2 REG_FT2IMR (Offset 0x11E0) */ 11702 11703#define BIT_FS_CLI3_EOSP_INT_EN BIT(28) 11704 11705/* 2 REG_FT2IMR (Offset 0x11E0) */ 11706 11707#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) 11708 11709/* 2 REG_FT2IMR (Offset 0x11E0) */ 11710 11711#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) 11712 11713/* 2 REG_FT2IMR (Offset 0x11E0) */ 11714 11715#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) 11716 11717/* 2 REG_FT2IMR (Offset 0x11E0) */ 11718 11719#define BIT_FS_CLI2_EOSP_INT_EN BIT(24) 11720 11721/* 2 REG_FT2IMR (Offset 0x11E0) */ 11722 11723#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) 11724 11725/* 2 REG_FT2IMR (Offset 0x11E0) */ 11726 11727#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) 11728 11729/* 2 REG_FT2IMR (Offset 0x11E0) */ 11730 11731#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) 11732 11733/* 2 REG_FT2IMR (Offset 0x11E0) */ 11734 11735#define BIT_FS_CLI1_EOSP_INT_EN BIT(20) 11736 11737/* 2 REG_FT2IMR (Offset 0x11E0) */ 11738 11739#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) 11740 11741/* 2 REG_FT2IMR (Offset 0x11E0) */ 11742 11743#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) 11744 11745/* 2 REG_FT2IMR (Offset 0x11E0) */ 11746 11747#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) 11748 11749/* 2 REG_FT2IMR (Offset 0x11E0) */ 11750 11751#define BIT_FS_CLI0_EOSP_INT_EN BIT(16) 11752 11753/* 2 REG_FT2IMR (Offset 0x11E0) */ 11754 11755#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) 11756 11757/* 2 REG_FT2IMR (Offset 0x11E0) */ 11758 11759#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) 11760 11761/* 2 REG_FT2IMR (Offset 0x11E0) */ 11762 11763#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) 11764 11765/* 2 REG_FT2IMR (Offset 0x11E0) */ 11766 11767#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) 11768 11769/* 2 REG_FT2IMR (Offset 0x11E0) */ 11770 11771#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) 11772 11773/* 2 REG_FT2IMR (Offset 0x11E0) */ 11774 11775#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) 11776 11777/* 2 REG_FT2IMR (Offset 0x11E0) */ 11778 11779#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) 11780 11781/* 2 REG_FT2IMR (Offset 0x11E0) */ 11782 11783#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) 11784 11785/* 2 REG_FT2IMR (Offset 0x11E0) */ 11786 11787#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) 11788 11789/* 2 REG_FT2IMR (Offset 0x11E0) */ 11790 11791#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) 11792 11793/* 2 REG_FT2ISR (Offset 0x11E4) */ 11794 11795#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) 11796 11797/* 2 REG_FT2ISR (Offset 0x11E4) */ 11798 11799#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) 11800 11801/* 2 REG_FT2ISR (Offset 0x11E4) */ 11802 11803#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) 11804 11805/* 2 REG_FT2ISR (Offset 0x11E4) */ 11806 11807#define BIT_FS_CLI3_EOSP_INT BIT(28) 11808 11809/* 2 REG_FT2ISR (Offset 0x11E4) */ 11810 11811#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) 11812 11813/* 2 REG_FT2ISR (Offset 0x11E4) */ 11814 11815#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) 11816 11817/* 2 REG_FT2ISR (Offset 0x11E4) */ 11818 11819#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) 11820 11821/* 2 REG_FT2ISR (Offset 0x11E4) */ 11822 11823#define BIT_FS_CLI2_EOSP_INT BIT(24) 11824 11825/* 2 REG_FT2ISR (Offset 0x11E4) */ 11826 11827#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) 11828 11829/* 2 REG_FT2ISR (Offset 0x11E4) */ 11830 11831#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) 11832 11833/* 2 REG_FT2ISR (Offset 0x11E4) */ 11834 11835#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) 11836 11837/* 2 REG_FT2ISR (Offset 0x11E4) */ 11838 11839#define BIT_FS_CLI1_EOSP_INT BIT(20) 11840 11841/* 2 REG_FT2ISR (Offset 0x11E4) */ 11842 11843#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) 11844 11845/* 2 REG_FT2ISR (Offset 0x11E4) */ 11846 11847#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) 11848 11849/* 2 REG_FT2ISR (Offset 0x11E4) */ 11850 11851#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) 11852 11853/* 2 REG_FT2ISR (Offset 0x11E4) */ 11854 11855#define BIT_FS_CLI0_EOSP_INT BIT(16) 11856 11857/* 2 REG_FT2ISR (Offset 0x11E4) */ 11858 11859#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) 11860 11861/* 2 REG_FT2ISR (Offset 0x11E4) */ 11862 11863#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) 11864 11865/* 2 REG_FT2ISR (Offset 0x11E4) */ 11866 11867#define BIT_FS_CLI3_TX_NULL1_INT BIT(7) 11868 11869/* 2 REG_FT2ISR (Offset 0x11E4) */ 11870 11871#define BIT_FS_CLI3_TX_NULL0_INT BIT(6) 11872 11873/* 2 REG_FT2ISR (Offset 0x11E4) */ 11874 11875#define BIT_FS_CLI2_TX_NULL1_INT BIT(5) 11876 11877/* 2 REG_FT2ISR (Offset 0x11E4) */ 11878 11879#define BIT_FS_CLI2_TX_NULL0_INT BIT(4) 11880 11881/* 2 REG_FT2ISR (Offset 0x11E4) */ 11882 11883#define BIT_FS_CLI1_TX_NULL1_INT BIT(3) 11884 11885/* 2 REG_FT2ISR (Offset 0x11E4) */ 11886 11887#define BIT_FS_CLI1_TX_NULL0_INT BIT(2) 11888 11889/* 2 REG_FT2ISR (Offset 0x11E4) */ 11890 11891#define BIT_FS_CLI0_TX_NULL1_INT BIT(1) 11892 11893/* 2 REG_FT2ISR (Offset 0x11E4) */ 11894 11895#define BIT_FS_CLI0_TX_NULL0_INT BIT(0) 11896 11897/* 2 REG_MSG2 (Offset 0x11F0) */ 11898 11899#define BIT_SHIFT_FW_MSG2 0 11900#define BIT_MASK_FW_MSG2 0xffffffffL 11901#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) 11902#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) 11903 11904/* 2 REG_MSG3 (Offset 0x11F4) */ 11905 11906#define BIT_SHIFT_FW_MSG3 0 11907#define BIT_MASK_FW_MSG3 0xffffffffL 11908#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) 11909#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) 11910 11911/* 2 REG_MSG4 (Offset 0x11F8) */ 11912 11913#define BIT_SHIFT_FW_MSG4 0 11914#define BIT_MASK_FW_MSG4 0xffffffffL 11915#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) 11916#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) 11917 11918/* 2 REG_MSG5 (Offset 0x11FC) */ 11919 11920#define BIT_SHIFT_FW_MSG5 0 11921#define BIT_MASK_FW_MSG5 0xffffffffL 11922#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) 11923#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) 11924 11925/* 2 REG_DDMA_CH0SA (Offset 0x1200) */ 11926 11927#define BIT_SHIFT_DDMACH0_SA 0 11928#define BIT_MASK_DDMACH0_SA 0xffffffffL 11929#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) 11930#define BIT_GET_DDMACH0_SA(x) \ 11931 (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) 11932 11933/* 2 REG_DDMA_CH0DA (Offset 0x1204) */ 11934 11935#define BIT_SHIFT_DDMACH0_DA 0 11936#define BIT_MASK_DDMACH0_DA 0xffffffffL 11937#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) 11938#define BIT_GET_DDMACH0_DA(x) \ 11939 (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) 11940 11941/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ 11942 11943#define BIT_DDMACH0_OWN BIT(31) 11944#define BIT_DDMACH0_CHKSUM_EN BIT(29) 11945#define BIT_DDMACH0_DA_W_DISABLE BIT(28) 11946#define BIT_DDMACH0_CHKSUM_STS BIT(27) 11947#define BIT_DDMACH0_DDMA_MODE BIT(26) 11948#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 11949#define BIT_DDMACH0_CHKSUM_CONT BIT(24) 11950 11951#define BIT_SHIFT_DDMACH0_DLEN 0 11952#define BIT_MASK_DDMACH0_DLEN 0x3ffff 11953#define BIT_DDMACH0_DLEN(x) \ 11954 (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) 11955#define BIT_GET_DDMACH0_DLEN(x) \ 11956 (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) 11957 11958/* 2 REG_DDMA_CH1SA (Offset 0x1210) */ 11959 11960#define BIT_SHIFT_DDMACH1_SA 0 11961#define BIT_MASK_DDMACH1_SA 0xffffffffL 11962#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) 11963#define BIT_GET_DDMACH1_SA(x) \ 11964 (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) 11965 11966/* 2 REG_DDMA_CH1DA (Offset 0x1214) */ 11967 11968#define BIT_SHIFT_DDMACH1_DA 0 11969#define BIT_MASK_DDMACH1_DA 0xffffffffL 11970#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) 11971#define BIT_GET_DDMACH1_DA(x) \ 11972 (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) 11973 11974/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ 11975 11976#define BIT_DDMACH1_OWN BIT(31) 11977#define BIT_DDMACH1_CHKSUM_EN BIT(29) 11978#define BIT_DDMACH1_DA_W_DISABLE BIT(28) 11979#define BIT_DDMACH1_CHKSUM_STS BIT(27) 11980#define BIT_DDMACH1_DDMA_MODE BIT(26) 11981#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) 11982#define BIT_DDMACH1_CHKSUM_CONT BIT(24) 11983 11984#define BIT_SHIFT_DDMACH1_DLEN 0 11985#define BIT_MASK_DDMACH1_DLEN 0x3ffff 11986#define BIT_DDMACH1_DLEN(x) \ 11987 (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) 11988#define BIT_GET_DDMACH1_DLEN(x) \ 11989 (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) 11990 11991/* 2 REG_DDMA_CH2SA (Offset 0x1220) */ 11992 11993#define BIT_SHIFT_DDMACH2_SA 0 11994#define BIT_MASK_DDMACH2_SA 0xffffffffL 11995#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) 11996#define BIT_GET_DDMACH2_SA(x) \ 11997 (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) 11998 11999/* 2 REG_DDMA_CH2DA (Offset 0x1224) */ 12000
12001#define BIT_SHIFT_DDMACH2_DA 0 12002#define BIT_MASK_DDMACH2_DA 0xffffffffL 12003#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) 12004#define BIT_GET_DDMACH2_DA(x) \ 12005 (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) 12006 12007/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ 12008 12009#define BIT_DDMACH2_OWN BIT(31) 12010#define BIT_DDMACH2_CHKSUM_EN BIT(29) 12011#define BIT_DDMACH2_DA_W_DISABLE BIT(28) 12012#define BIT_DDMACH2_CHKSUM_STS BIT(27) 12013#define BIT_DDMACH2_DDMA_MODE BIT(26) 12014#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) 12015#define BIT_DDMACH2_CHKSUM_CONT BIT(24) 12016 12017#define BIT_SHIFT_DDMACH2_DLEN 0 12018#define BIT_MASK_DDMACH2_DLEN 0x3ffff 12019#define BIT_DDMACH2_DLEN(x) \ 12020 (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) 12021#define BIT_GET_DDMACH2_DLEN(x) \ 12022 (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) 12023 12024/* 2 REG_DDMA_CH3SA (Offset 0x1230) */ 12025 12026#define BIT_SHIFT_DDMACH3_SA 0 12027#define BIT_MASK_DDMACH3_SA 0xffffffffL 12028#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) 12029#define BIT_GET_DDMACH3_SA(x) \ 12030 (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) 12031 12032/* 2 REG_DDMA_CH3DA (Offset 0x1234) */ 12033 12034#define BIT_SHIFT_DDMACH3_DA 0 12035#define BIT_MASK_DDMACH3_DA 0xffffffffL 12036#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) 12037#define BIT_GET_DDMACH3_DA(x) \ 12038 (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) 12039 12040/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ 12041 12042#define BIT_DDMACH3_OWN BIT(31) 12043#define BIT_DDMACH3_CHKSUM_EN BIT(29) 12044#define BIT_DDMACH3_DA_W_DISABLE BIT(28) 12045#define BIT_DDMACH3_CHKSUM_STS BIT(27) 12046#define BIT_DDMACH3_DDMA_MODE BIT(26) 12047#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) 12048#define BIT_DDMACH3_CHKSUM_CONT BIT(24) 12049 12050#define BIT_SHIFT_DDMACH3_DLEN 0 12051#define BIT_MASK_DDMACH3_DLEN 0x3ffff 12052#define BIT_DDMACH3_DLEN(x) \ 12053 (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) 12054#define BIT_GET_DDMACH3_DLEN(x) \ 12055 (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) 12056 12057/* 2 REG_DDMA_CH4SA (Offset 0x1240) */ 12058 12059#define BIT_SHIFT_DDMACH4_SA 0 12060#define BIT_MASK_DDMACH4_SA 0xffffffffL 12061#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) 12062#define BIT_GET_DDMACH4_SA(x) \ 12063 (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) 12064 12065/* 2 REG_DDMA_CH4DA (Offset 0x1244) */ 12066 12067#define BIT_SHIFT_DDMACH4_DA 0 12068#define BIT_MASK_DDMACH4_DA 0xffffffffL 12069#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) 12070#define BIT_GET_DDMACH4_DA(x) \ 12071 (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) 12072 12073/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ 12074 12075#define BIT_DDMACH4_OWN BIT(31) 12076#define BIT_DDMACH4_CHKSUM_EN BIT(29) 12077#define BIT_DDMACH4_DA_W_DISABLE BIT(28) 12078#define BIT_DDMACH4_CHKSUM_STS BIT(27) 12079#define BIT_DDMACH4_DDMA_MODE BIT(26) 12080#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) 12081#define BIT_DDMACH4_CHKSUM_CONT BIT(24) 12082 12083#define BIT_SHIFT_DDMACH4_DLEN 0 12084#define BIT_MASK_DDMACH4_DLEN 0x3ffff 12085#define BIT_DDMACH4_DLEN(x) \ 12086 (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) 12087#define BIT_GET_DDMACH4_DLEN(x) \ 12088 (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) 12089 12090/* 2 REG_DDMA_CH5SA (Offset 0x1250) */ 12091 12092#define BIT_SHIFT_DDMACH5_SA 0 12093#define BIT_MASK_DDMACH5_SA 0xffffffffL 12094#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) 12095#define BIT_GET_DDMACH5_SA(x) \ 12096 (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) 12097 12098/* 2 REG_DDMA_CH5DA (Offset 0x1254) */ 12099 12100#define BIT_DDMACH5_OWN BIT(31) 12101#define BIT_DDMACH5_CHKSUM_EN BIT(29) 12102#define BIT_DDMACH5_DA_W_DISABLE BIT(28) 12103#define BIT_DDMACH5_CHKSUM_STS BIT(27) 12104#define BIT_DDMACH5_DDMA_MODE BIT(26) 12105#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) 12106#define BIT_DDMACH5_CHKSUM_CONT BIT(24) 12107 12108#define BIT_SHIFT_DDMACH5_DA 0 12109#define BIT_MASK_DDMACH5_DA 0xffffffffL 12110#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) 12111#define BIT_GET_DDMACH5_DA(x) \ 12112 (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) 12113 12114#define BIT_SHIFT_DDMACH5_DLEN 0 12115#define BIT_MASK_DDMACH5_DLEN 0x3ffff 12116#define BIT_DDMACH5_DLEN(x) \ 12117 (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) 12118#define BIT_GET_DDMACH5_DLEN(x) \ 12119 (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) 12120 12121/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ 12122 12123#define BIT_DDMACH5_MSK BIT(5) 12124#define BIT_DDMACH4_MSK BIT(4) 12125#define BIT_DDMACH3_MSK BIT(3) 12126#define BIT_DDMACH2_MSK BIT(2) 12127#define BIT_DDMACH1_MSK BIT(1) 12128#define BIT_DDMACH0_MSK BIT(0) 12129 12130/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ 12131 12132#define BIT_DDMACH5_BUSY BIT(5) 12133#define BIT_DDMACH4_BUSY BIT(4) 12134#define BIT_DDMACH3_BUSY BIT(3) 12135#define BIT_DDMACH2_BUSY BIT(2) 12136#define BIT_DDMACH1_BUSY BIT(1) 12137#define BIT_DDMACH0_BUSY BIT(0) 12138 12139/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ 12140 12141#define BIT_SHIFT_IDDMA0_CHKSUM 0 12142#define BIT_MASK_IDDMA0_CHKSUM 0xffff 12143#define BIT_IDDMA0_CHKSUM(x) \ 12144 (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) 12145#define BIT_GET_IDDMA0_CHKSUM(x) \ 12146 (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) 12147 12148/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ 12149 12150#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) 12151#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) 12152#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) 12153#define BIT_ECRC_EN_V1 BIT(7) 12154#define BIT_MDIO_RFLAG_V1 BIT(6) 12155#define BIT_CH5_ERR BIT(5) 12156#define BIT_MDIO_WFLAG_V1 BIT(5) 12157#define BIT_CH4_ERR BIT(4) 12158#define BIT_CH3_ERR BIT(3) 12159#define BIT_CH2_ERR BIT(2) 12160#define BIT_CH1_ERR BIT(1) 12161#define BIT_CH0_ERR BIT(0) 12162 12163/* 2 REG_STC_INT_CS (Offset 0x1300) */ 12164 12165#define BIT_STC_INT_EN BIT(31) 12166 12167#define BIT_SHIFT_STC_INT_FLAG 16 12168#define BIT_MASK_STC_INT_FLAG 0xff 12169#define BIT_STC_INT_FLAG(x) \ 12170 (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) 12171#define BIT_GET_STC_INT_FLAG(x) \ 12172 (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) 12173 12174#define BIT_SHIFT_STC_INT_IDX 8 12175#define BIT_MASK_STC_INT_IDX 0x7 12176#define BIT_STC_INT_IDX(x) \ 12177 (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) 12178#define BIT_GET_STC_INT_IDX(x) \ 12179 (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) 12180 12181#define BIT_SHIFT_STC_INT_REALTIME_CS 0 12182#define BIT_MASK_STC_INT_REALTIME_CS 0x3f 12183#define BIT_STC_INT_REALTIME_CS(x) \ 12184 (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) 12185#define BIT_GET_STC_INT_REALTIME_CS(x) \ 12186 (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) 12187 12188/* 2 REG_ST_INT_CFG (Offset 0x1304) */ 12189 12190#define BIT_STC_INT_GRP_EN BIT(31) 12191 12192#define BIT_SHIFT_STC_INT_EXPECT_LS 8 12193#define BIT_MASK_STC_INT_EXPECT_LS 0x3f 12194#define BIT_STC_INT_EXPECT_LS(x) \ 12195 (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) 12196#define BIT_GET_STC_INT_EXPECT_LS(x) \ 12197 (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) 12198 12199#define BIT_SHIFT_STC_INT_EXPECT_CS 0 12200#define BIT_MASK_STC_INT_EXPECT_CS 0x3f 12201#define BIT_STC_INT_EXPECT_CS(x) \ 12202 (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) 12203#define BIT_GET_STC_INT_EXPECT_CS(x) \ 12204 (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) 12205 12206/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ 12207 12208#define BIT_CMU_DLY_EN BIT(31) 12209#define BIT_CMU_DLY_MODE BIT(30) 12210 12211#define BIT_SHIFT_CMU_DLY_PRE_DIV 0 12212#define BIT_MASK_CMU_DLY_PRE_DIV 0xff 12213#define BIT_CMU_DLY_PRE_DIV(x) \ 12214 (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) 12215#define BIT_GET_CMU_DLY_PRE_DIV(x) \ 12216 (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) 12217 12218/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ 12219 12220#define BIT_SHIFT_CMU_DLY_LTR_A2I 24 12221#define BIT_MASK_CMU_DLY_LTR_A2I 0xff 12222#define BIT_CMU_DLY_LTR_A2I(x) \ 12223 (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) 12224#define BIT_GET_CMU_DLY_LTR_A2I(x) \ 12225 (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) 12226 12227#define BIT_SHIFT_CMU_DLY_LTR_I2A 16 12228#define BIT_MASK_CMU_DLY_LTR_I2A 0xff 12229#define BIT_CMU_DLY_LTR_I2A(x) \ 12230 (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) 12231#define BIT_GET_CMU_DLY_LTR_I2A(x) \ 12232 (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) 12233 12234#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 12235#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff 12236#define BIT_CMU_DLY_LTR_IDLE(x) \ 12237 (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) 12238#define BIT_GET_CMU_DLY_LTR_IDLE(x) \ 12239 (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) 12240 12241#define BIT_SHIFT_CMU_DLY_LTR_ACT 0 12242#define BIT_MASK_CMU_DLY_LTR_ACT 0xff 12243#define BIT_CMU_DLY_LTR_ACT(x) \ 12244 (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) 12245#define BIT_GET_CMU_DLY_LTR_ACT(x) \ 12246 (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) 12247 12248/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ 12249 12250#define BIT_SHIFT_H2CQ_TXBD_DESA 0 12251#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL 12252#define BIT_H2CQ_TXBD_DESA(x) \ 12253 (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) 12254#define BIT_GET_H2CQ_TXBD_DESA(x) \ 12255 (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) 12256 12257/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ 12258 12259#define BIT_PCIE_H2CQ_FLAG BIT(14) 12260 12261/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ 12262 12263#define BIT_SHIFT_H2CQ_DESC_MODE 12 12264#define BIT_MASK_H2CQ_DESC_MODE 0x3 12265#define BIT_H2CQ_DESC_MODE(x) \ 12266 (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) 12267#define BIT_GET_H2CQ_DESC_MODE(x) \ 12268 (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) 12269 12270#define BIT_SHIFT_H2CQ_DESC_NUM 0 12271#define BIT_MASK_H2CQ_DESC_NUM 0xfff 12272#define BIT_H2CQ_DESC_NUM(x) \ 12273 (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) 12274#define BIT_GET_H2CQ_DESC_NUM(x) \ 12275 (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) 12276 12277/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ 12278 12279#define BIT_SHIFT_H2CQ_HW_IDX 16 12280#define BIT_MASK_H2CQ_HW_IDX 0xfff 12281#define BIT_H2CQ_HW_IDX(x) \ 12282 (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) 12283#define BIT_GET_H2CQ_HW_IDX(x) \ 12284 (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) 12285 12286#define BIT_SHIFT_H2CQ_HOST_IDX 0 12287#define BIT_MASK_H2CQ_HOST_IDX 0xfff 12288#define BIT_H2CQ_HOST_IDX(x) \ 12289 (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) 12290#define BIT_GET_H2CQ_HOST_IDX(x) \ 12291 (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) 12292 12293/* 2 REG_H2CQ_CSR (Offset 0x1330) */ 12294 12295#define BIT_H2CQ_FULL BIT(31) 12296#define BIT_CLR_H2CQ_HOST_IDX BIT(16) 12297#define BIT_CLR_H2CQ_HW_IDX BIT(8) 12298 12299/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12300 12301#define BIT_CHANGE_PCIE_SPEED BIT(18) 12302 12303/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12304 12305#define BIT_SHIFT_GEN1_GEN2 16 12306#define BIT_MASK_GEN1_GEN2 0x3 12307#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) 12308#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) 12309 12310/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12311 12312#define BIT_SHIFT_AUTO_HANG_RELEASE 0 12313#define BIT_MASK_AUTO_HANG_RELEASE 0x7 12314#define BIT_AUTO_HANG_RELEASE(x) \ 12315 (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) 12316#define BIT_GET_AUTO_HANG_RELEASE(x) \ 12317 (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) 12318 12319/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ 12320 12321#define BIT_OLD_DEHANG BIT(1) 12322 12323/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ 12324 12325#define BIT_SHIFT_AC1_PKT_INFO 16 12326#define BIT_MASK_AC1_PKT_INFO 0xfff 12327#define BIT_AC1_PKT_INFO(x) \ 12328 (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) 12329#define BIT_GET_AC1_PKT_INFO(x) \ 12330 (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) 12331 12332#define BIT_SHIFT_AC0_PKT_INFO 0 12333#define BIT_MASK_AC0_PKT_INFO 0xfff 12334#define BIT_AC0_PKT_INFO(x) \ 12335 (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) 12336#define BIT_GET_AC0_PKT_INFO(x) \ 12337 (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) 12338 12339/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ 12340 12341#define BIT_SHIFT_AC3_PKT_INFO 16 12342#define BIT_MASK_AC3_PKT_INFO 0xfff 12343#define BIT_AC3_PKT_INFO(x) \ 12344 (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) 12345#define BIT_GET_AC3_PKT_INFO(x) \ 12346 (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) 12347 12348#define BIT_SHIFT_AC2_PKT_INFO 0 12349#define BIT_MASK_AC2_PKT_INFO 0xfff 12350#define BIT_AC2_PKT_INFO(x) \ 12351 (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) 12352#define BIT_GET_AC2_PKT_INFO(x) \ 12353 (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) 12354 12355/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ 12356 12357#define BIT_SHIFT_AC5_PKT_INFO 16 12358#define BIT_MASK_AC5_PKT_INFO 0xfff 12359#define BIT_AC5_PKT_INFO(x) \ 12360 (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) 12361#define BIT_GET_AC5_PKT_INFO(x) \ 12362 (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) 12363 12364#define BIT_SHIFT_AC4_PKT_INFO 0 12365#define BIT_MASK_AC4_PKT_INFO 0xfff 12366#define BIT_AC4_PKT_INFO(x) \ 12367 (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) 12368#define BIT_GET_AC4_PKT_INFO(x) \ 12369 (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) 12370 12371/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ 12372 12373#define BIT_SHIFT_AC7_PKT_INFO 16 12374#define BIT_MASK_AC7_PKT_INFO 0xfff 12375#define BIT_AC7_PKT_INFO(x) \ 12376 (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) 12377#define BIT_GET_AC7_PKT_INFO(x) \ 12378 (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) 12379 12380#define BIT_SHIFT_AC6_PKT_INFO 0 12381#define BIT_MASK_AC6_PKT_INFO 0xfff 12382#define BIT_AC6_PKT_INFO(x) \ 12383 (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) 12384#define BIT_GET_AC6_PKT_INFO(x) \ 12385 (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) 12386 12387/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ 12388 12389#define BIT_SHIFT_HIQ_PKT_INFO 16 12390#define BIT_MASK_HIQ_PKT_INFO 0xfff 12391#define BIT_HIQ_PKT_INFO(x) \ 12392 (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) 12393#define BIT_GET_HIQ_PKT_INFO(x) \ 12394 (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) 12395 12396#define BIT_SHIFT_MGQ_PKT_INFO 0 12397#define BIT_MASK_MGQ_PKT_INFO 0xfff 12398#define BIT_MGQ_PKT_INFO(x) \ 12399 (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) 12400#define BIT_GET_MGQ_PKT_INFO(x) \ 12401 (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) 12402 12403/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ 12404 12405#define BIT_SHIFT_CMDQ_PKT_INFO 16 12406#define BIT_MASK_CMDQ_PKT_INFO 0xfff 12407#define BIT_CMDQ_PKT_INFO(x) \ 12408 (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) 12409#define BIT_GET_CMDQ_PKT_INFO(x) \ 12410 (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) 12411 12412/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ 12413 12414#define BIT_SHIFT_BCNQ_PKT_INFO 0 12415#define BIT_MASK_BCNQ_PKT_INFO 0xfff 12416#define BIT_BCNQ_PKT_INFO(x) \ 12417 (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) 12418#define BIT_GET_BCNQ_PKT_INFO(x) \ 12419 (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) 12420 12421/* 2 REG_USEREG_SETTING (Offset 0x1420) */ 12422 12423#define BIT_NDPA_USEREG BIT(21) 12424 12425#define BIT_SHIFT_RETRY_USEREG 19 12426#define BIT_MASK_RETRY_USEREG 0x3 12427#define BIT_RETRY_USEREG(x) \ 12428 (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) 12429#define BIT_GET_RETRY_USEREG(x) \ 12430 (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) 12431 12432#define BIT_SHIFT_TRYPKT_USEREG 17 12433#define BIT_MASK_TRYPKT_USEREG 0x3 12434#define BIT_TRYPKT_USEREG(x) \ 12435 (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) 12436#define BIT_GET_TRYPKT_USEREG(x) \ 12437 (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) 12438 12439#define BIT_CTLPKT_USEREG BIT(16) 12440 12441/* 2 REG_AESIV_SETTING (Offset 0x1424) */ 12442 12443#define BIT_SHIFT_AESIV_OFFSET 0 12444#define BIT_MASK_AESIV_OFFSET 0xfff 12445#define BIT_AESIV_OFFSET(x) \ 12446 (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) 12447#define BIT_GET_AESIV_OFFSET(x) \ 12448 (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) 12449 12450/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ 12451 12452#define BIT_BF0_TIMER_SET BIT(31) 12453#define BIT_BF0_TIMER_CLR BIT(30) 12454#define BIT_BF0_UPDATE_EN BIT(29) 12455#define BIT_BF0_TIMER_EN BIT(28) 12456 12457#define BIT_SHIFT_BF0_PRETIME_OVER 16 12458#define BIT_MASK_BF0_PRETIME_OVER 0xfff 12459#define BIT_BF0_PRETIME_OVER(x) \ 12460 (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) 12461#define BIT_GET_BF0_PRETIME_OVER(x) \ 12462 (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) 12463 12464#define BIT_SHIFT_BF0_LIFETIME 0 12465#define BIT_MASK_BF0_LIFETIME 0xffff 12466#define BIT_BF0_LIFETIME(x) \ 12467 (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) 12468#define BIT_GET_BF0_LIFETIME(x) \ 12469 (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) 12470 12471/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ 12472 12473#define BIT_BF1_TIMER_SET BIT(31) 12474#define BIT_BF1_TIMER_CLR BIT(30) 12475#define BIT_BF1_UPDATE_EN BIT(29) 12476#define BIT_BF1_TIMER_EN BIT(28) 12477 12478#define BIT_SHIFT_BF1_PRETIME_OVER 16 12479#define BIT_MASK_BF1_PRETIME_OVER 0xfff 12480#define BIT_BF1_PRETIME_OVER(x) \ 12481 (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) 12482#define BIT_GET_BF1_PRETIME_OVER(x) \ 12483 (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) 12484 12485#define BIT_SHIFT_BF1_LIFETIME 0 12486#define BIT_MASK_BF1_LIFETIME 0xffff 12487#define BIT_BF1_LIFETIME(x) \ 12488 (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) 12489#define BIT_GET_BF1_LIFETIME(x) \ 12490 (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) 12491 12492/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ 12493 12494#define BIT_EN_VHT_LDPC BIT(9) 12495#define BIT_EN_HT_LDPC BIT(8) 12496#define BIT_BF1_TIMEOUT_EN BIT(1) 12497#define BIT_BF0_TIMEOUT_EN BIT(0) 12498 12499/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ 12500 12501#define BIT_SHIFT_MACID31_0_RELEASE 0 12502#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL 12503#define BIT_MACID31_0_RELEASE(x) \ 12504 (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) 12505#define BIT_GET_MACID31_0_RELEASE(x) \ 12506 (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) 12507 12508/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ 12509 12510#define BIT_SHIFT_MACID63_32_RELEASE 0 12511#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL 12512#define BIT_MACID63_32_RELEASE(x) \ 12513 (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) 12514#define BIT_GET_MACID63_32_RELEASE(x) \ 12515 (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) 12516 12517/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ 12518 12519#define BIT_SHIFT_MACID95_64_RELEASE 0 12520#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL 12521#define BIT_MACID95_64_RELEASE(x) \ 12522 (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) 12523#define BIT_GET_MACID95_64_RELEASE(x) \ 12524 (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) 12525 12526/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ 12527 12528#define BIT_SHIFT_MACID127_96_RELEASE 0 12529#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL 12530#define BIT_MACID127_96_RELEASE(x) \ 12531 (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) 12532#define BIT_GET_MACID127_96_RELEASE(x) \ 12533 (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) 12534 12535/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ 12536 12537#define BIT_MACID_VALUE BIT(7) 12538 12539#define BIT_SHIFT_MACID_OFFSET 0 12540#define BIT_MASK_MACID_OFFSET 0x7f 12541#define BIT_MACID_OFFSET(x) \ 12542 (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) 12543#define BIT_GET_MACID_OFFSET(x) \ 12544 (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) 12545 12546/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ 12547 12548#define BIT_SHIFT_VI_FAST_EDCA_TO 24 12549#define BIT_MASK_VI_FAST_EDCA_TO 0xff 12550#define BIT_VI_FAST_EDCA_TO(x) \ 12551 (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) 12552#define BIT_GET_VI_FAST_EDCA_TO(x) \ 12553 (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) 12554 12555#define BIT_VI_THRESHOLD_SEL BIT(23) 12556 12557#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 12558#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f 12559#define BIT_VI_FAST_EDCA_PKT_TH(x) \ 12560 (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) 12561#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \ 12562 (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) 12563 12564#define BIT_SHIFT_VO_FAST_EDCA_TO 8 12565#define BIT_MASK_VO_FAST_EDCA_TO 0xff 12566#define BIT_VO_FAST_EDCA_TO(x) \ 12567 (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) 12568#define BIT_GET_VO_FAST_EDCA_TO(x) \ 12569 (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) 12570 12571#define BIT_VO_THRESHOLD_SEL BIT(7) 12572 12573#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 12574#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f 12575#define BIT_VO_FAST_EDCA_PKT_TH(x) \ 12576 (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) 12577#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \ 12578 (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) 12579 12580/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ 12581 12582#define BIT_SHIFT_BK_FAST_EDCA_TO 24 12583#define BIT_MASK_BK_FAST_EDCA_TO 0xff 12584#define BIT_BK_FAST_EDCA_TO(x) \ 12585 (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) 12586#define BIT_GET_BK_FAST_EDCA_TO(x) \ 12587 (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) 12588 12589#define BIT_BK_THRESHOLD_SEL BIT(23) 12590 12591#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 12592#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f 12593#define BIT_BK_FAST_EDCA_PKT_TH(x) \ 12594 (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) 12595#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \ 12596 (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) 12597 12598#define BIT_SHIFT_BE_FAST_EDCA_TO 8 12599#define BIT_MASK_BE_FAST_EDCA_TO 0xff 12600#define BIT_BE_FAST_EDCA_TO(x) \ 12601 (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) 12602#define BIT_GET_BE_FAST_EDCA_TO(x) \ 12603 (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) 12604 12605#define BIT_BE_THRESHOLD_SEL BIT(7) 12606 12607#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 12608#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f 12609#define BIT_BE_FAST_EDCA_PKT_TH(x) \ 12610 (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) 12611#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \ 12612 (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) 12613 12614/* 2 REG_MACID_DROP0 (Offset 0x1450) */ 12615 12616#define BIT_SHIFT_MACID31_0_DROP 0 12617#define BIT_MASK_MACID31_0_DROP 0xffffffffL 12618#define BIT_MACID31_0_DROP(x) \ 12619 (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) 12620#define BIT_GET_MACID31_0_DROP(x) \ 12621 (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) 12622 12623/* 2 REG_MACID_DROP1 (Offset 0x1454) */ 12624 12625#define BIT_SHIFT_MACID63_32_DROP 0 12626#define BIT_MASK_MACID63_32_DROP 0xffffffffL 12627#define BIT_MACID63_32_DROP(x) \ 12628 (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) 12629#define BIT_GET_MACID63_32_DROP(x) \ 12630 (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) 12631 12632/* 2 REG_MACID_DROP2 (Offset 0x1458) */ 12633 12634#define BIT_SHIFT_MACID95_64_DROP 0 12635#define BIT_MASK_MACID95_64_DROP 0xffffffffL 12636#define BIT_MACID95_64_DROP(x) \ 12637 (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) 12638#define BIT_GET_MACID95_64_DROP(x) \ 12639 (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) 12640 12641/* 2 REG_MACID_DROP3 (Offset 0x145C) */ 12642 12643#define BIT_SHIFT_MACID127_96_DROP 0 12644#define BIT_MASK_MACID127_96_DROP 0xffffffffL 12645#define BIT_MACID127_96_DROP(x) \ 12646 (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) 12647#define BIT_GET_MACID127_96_DROP(x) \ 12648 (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) 12649 12650/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ 12651 12652#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 12653#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL 12654#define BIT_R_MACID_RELEASE_SUCCESS_0(x) \ 12655 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \ 12656 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) 12657#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \ 12658 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \ 12659 BIT_MASK_R_MACID_RELEASE_SUCCESS_0) 12660 12661/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ 12662 12663#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 12664#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL 12665#define BIT_R_MACID_RELEASE_SUCCESS_1(x) \ 12666 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \ 12667 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) 12668#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \ 12669 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \ 12670 BIT_MASK_R_MACID_RELEASE_SUCCESS_1) 12671 12672/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ 12673 12674#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 12675#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL 12676#define BIT_R_MACID_RELEASE_SUCCESS_2(x) \ 12677 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \ 12678 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) 12679#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \ 12680 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \ 12681 BIT_MASK_R_MACID_RELEASE_SUCCESS_2) 12682 12683/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ 12684 12685#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 12686#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL 12687#define BIT_R_MACID_RELEASE_SUCCESS_3(x) \ 12688 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \ 12689 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) 12690#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \ 12691 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \ 12692 BIT_MASK_R_MACID_RELEASE_SUCCESS_3) 12693 12694/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ 12695 12696#define BIT_R_MGG_FIFO_EN BIT(31) 12697 12698#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 12699#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 12700#define BIT_R_MGG_FIFO_PG_SIZE(x) \ 12701 (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) 12702#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \ 12703 (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) 12704 12705#define BIT_SHIFT_R_MGG_FIFO_START_PG 16 12706#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff 12707#define BIT_R_MGG_FIFO_START_PG(x) \ 12708 (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) 12709#define BIT_GET_R_MGG_FIFO_START_PG(x) \ 12710 (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) 12711 12712#define BIT_SHIFT_R_MGG_FIFO_SIZE 14 12713#define BIT_MASK_R_MGG_FIFO_SIZE 0x3 12714#define BIT_R_MGG_FIFO_SIZE(x) \ 12715 (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) 12716#define BIT_GET_R_MGG_FIFO_SIZE(x) \ 12717 (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) 12718 12719#define BIT_R_MGG_FIFO_PAUSE BIT(13) 12720 12721#define BIT_SHIFT_R_MGG_FIFO_RPTR 8 12722#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f 12723#define BIT_R_MGG_FIFO_RPTR(x) \ 12724 (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) 12725#define BIT_GET_R_MGG_FIFO_RPTR(x) \ 12726 (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) 12727 12728#define BIT_R_MGG_FIFO_OV BIT(7) 12729#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) 12730#define BIT_R_EN_CPU_LIFETIME BIT(5) 12731 12732#define BIT_SHIFT_R_MGG_FIFO_WPTR 0 12733#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f 12734#define BIT_R_MGG_FIFO_WPTR(x) \ 12735 (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) 12736#define BIT_GET_R_MGG_FIFO_WPTR(x) \ 12737 (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) 12738 12739/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ 12740 12741#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 12742#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff 12743#define BIT_R_MGG_FIFO_INT_FLAG(x) \ 12744 (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) 12745#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \ 12746 (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) 12747 12748#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 12749#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff 12750#define BIT_R_MGG_FIFO_INT_MASK(x) \ 12751 (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) 12752#define BIT_GET_R_MGG_FIFO_INT_MASK(x) \ 12753 (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) 12754 12755/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ 12756 12757#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 12758#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff 12759#define BIT_R_MGG_FIFO_LIFETIME(x) \ 12760 (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) 12761#define BIT_GET_R_MGG_FIFO_LIFETIME(x) \ 12762 (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) 12763 12764#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 12765#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff 12766#define BIT_R_MGG_FIFO_VALID_MAP(x) \ 12767 (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \ 12768 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) 12769#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \ 12770 (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \ 12771 BIT_MASK_R_MGG_FIFO_VALID_MAP) 12772 12773/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ 12774 12775#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 12776#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f 12777#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ 12778 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \ 12779 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) 12780#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ 12781 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \ 12782 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) 12783 12784#define BIT_SHIFT_P2PON_DIS_TXTIME 0 12785#define BIT_MASK_P2PON_DIS_TXTIME 0xff 12786#define BIT_P2PON_DIS_TXTIME(x) \ 12787 (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) 12788#define BIT_GET_P2PON_DIS_TXTIME(x) \ 12789 (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) 12790 12791/* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */ 12792 12793#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0 12794#define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff 12795#define BIT_MACID_SHCUT_OFFSET_V1(x) \ 12796 (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) \ 12797 << BIT_SHIFT_MACID_SHCUT_OFFSET_V1) 12798#define BIT_GET_MACID_SHCUT_OFFSET_V1(x) \ 12799 (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & \ 12800 BIT_MASK_MACID_SHCUT_OFFSET_V1) 12801 12802/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ 12803 12804#define BIT_R_EN_REVERS_GTAB BIT(6) 12805 12806#define BIT_SHIFT_R_MU_TABLE_VALID 0 12807#define BIT_MASK_R_MU_TABLE_VALID 0x3f 12808#define BIT_R_MU_TABLE_VALID(x) \ 12809 (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) 12810#define BIT_GET_R_MU_TABLE_VALID(x) \ 12811 (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) 12812 12813#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 12814#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL 12815#define BIT_R_MU_STA_GTAB_VALID(x) \ 12816 (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) 12817#define BIT_GET_R_MU_STA_GTAB_VALID(x) \ 12818 (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) 12819 12820#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 12821#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL 12822#define BIT_R_MU_STA_GTAB_POSITION(x) \ 12823 (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \ 12824 << BIT_SHIFT_R_MU_STA_GTAB_POSITION) 12825#define BIT_GET_R_MU_STA_GTAB_POSITION(x) \ 12826 (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \ 12827 BIT_MASK_R_MU_STA_GTAB_POSITION) 12828 12829/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ 12830 12831#define BIT_MU_DNGCNT_RST BIT(20) 12832 12833#define BIT_SHIFT_MU_DBGCNT_SEL 16 12834#define BIT_MASK_MU_DBGCNT_SEL 0xf 12835#define BIT_MU_DBGCNT_SEL(x) \ 12836 (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) 12837#define BIT_GET_MU_DBGCNT_SEL(x) \ 12838 (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) 12839 12840#define BIT_SHIFT_MU_DNGCNT 0 12841#define BIT_MASK_MU_DNGCNT 0xffff 12842#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) 12843#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) 12844 12845/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ 12846 12847#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 12848#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL 12849#define BIT_CPUMGQ_TX_TIMER_V1(x) \ 12850 (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) 12851#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \ 12852 (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) 12853 12854/* 2 REG_PS_TIMER_A (Offset 0x1504) */ 12855 12856#define BIT_SHIFT_PS_TIMER_A_V1 0 12857#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL 12858#define BIT_PS_TIMER_A_V1(x) \ 12859 (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) 12860#define BIT_GET_PS_TIMER_A_V1(x) \ 12861 (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) 12862 12863/* 2 REG_PS_TIMER_B (Offset 0x1508) */ 12864 12865#define BIT_SHIFT_PS_TIMER_B_V1 0 12866#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL 12867#define BIT_PS_TIMER_B_V1(x) \ 12868 (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) 12869#define BIT_GET_PS_TIMER_B_V1(x) \ 12870 (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) 12871 12872/* 2 REG_PS_TIMER_C (Offset 0x150C) */ 12873 12874#define BIT_SHIFT_PS_TIMER_C_V1 0 12875#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL 12876#define BIT_PS_TIMER_C_V1(x) \ 12877 (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) 12878#define BIT_GET_PS_TIMER_C_V1(x) \ 12879 (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) 12880 12881/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ 12882 12883#define BIT_CPUMGQ_TIMER_EN BIT(31) 12884#define BIT_CPUMGQ_TX_EN BIT(28) 12885 12886#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 12887#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 12888#define BIT_CPUMGQ_TIMER_TSF_SEL(x) \ 12889 (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \ 12890 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) 12891#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \ 12892 (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \ 12893 BIT_MASK_CPUMGQ_TIMER_TSF_SEL) 12894 12895#define BIT_PS_TIMER_C_EN BIT(23) 12896 12897#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 12898#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 12899#define BIT_PS_TIMER_C_TSF_SEL(x) \ 12900 (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) 12901#define BIT_GET_PS_TIMER_C_TSF_SEL(x) \ 12902 (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) 12903 12904#define BIT_PS_TIMER_B_EN BIT(15) 12905 12906#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 12907#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 12908#define BIT_PS_TIMER_B_TSF_SEL(x) \ 12909 (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) 12910#define BIT_GET_PS_TIMER_B_TSF_SEL(x) \ 12911 (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) 12912 12913#define BIT_PS_TIMER_A_EN BIT(7) 12914 12915#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 12916#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 12917#define BIT_PS_TIMER_A_TSF_SEL(x) \ 12918 (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) 12919#define BIT_GET_PS_TIMER_A_TSF_SEL(x) \ 12920 (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) 12921 12922/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ 12923 12924#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 12925#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff 12926#define BIT_CPUMGQ_TX_TIMER_EARLY(x) \ 12927 (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \ 12928 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) 12929#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \ 12930 (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \ 12931 BIT_MASK_CPUMGQ_TX_TIMER_EARLY) 12932 12933/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ 12934 12935#define BIT_SHIFT_PS_TIMER_A_EARLY 0 12936#define BIT_MASK_PS_TIMER_A_EARLY 0xff 12937#define BIT_PS_TIMER_A_EARLY(x) \ 12938 (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) 12939#define BIT_GET_PS_TIMER_A_EARLY(x) \ 12940 (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) 12941 12942/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ 12943 12944#define BIT_SHIFT_PS_TIMER_B_EARLY 0 12945#define BIT_MASK_PS_TIMER_B_EARLY 0xff 12946#define BIT_PS_TIMER_B_EARLY(x) \ 12947 (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) 12948#define BIT_GET_PS_TIMER_B_EARLY(x) \ 12949 (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) 12950 12951/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ 12952 12953#define BIT_SHIFT_PS_TIMER_C_EARLY 0 12954#define BIT_MASK_PS_TIMER_C_EARLY 0xff 12955#define BIT_PS_TIMER_C_EARLY(x) \ 12956 (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) 12957#define BIT_GET_PS_TIMER_C_EARLY(x) \ 12958 (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) 12959 12960/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ 12961 12962#define BIT_SHIFT_DTIM_CNT2 24 12963#define BIT_MASK_DTIM_CNT2 0xff 12964#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) 12965#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) 12966 12967#define BIT_SHIFT_DTIM_PERIOD2 16 12968#define BIT_MASK_DTIM_PERIOD2 0xff 12969#define BIT_DTIM_PERIOD2(x) \ 12970 (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) 12971#define BIT_GET_DTIM_PERIOD2(x) \ 12972 (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) 12973 12974#define BIT_DTIM2 BIT(15) 12975#define BIT_TIM2 BIT(14) 12976 12977#define BIT_SHIFT_PS_AID_2 0 12978#define BIT_MASK_PS_AID_2 0x7ff 12979#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) 12980#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) 12981 12982/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ 12983 12984#define BIT_SHIFT_DTIM_CNT3 24 12985#define BIT_MASK_DTIM_CNT3 0xff 12986#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) 12987#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) 12988 12989#define BIT_SHIFT_DTIM_PERIOD3 16 12990#define BIT_MASK_DTIM_PERIOD3 0xff 12991#define BIT_DTIM_PERIOD3(x) \ 12992 (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) 12993#define BIT_GET_DTIM_PERIOD3(x) \ 12994 (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) 12995 12996#define BIT_DTIM3 BIT(15) 12997#define BIT_TIM3 BIT(14) 12998 12999#define BIT_SHIFT_PS_AID_3 0 13000#define BIT_MASK_PS_AID_3 0x7ff
13001#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) 13002#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) 13003 13004/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ 13005 13006#define BIT_SHIFT_DTIM_CNT4 24 13007#define BIT_MASK_DTIM_CNT4 0xff 13008#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) 13009#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) 13010 13011#define BIT_SHIFT_DTIM_PERIOD4 16 13012#define BIT_MASK_DTIM_PERIOD4 0xff 13013#define BIT_DTIM_PERIOD4(x) \ 13014 (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) 13015#define BIT_GET_DTIM_PERIOD4(x) \ 13016 (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) 13017 13018#define BIT_DTIM4 BIT(15) 13019#define BIT_TIM4 BIT(14) 13020 13021#define BIT_SHIFT_PS_AID_4 0 13022#define BIT_MASK_PS_AID_4 0x7ff 13023#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) 13024#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) 13025 13026/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ 13027 13028#define BIT_SHIFT_A1_ADDR_MASK 0 13029#define BIT_MASK_A1_ADDR_MASK 0xffffffffL 13030#define BIT_A1_ADDR_MASK(x) \ 13031 (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) 13032#define BIT_GET_A1_ADDR_MASK(x) \ 13033 (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) 13034 13035/* 2 REG_MACID2 (Offset 0x1620) */ 13036 13037#define BIT_SHIFT_MACID2 0 13038#define BIT_MASK_MACID2 0xffffffffffffL 13039#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) 13040#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) 13041 13042/* 2 REG_BSSID2 (Offset 0x1628) */ 13043 13044#define BIT_SHIFT_BSSID2 0 13045#define BIT_MASK_BSSID2 0xffffffffffffL 13046#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) 13047#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) 13048 13049/* 2 REG_MACID3 (Offset 0x1630) */ 13050 13051#define BIT_SHIFT_MACID3 0 13052#define BIT_MASK_MACID3 0xffffffffffffL 13053#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) 13054#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) 13055 13056/* 2 REG_BSSID3 (Offset 0x1638) */ 13057 13058#define BIT_SHIFT_BSSID3 0 13059#define BIT_MASK_BSSID3 0xffffffffffffL 13060#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) 13061#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) 13062 13063/* 2 REG_MACID4 (Offset 0x1640) */ 13064 13065#define BIT_SHIFT_MACID4 0 13066#define BIT_MASK_MACID4 0xffffffffffffL 13067#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) 13068#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) 13069 13070/* 2 REG_BSSID4 (Offset 0x1648) */ 13071 13072#define BIT_SHIFT_BSSID4 0 13073#define BIT_MASK_BSSID4 0xffffffffffffL 13074#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) 13075#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) 13076 13077/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ 13078 13079#define BIT_CLI3_PWRBIT_OW_EN BIT(7) 13080#define BIT_CLI3_PWR_ST BIT(6) 13081#define BIT_CLI2_PWRBIT_OW_EN BIT(5) 13082#define BIT_CLI2_PWR_ST BIT(4) 13083#define BIT_CLI1_PWRBIT_OW_EN BIT(3) 13084#define BIT_CLI1_PWR_ST BIT(2) 13085#define BIT_CLI0_PWRBIT_OW_EN BIT(1) 13086#define BIT_CLI0_PWR_ST BIT(0) 13087 13088/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13089 13090#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) 13091 13092/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13093 13094#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) 13095 13096/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13097 13098#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 13099#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 13100#define BIT_WMAC_TXMU_ACKPOLICY(x) \ 13101 (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) 13102#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \ 13103 (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) 13104 13105#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 13106#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 13107#define BIT_WMAC_MU_BFEE_PORT_SEL(x) \ 13108 (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \ 13109 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) 13110#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \ 13111 (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \ 13112 BIT_MASK_WMAC_MU_BFEE_PORT_SEL) 13113 13114#define BIT_WMAC_MU_BFEE_DIS BIT(0) 13115 13116/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ 13117 13118#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 13119#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff 13120#define BIT_WMAC_PAUSE_BB_CLR_TH(x) \ 13121 (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \ 13122 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) 13123#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \ 13124 (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \ 13125 BIT_MASK_WMAC_PAUSE_BB_CLR_TH) 13126 13127/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ 13128 13129#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) 13130#define BIT_WMAC_ARB_SW_EN BIT(6) 13131 13132#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 13133#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f 13134#define BIT_WMAC_ARB_SW_STATE(x) \ 13135 (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) 13136#define BIT_GET_WMAC_ARB_SW_STATE(x) \ 13137 (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) 13138 13139/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ 13140 13141#define BIT_SHIFT_WMAC_MU_DBGSEL 5 13142#define BIT_MASK_WMAC_MU_DBGSEL 0x3 13143#define BIT_WMAC_MU_DBGSEL(x) \ 13144 (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) 13145#define BIT_GET_WMAC_MU_DBGSEL(x) \ 13146 (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) 13147 13148#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 13149#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f 13150#define BIT_WMAC_MU_CPRD_TIMEOUT(x) \ 13151 (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \ 13152 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) 13153#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \ 13154 (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \ 13155 BIT_MASK_WMAC_MU_CPRD_TIMEOUT) 13156 13157/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ 13158 13159#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) 13160#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) 13161 13162#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 13163#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 13164#define BIT_WMAC_MU_BFRPTSEG_SEL(x) \ 13165 (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \ 13166 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) 13167#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \ 13168 (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \ 13169 BIT_MASK_WMAC_MU_BFRPTSEG_SEL) 13170 13171#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 13172#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff 13173#define BIT_WMAC_MU_BF_MYAID(x) \ 13174 (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) 13175#define BIT_GET_WMAC_MU_BF_MYAID(x) \ 13176 (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) 13177 13178#define BIT_SHIFT_BFRPT_PARA 0 13179#define BIT_MASK_BFRPT_PARA 0xfff 13180#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) 13181#define BIT_GET_BFRPT_PARA(x) \ 13182 (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) 13183 13184/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ 13185 13186#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 13187#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 13188#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \ 13189 (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \ 13190 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) 13191#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \ 13192 (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \ 13193 BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) 13194 13195/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ 13196 13197#define BIT_STATUS_BFEE2 BIT(10) 13198#define BIT_WMAC_MU_BFEE2_EN BIT(9) 13199 13200#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 13201#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff 13202#define BIT_WMAC_MU_BFEE2_AID(x) \ 13203 (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) 13204#define BIT_GET_WMAC_MU_BFEE2_AID(x) \ 13205 (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) 13206 13207/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ 13208 13209#define BIT_STATUS_BFEE3 BIT(10) 13210#define BIT_WMAC_MU_BFEE3_EN BIT(9) 13211 13212#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 13213#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff 13214#define BIT_WMAC_MU_BFEE3_AID(x) \ 13215 (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) 13216#define BIT_GET_WMAC_MU_BFEE3_AID(x) \ 13217 (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) 13218 13219/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ 13220 13221#define BIT_STATUS_BFEE4 BIT(10) 13222#define BIT_WMAC_MU_BFEE4_EN BIT(9) 13223 13224#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 13225#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff 13226#define BIT_WMAC_MU_BFEE4_AID(x) \ 13227 (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) 13228#define BIT_GET_WMAC_MU_BFEE4_AID(x) \ 13229 (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) 13230 13231/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ 13232 13233#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) 13234#define BIT_R_WMAC_RXRST_DLY BIT(54) 13235#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) 13236#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) 13237#define BIT_STATUS_BFEE5 BIT(10) 13238 13239/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ 13240 13241#define BIT_WMAC_MU_BFEE5_EN BIT(9) 13242 13243#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 13244#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff 13245#define BIT_WMAC_MU_BFEE5_AID(x) \ 13246 (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) 13247#define BIT_GET_WMAC_MU_BFEE5_AID(x) \ 13248 (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) 13249 13250/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ 13251 13252#define BIT_STATUS_BFEE6 BIT(10) 13253#define BIT_WMAC_MU_BFEE6_EN BIT(9) 13254 13255#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 13256#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff 13257#define BIT_WMAC_MU_BFEE6_AID(x) \ 13258 (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) 13259#define BIT_GET_WMAC_MU_BFEE6_AID(x) \ 13260 (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) 13261 13262/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ 13263 13264#define BIT_BIT_STATUS_BFEE4 BIT(10) 13265#define BIT_WMAC_MU_BFEE7_EN BIT(9) 13266 13267#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 13268#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff 13269#define BIT_WMAC_MU_BFEE7_AID(x) \ 13270 (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) 13271#define BIT_GET_WMAC_MU_BFEE7_AID(x) \ 13272 (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) 13273 13274/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ 13275 13276#define BIT_RST_ALL_COUNTER BIT(31) 13277 13278#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 13279#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff 13280#define BIT_ABORT_RX_VBON_COUNTER(x) \ 13281 (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \ 13282 << BIT_SHIFT_ABORT_RX_VBON_COUNTER) 13283#define BIT_GET_ABORT_RX_VBON_COUNTER(x) \ 13284 (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \ 13285 BIT_MASK_ABORT_RX_VBON_COUNTER) 13286 13287#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 13288#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff 13289#define BIT_ABORT_RX_RDRDY_COUNTER(x) \ 13290 (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \ 13291 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) 13292#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \ 13293 (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \ 13294 BIT_MASK_ABORT_RX_RDRDY_COUNTER) 13295 13296#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 13297#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff 13298#define BIT_VBON_EARLY_FALLING_COUNTER(x) \ 13299 (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \ 13300 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) 13301#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \ 13302 (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \ 13303 BIT_MASK_VBON_EARLY_FALLING_COUNTER) 13304 13305/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ 13306 13307#define BIT_WMAC_PLCP_TRX_SEL BIT(31) 13308 13309#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 13310#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 13311#define BIT_WMAC_PLCP_RDSIG_SEL(x) \ 13312 (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) 13313#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \ 13314 (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) 13315 13316#define BIT_SHIFT_WMAC_RATE_IDX 24 13317#define BIT_MASK_WMAC_RATE_IDX 0xf 13318#define BIT_WMAC_RATE_IDX(x) \ 13319 (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) 13320#define BIT_GET_WMAC_RATE_IDX(x) \ 13321 (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) 13322 13323#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 13324#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff 13325#define BIT_WMAC_PLCP_RDSIG(x) \ 13326 (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) 13327#define BIT_GET_WMAC_PLCP_RDSIG(x) \ 13328 (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) 13329 13330/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ 13331 13332#define BIT_WMAC_MUTX_IDX BIT(24) 13333 13334/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ 13335 13336#define BIT_SHIFT_TA0 0 13337#define BIT_MASK_TA0 0xffffffffffffL 13338#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) 13339#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) 13340 13341/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ 13342 13343#define BIT_SHIFT_TA1 0 13344#define BIT_MASK_TA1 0xffffffffffffL 13345#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) 13346#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) 13347 13348/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ 13349 13350#define BIT_SHIFT_TA2 0 13351#define BIT_MASK_TA2 0xffffffffffffL 13352#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) 13353#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) 13354 13355/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ 13356 13357#define BIT_SHIFT_TA3 0 13358#define BIT_MASK_TA3 0xffffffffffffL 13359#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) 13360#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) 13361 13362/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ 13363 13364#define BIT_SHIFT_TA4 0 13365#define BIT_MASK_TA4 0xffffffffffffL 13366#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) 13367#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) 13368 13369/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ 13370 13371#define BIT_LTECOEX_ACCESS_START_V1 BIT(31) 13372#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) 13373#define BIT_LTECOEX_READY_BIT_V1 BIT(29) 13374 13375#define BIT_SHIFT_WRITE_BYTE_EN_V1 16 13376#define BIT_MASK_WRITE_BYTE_EN_V1 0xf 13377#define BIT_WRITE_BYTE_EN_V1(x) \ 13378 (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) 13379#define BIT_GET_WRITE_BYTE_EN_V1(x) \ 13380 (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) 13381 13382#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 13383#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff 13384#define BIT_LTECOEX_REG_ADDR_V1(x) \ 13385 (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) 13386#define BIT_GET_LTECOEX_REG_ADDR_V1(x) \ 13387 (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) 13388 13389/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ 13390 13391#define BIT_SHIFT_LTECOEX_W_DATA_V1 0 13392#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL 13393#define BIT_LTECOEX_W_DATA_V1(x) \ 13394 (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) 13395#define BIT_GET_LTECOEX_W_DATA_V1(x) \ 13396 (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) 13397 13398/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ 13399 13400#define BIT_SHIFT_LTECOEX_R_DATA_V1 0 13401#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL 13402#define BIT_LTECOEX_R_DATA_V1(x) \ 13403 (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) 13404#define BIT_GET_LTECOEX_R_DATA_V1(x) \ 13405 (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) 13406 13407#endif /* __RTL_WLAN_BITDEF_H__ */ 13408