1
2
3
4
5
6
7#include <linux/module.h>
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/fs.h>
11#include <linux/slab.h>
12#include <linux/types.h>
13#include <linux/cdev.h>
14#include <linux/uaccess.h>
15#include <linux/device.h>
16#include <linux/spi/spi.h>
17#include <linux/of_gpio.h>
18
19#include <linux/string.h>
20#include "wilc_wlan_if.h"
21#include "wilc_wlan.h"
22#include "wilc_wfi_netdevice.h"
23
24struct wilc_spi {
25 int crc_off;
26 int nint;
27 int has_thrpt_enh;
28};
29
30static struct wilc_spi g_spi;
31static const struct wilc_hif_func wilc_hif_spi;
32
33static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
34static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
35
36
37
38
39
40
41
42static const u8 crc7_syndrome_table[256] = {
43 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
44 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
45 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
46 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
47 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
48 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
49 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
50 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
51 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
52 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
53 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
54 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
55 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
56 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
57 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
58 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
59 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
60 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
61 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
62 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
63 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
64 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
65 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
66 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
67 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
68 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
69 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
70 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
71 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
72 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
73 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
74 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
75};
76
77static u8 crc7_byte(u8 crc, u8 data)
78{
79 return crc7_syndrome_table[(crc << 1) ^ data];
80}
81
82static u8 crc7(u8 crc, const u8 *buffer, u32 len)
83{
84 while (len--)
85 crc = crc7_byte(crc, *buffer++);
86 return crc;
87}
88
89
90
91
92
93
94
95#define CMD_DMA_WRITE 0xc1
96#define CMD_DMA_READ 0xc2
97#define CMD_INTERNAL_WRITE 0xc3
98#define CMD_INTERNAL_READ 0xc4
99#define CMD_TERMINATE 0xc5
100#define CMD_REPEAT 0xc6
101#define CMD_DMA_EXT_WRITE 0xc7
102#define CMD_DMA_EXT_READ 0xc8
103#define CMD_SINGLE_WRITE 0xc9
104#define CMD_SINGLE_READ 0xca
105#define CMD_RESET 0xcf
106
107#define N_OK 1
108#define N_FAIL 0
109#define N_RESET -1
110#define N_RETRY -2
111
112#define DATA_PKT_SZ_256 256
113#define DATA_PKT_SZ_512 512
114#define DATA_PKT_SZ_1K 1024
115#define DATA_PKT_SZ_4K (4 * 1024)
116#define DATA_PKT_SZ_8K (8 * 1024)
117#define DATA_PKT_SZ DATA_PKT_SZ_8K
118
119#define USE_SPI_DMA 0
120
121static int wilc_bus_probe(struct spi_device *spi)
122{
123 int ret, gpio;
124 struct wilc *wilc;
125
126 gpio = of_get_gpio(spi->dev.of_node, 0);
127 if (gpio < 0)
128 gpio = GPIO_NUM;
129
130 ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
131 if (ret)
132 return ret;
133
134 spi_set_drvdata(spi, wilc);
135 wilc->dev = &spi->dev;
136
137 return 0;
138}
139
140static int wilc_bus_remove(struct spi_device *spi)
141{
142 wilc_netdev_cleanup(spi_get_drvdata(spi));
143 return 0;
144}
145
146static const struct of_device_id wilc1000_of_match[] = {
147 { .compatible = "atmel,wilc_spi", },
148 {}
149};
150MODULE_DEVICE_TABLE(of, wilc1000_of_match);
151
152static struct spi_driver wilc1000_spi_driver = {
153 .driver = {
154 .name = MODALIAS,
155 .of_match_table = wilc1000_of_match,
156 },
157 .probe = wilc_bus_probe,
158 .remove = wilc_bus_remove,
159};
160module_spi_driver(wilc1000_spi_driver);
161MODULE_LICENSE("GPL");
162
163static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
164{
165 struct spi_device *spi = to_spi_device(wilc->dev);
166 int ret;
167 struct spi_message msg;
168
169 if (len > 0 && b) {
170 struct spi_transfer tr = {
171 .tx_buf = b,
172 .len = len,
173 .delay_usecs = 0,
174 };
175 char *r_buffer = kzalloc(len, GFP_KERNEL);
176
177 if (!r_buffer)
178 return -ENOMEM;
179
180 tr.rx_buf = r_buffer;
181 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
182
183 memset(&msg, 0, sizeof(msg));
184 spi_message_init(&msg);
185 msg.spi = spi;
186 msg.is_dma_mapped = USE_SPI_DMA;
187 spi_message_add_tail(&tr, &msg);
188
189 ret = spi_sync(spi, &msg);
190 if (ret < 0)
191 dev_err(&spi->dev, "SPI transaction failed\n");
192
193 kfree(r_buffer);
194 } else {
195 dev_err(&spi->dev,
196 "can't write data with the following length: %d\n",
197 len);
198 ret = -EINVAL;
199 }
200
201 return ret;
202}
203
204static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
205{
206 struct spi_device *spi = to_spi_device(wilc->dev);
207 int ret;
208
209 if (rlen > 0) {
210 struct spi_message msg;
211 struct spi_transfer tr = {
212 .rx_buf = rb,
213 .len = rlen,
214 .delay_usecs = 0,
215
216 };
217 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
218
219 if (!t_buffer)
220 return -ENOMEM;
221
222 tr.tx_buf = t_buffer;
223
224 memset(&msg, 0, sizeof(msg));
225 spi_message_init(&msg);
226 msg.spi = spi;
227 msg.is_dma_mapped = USE_SPI_DMA;
228 spi_message_add_tail(&tr, &msg);
229
230 ret = spi_sync(spi, &msg);
231 if (ret < 0)
232 dev_err(&spi->dev, "SPI transaction failed\n");
233 kfree(t_buffer);
234 } else {
235 dev_err(&spi->dev,
236 "can't read data with the following length: %u\n",
237 rlen);
238 ret = -EINVAL;
239 }
240
241 return ret;
242}
243
244static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
245{
246 struct spi_device *spi = to_spi_device(wilc->dev);
247 int ret;
248
249 if (rlen > 0) {
250 struct spi_message msg;
251 struct spi_transfer tr = {
252 .rx_buf = rb,
253 .tx_buf = wb,
254 .len = rlen,
255 .bits_per_word = 8,
256 .delay_usecs = 0,
257
258 };
259
260 memset(&msg, 0, sizeof(msg));
261 spi_message_init(&msg);
262 msg.spi = spi;
263 msg.is_dma_mapped = USE_SPI_DMA;
264
265 spi_message_add_tail(&tr, &msg);
266 ret = spi_sync(spi, &msg);
267 if (ret < 0)
268 dev_err(&spi->dev, "SPI transaction failed\n");
269 } else {
270 dev_err(&spi->dev,
271 "can't read data with the following length: %u\n",
272 rlen);
273 ret = -EINVAL;
274 }
275
276 return ret;
277}
278
279static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
280 u8 clockless)
281{
282 struct spi_device *spi = to_spi_device(wilc->dev);
283 u8 wb[32], rb[32];
284 u8 wix, rix;
285 u32 len2;
286 u8 rsp;
287 int len = 0;
288 int result = N_OK;
289
290 wb[0] = cmd;
291 switch (cmd) {
292 case CMD_SINGLE_READ:
293 wb[1] = (u8)(adr >> 16);
294 wb[2] = (u8)(adr >> 8);
295 wb[3] = (u8)adr;
296 len = 5;
297 break;
298
299 case CMD_INTERNAL_READ:
300 wb[1] = (u8)(adr >> 8);
301 if (clockless == 1)
302 wb[1] |= BIT(7);
303 wb[2] = (u8)adr;
304 wb[3] = 0x00;
305 len = 5;
306 break;
307
308 case CMD_TERMINATE:
309 wb[1] = 0x00;
310 wb[2] = 0x00;
311 wb[3] = 0x00;
312 len = 5;
313 break;
314
315 case CMD_REPEAT:
316 wb[1] = 0x00;
317 wb[2] = 0x00;
318 wb[3] = 0x00;
319 len = 5;
320 break;
321
322 case CMD_RESET:
323 wb[1] = 0xff;
324 wb[2] = 0xff;
325 wb[3] = 0xff;
326 len = 5;
327 break;
328
329 case CMD_DMA_WRITE:
330 case CMD_DMA_READ:
331 wb[1] = (u8)(adr >> 16);
332 wb[2] = (u8)(adr >> 8);
333 wb[3] = (u8)adr;
334 wb[4] = (u8)(sz >> 8);
335 wb[5] = (u8)(sz);
336 len = 7;
337 break;
338
339 case CMD_DMA_EXT_WRITE:
340 case CMD_DMA_EXT_READ:
341 wb[1] = (u8)(adr >> 16);
342 wb[2] = (u8)(adr >> 8);
343 wb[3] = (u8)adr;
344 wb[4] = (u8)(sz >> 16);
345 wb[5] = (u8)(sz >> 8);
346 wb[6] = (u8)(sz);
347 len = 8;
348 break;
349
350 case CMD_INTERNAL_WRITE:
351 wb[1] = (u8)(adr >> 8);
352 if (clockless == 1)
353 wb[1] |= BIT(7);
354 wb[2] = (u8)(adr);
355 wb[3] = b[3];
356 wb[4] = b[2];
357 wb[5] = b[1];
358 wb[6] = b[0];
359 len = 8;
360 break;
361
362 case CMD_SINGLE_WRITE:
363 wb[1] = (u8)(adr >> 16);
364 wb[2] = (u8)(adr >> 8);
365 wb[3] = (u8)(adr);
366 wb[4] = b[3];
367 wb[5] = b[2];
368 wb[6] = b[1];
369 wb[7] = b[0];
370 len = 9;
371 break;
372
373 default:
374 result = N_FAIL;
375 break;
376 }
377
378 if (result != N_OK)
379 return result;
380
381 if (!g_spi.crc_off)
382 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
383 else
384 len -= 1;
385
386#define NUM_SKIP_BYTES (1)
387#define NUM_RSP_BYTES (2)
388#define NUM_DATA_HDR_BYTES (1)
389#define NUM_DATA_BYTES (4)
390#define NUM_CRC_BYTES (2)
391#define NUM_DUMMY_BYTES (3)
392 if ((cmd == CMD_RESET) ||
393 (cmd == CMD_TERMINATE) ||
394 (cmd == CMD_REPEAT)) {
395 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
396 } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
397 if (!g_spi.crc_off) {
398 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
399 + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
400 } else {
401 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
402 + NUM_DUMMY_BYTES);
403 }
404 } else {
405 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
406 }
407#undef NUM_DUMMY_BYTES
408
409 if (len2 > ARRAY_SIZE(wb)) {
410 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
411 len2, ARRAY_SIZE(wb));
412 return N_FAIL;
413 }
414
415 for (wix = len; wix < len2; wix++)
416 wb[wix] = 0;
417 rix = len;
418
419 if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
420 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
421 return N_FAIL;
422 }
423
424
425
426
427 if ((cmd == CMD_RESET) ||
428 (cmd == CMD_TERMINATE) ||
429 (cmd == CMD_REPEAT)) {
430 rix++;
431 }
432
433
434 rsp = rb[rix++];
435
436
437
438 if (rsp != cmd) {
439 dev_err(&spi->dev,
440 "Failed cmd response, cmd (%02x), resp (%02x)\n",
441 cmd, rsp);
442 return N_FAIL;
443 }
444
445
446
447
448 rsp = rb[rix++];
449 if (rsp != 0x00) {
450 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
451 rsp);
452 return N_FAIL;
453 }
454
455 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ) ||
456 (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
457 int retry;
458
459 u8 crc[2];
460
461
462
463 retry = 100;
464 do {
465
466 if (rix < len2) {
467 rsp = rb[rix++];
468 } else {
469 retry = 0;
470 break;
471 }
472 if (((rsp >> 4) & 0xf) == 0xf)
473 break;
474 } while (retry--);
475
476 if (retry <= 0) {
477 dev_err(&spi->dev,
478 "Error, data read response (%02x)\n", rsp);
479 return N_RESET;
480 }
481
482 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
483
484
485
486 if ((rix + 3) < len2) {
487 b[0] = rb[rix++];
488 b[1] = rb[rix++];
489 b[2] = rb[rix++];
490 b[3] = rb[rix++];
491 } else {
492 dev_err(&spi->dev,
493 "buffer overrun when reading data.\n");
494 return N_FAIL;
495 }
496
497 if (!g_spi.crc_off) {
498
499
500
501 if ((rix + 1) < len2) {
502 crc[0] = rb[rix++];
503 crc[1] = rb[rix++];
504 } else {
505 dev_err(&spi->dev, "buffer overrun when reading crc.\n");
506 return N_FAIL;
507 }
508 }
509 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
510 int ix;
511
512
513 for (ix = 0; (rix < len2) && (ix < sz); )
514 b[ix++] = rb[rix++];
515
516 sz -= ix;
517
518 if (sz > 0) {
519 int nbytes;
520
521 if (sz <= (DATA_PKT_SZ - ix))
522 nbytes = sz;
523 else
524 nbytes = DATA_PKT_SZ - ix;
525
526
527
528
529 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
530 dev_err(&spi->dev, "Failed data block read, bus error...\n");
531 result = N_FAIL;
532 goto _error_;
533 }
534
535
536
537
538 if (!g_spi.crc_off) {
539 if (wilc_spi_rx(wilc, crc, 2)) {
540 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
541 result = N_FAIL;
542 goto _error_;
543 }
544 }
545
546 ix += nbytes;
547 sz -= nbytes;
548 }
549
550
551 while (sz > 0) {
552 int nbytes;
553
554 if (sz <= DATA_PKT_SZ)
555 nbytes = sz;
556 else
557 nbytes = DATA_PKT_SZ;
558
559
560
561
562
563
564
565
566
567 retry = 10;
568 do {
569 if (wilc_spi_rx(wilc, &rsp, 1)) {
570 dev_err(&spi->dev, "Failed data response read, bus error...\n");
571 result = N_FAIL;
572 break;
573 }
574 if (((rsp >> 4) & 0xf) == 0xf)
575 break;
576 } while (retry--);
577
578 if (result == N_FAIL)
579 break;
580
581
582
583
584 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
585 dev_err(&spi->dev, "Failed data block read, bus error...\n");
586 result = N_FAIL;
587 break;
588 }
589
590
591
592
593 if (!g_spi.crc_off) {
594 if (wilc_spi_rx(wilc, crc, 2)) {
595 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
596 result = N_FAIL;
597 break;
598 }
599 }
600
601 ix += nbytes;
602 sz -= nbytes;
603 }
604 }
605 }
606_error_:
607 return result;
608}
609
610static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
611{
612 struct spi_device *spi = to_spi_device(wilc->dev);
613 int ix, nbytes;
614 int result = 1;
615 u8 cmd, order, crc[2] = {0};
616
617
618
619
620
621 ix = 0;
622 do {
623 if (sz <= DATA_PKT_SZ)
624 nbytes = sz;
625 else
626 nbytes = DATA_PKT_SZ;
627
628
629
630
631 cmd = 0xf0;
632 if (ix == 0) {
633 if (sz <= DATA_PKT_SZ)
634
635 order = 0x3;
636 else
637 order = 0x1;
638 } else {
639 if (sz <= DATA_PKT_SZ)
640 order = 0x3;
641 else
642 order = 0x2;
643 }
644 cmd |= order;
645 if (wilc_spi_tx(wilc, &cmd, 1)) {
646 dev_err(&spi->dev,
647 "Failed data block cmd write, bus error...\n");
648 result = N_FAIL;
649 break;
650 }
651
652
653
654
655 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
656 dev_err(&spi->dev,
657 "Failed data block write, bus error...\n");
658 result = N_FAIL;
659 break;
660 }
661
662
663
664
665 if (!g_spi.crc_off) {
666 if (wilc_spi_tx(wilc, crc, 2)) {
667 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
668 result = N_FAIL;
669 break;
670 }
671 }
672
673
674
675
676 ix += nbytes;
677 sz -= nbytes;
678 } while (sz);
679
680 return result;
681}
682
683
684
685
686
687
688
689static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
690{
691 struct spi_device *spi = to_spi_device(wilc->dev);
692 int result;
693
694 dat = cpu_to_le32(dat);
695 result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
696 0);
697 if (result != N_OK)
698 dev_err(&spi->dev, "Failed internal write cmd...\n");
699
700 return result;
701}
702
703static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
704{
705 struct spi_device *spi = to_spi_device(wilc->dev);
706 int result;
707
708 result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
709 0);
710 if (result != N_OK) {
711 dev_err(&spi->dev, "Failed internal read cmd...\n");
712 return 0;
713 }
714
715 *data = cpu_to_le32(*data);
716
717 return 1;
718}
719
720
721
722
723
724
725
726static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
727{
728 struct spi_device *spi = to_spi_device(wilc->dev);
729 int result = N_OK;
730 u8 cmd = CMD_SINGLE_WRITE;
731 u8 clockless = 0;
732
733 data = cpu_to_le32(data);
734 if (addr < 0x30) {
735
736 cmd = CMD_INTERNAL_WRITE;
737 clockless = 1;
738 }
739
740 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
741 if (result != N_OK)
742 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
743
744 return result;
745}
746
747static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
748{
749 struct spi_device *spi = to_spi_device(wilc->dev);
750 int result;
751 u8 cmd = CMD_DMA_EXT_WRITE;
752
753
754
755
756 if (size <= 4)
757 return 0;
758
759 result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
760 if (result != N_OK) {
761 dev_err(&spi->dev,
762 "Failed cmd, write block (%08x)...\n", addr);
763 return 0;
764 }
765
766
767
768
769 result = spi_data_write(wilc, buf, size);
770 if (result != N_OK)
771 dev_err(&spi->dev, "Failed block data write...\n");
772
773 return 1;
774}
775
776static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
777{
778 struct spi_device *spi = to_spi_device(wilc->dev);
779 int result = N_OK;
780 u8 cmd = CMD_SINGLE_READ;
781 u8 clockless = 0;
782
783 if (addr < 0x30) {
784
785
786 cmd = CMD_INTERNAL_READ;
787 clockless = 1;
788 }
789
790 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
791 if (result != N_OK) {
792 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
793 return 0;
794 }
795
796 *data = cpu_to_le32(*data);
797
798 return 1;
799}
800
801static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
802{
803 struct spi_device *spi = to_spi_device(wilc->dev);
804 u8 cmd = CMD_DMA_EXT_READ;
805 int result;
806
807 if (size <= 4)
808 return 0;
809
810 result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
811 if (result != N_OK) {
812 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
813 return 0;
814 }
815
816 return 1;
817}
818
819
820
821
822
823
824
825static int _wilc_spi_deinit(struct wilc *wilc)
826{
827
828
829
830 return 1;
831}
832
833static int wilc_spi_init(struct wilc *wilc, bool resume)
834{
835 struct spi_device *spi = to_spi_device(wilc->dev);
836 u32 reg;
837 u32 chipid;
838
839 static int isinit;
840
841 if (isinit) {
842 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
843 dev_err(&spi->dev, "Fail cmd read chip id...\n");
844 return 0;
845 }
846 return 1;
847 }
848
849 memset(&g_spi, 0, sizeof(struct wilc_spi));
850
851
852
853
854 g_spi.crc_off = 0;
855
856
857
858 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
859
860
861
862 g_spi.crc_off = 1;
863 dev_err(&spi->dev, "Failed internal read protocol with CRC on, retrying with CRC off...\n");
864 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
865
866 dev_err(&spi->dev,
867 "Failed internal read protocol...\n");
868 return 0;
869 }
870 }
871 if (g_spi.crc_off == 0) {
872 reg &= ~0xc;
873 reg &= ~0x70;
874 reg |= (0x5 << 4);
875 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
876 dev_err(&spi->dev, "[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
877 return 0;
878 }
879 g_spi.crc_off = 1;
880 }
881
882
883
884
885 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
886 dev_err(&spi->dev, "Fail cmd read chip id...\n");
887 return 0;
888 }
889
890
891 g_spi.has_thrpt_enh = 1;
892
893 isinit = 1;
894
895 return 1;
896}
897
898static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
899{
900 struct spi_device *spi = to_spi_device(wilc->dev);
901 int ret;
902
903 if (g_spi.has_thrpt_enh) {
904 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
905 size);
906 *size = *size & IRQ_DMA_WD_CNT_MASK;
907 } else {
908 u32 tmp;
909 u32 byte_cnt;
910
911 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
912 &byte_cnt);
913 if (!ret) {
914 dev_err(&spi->dev,
915 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
916 goto _fail_;
917 }
918 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
919 *size = tmp;
920 }
921
922_fail_:
923 return ret;
924}
925
926static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
927{
928 struct spi_device *spi = to_spi_device(wilc->dev);
929 int ret;
930 u32 tmp;
931 u32 byte_cnt;
932 int happened, j;
933 u32 unknown_mask;
934 u32 irq_flags;
935
936 if (g_spi.has_thrpt_enh) {
937 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
938 int_status);
939 } else {
940 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
941 &byte_cnt);
942 if (!ret) {
943 dev_err(&spi->dev,
944 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
945 goto _fail_;
946 }
947 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
948
949 j = 0;
950 do {
951 happened = 0;
952
953 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
954 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
955
956 if (g_spi.nint > 5) {
957 wilc_spi_read_reg(wilc, 0x1a94,
958 &irq_flags);
959 tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
960 }
961
962 unknown_mask = ~((1ul << g_spi.nint) - 1);
963
964 if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
965 dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unknown_mask);
966 happened = 1;
967 }
968
969 j++;
970 } while (happened);
971
972 *int_status = tmp;
973 }
974
975_fail_:
976 return ret;
977}
978
979static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
980{
981 struct spi_device *spi = to_spi_device(wilc->dev);
982 int ret;
983
984 if (g_spi.has_thrpt_enh) {
985 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
986 val);
987 } else {
988 u32 flags;
989
990 flags = val & (BIT(MAX_NUM_INT) - 1);
991 if (flags) {
992 int i;
993
994 ret = 1;
995 for (i = 0; i < g_spi.nint; i++) {
996
997 if (flags & 1)
998 ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
999 if (!ret)
1000 break;
1001 flags >>= 1;
1002 }
1003 if (!ret) {
1004 dev_err(&spi->dev,
1005 "Failed wilc_spi_write_reg, set reg %x ...\n",
1006 0x10c8 + i * 4);
1007 goto _fail_;
1008 }
1009 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1010 if (flags & 1)
1011 dev_err(&spi->dev,
1012 "Unexpected interrupt cleared %d...\n",
1013 i);
1014 flags >>= 1;
1015 }
1016 }
1017
1018 {
1019 u32 tbl_ctl;
1020
1021 tbl_ctl = 0;
1022
1023 if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1024 tbl_ctl |= BIT(0);
1025
1026 if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1027 tbl_ctl |= BIT(1);
1028
1029 ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL,
1030 tbl_ctl);
1031 if (!ret) {
1032 dev_err(&spi->dev,
1033 "fail write reg vmm_tbl_ctl...\n");
1034 goto _fail_;
1035 }
1036
1037 if ((val & EN_VMM) == EN_VMM) {
1038
1039
1040
1041 ret = wilc_spi_write_reg(wilc,
1042 WILC_VMM_CORE_CTL, 1);
1043 if (!ret) {
1044 dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1045 goto _fail_;
1046 }
1047 }
1048 }
1049 }
1050_fail_:
1051 return ret;
1052}
1053
1054static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1055{
1056 struct spi_device *spi = to_spi_device(wilc->dev);
1057 u32 reg;
1058 int ret, i;
1059
1060 if (nint > MAX_NUM_INT) {
1061 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1062 return 0;
1063 }
1064
1065 g_spi.nint = nint;
1066
1067
1068
1069
1070 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1071 if (!ret) {
1072 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1073 WILC_PIN_MUX_0);
1074 return 0;
1075 }
1076 reg |= BIT(8);
1077 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1078 if (!ret) {
1079 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1080 WILC_PIN_MUX_0);
1081 return 0;
1082 }
1083
1084
1085
1086
1087 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1088 if (!ret) {
1089 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1090 WILC_INTR_ENABLE);
1091 return 0;
1092 }
1093
1094 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1095 reg |= (BIT((27 + i)));
1096
1097 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1098 if (!ret) {
1099 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1100 WILC_INTR_ENABLE);
1101 return 0;
1102 }
1103 if (nint) {
1104 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1105 if (!ret) {
1106 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1107 WILC_INTR2_ENABLE);
1108 return 0;
1109 }
1110
1111 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1112 reg |= BIT(i);
1113
1114 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1115 if (!ret) {
1116 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1117 WILC_INTR2_ENABLE);
1118 return 0;
1119 }
1120 }
1121
1122 return 1;
1123}
1124
1125
1126static const struct wilc_hif_func wilc_hif_spi = {
1127 .hif_init = wilc_spi_init,
1128 .hif_deinit = _wilc_spi_deinit,
1129 .hif_read_reg = wilc_spi_read_reg,
1130 .hif_write_reg = wilc_spi_write_reg,
1131 .hif_block_rx = wilc_spi_read,
1132 .hif_block_tx = wilc_spi_write,
1133 .hif_read_int = wilc_spi_read_int,
1134 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1135 .hif_read_size = wilc_spi_read_size,
1136 .hif_block_tx_ext = wilc_spi_write,
1137 .hif_block_rx_ext = wilc_spi_read,
1138 .hif_sync_ext = wilc_spi_sync_ext,
1139};
1140
