linux/drivers/tty/serial/lantiq.c
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   1/*
   2 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License version 2 as published
   6 * by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  16 *
  17 * Copyright (C) 2004 Infineon IFAP DC COM CPE
  18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  19 * Copyright (C) 2007 John Crispin <john@phrozen.org>
  20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
  21 */
  22
  23#include <linux/slab.h>
  24#include <linux/ioport.h>
  25#include <linux/init.h>
  26#include <linux/console.h>
  27#include <linux/sysrq.h>
  28#include <linux/device.h>
  29#include <linux/tty.h>
  30#include <linux/tty_flip.h>
  31#include <linux/serial_core.h>
  32#include <linux/serial.h>
  33#include <linux/of_platform.h>
  34#include <linux/of_address.h>
  35#include <linux/of_irq.h>
  36#include <linux/io.h>
  37#include <linux/clk.h>
  38#include <linux/gpio.h>
  39
  40#include <lantiq_soc.h>
  41
  42#define PORT_LTQ_ASC            111
  43#define MAXPORTS                2
  44#define UART_DUMMY_UER_RX       1
  45#define DRVNAME                 "lantiq,asc"
  46#ifdef __BIG_ENDIAN
  47#define LTQ_ASC_TBUF            (0x0020 + 3)
  48#define LTQ_ASC_RBUF            (0x0024 + 3)
  49#else
  50#define LTQ_ASC_TBUF            0x0020
  51#define LTQ_ASC_RBUF            0x0024
  52#endif
  53#define LTQ_ASC_FSTAT           0x0048
  54#define LTQ_ASC_WHBSTATE        0x0018
  55#define LTQ_ASC_STATE           0x0014
  56#define LTQ_ASC_IRNCR           0x00F8
  57#define LTQ_ASC_CLC             0x0000
  58#define LTQ_ASC_ID              0x0008
  59#define LTQ_ASC_PISEL           0x0004
  60#define LTQ_ASC_TXFCON          0x0044
  61#define LTQ_ASC_RXFCON          0x0040
  62#define LTQ_ASC_CON             0x0010
  63#define LTQ_ASC_BG              0x0050
  64#define LTQ_ASC_IRNREN          0x00F4
  65
  66#define ASC_IRNREN_TX           0x1
  67#define ASC_IRNREN_RX           0x2
  68#define ASC_IRNREN_ERR          0x4
  69#define ASC_IRNREN_TX_BUF       0x8
  70#define ASC_IRNCR_TIR           0x1
  71#define ASC_IRNCR_RIR           0x2
  72#define ASC_IRNCR_EIR           0x4
  73
  74#define ASCOPT_CSIZE            0x3
  75#define TXFIFO_FL               1
  76#define RXFIFO_FL               1
  77#define ASCCLC_DISS             0x2
  78#define ASCCLC_RMCMASK          0x0000FF00
  79#define ASCCLC_RMCOFFSET        8
  80#define ASCCON_M_8ASYNC         0x0
  81#define ASCCON_M_7ASYNC         0x2
  82#define ASCCON_ODD              0x00000020
  83#define ASCCON_STP              0x00000080
  84#define ASCCON_BRS              0x00000100
  85#define ASCCON_FDE              0x00000200
  86#define ASCCON_R                0x00008000
  87#define ASCCON_FEN              0x00020000
  88#define ASCCON_ROEN             0x00080000
  89#define ASCCON_TOEN             0x00100000
  90#define ASCSTATE_PE             0x00010000
  91#define ASCSTATE_FE             0x00020000
  92#define ASCSTATE_ROE            0x00080000
  93#define ASCSTATE_ANY            (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
  94#define ASCWHBSTATE_CLRREN      0x00000001
  95#define ASCWHBSTATE_SETREN      0x00000002
  96#define ASCWHBSTATE_CLRPE       0x00000004
  97#define ASCWHBSTATE_CLRFE       0x00000008
  98#define ASCWHBSTATE_CLRROE      0x00000020
  99#define ASCTXFCON_TXFEN         0x0001
 100#define ASCTXFCON_TXFFLU        0x0002
 101#define ASCTXFCON_TXFITLMASK    0x3F00
 102#define ASCTXFCON_TXFITLOFF     8
 103#define ASCRXFCON_RXFEN         0x0001
 104#define ASCRXFCON_RXFFLU        0x0002
 105#define ASCRXFCON_RXFITLMASK    0x3F00
 106#define ASCRXFCON_RXFITLOFF     8
 107#define ASCFSTAT_RXFFLMASK      0x003F
 108#define ASCFSTAT_TXFFLMASK      0x3F00
 109#define ASCFSTAT_TXFREEMASK     0x3F000000
 110#define ASCFSTAT_TXFREEOFF      24
 111
 112static void lqasc_tx_chars(struct uart_port *port);
 113static struct ltq_uart_port *lqasc_port[MAXPORTS];
 114static struct uart_driver lqasc_reg;
 115static DEFINE_SPINLOCK(ltq_asc_lock);
 116
 117struct ltq_uart_port {
 118        struct uart_port        port;
 119        /* clock used to derive divider */
 120        struct clk              *fpiclk;
 121        /* clock gating of the ASC core */
 122        struct clk              *clk;
 123        unsigned int            tx_irq;
 124        unsigned int            rx_irq;
 125        unsigned int            err_irq;
 126};
 127
 128static inline struct
 129ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
 130{
 131        return container_of(port, struct ltq_uart_port, port);
 132}
 133
 134static void
 135lqasc_stop_tx(struct uart_port *port)
 136{
 137        return;
 138}
 139
 140static void
 141lqasc_start_tx(struct uart_port *port)
 142{
 143        unsigned long flags;
 144        spin_lock_irqsave(&ltq_asc_lock, flags);
 145        lqasc_tx_chars(port);
 146        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 147        return;
 148}
 149
 150static void
 151lqasc_stop_rx(struct uart_port *port)
 152{
 153        ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
 154}
 155
 156static int
 157lqasc_rx_chars(struct uart_port *port)
 158{
 159        struct tty_port *tport = &port->state->port;
 160        unsigned int ch = 0, rsr = 0, fifocnt;
 161
 162        fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
 163        while (fifocnt--) {
 164                u8 flag = TTY_NORMAL;
 165                ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
 166                rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
 167                        & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
 168                tty_flip_buffer_push(tport);
 169                port->icount.rx++;
 170
 171                /*
 172                 * Note that the error handling code is
 173                 * out of the main execution path
 174                 */
 175                if (rsr & ASCSTATE_ANY) {
 176                        if (rsr & ASCSTATE_PE) {
 177                                port->icount.parity++;
 178                                ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
 179                                        port->membase + LTQ_ASC_WHBSTATE);
 180                        } else if (rsr & ASCSTATE_FE) {
 181                                port->icount.frame++;
 182                                ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
 183                                        port->membase + LTQ_ASC_WHBSTATE);
 184                        }
 185                        if (rsr & ASCSTATE_ROE) {
 186                                port->icount.overrun++;
 187                                ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
 188                                        port->membase + LTQ_ASC_WHBSTATE);
 189                        }
 190
 191                        rsr &= port->read_status_mask;
 192
 193                        if (rsr & ASCSTATE_PE)
 194                                flag = TTY_PARITY;
 195                        else if (rsr & ASCSTATE_FE)
 196                                flag = TTY_FRAME;
 197                }
 198
 199                if ((rsr & port->ignore_status_mask) == 0)
 200                        tty_insert_flip_char(tport, ch, flag);
 201
 202                if (rsr & ASCSTATE_ROE)
 203                        /*
 204                         * Overrun is special, since it's reported
 205                         * immediately, and doesn't affect the current
 206                         * character
 207                         */
 208                        tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 209        }
 210
 211        if (ch != 0)
 212                tty_flip_buffer_push(tport);
 213
 214        return 0;
 215}
 216
 217static void
 218lqasc_tx_chars(struct uart_port *port)
 219{
 220        struct circ_buf *xmit = &port->state->xmit;
 221        if (uart_tx_stopped(port)) {
 222                lqasc_stop_tx(port);
 223                return;
 224        }
 225
 226        while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
 227                ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
 228                if (port->x_char) {
 229                        ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
 230                        port->icount.tx++;
 231                        port->x_char = 0;
 232                        continue;
 233                }
 234
 235                if (uart_circ_empty(xmit))
 236                        break;
 237
 238                ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
 239                        port->membase + LTQ_ASC_TBUF);
 240                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 241                port->icount.tx++;
 242        }
 243
 244        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 245                uart_write_wakeup(port);
 246}
 247
 248static irqreturn_t
 249lqasc_tx_int(int irq, void *_port)
 250{
 251        unsigned long flags;
 252        struct uart_port *port = (struct uart_port *)_port;
 253        spin_lock_irqsave(&ltq_asc_lock, flags);
 254        ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
 255        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 256        lqasc_start_tx(port);
 257        return IRQ_HANDLED;
 258}
 259
 260static irqreturn_t
 261lqasc_err_int(int irq, void *_port)
 262{
 263        unsigned long flags;
 264        struct uart_port *port = (struct uart_port *)_port;
 265        spin_lock_irqsave(&ltq_asc_lock, flags);
 266        /* clear any pending interrupts */
 267        ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
 268                ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
 269        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 270        return IRQ_HANDLED;
 271}
 272
 273static irqreturn_t
 274lqasc_rx_int(int irq, void *_port)
 275{
 276        unsigned long flags;
 277        struct uart_port *port = (struct uart_port *)_port;
 278        spin_lock_irqsave(&ltq_asc_lock, flags);
 279        ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
 280        lqasc_rx_chars(port);
 281        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 282        return IRQ_HANDLED;
 283}
 284
 285static unsigned int
 286lqasc_tx_empty(struct uart_port *port)
 287{
 288        int status;
 289        status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
 290        return status ? 0 : TIOCSER_TEMT;
 291}
 292
 293static unsigned int
 294lqasc_get_mctrl(struct uart_port *port)
 295{
 296        return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
 297}
 298
 299static void
 300lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
 301{
 302}
 303
 304static void
 305lqasc_break_ctl(struct uart_port *port, int break_state)
 306{
 307}
 308
 309static int
 310lqasc_startup(struct uart_port *port)
 311{
 312        struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 313        int retval;
 314
 315        if (!IS_ERR(ltq_port->clk))
 316                clk_enable(ltq_port->clk);
 317        port->uartclk = clk_get_rate(ltq_port->fpiclk);
 318
 319        ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
 320                port->membase + LTQ_ASC_CLC);
 321
 322        ltq_w32(0, port->membase + LTQ_ASC_PISEL);
 323        ltq_w32(
 324                ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
 325                ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
 326                port->membase + LTQ_ASC_TXFCON);
 327        ltq_w32(
 328                ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
 329                | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
 330                port->membase + LTQ_ASC_RXFCON);
 331        /* make sure other settings are written to hardware before
 332         * setting enable bits
 333         */
 334        wmb();
 335        ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
 336                ASCCON_ROEN, port->membase + LTQ_ASC_CON);
 337
 338        retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
 339                0, "asc_tx", port);
 340        if (retval) {
 341                pr_err("failed to request lqasc_tx_int\n");
 342                return retval;
 343        }
 344
 345        retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
 346                0, "asc_rx", port);
 347        if (retval) {
 348                pr_err("failed to request lqasc_rx_int\n");
 349                goto err1;
 350        }
 351
 352        retval = request_irq(ltq_port->err_irq, lqasc_err_int,
 353                0, "asc_err", port);
 354        if (retval) {
 355                pr_err("failed to request lqasc_err_int\n");
 356                goto err2;
 357        }
 358
 359        ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
 360                port->membase + LTQ_ASC_IRNREN);
 361        return 0;
 362
 363err2:
 364        free_irq(ltq_port->rx_irq, port);
 365err1:
 366        free_irq(ltq_port->tx_irq, port);
 367        return retval;
 368}
 369
 370static void
 371lqasc_shutdown(struct uart_port *port)
 372{
 373        struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 374        free_irq(ltq_port->tx_irq, port);
 375        free_irq(ltq_port->rx_irq, port);
 376        free_irq(ltq_port->err_irq, port);
 377
 378        ltq_w32(0, port->membase + LTQ_ASC_CON);
 379        ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
 380                port->membase + LTQ_ASC_RXFCON);
 381        ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
 382                port->membase + LTQ_ASC_TXFCON);
 383        if (!IS_ERR(ltq_port->clk))
 384                clk_disable(ltq_port->clk);
 385}
 386
 387static void
 388lqasc_set_termios(struct uart_port *port,
 389        struct ktermios *new, struct ktermios *old)
 390{
 391        unsigned int cflag;
 392        unsigned int iflag;
 393        unsigned int divisor;
 394        unsigned int baud;
 395        unsigned int con = 0;
 396        unsigned long flags;
 397
 398        cflag = new->c_cflag;
 399        iflag = new->c_iflag;
 400
 401        switch (cflag & CSIZE) {
 402        case CS7:
 403                con = ASCCON_M_7ASYNC;
 404                break;
 405
 406        case CS5:
 407        case CS6:
 408        default:
 409                new->c_cflag &= ~ CSIZE;
 410                new->c_cflag |= CS8;
 411                con = ASCCON_M_8ASYNC;
 412                break;
 413        }
 414
 415        cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
 416
 417        if (cflag & CSTOPB)
 418                con |= ASCCON_STP;
 419
 420        if (cflag & PARENB) {
 421                if (!(cflag & PARODD))
 422                        con &= ~ASCCON_ODD;
 423                else
 424                        con |= ASCCON_ODD;
 425        }
 426
 427        port->read_status_mask = ASCSTATE_ROE;
 428        if (iflag & INPCK)
 429                port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 430
 431        port->ignore_status_mask = 0;
 432        if (iflag & IGNPAR)
 433                port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 434
 435        if (iflag & IGNBRK) {
 436                /*
 437                 * If we're ignoring parity and break indicators,
 438                 * ignore overruns too (for real raw support).
 439                 */
 440                if (iflag & IGNPAR)
 441                        port->ignore_status_mask |= ASCSTATE_ROE;
 442        }
 443
 444        if ((cflag & CREAD) == 0)
 445                port->ignore_status_mask |= UART_DUMMY_UER_RX;
 446
 447        /* set error signals  - framing, parity  and overrun, enable receiver */
 448        con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
 449
 450        spin_lock_irqsave(&ltq_asc_lock, flags);
 451
 452        /* set up CON */
 453        ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
 454
 455        /* Set baud rate - take a divider of 2 into account */
 456        baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
 457        divisor = uart_get_divisor(port, baud);
 458        divisor = divisor / 2 - 1;
 459
 460        /* disable the baudrate generator */
 461        ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
 462
 463        /* make sure the fractional divider is off */
 464        ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
 465
 466        /* set up to use divisor of 2 */
 467        ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
 468
 469        /* now we can write the new baudrate into the register */
 470        ltq_w32(divisor, port->membase + LTQ_ASC_BG);
 471
 472        /* turn the baudrate generator back on */
 473        ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
 474
 475        /* enable rx */
 476        ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
 477
 478        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 479
 480        /* Don't rewrite B0 */
 481        if (tty_termios_baud_rate(new))
 482                tty_termios_encode_baud_rate(new, baud, baud);
 483
 484        uart_update_timeout(port, cflag, baud);
 485}
 486
 487static const char*
 488lqasc_type(struct uart_port *port)
 489{
 490        if (port->type == PORT_LTQ_ASC)
 491                return DRVNAME;
 492        else
 493                return NULL;
 494}
 495
 496static void
 497lqasc_release_port(struct uart_port *port)
 498{
 499        struct platform_device *pdev = to_platform_device(port->dev);
 500
 501        if (port->flags & UPF_IOREMAP) {
 502                devm_iounmap(&pdev->dev, port->membase);
 503                port->membase = NULL;
 504        }
 505}
 506
 507static int
 508lqasc_request_port(struct uart_port *port)
 509{
 510        struct platform_device *pdev = to_platform_device(port->dev);
 511        struct resource *res;
 512        int size;
 513
 514        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 515        if (!res) {
 516                dev_err(&pdev->dev, "cannot obtain I/O memory region");
 517                return -ENODEV;
 518        }
 519        size = resource_size(res);
 520
 521        res = devm_request_mem_region(&pdev->dev, res->start,
 522                size, dev_name(&pdev->dev));
 523        if (!res) {
 524                dev_err(&pdev->dev, "cannot request I/O memory region");
 525                return -EBUSY;
 526        }
 527
 528        if (port->flags & UPF_IOREMAP) {
 529                port->membase = devm_ioremap_nocache(&pdev->dev,
 530                        port->mapbase, size);
 531                if (port->membase == NULL)
 532                        return -ENOMEM;
 533        }
 534        return 0;
 535}
 536
 537static void
 538lqasc_config_port(struct uart_port *port, int flags)
 539{
 540        if (flags & UART_CONFIG_TYPE) {
 541                port->type = PORT_LTQ_ASC;
 542                lqasc_request_port(port);
 543        }
 544}
 545
 546static int
 547lqasc_verify_port(struct uart_port *port,
 548        struct serial_struct *ser)
 549{
 550        int ret = 0;
 551        if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
 552                ret = -EINVAL;
 553        if (ser->irq < 0 || ser->irq >= NR_IRQS)
 554                ret = -EINVAL;
 555        if (ser->baud_base < 9600)
 556                ret = -EINVAL;
 557        return ret;
 558}
 559
 560static const struct uart_ops lqasc_pops = {
 561        .tx_empty =     lqasc_tx_empty,
 562        .set_mctrl =    lqasc_set_mctrl,
 563        .get_mctrl =    lqasc_get_mctrl,
 564        .stop_tx =      lqasc_stop_tx,
 565        .start_tx =     lqasc_start_tx,
 566        .stop_rx =      lqasc_stop_rx,
 567        .break_ctl =    lqasc_break_ctl,
 568        .startup =      lqasc_startup,
 569        .shutdown =     lqasc_shutdown,
 570        .set_termios =  lqasc_set_termios,
 571        .type =         lqasc_type,
 572        .release_port = lqasc_release_port,
 573        .request_port = lqasc_request_port,
 574        .config_port =  lqasc_config_port,
 575        .verify_port =  lqasc_verify_port,
 576};
 577
 578static void
 579lqasc_console_putchar(struct uart_port *port, int ch)
 580{
 581        int fifofree;
 582
 583        if (!port->membase)
 584                return;
 585
 586        do {
 587                fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
 588                        & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
 589        } while (fifofree == 0);
 590        ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
 591}
 592
 593static void lqasc_serial_port_write(struct uart_port *port, const char *s,
 594                                    u_int count)
 595{
 596        unsigned long flags;
 597
 598        spin_lock_irqsave(&ltq_asc_lock, flags);
 599        uart_console_write(port, s, count, lqasc_console_putchar);
 600        spin_unlock_irqrestore(&ltq_asc_lock, flags);
 601}
 602
 603static void
 604lqasc_console_write(struct console *co, const char *s, u_int count)
 605{
 606        struct ltq_uart_port *ltq_port;
 607
 608        if (co->index >= MAXPORTS)
 609                return;
 610
 611        ltq_port = lqasc_port[co->index];
 612        if (!ltq_port)
 613                return;
 614
 615        lqasc_serial_port_write(&ltq_port->port, s, count);
 616}
 617
 618static int __init
 619lqasc_console_setup(struct console *co, char *options)
 620{
 621        struct ltq_uart_port *ltq_port;
 622        struct uart_port *port;
 623        int baud = 115200;
 624        int bits = 8;
 625        int parity = 'n';
 626        int flow = 'n';
 627
 628        if (co->index >= MAXPORTS)
 629                return -ENODEV;
 630
 631        ltq_port = lqasc_port[co->index];
 632        if (!ltq_port)
 633                return -ENODEV;
 634
 635        port = &ltq_port->port;
 636
 637        if (!IS_ERR(ltq_port->clk))
 638                clk_enable(ltq_port->clk);
 639
 640        port->uartclk = clk_get_rate(ltq_port->fpiclk);
 641
 642        if (options)
 643                uart_parse_options(options, &baud, &parity, &bits, &flow);
 644        return uart_set_options(port, co, baud, parity, bits, flow);
 645}
 646
 647static struct console lqasc_console = {
 648        .name =         "ttyLTQ",
 649        .write =        lqasc_console_write,
 650        .device =       uart_console_device,
 651        .setup =        lqasc_console_setup,
 652        .flags =        CON_PRINTBUFFER,
 653        .index =        -1,
 654        .data =         &lqasc_reg,
 655};
 656
 657static int __init
 658lqasc_console_init(void)
 659{
 660        register_console(&lqasc_console);
 661        return 0;
 662}
 663console_initcall(lqasc_console_init);
 664
 665static void lqasc_serial_early_console_write(struct console *co,
 666                                             const char *s,
 667                                             u_int count)
 668{
 669        struct earlycon_device *dev = co->data;
 670
 671        lqasc_serial_port_write(&dev->port, s, count);
 672}
 673
 674static int __init
 675lqasc_serial_early_console_setup(struct earlycon_device *device,
 676                                 const char *opt)
 677{
 678        if (!device->port.membase)
 679                return -ENODEV;
 680
 681        device->con->write = lqasc_serial_early_console_write;
 682        return 0;
 683}
 684OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
 685
 686static struct uart_driver lqasc_reg = {
 687        .owner =        THIS_MODULE,
 688        .driver_name =  DRVNAME,
 689        .dev_name =     "ttyLTQ",
 690        .major =        0,
 691        .minor =        0,
 692        .nr =           MAXPORTS,
 693        .cons =         &lqasc_console,
 694};
 695
 696static int __init
 697lqasc_probe(struct platform_device *pdev)
 698{
 699        struct device_node *node = pdev->dev.of_node;
 700        struct ltq_uart_port *ltq_port;
 701        struct uart_port *port;
 702        struct resource *mmres, irqres[3];
 703        int line = 0;
 704        int ret;
 705
 706        mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 707        ret = of_irq_to_resource_table(node, irqres, 3);
 708        if (!mmres || (ret != 3)) {
 709                dev_err(&pdev->dev,
 710                        "failed to get memory/irq for serial port\n");
 711                return -ENODEV;
 712        }
 713
 714        /* check if this is the console port */
 715        if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC))
 716                line = 1;
 717
 718        if (lqasc_port[line]) {
 719                dev_err(&pdev->dev, "port %d already allocated\n", line);
 720                return -EBUSY;
 721        }
 722
 723        ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
 724                        GFP_KERNEL);
 725        if (!ltq_port)
 726                return -ENOMEM;
 727
 728        port = &ltq_port->port;
 729
 730        port->iotype    = SERIAL_IO_MEM;
 731        port->flags     = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
 732        port->ops       = &lqasc_pops;
 733        port->fifosize  = 16;
 734        port->type      = PORT_LTQ_ASC,
 735        port->line      = line;
 736        port->dev       = &pdev->dev;
 737        /* unused, just to be backward-compatible */
 738        port->irq       = irqres[0].start;
 739        port->mapbase   = mmres->start;
 740
 741        ltq_port->fpiclk = clk_get_fpi();
 742        if (IS_ERR(ltq_port->fpiclk)) {
 743                pr_err("failed to get fpi clk\n");
 744                return -ENOENT;
 745        }
 746
 747        /* not all asc ports have clock gates, lets ignore the return code */
 748        ltq_port->clk = clk_get(&pdev->dev, NULL);
 749
 750        ltq_port->tx_irq = irqres[0].start;
 751        ltq_port->rx_irq = irqres[1].start;
 752        ltq_port->err_irq = irqres[2].start;
 753
 754        lqasc_port[line] = ltq_port;
 755        platform_set_drvdata(pdev, ltq_port);
 756
 757        ret = uart_add_one_port(&lqasc_reg, port);
 758
 759        return ret;
 760}
 761
 762static const struct of_device_id ltq_asc_match[] = {
 763        { .compatible = DRVNAME },
 764        {},
 765};
 766
 767static struct platform_driver lqasc_driver = {
 768        .driver         = {
 769                .name   = DRVNAME,
 770                .of_match_table = ltq_asc_match,
 771        },
 772};
 773
 774int __init
 775init_lqasc(void)
 776{
 777        int ret;
 778
 779        ret = uart_register_driver(&lqasc_reg);
 780        if (ret != 0)
 781                return ret;
 782
 783        ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
 784        if (ret != 0)
 785                uart_unregister_driver(&lqasc_reg);
 786
 787        return ret;
 788}
 789device_initcall(init_lqasc);
 790