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13#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
14
15#include <linux/console.h>
16#include <linux/pci_regs.h>
17#include <linux/pci_ids.h>
18#include <linux/bootmem.h>
19#include <linux/io.h>
20#include <asm/pci-direct.h>
21#include <asm/fixmap.h>
22#include <linux/bcd.h>
23#include <linux/export.h>
24#include <linux/version.h>
25#include <linux/module.h>
26#include <linux/delay.h>
27#include <linux/kthread.h>
28
29#include "../host/xhci.h"
30#include "xhci-dbc.h"
31
32static struct xdbc_state xdbc;
33static bool early_console_keep;
34
35#ifdef XDBC_TRACE
36#define xdbc_trace trace_printk
37#else
38static inline void xdbc_trace(const char *fmt, ...) { }
39#endif
40
41static void __iomem * __init xdbc_map_pci_mmio(u32 bus, u32 dev, u32 func)
42{
43 u64 val64, sz64, mask64;
44 void __iomem *base;
45 u32 val, sz;
46 u8 byte;
47
48 val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
49 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, ~0);
50 sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
51 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val);
52
53 if (val == 0xffffffff || sz == 0xffffffff) {
54 pr_notice("invalid mmio bar\n");
55 return NULL;
56 }
57
58 val64 = val & PCI_BASE_ADDRESS_MEM_MASK;
59 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
60 mask64 = PCI_BASE_ADDRESS_MEM_MASK;
61
62 if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
63 val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
64 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, ~0);
65 sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
66 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val);
67
68 val64 |= (u64)val << 32;
69 sz64 |= (u64)sz << 32;
70 mask64 |= ~0ULL << 32;
71 }
72
73 sz64 &= mask64;
74
75 if (!sz64) {
76 pr_notice("invalid mmio address\n");
77 return NULL;
78 }
79
80 sz64 = 1ULL << __ffs64(sz64);
81
82
83 byte = read_pci_config_byte(bus, dev, func, PCI_COMMAND);
84 if (!(byte & PCI_COMMAND_MEMORY)) {
85 byte |= PCI_COMMAND_MEMORY;
86 write_pci_config_byte(bus, dev, func, PCI_COMMAND, byte);
87 }
88
89 xdbc.xhci_start = val64;
90 xdbc.xhci_length = sz64;
91 base = early_ioremap(val64, sz64);
92
93 return base;
94}
95
96static void * __init xdbc_get_page(dma_addr_t *dma_addr)
97{
98 void *virt;
99
100 virt = alloc_bootmem_pages_nopanic(PAGE_SIZE);
101 if (!virt)
102 return NULL;
103
104 if (dma_addr)
105 *dma_addr = (dma_addr_t)__pa(virt);
106
107 return virt;
108}
109
110static u32 __init xdbc_find_dbgp(int xdbc_num, u32 *b, u32 *d, u32 *f)
111{
112 u32 bus, dev, func, class;
113
114 for (bus = 0; bus < XDBC_PCI_MAX_BUSES; bus++) {
115 for (dev = 0; dev < XDBC_PCI_MAX_DEVICES; dev++) {
116 for (func = 0; func < XDBC_PCI_MAX_FUNCTION; func++) {
117
118 class = read_pci_config(bus, dev, func, PCI_CLASS_REVISION);
119 if ((class >> 8) != PCI_CLASS_SERIAL_USB_XHCI)
120 continue;
121
122 if (xdbc_num-- != 0)
123 continue;
124
125 *b = bus;
126 *d = dev;
127 *f = func;
128
129 return 0;
130 }
131 }
132 }
133
134 return -1;
135}
136
137static int handshake(void __iomem *ptr, u32 mask, u32 done, int wait, int delay)
138{
139 u32 result;
140
141 do {
142 result = readl(ptr);
143 result &= mask;
144 if (result == done)
145 return 0;
146 udelay(delay);
147 wait -= delay;
148 } while (wait > 0);
149
150 return -ETIMEDOUT;
151}
152
153static void __init xdbc_bios_handoff(void)
154{
155 int offset, timeout;
156 u32 val;
157
158 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_LEGACY);
159 val = readl(xdbc.xhci_base + offset);
160
161 if (val & XHCI_HC_BIOS_OWNED) {
162 writel(val | XHCI_HC_OS_OWNED, xdbc.xhci_base + offset);
163 timeout = handshake(xdbc.xhci_base + offset, XHCI_HC_BIOS_OWNED, 0, 5000, 10);
164
165 if (timeout) {
166 pr_notice("failed to hand over xHCI control from BIOS\n");
167 writel(val & ~XHCI_HC_BIOS_OWNED, xdbc.xhci_base + offset);
168 }
169 }
170
171
172 val = readl(xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET);
173 val &= XHCI_LEGACY_DISABLE_SMI;
174 val |= XHCI_LEGACY_SMI_EVENTS;
175 writel(val, xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET);
176}
177
178static int __init
179xdbc_alloc_ring(struct xdbc_segment *seg, struct xdbc_ring *ring)
180{
181 seg->trbs = xdbc_get_page(&seg->dma);
182 if (!seg->trbs)
183 return -ENOMEM;
184
185 ring->segment = seg;
186
187 return 0;
188}
189
190static void __init xdbc_free_ring(struct xdbc_ring *ring)
191{
192 struct xdbc_segment *seg = ring->segment;
193
194 if (!seg)
195 return;
196
197 free_bootmem(seg->dma, PAGE_SIZE);
198 ring->segment = NULL;
199}
200
201static void xdbc_reset_ring(struct xdbc_ring *ring)
202{
203 struct xdbc_segment *seg = ring->segment;
204 struct xdbc_trb *link_trb;
205
206 memset(seg->trbs, 0, PAGE_SIZE);
207
208 ring->enqueue = seg->trbs;
209 ring->dequeue = seg->trbs;
210 ring->cycle_state = 1;
211
212 if (ring != &xdbc.evt_ring) {
213 link_trb = &seg->trbs[XDBC_TRBS_PER_SEGMENT - 1];
214 link_trb->field[0] = cpu_to_le32(lower_32_bits(seg->dma));
215 link_trb->field[1] = cpu_to_le32(upper_32_bits(seg->dma));
216 link_trb->field[3] = cpu_to_le32(TRB_TYPE(TRB_LINK)) | cpu_to_le32(LINK_TOGGLE);
217 }
218}
219
220static inline void xdbc_put_utf16(u16 *s, const char *c, size_t size)
221{
222 int i;
223
224 for (i = 0; i < size; i++)
225 s[i] = cpu_to_le16(c[i]);
226}
227
228static void xdbc_mem_init(void)
229{
230 struct xdbc_ep_context *ep_in, *ep_out;
231 struct usb_string_descriptor *s_desc;
232 struct xdbc_erst_entry *entry;
233 struct xdbc_strings *strings;
234 struct xdbc_context *ctx;
235 unsigned int max_burst;
236 u32 string_length;
237 int index = 0;
238 u32 dev_info;
239
240 xdbc_reset_ring(&xdbc.evt_ring);
241 xdbc_reset_ring(&xdbc.in_ring);
242 xdbc_reset_ring(&xdbc.out_ring);
243 memset(xdbc.table_base, 0, PAGE_SIZE);
244 memset(xdbc.out_buf, 0, PAGE_SIZE);
245
246
247 xdbc.erst_size = 16;
248 xdbc.erst_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
249 xdbc.erst_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
250
251 index += XDBC_ERST_ENTRY_NUM;
252 entry = (struct xdbc_erst_entry *)xdbc.erst_base;
253
254 entry->seg_addr = cpu_to_le64(xdbc.evt_seg.dma);
255 entry->seg_size = cpu_to_le32(XDBC_TRBS_PER_SEGMENT);
256 entry->__reserved_0 = 0;
257
258
259 writel(1, &xdbc.xdbc_reg->ersts);
260 xdbc_write64(xdbc.erst_dma, &xdbc.xdbc_reg->erstba);
261 xdbc_write64(xdbc.evt_seg.dma, &xdbc.xdbc_reg->erdp);
262
263
264 xdbc.dbcc_size = 64 * 3;
265 xdbc.dbcc_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
266 xdbc.dbcc_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
267
268 index += XDBC_DBCC_ENTRY_NUM;
269
270
271 xdbc.string_size = sizeof(struct xdbc_strings);
272 xdbc.string_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
273 xdbc.string_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
274 strings = (struct xdbc_strings *)xdbc.string_base;
275
276 index += XDBC_STRING_ENTRY_NUM;
277
278
279 s_desc = (struct usb_string_descriptor *)strings->serial;
280 s_desc->bLength = (strlen(XDBC_STRING_SERIAL) + 1) * 2;
281 s_desc->bDescriptorType = USB_DT_STRING;
282
283 xdbc_put_utf16(s_desc->wData, XDBC_STRING_SERIAL, strlen(XDBC_STRING_SERIAL));
284 string_length = s_desc->bLength;
285 string_length <<= 8;
286
287
288 s_desc = (struct usb_string_descriptor *)strings->product;
289 s_desc->bLength = (strlen(XDBC_STRING_PRODUCT) + 1) * 2;
290 s_desc->bDescriptorType = USB_DT_STRING;
291
292 xdbc_put_utf16(s_desc->wData, XDBC_STRING_PRODUCT, strlen(XDBC_STRING_PRODUCT));
293 string_length += s_desc->bLength;
294 string_length <<= 8;
295
296
297 s_desc = (struct usb_string_descriptor *)strings->manufacturer;
298 s_desc->bLength = (strlen(XDBC_STRING_MANUFACTURER) + 1) * 2;
299 s_desc->bDescriptorType = USB_DT_STRING;
300
301 xdbc_put_utf16(s_desc->wData, XDBC_STRING_MANUFACTURER, strlen(XDBC_STRING_MANUFACTURER));
302 string_length += s_desc->bLength;
303 string_length <<= 8;
304
305
306 strings->string0[0] = 4;
307 strings->string0[1] = USB_DT_STRING;
308 strings->string0[2] = 0x09;
309 strings->string0[3] = 0x04;
310
311 string_length += 4;
312
313
314 ctx = (struct xdbc_context *)xdbc.dbcc_base;
315
316 ctx->info.string0 = cpu_to_le64(xdbc.string_dma);
317 ctx->info.manufacturer = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH);
318 ctx->info.product = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 2);
319 ctx->info.serial = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 3);
320 ctx->info.length = cpu_to_le32(string_length);
321
322
323 max_burst = DEBUG_MAX_BURST(readl(&xdbc.xdbc_reg->control));
324 ep_out = (struct xdbc_ep_context *)&ctx->out;
325
326 ep_out->ep_info1 = 0;
327 ep_out->ep_info2 = cpu_to_le32(EP_TYPE(BULK_OUT_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst));
328 ep_out->deq = cpu_to_le64(xdbc.out_seg.dma | xdbc.out_ring.cycle_state);
329
330
331 ep_in = (struct xdbc_ep_context *)&ctx->in;
332
333 ep_in->ep_info1 = 0;
334 ep_in->ep_info2 = cpu_to_le32(EP_TYPE(BULK_OUT_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst));
335 ep_in->deq = cpu_to_le64(xdbc.in_seg.dma | xdbc.in_ring.cycle_state);
336
337
338 xdbc_write64(xdbc.dbcc_dma, &xdbc.xdbc_reg->dccp);
339
340 dev_info = cpu_to_le32((XDBC_VENDOR_ID << 16) | XDBC_PROTOCOL);
341 writel(dev_info, &xdbc.xdbc_reg->devinfo1);
342
343 dev_info = cpu_to_le32((XDBC_DEVICE_REV << 16) | XDBC_PRODUCT_ID);
344 writel(dev_info, &xdbc.xdbc_reg->devinfo2);
345
346 xdbc.in_buf = xdbc.out_buf + XDBC_MAX_PACKET;
347 xdbc.in_dma = xdbc.out_dma + XDBC_MAX_PACKET;
348}
349
350static void xdbc_do_reset_debug_port(u32 id, u32 count)
351{
352 void __iomem *ops_reg;
353 void __iomem *portsc;
354 u32 val, cap_length;
355 int i;
356
357 cap_length = readl(xdbc.xhci_base) & 0xff;
358 ops_reg = xdbc.xhci_base + cap_length;
359
360 id--;
361 for (i = id; i < (id + count); i++) {
362 portsc = ops_reg + 0x400 + i * 0x10;
363 val = readl(portsc);
364 if (!(val & PORT_CONNECT))
365 writel(val | PORT_RESET, portsc);
366 }
367}
368
369static void xdbc_reset_debug_port(void)
370{
371 u32 val, port_offset, port_count;
372 int offset = 0;
373
374 do {
375 offset = xhci_find_next_ext_cap(xdbc.xhci_base, offset, XHCI_EXT_CAPS_PROTOCOL);
376 if (!offset)
377 break;
378
379 val = readl(xdbc.xhci_base + offset);
380 if (XHCI_EXT_PORT_MAJOR(val) != 0x3)
381 continue;
382
383 val = readl(xdbc.xhci_base + offset + 8);
384 port_offset = XHCI_EXT_PORT_OFF(val);
385 port_count = XHCI_EXT_PORT_COUNT(val);
386
387 xdbc_do_reset_debug_port(port_offset, port_count);
388 } while (1);
389}
390
391static void
392xdbc_queue_trb(struct xdbc_ring *ring, u32 field1, u32 field2, u32 field3, u32 field4)
393{
394 struct xdbc_trb *trb, *link_trb;
395
396 trb = ring->enqueue;
397 trb->field[0] = cpu_to_le32(field1);
398 trb->field[1] = cpu_to_le32(field2);
399 trb->field[2] = cpu_to_le32(field3);
400 trb->field[3] = cpu_to_le32(field4);
401
402 ++(ring->enqueue);
403 if (ring->enqueue >= &ring->segment->trbs[TRBS_PER_SEGMENT - 1]) {
404 link_trb = ring->enqueue;
405 if (ring->cycle_state)
406 link_trb->field[3] |= cpu_to_le32(TRB_CYCLE);
407 else
408 link_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
409
410 ring->enqueue = ring->segment->trbs;
411 ring->cycle_state ^= 1;
412 }
413}
414
415static void xdbc_ring_doorbell(int target)
416{
417 writel(DOOR_BELL_TARGET(target), &xdbc.xdbc_reg->doorbell);
418}
419
420static int xdbc_start(void)
421{
422 u32 ctrl, status;
423 int ret;
424
425 ctrl = readl(&xdbc.xdbc_reg->control);
426 writel(ctrl | CTRL_DBC_ENABLE | CTRL_PORT_ENABLE, &xdbc.xdbc_reg->control);
427 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, CTRL_DBC_ENABLE, 100000, 100);
428 if (ret) {
429 xdbc_trace("failed to initialize hardware\n");
430 return ret;
431 }
432
433
434 if (xdbc.vendor == PCI_VENDOR_ID_INTEL)
435 xdbc_reset_debug_port();
436
437
438 ret = handshake(&xdbc.xdbc_reg->portsc, PORTSC_CONN_STATUS, PORTSC_CONN_STATUS, 5000000, 100);
439 if (ret) {
440 xdbc_trace("waiting for connection timed out\n");
441 return ret;
442 }
443
444
445 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_RUN, CTRL_DBC_RUN, 5000000, 100);
446 if (ret) {
447 xdbc_trace("waiting for device configuration timed out\n");
448 return ret;
449 }
450
451
452 status = readl(&xdbc.xdbc_reg->status);
453 if (!DCST_DEBUG_PORT(status)) {
454 xdbc_trace("invalid root hub port number\n");
455 return -ENODEV;
456 }
457
458 xdbc.port_number = DCST_DEBUG_PORT(status);
459
460 xdbc_trace("DbC is running now, control 0x%08x port ID %d\n",
461 readl(&xdbc.xdbc_reg->control), xdbc.port_number);
462
463 return 0;
464}
465
466static int xdbc_bulk_transfer(void *data, int size, bool read)
467{
468 struct xdbc_ring *ring;
469 struct xdbc_trb *trb;
470 u32 length, control;
471 u32 cycle;
472 u64 addr;
473
474 if (size > XDBC_MAX_PACKET) {
475 xdbc_trace("bad parameter, size %d\n", size);
476 return -EINVAL;
477 }
478
479 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED) ||
480 !(xdbc.flags & XDBC_FLAGS_CONFIGURED) ||
481 (!read && (xdbc.flags & XDBC_FLAGS_OUT_STALL)) ||
482 (read && (xdbc.flags & XDBC_FLAGS_IN_STALL))) {
483
484 xdbc_trace("connection not ready, flags %08x\n", xdbc.flags);
485 return -EIO;
486 }
487
488 ring = (read ? &xdbc.in_ring : &xdbc.out_ring);
489 trb = ring->enqueue;
490 cycle = ring->cycle_state;
491 length = TRB_LEN(size);
492 control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
493
494 if (cycle)
495 control &= cpu_to_le32(~TRB_CYCLE);
496 else
497 control |= cpu_to_le32(TRB_CYCLE);
498
499 if (read) {
500 memset(xdbc.in_buf, 0, XDBC_MAX_PACKET);
501 addr = xdbc.in_dma;
502 xdbc.flags |= XDBC_FLAGS_IN_PROCESS;
503 } else {
504 memset(xdbc.out_buf, 0, XDBC_MAX_PACKET);
505 memcpy(xdbc.out_buf, data, size);
506 addr = xdbc.out_dma;
507 xdbc.flags |= XDBC_FLAGS_OUT_PROCESS;
508 }
509
510 xdbc_queue_trb(ring, lower_32_bits(addr), upper_32_bits(addr), length, control);
511
512
513
514
515
516 wmb();
517 if (cycle)
518 trb->field[3] |= cpu_to_le32(cycle);
519 else
520 trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
521
522 xdbc_ring_doorbell(read ? IN_EP_DOORBELL : OUT_EP_DOORBELL);
523
524 return size;
525}
526
527static int xdbc_handle_external_reset(void)
528{
529 int ret = 0;
530
531 xdbc.flags = 0;
532 writel(0, &xdbc.xdbc_reg->control);
533 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 10);
534 if (ret)
535 goto reset_out;
536
537 xdbc_mem_init();
538
539 mmiowb();
540
541 ret = xdbc_start();
542 if (ret < 0)
543 goto reset_out;
544
545 xdbc_trace("dbc recovered\n");
546
547 xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED;
548
549 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
550
551 return 0;
552
553reset_out:
554 xdbc_trace("failed to recover from external reset\n");
555 return ret;
556}
557
558static int __init xdbc_early_setup(void)
559{
560 int ret;
561
562 writel(0, &xdbc.xdbc_reg->control);
563 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 100);
564 if (ret)
565 return ret;
566
567
568 xdbc.table_base = xdbc_get_page(&xdbc.table_dma);
569 if (!xdbc.table_base)
570 return -ENOMEM;
571
572
573 xdbc.out_buf = xdbc_get_page(&xdbc.out_dma);
574 if (!xdbc.out_buf)
575 return -ENOMEM;
576
577
578 ret = xdbc_alloc_ring(&xdbc.evt_seg, &xdbc.evt_ring);
579 if (ret < 0)
580 return ret;
581
582
583 ret = xdbc_alloc_ring(&xdbc.in_seg, &xdbc.in_ring);
584 if (ret < 0)
585 return ret;
586
587 ret = xdbc_alloc_ring(&xdbc.out_seg, &xdbc.out_ring);
588 if (ret < 0)
589 return ret;
590
591 xdbc_mem_init();
592
593 mmiowb();
594
595 ret = xdbc_start();
596 if (ret < 0) {
597 writel(0, &xdbc.xdbc_reg->control);
598 return ret;
599 }
600
601 xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED;
602
603 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
604
605 return 0;
606}
607
608int __init early_xdbc_parse_parameter(char *s)
609{
610 unsigned long dbgp_num = 0;
611 u32 bus, dev, func, offset;
612 int ret;
613
614 if (!early_pci_allowed())
615 return -EPERM;
616
617 if (strstr(s, "keep"))
618 early_console_keep = true;
619
620 if (xdbc.xdbc_reg)
621 return 0;
622
623 if (*s && kstrtoul(s, 0, &dbgp_num))
624 dbgp_num = 0;
625
626 pr_notice("dbgp_num: %lu\n", dbgp_num);
627
628
629 ret = xdbc_find_dbgp(dbgp_num, &bus, &dev, &func);
630 if (ret) {
631 pr_notice("failed to locate xhci host\n");
632 return -ENODEV;
633 }
634
635 xdbc.vendor = read_pci_config_16(bus, dev, func, PCI_VENDOR_ID);
636 xdbc.device = read_pci_config_16(bus, dev, func, PCI_DEVICE_ID);
637 xdbc.bus = bus;
638 xdbc.dev = dev;
639 xdbc.func = func;
640
641
642 xdbc.xhci_base = xdbc_map_pci_mmio(bus, dev, func);
643 if (!xdbc.xhci_base)
644 return -EINVAL;
645
646
647 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG);
648 if (!offset) {
649 pr_notice("xhci host doesn't support debug capability\n");
650 early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
651 xdbc.xhci_base = NULL;
652 xdbc.xhci_length = 0;
653
654 return -ENODEV;
655 }
656 xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset);
657
658 return 0;
659}
660
661int __init early_xdbc_setup_hardware(void)
662{
663 int ret;
664
665 if (!xdbc.xdbc_reg)
666 return -ENODEV;
667
668 xdbc_bios_handoff();
669
670 raw_spin_lock_init(&xdbc.lock);
671
672 ret = xdbc_early_setup();
673 if (ret) {
674 pr_notice("failed to setup the connection to host\n");
675
676 xdbc_free_ring(&xdbc.evt_ring);
677 xdbc_free_ring(&xdbc.out_ring);
678 xdbc_free_ring(&xdbc.in_ring);
679
680 if (xdbc.table_dma)
681 free_bootmem(xdbc.table_dma, PAGE_SIZE);
682
683 if (xdbc.out_dma)
684 free_bootmem(xdbc.out_dma, PAGE_SIZE);
685
686 xdbc.table_base = NULL;
687 xdbc.out_buf = NULL;
688 }
689
690 return ret;
691}
692
693static void xdbc_handle_port_status(struct xdbc_trb *evt_trb)
694{
695 u32 port_reg;
696
697 port_reg = readl(&xdbc.xdbc_reg->portsc);
698 if (port_reg & PORTSC_CONN_CHANGE) {
699 xdbc_trace("connect status change event\n");
700
701
702 if (!(port_reg & PORTSC_CONN_STATUS)) {
703 xdbc.flags = 0;
704 xdbc_trace("cable unplugged\n");
705 }
706 }
707
708 if (port_reg & PORTSC_RESET_CHANGE)
709 xdbc_trace("port reset change event\n");
710
711 if (port_reg & PORTSC_LINK_CHANGE)
712 xdbc_trace("port link status change event\n");
713
714 if (port_reg & PORTSC_CONFIG_CHANGE)
715 xdbc_trace("config error change\n");
716
717
718 writel(port_reg, &xdbc.xdbc_reg->portsc);
719}
720
721static void xdbc_handle_tx_event(struct xdbc_trb *evt_trb)
722{
723 size_t remain_length;
724 u32 comp_code;
725 int ep_id;
726
727 comp_code = GET_COMP_CODE(le32_to_cpu(evt_trb->field[2]));
728 remain_length = EVENT_TRB_LEN(le32_to_cpu(evt_trb->field[2]));
729 ep_id = TRB_TO_EP_ID(le32_to_cpu(evt_trb->field[3]));
730
731 switch (comp_code) {
732 case COMP_SUCCESS:
733 remain_length = 0;
734 case COMP_SHORT_PACKET:
735 break;
736 case COMP_TRB_ERROR:
737 case COMP_BABBLE_DETECTED_ERROR:
738 case COMP_USB_TRANSACTION_ERROR:
739 case COMP_STALL_ERROR:
740 default:
741 if (ep_id == XDBC_EPID_OUT)
742 xdbc.flags |= XDBC_FLAGS_OUT_STALL;
743 if (ep_id == XDBC_EPID_IN)
744 xdbc.flags |= XDBC_FLAGS_IN_STALL;
745
746 xdbc_trace("endpoint %d stalled\n", ep_id);
747 break;
748 }
749
750 if (ep_id == XDBC_EPID_IN) {
751 xdbc.flags &= ~XDBC_FLAGS_IN_PROCESS;
752 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
753 } else if (ep_id == XDBC_EPID_OUT) {
754 xdbc.flags &= ~XDBC_FLAGS_OUT_PROCESS;
755 } else {
756 xdbc_trace("invalid endpoint id %d\n", ep_id);
757 }
758}
759
760static void xdbc_handle_events(void)
761{
762 struct xdbc_trb *evt_trb;
763 bool update_erdp = false;
764 u32 reg;
765 u8 cmd;
766
767 cmd = read_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND);
768 if (!(cmd & PCI_COMMAND_MASTER)) {
769 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
770 write_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND, cmd);
771 }
772
773 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED))
774 return;
775
776
777 reg = readl(&xdbc.xdbc_reg->control);
778 if (!(reg & CTRL_DBC_ENABLE)) {
779 if (xdbc_handle_external_reset()) {
780 xdbc_trace("failed to recover connection\n");
781 return;
782 }
783 }
784
785
786 reg = readl(&xdbc.xdbc_reg->control);
787 if (reg & CTRL_DBC_RUN_CHANGE) {
788 writel(reg, &xdbc.xdbc_reg->control);
789 if (reg & CTRL_DBC_RUN)
790 xdbc.flags |= XDBC_FLAGS_CONFIGURED;
791 else
792 xdbc.flags &= ~XDBC_FLAGS_CONFIGURED;
793 }
794
795
796 reg = readl(&xdbc.xdbc_reg->control);
797 if (reg & CTRL_HALT_IN_TR) {
798 xdbc.flags |= XDBC_FLAGS_IN_STALL;
799 } else {
800 xdbc.flags &= ~XDBC_FLAGS_IN_STALL;
801 if (!(xdbc.flags & XDBC_FLAGS_IN_PROCESS))
802 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
803 }
804
805 if (reg & CTRL_HALT_OUT_TR)
806 xdbc.flags |= XDBC_FLAGS_OUT_STALL;
807 else
808 xdbc.flags &= ~XDBC_FLAGS_OUT_STALL;
809
810
811 evt_trb = xdbc.evt_ring.dequeue;
812 while ((le32_to_cpu(evt_trb->field[3]) & TRB_CYCLE) == xdbc.evt_ring.cycle_state) {
813
814
815
816
817 rmb();
818
819 switch ((le32_to_cpu(evt_trb->field[3]) & TRB_TYPE_BITMASK)) {
820 case TRB_TYPE(TRB_PORT_STATUS):
821 xdbc_handle_port_status(evt_trb);
822 break;
823 case TRB_TYPE(TRB_TRANSFER):
824 xdbc_handle_tx_event(evt_trb);
825 break;
826 default:
827 break;
828 }
829
830 ++(xdbc.evt_ring.dequeue);
831 if (xdbc.evt_ring.dequeue == &xdbc.evt_seg.trbs[TRBS_PER_SEGMENT]) {
832 xdbc.evt_ring.dequeue = xdbc.evt_seg.trbs;
833 xdbc.evt_ring.cycle_state ^= 1;
834 }
835
836 evt_trb = xdbc.evt_ring.dequeue;
837 update_erdp = true;
838 }
839
840
841 if (update_erdp)
842 xdbc_write64(__pa(xdbc.evt_ring.dequeue), &xdbc.xdbc_reg->erdp);
843}
844
845static int xdbc_bulk_write(const char *bytes, int size)
846{
847 int ret, timeout = 0;
848 unsigned long flags;
849
850retry:
851 if (in_nmi()) {
852 if (!raw_spin_trylock_irqsave(&xdbc.lock, flags))
853 return -EAGAIN;
854 } else {
855 raw_spin_lock_irqsave(&xdbc.lock, flags);
856 }
857
858 xdbc_handle_events();
859
860
861 if ((xdbc.flags & XDBC_FLAGS_OUT_PROCESS) && (timeout < 2000000)) {
862 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
863 udelay(100);
864 timeout += 100;
865 goto retry;
866 }
867
868 if (xdbc.flags & XDBC_FLAGS_OUT_PROCESS) {
869 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
870 xdbc_trace("previous transfer not completed yet\n");
871
872 return -ETIMEDOUT;
873 }
874
875 ret = xdbc_bulk_transfer((void *)bytes, size, false);
876 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
877
878 return ret;
879}
880
881static void early_xdbc_write(struct console *con, const char *str, u32 n)
882{
883 static char buf[XDBC_MAX_PACKET];
884 int chunk, ret;
885 int use_cr = 0;
886
887 if (!xdbc.xdbc_reg)
888 return;
889 memset(buf, 0, XDBC_MAX_PACKET);
890 while (n > 0) {
891 for (chunk = 0; chunk < XDBC_MAX_PACKET && n > 0; str++, chunk++, n--) {
892
893 if (!use_cr && *str == '\n') {
894 use_cr = 1;
895 buf[chunk] = '\r';
896 str--;
897 n++;
898 continue;
899 }
900
901 if (use_cr)
902 use_cr = 0;
903 buf[chunk] = *str;
904 }
905
906 if (chunk > 0) {
907 ret = xdbc_bulk_write(buf, chunk);
908 if (ret < 0)
909 xdbc_trace("missed message {%s}\n", buf);
910 }
911 }
912}
913
914static struct console early_xdbc_console = {
915 .name = "earlyxdbc",
916 .write = early_xdbc_write,
917 .flags = CON_PRINTBUFFER,
918 .index = -1,
919};
920
921void __init early_xdbc_register_console(void)
922{
923 if (early_console)
924 return;
925
926 early_console = &early_xdbc_console;
927 if (early_console_keep)
928 early_console->flags &= ~CON_BOOT;
929 else
930 early_console->flags |= CON_BOOT;
931 register_console(early_console);
932}
933
934static void xdbc_unregister_console(void)
935{
936 if (early_xdbc_console.flags & CON_ENABLED)
937 unregister_console(&early_xdbc_console);
938}
939
940static int xdbc_scrub_function(void *ptr)
941{
942 unsigned long flags;
943
944 while (true) {
945 raw_spin_lock_irqsave(&xdbc.lock, flags);
946 xdbc_handle_events();
947
948 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED)) {
949 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
950 break;
951 }
952
953 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
954 schedule_timeout_interruptible(1);
955 }
956
957 xdbc_unregister_console();
958 writel(0, &xdbc.xdbc_reg->control);
959 xdbc_trace("dbc scrub function exits\n");
960
961 return 0;
962}
963
964static int __init xdbc_init(void)
965{
966 unsigned long flags;
967 void __iomem *base;
968 int ret = 0;
969 u32 offset;
970
971 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED))
972 return 0;
973
974
975
976
977
978 if (early_xdbc_console.index == -1 ||
979 (early_xdbc_console.flags & CON_BOOT)) {
980 xdbc_trace("hardware not used anymore\n");
981 goto free_and_quit;
982 }
983
984 base = ioremap_nocache(xdbc.xhci_start, xdbc.xhci_length);
985 if (!base) {
986 xdbc_trace("failed to remap the io address\n");
987 ret = -ENOMEM;
988 goto free_and_quit;
989 }
990
991 raw_spin_lock_irqsave(&xdbc.lock, flags);
992 early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
993 xdbc.xhci_base = base;
994 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG);
995 xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset);
996 raw_spin_unlock_irqrestore(&xdbc.lock, flags);
997
998 kthread_run(xdbc_scrub_function, NULL, "%s", "xdbc");
999
1000 return 0;
1001
1002free_and_quit:
1003 xdbc_free_ring(&xdbc.evt_ring);
1004 xdbc_free_ring(&xdbc.out_ring);
1005 xdbc_free_ring(&xdbc.in_ring);
1006 free_bootmem(xdbc.table_dma, PAGE_SIZE);
1007 free_bootmem(xdbc.out_dma, PAGE_SIZE);
1008 writel(0, &xdbc.xdbc_reg->control);
1009 early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
1010
1011 return ret;
1012}
1013subsys_initcall(xdbc_init);
1014
