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44#ifndef __ACTBL2_H__
45#define __ACTBL2_H__
46
47
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62
63
64#define ACPI_SIG_ASF "ASF!"
65#define ACPI_SIG_BOOT "BOOT"
66#define ACPI_SIG_CSRT "CSRT"
67#define ACPI_SIG_DBG2 "DBG2"
68#define ACPI_SIG_DBGP "DBGP"
69#define ACPI_SIG_DMAR "DMAR"
70#define ACPI_SIG_HPET "HPET"
71#define ACPI_SIG_IBFT "IBFT"
72#define ACPI_SIG_IORT "IORT"
73#define ACPI_SIG_IVRS "IVRS"
74#define ACPI_SIG_LPIT "LPIT"
75#define ACPI_SIG_MCFG "MCFG"
76#define ACPI_SIG_MCHI "MCHI"
77#define ACPI_SIG_MSDM "MSDM"
78#define ACPI_SIG_MTMR "MTMR"
79#define ACPI_SIG_SDEI "SDEI"
80#define ACPI_SIG_SLIC "SLIC"
81#define ACPI_SIG_SPCR "SPCR"
82#define ACPI_SIG_SPMI "SPMI"
83#define ACPI_SIG_TCPA "TCPA"
84#define ACPI_SIG_TPM2 "TPM2"
85#define ACPI_SIG_UEFI "UEFI"
86#define ACPI_SIG_VRTC "VRTC"
87#define ACPI_SIG_WAET "WAET"
88#define ACPI_SIG_WDAT "WDAT"
89#define ACPI_SIG_WDDT "WDDT"
90#define ACPI_SIG_WDRT "WDRT"
91#define ACPI_SIG_WSMT "WSMT"
92#define ACPI_SIG_XXXX "XXXX"
93
94#ifdef ACPI_UNDEFINED_TABLES
95
96
97
98#define ACPI_SIG_ATKG "ATKG"
99#define ACPI_SIG_GSCI "GSCI"
100#define ACPI_SIG_IEIT "IEIT"
101#endif
102
103
104
105
106
107#pragma pack(1)
108
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128
129
130struct acpi_table_asf {
131 struct acpi_table_header header;
132};
133
134
135
136struct acpi_asf_header {
137 u8 type;
138 u8 reserved;
139 u16 length;
140};
141
142
143
144enum acpi_asf_type {
145 ACPI_ASF_TYPE_INFO = 0,
146 ACPI_ASF_TYPE_ALERT = 1,
147 ACPI_ASF_TYPE_CONTROL = 2,
148 ACPI_ASF_TYPE_BOOT = 3,
149 ACPI_ASF_TYPE_ADDRESS = 4,
150 ACPI_ASF_TYPE_RESERVED = 5
151};
152
153
154
155
156
157
158
159struct acpi_asf_info {
160 struct acpi_asf_header header;
161 u8 min_reset_value;
162 u8 min_poll_interval;
163 u16 system_id;
164 u32 mfg_id;
165 u8 flags;
166 u8 reserved2[3];
167};
168
169
170
171#define ACPI_ASF_SMBUS_PROTOCOLS (1)
172
173
174
175struct acpi_asf_alert {
176 struct acpi_asf_header header;
177 u8 assert_mask;
178 u8 deassert_mask;
179 u8 alerts;
180 u8 data_length;
181};
182
183struct acpi_asf_alert_data {
184 u8 address;
185 u8 command;
186 u8 mask;
187 u8 value;
188 u8 sensor_type;
189 u8 type;
190 u8 offset;
191 u8 source_type;
192 u8 severity;
193 u8 sensor_number;
194 u8 entity;
195 u8 instance;
196};
197
198
199
200struct acpi_asf_remote {
201 struct acpi_asf_header header;
202 u8 controls;
203 u8 data_length;
204 u16 reserved2;
205};
206
207struct acpi_asf_control_data {
208 u8 function;
209 u8 address;
210 u8 command;
211 u8 value;
212};
213
214
215
216struct acpi_asf_rmcp {
217 struct acpi_asf_header header;
218 u8 capabilities[7];
219 u8 completion_code;
220 u32 enterprise_id;
221 u8 command;
222 u16 parameter;
223 u16 boot_options;
224 u16 oem_parameters;
225};
226
227
228
229struct acpi_asf_address {
230 struct acpi_asf_header header;
231 u8 eprom_address;
232 u8 devices;
233};
234
235
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242
243
244struct acpi_table_boot {
245 struct acpi_table_header header;
246 u8 cmos_index;
247 u8 reserved[3];
248};
249
250
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256
257
258
259struct acpi_table_csrt {
260 struct acpi_table_header header;
261};
262
263
264
265struct acpi_csrt_group {
266 u32 length;
267 u32 vendor_id;
268 u32 subvendor_id;
269 u16 device_id;
270 u16 subdevice_id;
271 u16 revision;
272 u16 reserved;
273 u32 shared_info_length;
274
275
276};
277
278
279
280struct acpi_csrt_shared_info {
281 u16 major_version;
282 u16 minor_version;
283 u32 mmio_base_low;
284 u32 mmio_base_high;
285 u32 gsi_interrupt;
286 u8 interrupt_polarity;
287 u8 interrupt_mode;
288 u8 num_channels;
289 u8 dma_address_width;
290 u16 base_request_line;
291 u16 num_handshake_signals;
292 u32 max_block_size;
293
294
295};
296
297
298
299struct acpi_csrt_descriptor {
300 u32 length;
301 u16 type;
302 u16 subtype;
303 u32 uid;
304
305
306};
307
308
309
310#define ACPI_CSRT_TYPE_INTERRUPT 0x0001
311#define ACPI_CSRT_TYPE_TIMER 0x0002
312#define ACPI_CSRT_TYPE_DMA 0x0003
313
314
315
316#define ACPI_CSRT_XRUPT_LINE 0x0000
317#define ACPI_CSRT_XRUPT_CONTROLLER 0x0001
318#define ACPI_CSRT_TIMER 0x0000
319#define ACPI_CSRT_DMA_CHANNEL 0x0000
320#define ACPI_CSRT_DMA_CONTROLLER 0x0001
321
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328
329
330
331struct acpi_table_dbg2 {
332 struct acpi_table_header header;
333 u32 info_offset;
334 u32 info_count;
335};
336
337struct acpi_dbg2_header {
338 u32 info_offset;
339 u32 info_count;
340};
341
342
343
344struct acpi_dbg2_device {
345 u8 revision;
346 u16 length;
347 u8 register_count;
348 u16 namepath_length;
349 u16 namepath_offset;
350 u16 oem_data_length;
351 u16 oem_data_offset;
352 u16 port_type;
353 u16 port_subtype;
354 u16 reserved;
355 u16 base_address_offset;
356 u16 address_size_offset;
357
358
359
360
361
362
363
364};
365
366
367
368#define ACPI_DBG2_SERIAL_PORT 0x8000
369#define ACPI_DBG2_1394_PORT 0x8001
370#define ACPI_DBG2_USB_PORT 0x8002
371#define ACPI_DBG2_NET_PORT 0x8003
372
373
374
375#define ACPI_DBG2_16550_COMPATIBLE 0x0000
376#define ACPI_DBG2_16550_SUBSET 0x0001
377#define ACPI_DBG2_ARM_PL011 0x0003
378#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D
379#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E
380#define ACPI_DBG2_ARM_DCC 0x000F
381#define ACPI_DBG2_BCM2835 0x0010
382
383#define ACPI_DBG2_1394_STANDARD 0x0000
384
385#define ACPI_DBG2_USB_XHCI 0x0000
386#define ACPI_DBG2_USB_EHCI 0x0001
387
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395
396
397struct acpi_table_dbgp {
398 struct acpi_table_header header;
399 u8 type;
400 u8 reserved[3];
401 struct acpi_generic_address debug_port;
402};
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412
413
414struct acpi_table_dmar {
415 struct acpi_table_header header;
416 u8 width;
417 u8 flags;
418 u8 reserved[10];
419};
420
421
422
423#define ACPI_DMAR_INTR_REMAP (1)
424#define ACPI_DMAR_X2APIC_OPT_OUT (1<<1)
425#define ACPI_DMAR_X2APIC_MODE (1<<2)
426
427
428
429struct acpi_dmar_header {
430 u16 type;
431 u16 length;
432};
433
434
435
436enum acpi_dmar_type {
437 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
438 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
439 ACPI_DMAR_TYPE_ROOT_ATS = 2,
440 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
441 ACPI_DMAR_TYPE_NAMESPACE = 4,
442 ACPI_DMAR_TYPE_RESERVED = 5
443};
444
445
446
447struct acpi_dmar_device_scope {
448 u8 entry_type;
449 u8 length;
450 u16 reserved;
451 u8 enumeration_id;
452 u8 bus;
453};
454
455
456
457enum acpi_dmar_scope_type {
458 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
459 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,
460 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
461 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
462 ACPI_DMAR_SCOPE_TYPE_HPET = 4,
463 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,
464 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6
465};
466
467struct acpi_dmar_pci_path {
468 u8 device;
469 u8 function;
470};
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472
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476
477
478struct acpi_dmar_hardware_unit {
479 struct acpi_dmar_header header;
480 u8 flags;
481 u8 reserved;
482 u16 segment;
483 u64 address;
484};
485
486
487
488#define ACPI_DMAR_INCLUDE_ALL (1)
489
490
491
492struct acpi_dmar_reserved_memory {
493 struct acpi_dmar_header header;
494 u16 reserved;
495 u16 segment;
496 u64 base_address;
497 u64 end_address;
498};
499
500
501
502#define ACPI_DMAR_ALLOW_ALL (1)
503
504
505
506struct acpi_dmar_atsr {
507 struct acpi_dmar_header header;
508 u8 flags;
509 u8 reserved;
510 u16 segment;
511};
512
513
514
515#define ACPI_DMAR_ALL_PORTS (1)
516
517
518
519struct acpi_dmar_rhsa {
520 struct acpi_dmar_header header;
521 u32 reserved;
522 u64 base_address;
523 u32 proximity_domain;
524};
525
526
527
528struct acpi_dmar_andd {
529 struct acpi_dmar_header header;
530 u8 reserved[3];
531 u8 device_number;
532 char device_name[1];
533};
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541
542
543
544
545struct acpi_table_hpet {
546 struct acpi_table_header header;
547 u32 id;
548 struct acpi_generic_address address;
549 u8 sequence;
550 u16 minimum_tick;
551 u8 flags;
552};
553
554
555
556#define ACPI_HPET_PAGE_PROTECT_MASK (3)
557
558
559
560enum acpi_hpet_page_protect {
561 ACPI_HPET_NO_PAGE_PROTECT = 0,
562 ACPI_HPET_PAGE_PROTECT4 = 1,
563 ACPI_HPET_PAGE_PROTECT64 = 2
564};
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579struct acpi_table_ibft {
580 struct acpi_table_header header;
581 u8 reserved[12];
582};
583
584
585
586struct acpi_ibft_header {
587 u8 type;
588 u8 version;
589 u16 length;
590 u8 index;
591 u8 flags;
592};
593
594
595
596enum acpi_ibft_type {
597 ACPI_IBFT_TYPE_NOT_USED = 0,
598 ACPI_IBFT_TYPE_CONTROL = 1,
599 ACPI_IBFT_TYPE_INITIATOR = 2,
600 ACPI_IBFT_TYPE_NIC = 3,
601 ACPI_IBFT_TYPE_TARGET = 4,
602 ACPI_IBFT_TYPE_EXTENSIONS = 5,
603 ACPI_IBFT_TYPE_RESERVED = 6
604};
605
606
607
608struct acpi_ibft_control {
609 struct acpi_ibft_header header;
610 u16 extensions;
611 u16 initiator_offset;
612 u16 nic0_offset;
613 u16 target0_offset;
614 u16 nic1_offset;
615 u16 target1_offset;
616};
617
618struct acpi_ibft_initiator {
619 struct acpi_ibft_header header;
620 u8 sns_server[16];
621 u8 slp_server[16];
622 u8 primary_server[16];
623 u8 secondary_server[16];
624 u16 name_length;
625 u16 name_offset;
626};
627
628struct acpi_ibft_nic {
629 struct acpi_ibft_header header;
630 u8 ip_address[16];
631 u8 subnet_mask_prefix;
632 u8 origin;
633 u8 gateway[16];
634 u8 primary_dns[16];
635 u8 secondary_dns[16];
636 u8 dhcp[16];
637 u16 vlan;
638 u8 mac_address[6];
639 u16 pci_address;
640 u16 name_length;
641 u16 name_offset;
642};
643
644struct acpi_ibft_target {
645 struct acpi_ibft_header header;
646 u8 target_ip_address[16];
647 u16 target_ip_socket;
648 u8 target_boot_lun[8];
649 u8 chap_type;
650 u8 nic_association;
651 u16 target_name_length;
652 u16 target_name_offset;
653 u16 chap_name_length;
654 u16 chap_name_offset;
655 u16 chap_secret_length;
656 u16 chap_secret_offset;
657 u16 reverse_chap_name_length;
658 u16 reverse_chap_name_offset;
659 u16 reverse_chap_secret_length;
660 u16 reverse_chap_secret_offset;
661};
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671
672struct acpi_table_iort {
673 struct acpi_table_header header;
674 u32 node_count;
675 u32 node_offset;
676 u32 reserved;
677};
678
679
680
681
682struct acpi_iort_node {
683 u8 type;
684 u16 length;
685 u8 revision;
686 u32 reserved;
687 u32 mapping_count;
688 u32 mapping_offset;
689 char node_data[1];
690};
691
692
693
694enum acpi_iort_node_type {
695 ACPI_IORT_NODE_ITS_GROUP = 0x00,
696 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
697 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
698 ACPI_IORT_NODE_SMMU = 0x03,
699 ACPI_IORT_NODE_SMMU_V3 = 0x04
700};
701
702struct acpi_iort_id_mapping {
703 u32 input_base;
704 u32 id_count;
705 u32 output_base;
706 u32 output_reference;
707 u32 flags;
708};
709
710
711
712#define ACPI_IORT_ID_SINGLE_MAPPING (1)
713
714struct acpi_iort_memory_access {
715 u32 cache_coherency;
716 u8 hints;
717 u16 reserved;
718 u8 memory_flags;
719};
720
721
722
723#define ACPI_IORT_NODE_COHERENT 0x00000001
724#define ACPI_IORT_NODE_NOT_COHERENT 0x00000000
725
726
727
728#define ACPI_IORT_HT_TRANSIENT (1)
729#define ACPI_IORT_HT_WRITE (1<<1)
730#define ACPI_IORT_HT_READ (1<<2)
731#define ACPI_IORT_HT_OVERRIDE (1<<3)
732
733
734
735#define ACPI_IORT_MF_COHERENCY (1)
736#define ACPI_IORT_MF_ATTRIBUTES (1<<1)
737
738
739
740
741struct acpi_iort_its_group {
742 u32 its_count;
743 u32 identifiers[1];
744};
745
746struct acpi_iort_named_component {
747 u32 node_flags;
748 u64 memory_properties;
749 u8 memory_address_limit;
750 char device_name[1];
751};
752
753struct acpi_iort_root_complex {
754 u64 memory_properties;
755 u32 ats_attribute;
756 u32 pci_segment_number;
757};
758
759
760
761#define ACPI_IORT_ATS_SUPPORTED 0x00000001
762#define ACPI_IORT_ATS_UNSUPPORTED 0x00000000
763
764struct acpi_iort_smmu {
765 u64 base_address;
766 u64 span;
767 u32 model;
768 u32 flags;
769 u32 global_interrupt_offset;
770 u32 context_interrupt_count;
771 u32 context_interrupt_offset;
772 u32 pmu_interrupt_count;
773 u32 pmu_interrupt_offset;
774 u64 interrupts[1];
775};
776
777
778
779#define ACPI_IORT_SMMU_V1 0x00000000
780#define ACPI_IORT_SMMU_V2 0x00000001
781#define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002
782#define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003
783#define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004
784#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005
785
786
787
788#define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
789#define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
790
791
792
793struct acpi_iort_smmu_gsi {
794 u32 nsg_irpt;
795 u32 nsg_irpt_flags;
796 u32 nsg_cfg_irpt;
797 u32 nsg_cfg_irpt_flags;
798};
799
800struct acpi_iort_smmu_v3 {
801 u64 base_address;
802 u32 flags;
803 u32 reserved;
804 u64 vatos_address;
805 u32 model;
806 u32 event_gsiv;
807 u32 pri_gsiv;
808 u32 gerr_gsiv;
809 u32 sync_gsiv;
810 u8 pxm;
811 u8 reserved1;
812 u16 reserved2;
813};
814
815
816
817#define ACPI_IORT_SMMU_V3_GENERIC 0x00000000
818#define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001
819#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002
820
821
822
823#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
824#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (1<<1)
825#define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
826
827
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829
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831
832
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834
835
836
837struct acpi_table_ivrs {
838 struct acpi_table_header header;
839 u32 info;
840 u64 reserved;
841};
842
843
844
845#define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00
846#define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000
847#define ACPI_IVRS_ATS_RESERVED 0x00400000
848
849
850
851struct acpi_ivrs_header {
852 u8 type;
853 u8 flags;
854 u16 length;
855 u16 device_id;
856};
857
858
859
860enum acpi_ivrs_type {
861 ACPI_IVRS_TYPE_HARDWARE = 0x10,
862 ACPI_IVRS_TYPE_MEMORY1 = 0x20,
863 ACPI_IVRS_TYPE_MEMORY2 = 0x21,
864 ACPI_IVRS_TYPE_MEMORY3 = 0x22
865};
866
867
868
869#define ACPI_IVHD_TT_ENABLE (1)
870#define ACPI_IVHD_PASS_PW (1<<1)
871#define ACPI_IVHD_RES_PASS_PW (1<<2)
872#define ACPI_IVHD_ISOC (1<<3)
873#define ACPI_IVHD_IOTLB (1<<4)
874
875
876
877#define ACPI_IVMD_UNITY (1)
878#define ACPI_IVMD_READ (1<<1)
879#define ACPI_IVMD_WRITE (1<<2)
880#define ACPI_IVMD_EXCLUSION_RANGE (1<<3)
881
882
883
884
885
886
887
888struct acpi_ivrs_hardware {
889 struct acpi_ivrs_header header;
890 u16 capability_offset;
891 u64 base_address;
892 u16 pci_segment_group;
893 u16 info;
894 u32 reserved;
895};
896
897
898
899#define ACPI_IVHD_MSI_NUMBER_MASK 0x001F
900#define ACPI_IVHD_UNIT_ID_MASK 0x1F00
901
902
903
904
905
906
907
908struct acpi_ivrs_de_header {
909 u8 type;
910 u16 id;
911 u8 data_setting;
912};
913
914
915
916#define ACPI_IVHD_ENTRY_LENGTH 0xC0
917
918
919
920enum acpi_ivrs_device_entry_type {
921
922
923 ACPI_IVRS_TYPE_PAD4 = 0,
924 ACPI_IVRS_TYPE_ALL = 1,
925 ACPI_IVRS_TYPE_SELECT = 2,
926 ACPI_IVRS_TYPE_START = 3,
927 ACPI_IVRS_TYPE_END = 4,
928
929
930
931 ACPI_IVRS_TYPE_PAD8 = 64,
932 ACPI_IVRS_TYPE_NOT_USED = 65,
933 ACPI_IVRS_TYPE_ALIAS_SELECT = 66,
934 ACPI_IVRS_TYPE_ALIAS_START = 67,
935 ACPI_IVRS_TYPE_EXT_SELECT = 70,
936 ACPI_IVRS_TYPE_EXT_START = 71,
937 ACPI_IVRS_TYPE_SPECIAL = 72
938};
939
940
941
942#define ACPI_IVHD_INIT_PASS (1)
943#define ACPI_IVHD_EINT_PASS (1<<1)
944#define ACPI_IVHD_NMI_PASS (1<<2)
945#define ACPI_IVHD_SYSTEM_MGMT (3<<4)
946#define ACPI_IVHD_LINT0_PASS (1<<6)
947#define ACPI_IVHD_LINT1_PASS (1<<7)
948
949
950
951struct acpi_ivrs_device4 {
952 struct acpi_ivrs_de_header header;
953};
954
955
956
957struct acpi_ivrs_device8a {
958 struct acpi_ivrs_de_header header;
959 u8 reserved1;
960 u16 used_id;
961 u8 reserved2;
962};
963
964
965
966struct acpi_ivrs_device8b {
967 struct acpi_ivrs_de_header header;
968 u32 extended_data;
969};
970
971
972
973#define ACPI_IVHD_ATS_DISABLED (1<<31)
974
975
976
977struct acpi_ivrs_device8c {
978 struct acpi_ivrs_de_header header;
979 u8 handle;
980 u16 used_id;
981 u8 variety;
982};
983
984
985
986#define ACPI_IVHD_IOAPIC 1
987#define ACPI_IVHD_HPET 2
988
989
990
991struct acpi_ivrs_memory {
992 struct acpi_ivrs_header header;
993 u16 aux_data;
994 u64 reserved;
995 u64 start_address;
996 u64 memory_length;
997};
998
999
1000
1001
1002
1003
1004
1005
1006
1007struct acpi_table_lpit {
1008 struct acpi_table_header header;
1009};
1010
1011
1012
1013struct acpi_lpit_header {
1014 u32 type;
1015 u32 length;
1016 u16 unique_id;
1017 u16 reserved;
1018 u32 flags;
1019};
1020
1021
1022
1023enum acpi_lpit_type {
1024 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
1025 ACPI_LPIT_TYPE_RESERVED = 0x01
1026};
1027
1028
1029
1030#define ACPI_LPIT_STATE_DISABLED (1)
1031#define ACPI_LPIT_NO_COUNTER (1<<1)
1032
1033
1034
1035
1036
1037
1038
1039struct acpi_lpit_native {
1040 struct acpi_lpit_header header;
1041 struct acpi_generic_address entry_trigger;
1042 u32 residency;
1043 u32 latency;
1044 struct acpi_generic_address residency_counter;
1045 u64 counter_frequency;
1046};
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057struct acpi_table_mcfg {
1058 struct acpi_table_header header;
1059 u8 reserved[8];
1060};
1061
1062
1063
1064struct acpi_mcfg_allocation {
1065 u64 address;
1066 u16 pci_segment;
1067 u8 start_bus_number;
1068 u8 end_bus_number;
1069 u32 reserved;
1070};
1071
1072
1073
1074
1075
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1078
1079
1080
1081
1082struct acpi_table_mchi {
1083 struct acpi_table_header header;
1084 u8 interface_type;
1085 u8 protocol;
1086 u64 protocol_data;
1087 u8 interrupt_type;
1088 u8 gpe;
1089 u8 pci_device_flag;
1090 u32 global_interrupt;
1091 struct acpi_generic_address control_register;
1092 u8 pci_segment;
1093 u8 pci_bus;
1094 u8 pci_device;
1095 u8 pci_function;
1096};
1097
1098
1099
1100
1101
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1103
1104
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1108
1109struct acpi_table_msdm {
1110 struct acpi_table_header header;
1111};
1112
1113
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1116
1117
1118
1119
1120
1121
1122
1123
1124struct acpi_table_mtmr {
1125 struct acpi_table_header header;
1126};
1127
1128
1129
1130struct acpi_mtmr_entry {
1131 struct acpi_generic_address physical_address;
1132 u32 frequency;
1133 u32 irq;
1134};
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145struct acpi_table_sdei {
1146 struct acpi_table_header header;
1147};
1148
1149
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1159
1160struct acpi_table_slic {
1161 struct acpi_table_header header;
1162};
1163
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1171
1172
1173
1174struct acpi_table_spcr {
1175 struct acpi_table_header header;
1176 u8 interface_type;
1177 u8 reserved[3];
1178 struct acpi_generic_address serial_port;
1179 u8 interrupt_type;
1180 u8 pc_interrupt;
1181 u32 interrupt;
1182 u8 baud_rate;
1183 u8 parity;
1184 u8 stop_bits;
1185 u8 flow_control;
1186 u8 terminal_type;
1187 u8 reserved1;
1188 u16 pci_device_id;
1189 u16 pci_vendor_id;
1190 u8 pci_bus;
1191 u8 pci_device;
1192 u8 pci_function;
1193 u32 pci_flags;
1194 u8 pci_segment;
1195 u32 reserved2;
1196};
1197
1198
1199
1200#define ACPI_SPCR_DO_NOT_DISABLE (1)
1201
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1214
1215struct acpi_table_spmi {
1216 struct acpi_table_header header;
1217 u8 interface_type;
1218 u8 reserved;
1219 u16 spec_revision;
1220 u8 interrupt_type;
1221 u8 gpe_number;
1222 u8 reserved1;
1223 u8 pci_device_flag;
1224 u32 interrupt;
1225 struct acpi_generic_address ipmi_register;
1226 u8 pci_segment;
1227 u8 pci_bus;
1228 u8 pci_device;
1229 u8 pci_function;
1230 u8 reserved2;
1231};
1232
1233
1234
1235enum acpi_spmi_interface_types {
1236 ACPI_SPMI_NOT_USED = 0,
1237 ACPI_SPMI_KEYBOARD = 1,
1238 ACPI_SPMI_SMI = 2,
1239 ACPI_SPMI_BLOCK_TRANSFER = 3,
1240 ACPI_SPMI_SMBUS = 4,
1241 ACPI_SPMI_RESERVED = 5
1242};
1243
1244
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1246
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1258
1259struct acpi_table_tcpa_hdr {
1260 struct acpi_table_header header;
1261 u16 platform_class;
1262};
1263
1264
1265
1266
1267
1268#define ACPI_TCPA_CLIENT_TABLE 0
1269#define ACPI_TCPA_SERVER_TABLE 1
1270
1271struct acpi_table_tcpa_client {
1272 u32 minimum_log_length;
1273 u64 log_address;
1274};
1275
1276struct acpi_table_tcpa_server {
1277 u16 reserved;
1278 u64 minimum_log_length;
1279 u64 log_address;
1280 u16 spec_revision;
1281 u8 device_flags;
1282 u8 interrupt_flags;
1283 u8 gpe_number;
1284 u8 reserved2[3];
1285 u32 global_interrupt;
1286 struct acpi_generic_address address;
1287 u32 reserved3;
1288 struct acpi_generic_address config_address;
1289 u8 group;
1290 u8 bus;
1291 u8 device;
1292 u8 function;
1293};
1294
1295
1296
1297#define ACPI_TCPA_PCI_DEVICE (1)
1298#define ACPI_TCPA_BUS_PNP (1<<1)
1299#define ACPI_TCPA_ADDRESS_VALID (1<<2)
1300
1301
1302
1303#define ACPI_TCPA_INTERRUPT_MODE (1)
1304#define ACPI_TCPA_INTERRUPT_POLARITY (1<<1)
1305#define ACPI_TCPA_SCI_VIA_GPE (1<<2)
1306#define ACPI_TCPA_GLOBAL_INTERRUPT (1<<3)
1307
1308
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1315
1316
1317
1318
1319struct acpi_table_tpm2 {
1320 struct acpi_table_header header;
1321 u16 platform_class;
1322 u16 reserved;
1323 u64 control_address;
1324 u32 start_method;
1325
1326
1327};
1328
1329
1330
1331#define ACPI_TPM2_NOT_ALLOWED 0
1332#define ACPI_TPM2_START_METHOD 2
1333#define ACPI_TPM2_MEMORY_MAPPED 6
1334#define ACPI_TPM2_COMMAND_BUFFER 7
1335#define ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD 8
1336#define ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC 11
1337
1338
1339
1340struct acpi_tpm2_trailer {
1341 u32 minimum_log_length;
1342 u64 log_address;
1343};
1344
1345
1346
1347
1348
1349
1350
1351struct acpi_tpm2_arm_smc {
1352 u32 global_interrupt;
1353 u8 interrupt_flags;
1354 u8 operation_flags;
1355 u16 reserved;
1356 u32 function_id;
1357};
1358
1359
1360
1361#define ACPI_TPM2_INTERRUPT_SUPPORT (1)
1362
1363
1364
1365#define ACPI_TPM2_IDLE_SUPPORT (1)
1366
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1371
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1375
1376
1377struct acpi_table_uefi {
1378 struct acpi_table_header header;
1379 u8 identifier[16];
1380 u16 data_offset;
1381};
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394struct acpi_table_vrtc {
1395 struct acpi_table_header header;
1396};
1397
1398
1399
1400struct acpi_vrtc_entry {
1401 struct acpi_generic_address physical_address;
1402 u32 irq;
1403};
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414struct acpi_table_waet {
1415 struct acpi_table_header header;
1416 u32 flags;
1417};
1418
1419
1420
1421#define ACPI_WAET_RTC_NO_ACK (1)
1422#define ACPI_WAET_TIMER_ONE_READ (1<<1)
1423
1424
1425
1426
1427
1428
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1430
1431
1432
1433
1434struct acpi_table_wdat {
1435 struct acpi_table_header header;
1436 u32 header_length;
1437 u16 pci_segment;
1438 u8 pci_bus;
1439 u8 pci_device;
1440 u8 pci_function;
1441 u8 reserved[3];
1442 u32 timer_period;
1443 u32 max_count;
1444 u32 min_count;
1445 u8 flags;
1446 u8 reserved2[3];
1447 u32 entries;
1448};
1449
1450
1451
1452#define ACPI_WDAT_ENABLED (1)
1453#define ACPI_WDAT_STOPPED 0x80
1454
1455
1456
1457struct acpi_wdat_entry {
1458 u8 action;
1459 u8 instruction;
1460 u16 reserved;
1461 struct acpi_generic_address register_region;
1462 u32 value;
1463 u32 mask;
1464};
1465
1466
1467
1468enum acpi_wdat_actions {
1469 ACPI_WDAT_RESET = 1,
1470 ACPI_WDAT_GET_CURRENT_COUNTDOWN = 4,
1471 ACPI_WDAT_GET_COUNTDOWN = 5,
1472 ACPI_WDAT_SET_COUNTDOWN = 6,
1473 ACPI_WDAT_GET_RUNNING_STATE = 8,
1474 ACPI_WDAT_SET_RUNNING_STATE = 9,
1475 ACPI_WDAT_GET_STOPPED_STATE = 10,
1476 ACPI_WDAT_SET_STOPPED_STATE = 11,
1477 ACPI_WDAT_GET_REBOOT = 16,
1478 ACPI_WDAT_SET_REBOOT = 17,
1479 ACPI_WDAT_GET_SHUTDOWN = 18,
1480 ACPI_WDAT_SET_SHUTDOWN = 19,
1481 ACPI_WDAT_GET_STATUS = 32,
1482 ACPI_WDAT_SET_STATUS = 33,
1483 ACPI_WDAT_ACTION_RESERVED = 34
1484};
1485
1486
1487
1488enum acpi_wdat_instructions {
1489 ACPI_WDAT_READ_VALUE = 0,
1490 ACPI_WDAT_READ_COUNTDOWN = 1,
1491 ACPI_WDAT_WRITE_VALUE = 2,
1492 ACPI_WDAT_WRITE_COUNTDOWN = 3,
1493 ACPI_WDAT_INSTRUCTION_RESERVED = 4,
1494 ACPI_WDAT_PRESERVE_REGISTER = 0x80
1495};
1496
1497
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1499
1500
1501
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1503
1504
1505
1506
1507struct acpi_table_wddt {
1508 struct acpi_table_header header;
1509 u16 spec_version;
1510 u16 table_version;
1511 u16 pci_vendor_id;
1512 struct acpi_generic_address address;
1513 u16 max_count;
1514 u16 min_count;
1515 u16 period;
1516 u16 status;
1517 u16 capability;
1518};
1519
1520
1521
1522#define ACPI_WDDT_AVAILABLE (1)
1523#define ACPI_WDDT_ACTIVE (1<<1)
1524#define ACPI_WDDT_TCO_OS_OWNED (1<<2)
1525#define ACPI_WDDT_USER_RESET (1<<11)
1526#define ACPI_WDDT_WDT_RESET (1<<12)
1527#define ACPI_WDDT_POWER_FAIL (1<<13)
1528#define ACPI_WDDT_UNKNOWN_RESET (1<<14)
1529
1530
1531
1532#define ACPI_WDDT_AUTO_RESET (1)
1533#define ACPI_WDDT_ALERT_SUPPORT (1<<1)
1534
1535
1536
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1538
1539
1540
1541
1542
1543
1544
1545struct acpi_table_wdrt {
1546 struct acpi_table_header header;
1547 struct acpi_generic_address control_register;
1548 struct acpi_generic_address count_register;
1549 u16 pci_device_id;
1550 u16 pci_vendor_id;
1551 u8 pci_bus;
1552 u8 pci_device;
1553 u8 pci_function;
1554 u8 pci_segment;
1555 u16 max_count;
1556 u8 units;
1557};
1558
1559
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1561
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1565
1566
1567
1568
1569struct acpi_table_wsmt {
1570 struct acpi_table_header header;
1571 u32 protection_flags;
1572};
1573
1574
1575
1576#define ACPI_WSMT_FIXED_COMM_BUFFERS (1)
1577#define ACPI_WSMT_COMM_BUFFER_NESTED_PTR_PROTECTION (2)
1578#define ACPI_WSMT_SYSTEM_RESOURCE_PROTECTION (4)
1579
1580
1581
1582#pragma pack()
1583
1584#endif
1585