1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Exynos4 clock controller. 10*/ 11 12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 13#define _DT_BINDINGS_CLOCK_EXYNOS_4_H 14 15/* core clocks */ 16#define CLK_XXTI 1 17#define CLK_XUSBXTI 2 18#define CLK_FIN_PLL 3 19#define CLK_FOUT_APLL 4 20#define CLK_FOUT_MPLL 5 21#define CLK_FOUT_EPLL 6 22#define CLK_FOUT_VPLL 7 23#define CLK_SCLK_APLL 8 24#define CLK_SCLK_MPLL 9 25#define CLK_SCLK_EPLL 10 26#define CLK_SCLK_VPLL 11 27#define CLK_ARM_CLK 12 28#define CLK_ACLK200 13 29#define CLK_ACLK100 14 30#define CLK_ACLK160 15 31#define CLK_ACLK133 16 32#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 33#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 34#define CLK_MOUT_CORE 19 35#define CLK_MOUT_APLL 20 36#define CLK_SCLK_HDMIPHY 22 37#define CLK_OUT_DMC 23 38#define CLK_OUT_TOP 24 39#define CLK_OUT_LEFTBUS 25 40#define CLK_OUT_RIGHTBUS 26 41#define CLK_OUT_CPU 27 42 43/* gate for special clocks (sclk) */ 44#define CLK_SCLK_FIMC0 128 45#define CLK_SCLK_FIMC1 129 46#define CLK_SCLK_FIMC2 130 47#define CLK_SCLK_FIMC3 131 48#define CLK_SCLK_CAM0 132 49#define CLK_SCLK_CAM1 133 50#define CLK_SCLK_CSIS0 134 51#define CLK_SCLK_CSIS1 135 52#define CLK_SCLK_HDMI 136 53#define CLK_SCLK_MIXER 137 54#define CLK_SCLK_DAC 138 55#define CLK_SCLK_PIXEL 139 56#define CLK_SCLK_FIMD0 140 57#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 58#define CLK_SCLK_MDNIE_PWM0 142 59#define CLK_SCLK_MIPI0 143 60#define CLK_SCLK_AUDIO0 144 61#define CLK_SCLK_MMC0 145 62#define CLK_SCLK_MMC1 146 63#define CLK_SCLK_MMC2 147 64#define CLK_SCLK_MMC3 148 65#define CLK_SCLK_MMC4 149 66#define CLK_SCLK_SATA 150 /* Exynos4210 only */ 67#define CLK_SCLK_UART0 151 68#define CLK_SCLK_UART1 152 69#define CLK_SCLK_UART2 153 70#define CLK_SCLK_UART3 154 71#define CLK_SCLK_UART4 155 72#define CLK_SCLK_AUDIO1 156 73#define CLK_SCLK_AUDIO2 157 74#define CLK_SCLK_SPDIF 158 75#define CLK_SCLK_SPI0 159 76#define CLK_SCLK_SPI1 160 77#define CLK_SCLK_SPI2 161 78#define CLK_SCLK_SLIMBUS 162 79#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 80#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 81#define CLK_SCLK_PCM1 165 82#define CLK_SCLK_PCM2 166 83#define CLK_SCLK_I2S1 167 84#define CLK_SCLK_I2S2 168 85#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 86#define CLK_SCLK_MFC 170 87#define CLK_SCLK_PCM0 171 88#define CLK_SCLK_G3D 172 89#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 90#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 91#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 92#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 93#define CLK_SCLK_FIMG2D 177 94 95/* gate clocks */ 96#define CLK_SSS 255 97#define CLK_FIMC0 256 98#define CLK_FIMC1 257 99#define CLK_FIMC2 258 100#define CLK_FIMC3 259 101#define CLK_CSIS0 260 102#define CLK_CSIS1 261 103#define CLK_JPEG 262 104#define CLK_SMMU_FIMC0 263 105#define CLK_SMMU_FIMC1 264 106#define CLK_SMMU_FIMC2 265 107#define CLK_SMMU_FIMC3 266 108#define CLK_SMMU_JPEG 267 109#define CLK_VP 268 110#define CLK_MIXER 269 111#define CLK_TVENC 270 /* Exynos4210 only */ 112#define CLK_HDMI 271 113#define CLK_SMMU_TV 272 114#define CLK_MFC 273 115#define CLK_SMMU_MFCL 274 116#define CLK_SMMU_MFCR 275 117#define CLK_G3D 276 118#define CLK_G2D 277 119#define CLK_ROTATOR 278 120#define CLK_MDMA 279 121#define CLK_SMMU_G2D 280 122#define CLK_SMMU_ROTATOR 281 123#define CLK_SMMU_MDMA 282 124#define CLK_FIMD0 283 125#define CLK_MIE0 284 126#define CLK_MDNIE0 285 /* Exynos4412 only */ 127#define CLK_DSIM0 286 128#define CLK_SMMU_FIMD0 287 129#define CLK_FIMD1 288 /* Exynos4210 only */ 130#define CLK_MIE1 289 /* Exynos4210 only */ 131#define CLK_DSIM1 290 /* Exynos4210 only */ 132#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 133#define CLK_PDMA0 292 134#define CLK_PDMA1 293 135#define CLK_PCIE_PHY 294 136#define CLK_SATA_PHY 295 /* Exynos4210 only */ 137#define CLK_TSI 296 138#define CLK_SDMMC0 297 139#define CLK_SDMMC1 298 140#define CLK_SDMMC2 299 141#define CLK_SDMMC3 300 142#define CLK_SDMMC4 301 143#define CLK_SATA 302 /* Exynos4210 only */ 144#define CLK_SROMC 303 145#define CLK_USB_HOST 304 146#define CLK_USB_DEVICE 305 147#define CLK_PCIE 306 148#define CLK_ONENAND 307 149#define CLK_NFCON 308 150#define CLK_SMMU_PCIE 309 151#define CLK_GPS 310 152#define CLK_SMMU_GPS 311 153#define CLK_UART0 312 154#define CLK_UART1 313 155#define CLK_UART2 314 156#define CLK_UART3 315 157#define CLK_UART4 316 158#define CLK_I2C0 317 159#define CLK_I2C1 318 160#define CLK_I2C2 319 161#define CLK_I2C3 320 162#define CLK_I2C4 321 163#define CLK_I2C5 322 164#define CLK_I2C6 323 165#define CLK_I2C7 324 166#define CLK_I2C_HDMI 325 167#define CLK_TSADC 326 168#define CLK_SPI0 327 169#define CLK_SPI1 328 170#define CLK_SPI2 329 171#define CLK_I2S1 330 172#define CLK_I2S2 331 173#define CLK_PCM0 332 174#define CLK_I2S0 333 175#define CLK_PCM1 334 176#define CLK_PCM2 335 177#define CLK_PWM 336 178#define CLK_SLIMBUS 337 179#define CLK_SPDIF 338 180#define CLK_AC97 339 181#define CLK_MODEMIF 340 182#define CLK_CHIPID 341 183#define CLK_SYSREG 342 184#define CLK_HDMI_CEC 343 185#define CLK_MCT 344 186#define CLK_WDT 345 187#define CLK_RTC 346 188#define CLK_KEYIF 347 189#define CLK_AUDSS 348 190#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 191#define CLK_PIXELASYNCM0 351 192#define CLK_PIXELASYNCM1 352 193#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ 194#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ 195#define CLK_PPMUISPX 355 /* Exynos4x12 only */ 196#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ 197#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ 198#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ 199#define CLK_FIMC_FD 359 /* Exynos4x12 only */ 200#define CLK_MCUISP 360 /* Exynos4x12 only */ 201#define CLK_GICISP 361 /* Exynos4x12 only */ 202#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ 203#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ 204#define CLK_SMMU_FD 364 /* Exynos4x12 only */ 205#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ 206#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ 207#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ 208#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ 209#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ 210#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ 211#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ 212#define CLK_PWM_ISP 372 /* Exynos4x12 only */ 213#define CLK_WDT_ISP 373 /* Exynos4x12 only */ 214#define CLK_UART_ISP 374 /* Exynos4x12 only */ 215#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ 216#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ 217#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ 218#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ 219#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 220#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 221#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 222#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 223#define CLK_TMU_APBIF 383 224 225/* mux clocks */ 226#define CLK_MOUT_FIMC0 384 227#define CLK_MOUT_FIMC1 385 228#define CLK_MOUT_FIMC2 386 229#define CLK_MOUT_FIMC3 387 230#define CLK_MOUT_CAM0 388 231#define CLK_MOUT_CAM1 389 232#define CLK_MOUT_CSIS0 390 233#define CLK_MOUT_CSIS1 391 234#define CLK_MOUT_G3D0 392 235#define CLK_MOUT_G3D1 393 236#define CLK_MOUT_G3D 394 237#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 238#define CLK_MOUT_HDMI 396 239#define CLK_MOUT_MIXER 397 240 241/* gate clocks - ppmu */ 242#define CLK_PPMULEFT 400 243#define CLK_PPMURIGHT 401 244#define CLK_PPMUCAMIF 402 245#define CLK_PPMUTV 403 246#define CLK_PPMUMFC_L 404 247#define CLK_PPMUMFC_R 405 248#define CLK_PPMUG3D 406 249#define CLK_PPMUIMAGE 407 250#define CLK_PPMULCD0 408 251#define CLK_PPMULCD1 409 /* Exynos4210 only */ 252#define CLK_PPMUFILE 410 253#define CLK_PPMUGPS 411 254#define CLK_PPMUDMC0 412 255#define CLK_PPMUDMC1 413 256#define CLK_PPMUCPU 414 257#define CLK_PPMUACP 415 258 259/* div clocks */ 260#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ 261#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ 262#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ 263#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 264#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 265#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 266#define CLK_DIV_ACP 456 267#define CLK_DIV_DMC 457 268#define CLK_DIV_C2C 458 /* Exynos4x12 only */ 269#define CLK_DIV_GDL 459 270#define CLK_DIV_GDR 460 271 272/* must be greater than maximal clock id */ 273#define CLK_NR_CLKS 461 274 275#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 276