1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#include <linux/init.h>
34#include <linux/io.h>
35#include <linux/module.h>
36#include <linux/interrupt.h>
37#include <linux/clk.h>
38#include <linux/ctype.h>
39#include <linux/device.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/of.h>
44#include <linux/of_address.h>
45#include <linux/of_irq.h>
46#include <linux/of_platform.h>
47
48#include <sound/core.h>
49#include <sound/pcm.h>
50#include <sound/pcm_params.h>
51#include <sound/initval.h>
52#include <sound/soc.h>
53#include <sound/dmaengine_pcm.h>
54
55#include "fsl_ssi.h"
56#include "imx-pcm.h"
57
58
59
60
61
62
63
64
65
66
67
68
69
70#ifdef __BIG_ENDIAN
71#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
72 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
73 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
74#else
75#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
76 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
77 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
78#endif
79
80#define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
81 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
82 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
83#define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
84 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
85 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
86
87enum fsl_ssi_type {
88 FSL_SSI_MCP8610,
89 FSL_SSI_MX21,
90 FSL_SSI_MX35,
91 FSL_SSI_MX51,
92};
93
94struct fsl_ssi_reg_val {
95 u32 sier;
96 u32 srcr;
97 u32 stcr;
98 u32 scr;
99};
100
101struct fsl_ssi_rxtx_reg_val {
102 struct fsl_ssi_reg_val rx;
103 struct fsl_ssi_reg_val tx;
104};
105
106static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
107{
108 switch (reg) {
109 case CCSR_SSI_SACCEN:
110 case CCSR_SSI_SACCDIS:
111 return false;
112 default:
113 return true;
114 }
115}
116
117static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
118{
119 switch (reg) {
120 case CCSR_SSI_STX0:
121 case CCSR_SSI_STX1:
122 case CCSR_SSI_SRX0:
123 case CCSR_SSI_SRX1:
124 case CCSR_SSI_SISR:
125 case CCSR_SSI_SFCSR:
126 case CCSR_SSI_SACNT:
127 case CCSR_SSI_SACADD:
128 case CCSR_SSI_SACDAT:
129 case CCSR_SSI_SATAG:
130 case CCSR_SSI_SACCST:
131 case CCSR_SSI_SOR:
132 return true;
133 default:
134 return false;
135 }
136}
137
138static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
139{
140 switch (reg) {
141 case CCSR_SSI_SRX0:
142 case CCSR_SSI_SRX1:
143 case CCSR_SSI_SISR:
144 case CCSR_SSI_SACADD:
145 case CCSR_SSI_SACDAT:
146 case CCSR_SSI_SATAG:
147 return true;
148 default:
149 return false;
150 }
151}
152
153static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
154{
155 switch (reg) {
156 case CCSR_SSI_SRX0:
157 case CCSR_SSI_SRX1:
158 case CCSR_SSI_SACCST:
159 return false;
160 default:
161 return true;
162 }
163}
164
165static const struct regmap_config fsl_ssi_regconfig = {
166 .max_register = CCSR_SSI_SACCDIS,
167 .reg_bits = 32,
168 .val_bits = 32,
169 .reg_stride = 4,
170 .val_format_endian = REGMAP_ENDIAN_NATIVE,
171 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
172 .readable_reg = fsl_ssi_readable_reg,
173 .volatile_reg = fsl_ssi_volatile_reg,
174 .precious_reg = fsl_ssi_precious_reg,
175 .writeable_reg = fsl_ssi_writeable_reg,
176 .cache_type = REGCACHE_FLAT,
177};
178
179struct fsl_ssi_soc_data {
180 bool imx;
181 bool imx21regs;
182 bool offline_config;
183 u32 sisr_write_mask;
184};
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225struct fsl_ssi_private {
226 struct regmap *regs;
227 int irq;
228 struct snd_soc_dai_driver cpu_dai_drv;
229
230 unsigned int dai_fmt;
231 u8 i2s_mode;
232 bool use_dma;
233 bool use_dual_fifo;
234 bool has_ipg_clk_name;
235 unsigned int fifo_depth;
236 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
237
238 struct clk *clk;
239 struct clk *baudclk;
240 unsigned int baudclk_streams;
241 unsigned int bitclk_freq;
242
243
244 u32 regcache_sfcsr;
245 u32 regcache_sacnt;
246
247
248 struct snd_dmaengine_dai_dma_data dma_params_tx;
249 struct snd_dmaengine_dai_dma_data dma_params_rx;
250 dma_addr_t ssi_phys;
251
252
253 struct imx_pcm_fiq_params fiq_params;
254
255
256
257 struct platform_device *pdev;
258
259 struct fsl_ssi_dbg dbg_stats;
260
261 const struct fsl_ssi_soc_data *soc;
262 struct device *dev;
263
264 u32 fifo_watermark;
265 u32 dma_maxburst;
266};
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
285 .imx = false,
286 .offline_config = true,
287 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
288 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
289 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
290};
291
292static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
293 .imx = true,
294 .imx21regs = true,
295 .offline_config = true,
296 .sisr_write_mask = 0,
297};
298
299static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
300 .imx = true,
301 .offline_config = true,
302 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
303 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
304 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
305};
306
307static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
308 .imx = true,
309 .offline_config = false,
310 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
311 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
312};
313
314static const struct of_device_id fsl_ssi_ids[] = {
315 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
316 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
317 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
318 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
319 {}
320};
321MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
322
323static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
324{
325 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
326 SND_SOC_DAIFMT_AC97;
327}
328
329static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
330{
331 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
332 SND_SOC_DAIFMT_CBS_CFS;
333}
334
335static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
336{
337 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
338 SND_SOC_DAIFMT_CBM_CFS;
339}
340
341
342
343
344
345
346
347
348
349
350
351
352static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
353{
354 struct fsl_ssi_private *ssi_private = dev_id;
355 struct regmap *regs = ssi_private->regs;
356 __be32 sisr;
357 __be32 sisr2;
358
359
360
361
362
363 regmap_read(regs, CCSR_SSI_SISR, &sisr);
364
365 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
366
367 if (sisr2)
368 regmap_write(regs, CCSR_SSI_SISR, sisr2);
369
370 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
371
372 return IRQ_HANDLED;
373}
374
375
376
377
378static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
379 bool enable)
380{
381 struct regmap *regs = ssi_private->regs;
382 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
383
384 if (enable) {
385 regmap_update_bits(regs, CCSR_SSI_SIER,
386 vals->rx.sier | vals->tx.sier,
387 vals->rx.sier | vals->tx.sier);
388 regmap_update_bits(regs, CCSR_SSI_SRCR,
389 vals->rx.srcr | vals->tx.srcr,
390 vals->rx.srcr | vals->tx.srcr);
391 regmap_update_bits(regs, CCSR_SSI_STCR,
392 vals->rx.stcr | vals->tx.stcr,
393 vals->rx.stcr | vals->tx.stcr);
394 } else {
395 regmap_update_bits(regs, CCSR_SSI_SRCR,
396 vals->rx.srcr | vals->tx.srcr, 0);
397 regmap_update_bits(regs, CCSR_SSI_STCR,
398 vals->rx.stcr | vals->tx.stcr, 0);
399 regmap_update_bits(regs, CCSR_SSI_SIER,
400 vals->rx.sier | vals->tx.sier, 0);
401 }
402}
403
404
405
406
407
408
409
410
411
412static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private,
413 bool is_rx)
414{
415 if (is_rx) {
416 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
417 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR);
418 } else {
419 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR,
420 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR);
421 }
422}
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440#define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
441 ((vals_disable) & \
442 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
443
444
445
446
447
448static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
449 struct fsl_ssi_reg_val *vals)
450{
451 struct regmap *regs = ssi_private->regs;
452 struct fsl_ssi_reg_val *avals;
453 int nr_active_streams;
454 u32 scr_val;
455 int keep_active;
456
457 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
458
459 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
460 !!(scr_val & CCSR_SSI_SCR_RE);
461
462 if (nr_active_streams - 1 > 0)
463 keep_active = 1;
464 else
465 keep_active = 0;
466
467
468
469 if (&ssi_private->rxtx_reg_val.rx == vals)
470 avals = &ssi_private->rxtx_reg_val.tx;
471 else
472 avals = &ssi_private->rxtx_reg_val.rx;
473
474
475 if (!enable) {
476 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
477 keep_active);
478 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
479 }
480
481
482
483
484
485
486 if (ssi_private->soc->offline_config) {
487 if ((enable && !nr_active_streams) ||
488 (!enable && !keep_active))
489 fsl_ssi_rxtx_config(ssi_private, enable);
490
491 goto config_done;
492 }
493
494
495
496
497
498 if (enable) {
499 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE);
500
501 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
502 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
503 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
504 } else {
505 u32 sier;
506 u32 srcr;
507 u32 stcr;
508
509
510
511
512
513
514
515
516
517
518
519 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
520 keep_active);
521 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
522 keep_active);
523 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
524 keep_active);
525
526 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
527 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
528 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
529 }
530
531config_done:
532
533 if (enable) {
534 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) {
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550 int i;
551 int max_loop = 100;
552 regmap_update_bits(regs, CCSR_SSI_SCR,
553 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN);
554 for (i = 0; i < max_loop; i++) {
555 u32 sfcsr;
556 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr);
557 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr))
558 break;
559 }
560 if (i == max_loop) {
561 dev_err(ssi_private->dev,
562 "Timeout waiting TX FIFO filling\n");
563 }
564 }
565 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
566 }
567}
568
569
570static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
571{
572 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
573}
574
575static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
576{
577 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
578}
579
580
581
582
583
584
585static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
586{
587 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
588
589 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
591 reg->rx.scr = 0;
592 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
594 reg->tx.scr = 0;
595
596 if (!fsl_ssi_is_ac97(ssi_private)) {
597 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
601 }
602
603 if (ssi_private->use_dma) {
604 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
606 } else {
607 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608 reg->tx.sier |= CCSR_SSI_SIER_TIE;
609 }
610
611 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
613}
614
615static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
616{
617 struct regmap *regs = ssi_private->regs;
618
619
620
621
622 regmap_write(regs, CCSR_SSI_STCCR,
623 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
624 regmap_write(regs, CCSR_SSI_SRCCR,
625 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
626
627
628
629
630 regmap_write(regs, CCSR_SSI_SACNT,
631 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
632
633
634 if (!ssi_private->soc->imx21regs) {
635 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
636 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
637 }
638
639
640
641
642
643 regmap_update_bits(regs, CCSR_SSI_SCR,
644 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
645 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
646
647 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
648}
649
650
651
652
653
654
655
656
657
658static int fsl_ssi_startup(struct snd_pcm_substream *substream,
659 struct snd_soc_dai *dai)
660{
661 struct snd_soc_pcm_runtime *rtd = substream->private_data;
662 struct fsl_ssi_private *ssi_private =
663 snd_soc_dai_get_drvdata(rtd->cpu_dai);
664 int ret;
665
666 ret = clk_prepare_enable(ssi_private->clk);
667 if (ret)
668 return ret;
669
670
671
672
673
674
675 if (ssi_private->use_dual_fifo)
676 snd_pcm_hw_constraint_step(substream->runtime, 0,
677 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
678
679 return 0;
680}
681
682
683
684
685
686static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
687 struct snd_soc_dai *dai)
688{
689 struct snd_soc_pcm_runtime *rtd = substream->private_data;
690 struct fsl_ssi_private *ssi_private =
691 snd_soc_dai_get_drvdata(rtd->cpu_dai);
692
693 clk_disable_unprepare(ssi_private->clk);
694
695}
696
697
698
699
700
701
702
703
704
705
706static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
707 struct snd_soc_dai *cpu_dai,
708 struct snd_pcm_hw_params *hw_params)
709{
710 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
711 struct regmap *regs = ssi_private->regs;
712 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
713 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
714 unsigned long clkrate, baudrate, tmprate;
715 u64 sub, savesub = 100000;
716 unsigned int freq;
717 bool baudclk_is_used;
718
719
720 if (ssi_private->bitclk_freq)
721 freq = ssi_private->bitclk_freq;
722 else
723 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
724
725
726 if (IS_ERR(ssi_private->baudclk))
727 return -EINVAL;
728
729
730
731
732
733 if (freq * 5 > clk_get_rate(ssi_private->clk)) {
734 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
735 return -EINVAL;
736 }
737
738 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
739
740
741 psr = 0;
742 div2 = 0;
743
744 factor = (div2 + 1) * (7 * psr + 1) * 2;
745
746 for (i = 0; i < 255; i++) {
747 tmprate = freq * factor * (i + 1);
748
749 if (baudclk_is_used)
750 clkrate = clk_get_rate(ssi_private->baudclk);
751 else
752 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
753
754 clkrate /= factor;
755 afreq = clkrate / (i + 1);
756
757 if (freq == afreq)
758 sub = 0;
759 else if (freq / afreq == 1)
760 sub = freq - afreq;
761 else if (afreq / freq == 1)
762 sub = afreq - freq;
763 else
764 continue;
765
766
767 sub *= 100000;
768 do_div(sub, freq);
769
770 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
771 baudrate = tmprate;
772 savesub = sub;
773 pm = i;
774 }
775
776
777 if (savesub == 0)
778 break;
779 }
780
781
782 if (pm == 999) {
783 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
784 return -EINVAL;
785 }
786
787 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
788 (psr ? CCSR_SSI_SxCCR_PSR : 0);
789 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
790 CCSR_SSI_SxCCR_PSR;
791
792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
793 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
794 else
795 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
796
797 if (!baudclk_is_used) {
798 ret = clk_set_rate(ssi_private->baudclk, baudrate);
799 if (ret) {
800 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
801 return -EINVAL;
802 }
803 }
804
805 return 0;
806}
807
808static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
809 int clk_id, unsigned int freq, int dir)
810{
811 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
812
813 ssi_private->bitclk_freq = freq;
814
815 return 0;
816}
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
832 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
833{
834 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
835 struct regmap *regs = ssi_private->regs;
836 unsigned int channels = params_channels(hw_params);
837 unsigned int sample_size = params_width(hw_params);
838 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
839 int ret;
840 u32 scr_val;
841 int enabled;
842
843 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
844 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
845
846
847
848
849
850 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
851 return 0;
852
853 if (fsl_ssi_is_i2s_master(ssi_private)) {
854 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
855 if (ret)
856 return ret;
857
858
859 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
860 ret = clk_prepare_enable(ssi_private->baudclk);
861 if (ret)
862 return ret;
863
864 ssi_private->baudclk_streams |= BIT(substream->stream);
865 }
866 }
867
868 if (!fsl_ssi_is_ac97(ssi_private)) {
869 u8 i2smode;
870
871
872
873
874 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
875 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
876 CCSR_SSI_SCR_NET;
877 else
878 i2smode = ssi_private->i2s_mode;
879
880 regmap_update_bits(regs, CCSR_SSI_SCR,
881 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
882 channels == 1 ? 0 : i2smode);
883 }
884
885
886
887
888
889
890
891
892
893
894
895
896 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
897 ssi_private->cpu_dai_drv.symmetric_rates)
898 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
899 wl);
900 else
901 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
902 wl);
903
904 return 0;
905}
906
907static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
908 struct snd_soc_dai *cpu_dai)
909{
910 struct snd_soc_pcm_runtime *rtd = substream->private_data;
911 struct fsl_ssi_private *ssi_private =
912 snd_soc_dai_get_drvdata(rtd->cpu_dai);
913
914 if (fsl_ssi_is_i2s_master(ssi_private) &&
915 ssi_private->baudclk_streams & BIT(substream->stream)) {
916 clk_disable_unprepare(ssi_private->baudclk);
917 ssi_private->baudclk_streams &= ~BIT(substream->stream);
918 }
919
920 return 0;
921}
922
923static int _fsl_ssi_set_dai_fmt(struct device *dev,
924 struct fsl_ssi_private *ssi_private,
925 unsigned int fmt)
926{
927 struct regmap *regs = ssi_private->regs;
928 u32 strcr = 0, stcr, srcr, scr, mask;
929 u8 wm;
930
931 ssi_private->dai_fmt = fmt;
932
933 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
934 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
935 return -EINVAL;
936 }
937
938 fsl_ssi_setup_reg_vals(ssi_private);
939
940 regmap_read(regs, CCSR_SSI_SCR, &scr);
941 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
942 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
943
944 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
945 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
946 CCSR_SSI_STCR_TEFS;
947 regmap_read(regs, CCSR_SSI_STCR, &stcr);
948 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
949 stcr &= ~mask;
950 srcr &= ~mask;
951
952 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
953 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
954 case SND_SOC_DAIFMT_I2S:
955 regmap_update_bits(regs, CCSR_SSI_STCCR,
956 CCSR_SSI_SxCCR_DC_MASK,
957 CCSR_SSI_SxCCR_DC(2));
958 regmap_update_bits(regs, CCSR_SSI_SRCCR,
959 CCSR_SSI_SxCCR_DC_MASK,
960 CCSR_SSI_SxCCR_DC(2));
961 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
962 case SND_SOC_DAIFMT_CBM_CFS:
963 case SND_SOC_DAIFMT_CBS_CFS:
964 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
965 break;
966 case SND_SOC_DAIFMT_CBM_CFM:
967 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
968 break;
969 default:
970 return -EINVAL;
971 }
972
973
974 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
975 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
976 break;
977 case SND_SOC_DAIFMT_LEFT_J:
978
979 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
980 break;
981 case SND_SOC_DAIFMT_DSP_A:
982
983 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
984 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
985 break;
986 case SND_SOC_DAIFMT_DSP_B:
987
988 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
989 CCSR_SSI_STCR_TXBIT0;
990 break;
991 case SND_SOC_DAIFMT_AC97:
992 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
993 break;
994 default:
995 return -EINVAL;
996 }
997 scr |= ssi_private->i2s_mode;
998
999
1000 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1001 case SND_SOC_DAIFMT_NB_NF:
1002
1003 break;
1004 case SND_SOC_DAIFMT_IB_NF:
1005
1006 strcr ^= CCSR_SSI_STCR_TSCKP;
1007 break;
1008 case SND_SOC_DAIFMT_NB_IF:
1009
1010 strcr ^= CCSR_SSI_STCR_TFSI;
1011 break;
1012 case SND_SOC_DAIFMT_IB_IF:
1013
1014 strcr ^= CCSR_SSI_STCR_TSCKP;
1015 strcr ^= CCSR_SSI_STCR_TFSI;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
1020
1021
1022 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1023 case SND_SOC_DAIFMT_CBS_CFS:
1024 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
1025 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
1026 break;
1027 case SND_SOC_DAIFMT_CBM_CFM:
1028 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1029 break;
1030 case SND_SOC_DAIFMT_CBM_CFS:
1031 strcr &= ~CCSR_SSI_STCR_TXDIR;
1032 strcr |= CCSR_SSI_STCR_TFDIR;
1033 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1034 break;
1035 default:
1036 if (!fsl_ssi_is_ac97(ssi_private))
1037 return -EINVAL;
1038 }
1039
1040 stcr |= strcr;
1041 srcr |= strcr;
1042
1043 if (ssi_private->cpu_dai_drv.symmetric_rates
1044 || fsl_ssi_is_ac97(ssi_private)) {
1045
1046 srcr &= ~CCSR_SSI_SRCR_RXDIR;
1047 scr |= CCSR_SSI_SCR_SYN;
1048 }
1049
1050 regmap_write(regs, CCSR_SSI_STCR, stcr);
1051 regmap_write(regs, CCSR_SSI_SRCR, srcr);
1052 regmap_write(regs, CCSR_SSI_SCR, scr);
1053
1054 wm = ssi_private->fifo_watermark;
1055
1056 regmap_write(regs, CCSR_SSI_SFCSR,
1057 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1058 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1059
1060 if (ssi_private->use_dual_fifo) {
1061 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1062 CCSR_SSI_SRCR_RFEN1);
1063 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1064 CCSR_SSI_STCR_TFEN1);
1065 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1066 CCSR_SSI_SCR_TCH_EN);
1067 }
1068
1069 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1070 fsl_ssi_setup_ac97(ssi_private);
1071
1072 return 0;
1073
1074}
1075
1076
1077
1078
1079static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1080{
1081 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1082
1083 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1084}
1085
1086
1087
1088
1089
1090
1091static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1092 u32 rx_mask, int slots, int slot_width)
1093{
1094 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1095 struct regmap *regs = ssi_private->regs;
1096 u32 val;
1097
1098
1099 regmap_read(regs, CCSR_SSI_SCR, &val);
1100 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1101 if (val && slots < 2) {
1102 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1103 return -EINVAL;
1104 }
1105
1106 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1107 CCSR_SSI_SxCCR_DC(slots));
1108 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1109 CCSR_SSI_SxCCR_DC(slots));
1110
1111
1112
1113
1114 regmap_read(regs, CCSR_SSI_SCR, &val);
1115 val &= CCSR_SSI_SCR_SSIEN;
1116 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1117 CCSR_SSI_SCR_SSIEN);
1118
1119 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1120 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1121
1122 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1123
1124 return 0;
1125}
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1137 struct snd_soc_dai *dai)
1138{
1139 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1140 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1141 struct regmap *regs = ssi_private->regs;
1142
1143 switch (cmd) {
1144 case SNDRV_PCM_TRIGGER_START:
1145 case SNDRV_PCM_TRIGGER_RESUME:
1146 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1147 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1148 fsl_ssi_tx_config(ssi_private, true);
1149 else
1150 fsl_ssi_rx_config(ssi_private, true);
1151 break;
1152
1153 case SNDRV_PCM_TRIGGER_STOP:
1154 case SNDRV_PCM_TRIGGER_SUSPEND:
1155 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1156 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1157 fsl_ssi_tx_config(ssi_private, false);
1158 else
1159 fsl_ssi_rx_config(ssi_private, false);
1160 break;
1161
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 if (fsl_ssi_is_ac97(ssi_private)) {
1167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1168 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1169 else
1170 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1171 }
1172
1173 return 0;
1174}
1175
1176static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1177{
1178 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1179
1180 if (ssi_private->soc->imx && ssi_private->use_dma) {
1181 dai->playback_dma_data = &ssi_private->dma_params_tx;
1182 dai->capture_dma_data = &ssi_private->dma_params_rx;
1183 }
1184
1185 return 0;
1186}
1187
1188static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1189 .startup = fsl_ssi_startup,
1190 .shutdown = fsl_ssi_shutdown,
1191 .hw_params = fsl_ssi_hw_params,
1192 .hw_free = fsl_ssi_hw_free,
1193 .set_fmt = fsl_ssi_set_dai_fmt,
1194 .set_sysclk = fsl_ssi_set_dai_sysclk,
1195 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1196 .trigger = fsl_ssi_trigger,
1197};
1198
1199
1200static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1201 .probe = fsl_ssi_dai_probe,
1202 .playback = {
1203 .stream_name = "CPU-Playback",
1204 .channels_min = 1,
1205 .channels_max = 32,
1206 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1207 .formats = FSLSSI_I2S_FORMATS,
1208 },
1209 .capture = {
1210 .stream_name = "CPU-Capture",
1211 .channels_min = 1,
1212 .channels_max = 32,
1213 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1214 .formats = FSLSSI_I2S_FORMATS,
1215 },
1216 .ops = &fsl_ssi_dai_ops,
1217};
1218
1219static const struct snd_soc_component_driver fsl_ssi_component = {
1220 .name = "fsl-ssi",
1221};
1222
1223static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1224 .bus_control = true,
1225 .probe = fsl_ssi_dai_probe,
1226 .playback = {
1227 .stream_name = "AC97 Playback",
1228 .channels_min = 2,
1229 .channels_max = 2,
1230 .rates = SNDRV_PCM_RATE_8000_48000,
1231 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1232 },
1233 .capture = {
1234 .stream_name = "AC97 Capture",
1235 .channels_min = 2,
1236 .channels_max = 2,
1237 .rates = SNDRV_PCM_RATE_48000,
1238 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1239 },
1240 .ops = &fsl_ssi_dai_ops,
1241};
1242
1243
1244static struct fsl_ssi_private *fsl_ac97_data;
1245
1246static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1247 unsigned short val)
1248{
1249 struct regmap *regs = fsl_ac97_data->regs;
1250 unsigned int lreg;
1251 unsigned int lval;
1252 int ret;
1253
1254 if (reg > 0x7f)
1255 return;
1256
1257 ret = clk_prepare_enable(fsl_ac97_data->clk);
1258 if (ret) {
1259 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1260 ret);
1261 return;
1262 }
1263
1264 lreg = reg << 12;
1265 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1266
1267 lval = val << 4;
1268 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1269
1270 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1271 CCSR_SSI_SACNT_WR);
1272 udelay(100);
1273
1274 clk_disable_unprepare(fsl_ac97_data->clk);
1275}
1276
1277static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1278 unsigned short reg)
1279{
1280 struct regmap *regs = fsl_ac97_data->regs;
1281
1282 unsigned short val = -1;
1283 u32 reg_val;
1284 unsigned int lreg;
1285 int ret;
1286
1287 ret = clk_prepare_enable(fsl_ac97_data->clk);
1288 if (ret) {
1289 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1290 ret);
1291 return -1;
1292 }
1293
1294 lreg = (reg & 0x7f) << 12;
1295 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1296 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1297 CCSR_SSI_SACNT_RD);
1298
1299 udelay(100);
1300
1301 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1302 val = (reg_val >> 4) & 0xffff;
1303
1304 clk_disable_unprepare(fsl_ac97_data->clk);
1305
1306 return val;
1307}
1308
1309static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1310 .read = fsl_ssi_ac97_read,
1311 .write = fsl_ssi_ac97_write,
1312};
1313
1314
1315
1316
1317static void make_lowercase(char *s)
1318{
1319 if (!s)
1320 return;
1321 for (; *s; s++)
1322 *s = tolower(*s);
1323}
1324
1325static int fsl_ssi_imx_probe(struct platform_device *pdev,
1326 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1327{
1328 struct device_node *np = pdev->dev.of_node;
1329 u32 dmas[4];
1330 int ret;
1331
1332 if (ssi_private->has_ipg_clk_name)
1333 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1334 else
1335 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1336 if (IS_ERR(ssi_private->clk)) {
1337 ret = PTR_ERR(ssi_private->clk);
1338 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1339 return ret;
1340 }
1341
1342 if (!ssi_private->has_ipg_clk_name) {
1343 ret = clk_prepare_enable(ssi_private->clk);
1344 if (ret) {
1345 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1346 return ret;
1347 }
1348 }
1349
1350
1351
1352
1353 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1354 if (IS_ERR(ssi_private->baudclk))
1355 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1356 PTR_ERR(ssi_private->baudclk));
1357
1358 ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst;
1359 ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst;
1360 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1361 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1362
1363 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1364 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1365 ssi_private->use_dual_fifo = true;
1366
1367
1368
1369 ssi_private->dma_params_tx.maxburst &= ~0x1;
1370 ssi_private->dma_params_rx.maxburst &= ~0x1;
1371 }
1372
1373 if (!ssi_private->use_dma) {
1374
1375
1376
1377
1378
1379
1380
1381
1382 ssi_private->fiq_params.irq = ssi_private->irq;
1383 ssi_private->fiq_params.base = iomem;
1384 ssi_private->fiq_params.dma_params_rx =
1385 &ssi_private->dma_params_rx;
1386 ssi_private->fiq_params.dma_params_tx =
1387 &ssi_private->dma_params_tx;
1388
1389 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1390 if (ret)
1391 goto error_pcm;
1392 } else {
1393 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1394 if (ret)
1395 goto error_pcm;
1396 }
1397
1398 return 0;
1399
1400error_pcm:
1401
1402 if (!ssi_private->has_ipg_clk_name)
1403 clk_disable_unprepare(ssi_private->clk);
1404 return ret;
1405}
1406
1407static void fsl_ssi_imx_clean(struct platform_device *pdev,
1408 struct fsl_ssi_private *ssi_private)
1409{
1410 if (!ssi_private->use_dma)
1411 imx_pcm_fiq_exit(pdev);
1412 if (!ssi_private->has_ipg_clk_name)
1413 clk_disable_unprepare(ssi_private->clk);
1414}
1415
1416static int fsl_ssi_probe(struct platform_device *pdev)
1417{
1418 struct fsl_ssi_private *ssi_private;
1419 int ret = 0;
1420 struct device_node *np = pdev->dev.of_node;
1421 const struct of_device_id *of_id;
1422 const char *p, *sprop;
1423 const uint32_t *iprop;
1424 struct resource *res;
1425 void __iomem *iomem;
1426 char name[64];
1427 struct regmap_config regconfig = fsl_ssi_regconfig;
1428
1429 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1430 if (!of_id || !of_id->data)
1431 return -EINVAL;
1432
1433 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1434 GFP_KERNEL);
1435 if (!ssi_private)
1436 return -ENOMEM;
1437
1438 ssi_private->soc = of_id->data;
1439 ssi_private->dev = &pdev->dev;
1440
1441 sprop = of_get_property(np, "fsl,mode", NULL);
1442 if (sprop) {
1443 if (!strcmp(sprop, "ac97-slave"))
1444 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1445 }
1446
1447 ssi_private->use_dma = !of_property_read_bool(np,
1448 "fsl,fiq-stream-filter");
1449
1450 if (fsl_ssi_is_ac97(ssi_private)) {
1451 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1452 sizeof(fsl_ssi_ac97_dai));
1453
1454 fsl_ac97_data = ssi_private;
1455
1456 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1457 if (ret) {
1458 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1459 return ret;
1460 }
1461 } else {
1462
1463 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1464 sizeof(fsl_ssi_dai_template));
1465 }
1466 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1467
1468 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1469 iomem = devm_ioremap_resource(&pdev->dev, res);
1470 if (IS_ERR(iomem))
1471 return PTR_ERR(iomem);
1472 ssi_private->ssi_phys = res->start;
1473
1474 if (ssi_private->soc->imx21regs) {
1475
1476
1477
1478
1479 regconfig.max_register = CCSR_SSI_SRMSK;
1480 regconfig.num_reg_defaults_raw =
1481 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1482 }
1483
1484 ret = of_property_match_string(np, "clock-names", "ipg");
1485 if (ret < 0) {
1486 ssi_private->has_ipg_clk_name = false;
1487 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1488 ®config);
1489 } else {
1490 ssi_private->has_ipg_clk_name = true;
1491 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1492 "ipg", iomem, ®config);
1493 }
1494 if (IS_ERR(ssi_private->regs)) {
1495 dev_err(&pdev->dev, "Failed to init register map\n");
1496 return PTR_ERR(ssi_private->regs);
1497 }
1498
1499 ssi_private->irq = platform_get_irq(pdev, 0);
1500 if (ssi_private->irq < 0) {
1501 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1502 return ssi_private->irq;
1503 }
1504
1505
1506 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1507 if (!fsl_ssi_is_ac97(ssi_private))
1508 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1509
1510 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1511 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1512 }
1513
1514
1515 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1516 if (iprop)
1517 ssi_private->fifo_depth = be32_to_cpup(iprop);
1518 else
1519
1520 ssi_private->fifo_depth = 8;
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537 switch (ssi_private->fifo_depth) {
1538 case 15:
1539
1540
1541
1542
1543
1544
1545
1546 ssi_private->fifo_watermark = 8;
1547 ssi_private->dma_maxburst = 8;
1548 break;
1549 case 8:
1550 default:
1551
1552
1553
1554
1555
1556
1557
1558 ssi_private->fifo_watermark = ssi_private->fifo_depth - 2;
1559 ssi_private->dma_maxburst = ssi_private->fifo_depth - 2;
1560 break;
1561 }
1562
1563 dev_set_drvdata(&pdev->dev, ssi_private);
1564
1565 if (ssi_private->soc->imx) {
1566 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1567 if (ret)
1568 return ret;
1569 }
1570
1571 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1572 &ssi_private->cpu_dai_drv, 1);
1573 if (ret) {
1574 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1575 goto error_asoc_register;
1576 }
1577
1578 if (ssi_private->use_dma) {
1579 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1580 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1581 ssi_private);
1582 if (ret < 0) {
1583 dev_err(&pdev->dev, "could not claim irq %u\n",
1584 ssi_private->irq);
1585 goto error_asoc_register;
1586 }
1587 }
1588
1589 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1590 if (ret)
1591 goto error_asoc_register;
1592
1593
1594
1595
1596
1597
1598 if (!of_get_property(np, "codec-handle", NULL))
1599 goto done;
1600
1601
1602
1603
1604
1605
1606 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1607
1608 p = strrchr(sprop, ',');
1609 if (p)
1610 sprop = p + 1;
1611 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1612 make_lowercase(name);
1613
1614 ssi_private->pdev =
1615 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1616 if (IS_ERR(ssi_private->pdev)) {
1617 ret = PTR_ERR(ssi_private->pdev);
1618 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1619 goto error_sound_card;
1620 }
1621
1622done:
1623 if (ssi_private->dai_fmt)
1624 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1625 ssi_private->dai_fmt);
1626
1627 if (fsl_ssi_is_ac97(ssi_private)) {
1628 u32 ssi_idx;
1629
1630 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1631 if (ret) {
1632 dev_err(&pdev->dev, "cannot get SSI index property\n");
1633 goto error_sound_card;
1634 }
1635
1636 ssi_private->pdev =
1637 platform_device_register_data(NULL,
1638 "ac97-codec", ssi_idx, NULL, 0);
1639 if (IS_ERR(ssi_private->pdev)) {
1640 ret = PTR_ERR(ssi_private->pdev);
1641 dev_err(&pdev->dev,
1642 "failed to register AC97 codec platform: %d\n",
1643 ret);
1644 goto error_sound_card;
1645 }
1646 }
1647
1648 return 0;
1649
1650error_sound_card:
1651 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1652
1653error_asoc_register:
1654 if (ssi_private->soc->imx)
1655 fsl_ssi_imx_clean(pdev, ssi_private);
1656
1657 return ret;
1658}
1659
1660static int fsl_ssi_remove(struct platform_device *pdev)
1661{
1662 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1663
1664 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1665
1666 if (ssi_private->pdev)
1667 platform_device_unregister(ssi_private->pdev);
1668
1669 if (ssi_private->soc->imx)
1670 fsl_ssi_imx_clean(pdev, ssi_private);
1671
1672 if (fsl_ssi_is_ac97(ssi_private))
1673 snd_soc_set_ac97_ops(NULL);
1674
1675 return 0;
1676}
1677
1678#ifdef CONFIG_PM_SLEEP
1679static int fsl_ssi_suspend(struct device *dev)
1680{
1681 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1682 struct regmap *regs = ssi_private->regs;
1683
1684 regmap_read(regs, CCSR_SSI_SFCSR,
1685 &ssi_private->regcache_sfcsr);
1686 regmap_read(regs, CCSR_SSI_SACNT,
1687 &ssi_private->regcache_sacnt);
1688
1689 regcache_cache_only(regs, true);
1690 regcache_mark_dirty(regs);
1691
1692 return 0;
1693}
1694
1695static int fsl_ssi_resume(struct device *dev)
1696{
1697 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1698 struct regmap *regs = ssi_private->regs;
1699
1700 regcache_cache_only(regs, false);
1701
1702 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1703 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1704 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1705 ssi_private->regcache_sfcsr);
1706 regmap_write(regs, CCSR_SSI_SACNT,
1707 ssi_private->regcache_sacnt);
1708
1709 return regcache_sync(regs);
1710}
1711#endif
1712
1713static const struct dev_pm_ops fsl_ssi_pm = {
1714 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1715};
1716
1717static struct platform_driver fsl_ssi_driver = {
1718 .driver = {
1719 .name = "fsl-ssi-dai",
1720 .of_match_table = fsl_ssi_ids,
1721 .pm = &fsl_ssi_pm,
1722 },
1723 .probe = fsl_ssi_probe,
1724 .remove = fsl_ssi_remove,
1725};
1726
1727module_platform_driver(fsl_ssi_driver);
1728
1729MODULE_ALIAS("platform:fsl-ssi-dai");
1730MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1731MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1732MODULE_LICENSE("GPL v2");
1733