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19#include <linux/clk.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_irq.h>
23#include <linux/of_platform.h>
24#include <linux/regmap.h>
25
26#include <sound/core.h>
27#include <sound/dmaengine_pcm.h>
28#include <sound/pcm_params.h>
29
30#include "stm32_sai.h"
31
32#define SAI_FREE_PROTOCOL 0x0
33
34#define SAI_SLOT_SIZE_AUTO 0x0
35#define SAI_SLOT_SIZE_16 0x1
36#define SAI_SLOT_SIZE_32 0x2
37
38#define SAI_DATASIZE_8 0x2
39#define SAI_DATASIZE_10 0x3
40#define SAI_DATASIZE_16 0x4
41#define SAI_DATASIZE_20 0x5
42#define SAI_DATASIZE_24 0x6
43#define SAI_DATASIZE_32 0x7
44
45#define STM_SAI_FIFO_SIZE 8
46#define STM_SAI_DAI_NAME_SIZE 15
47
48#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
49#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
50
51#define STM_SAI_A_ID 0x0
52#define STM_SAI_B_ID 0x1
53
54#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
55#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
56#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
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82struct stm32_sai_sub_data {
83 struct platform_device *pdev;
84 struct regmap *regmap;
85 const struct regmap_config *regmap_config;
86 struct snd_dmaengine_dai_dma_data dma_params;
87 struct snd_soc_dai_driver *cpu_dai_drv;
88 struct snd_soc_dai *cpu_dai;
89 struct snd_pcm_substream *substream;
90 struct stm32_sai_data *pdata;
91 struct clk *sai_ck;
92 dma_addr_t phys_addr;
93 unsigned int mclk_rate;
94 unsigned int id;
95 int dir;
96 bool master;
97 int fmt;
98 int sync;
99 int fs_length;
100 int slots;
101 int slot_width;
102 int slot_mask;
103 int data_size;
104};
105
106enum stm32_sai_fifo_th {
107 STM_SAI_FIFO_TH_EMPTY,
108 STM_SAI_FIFO_TH_QUARTER,
109 STM_SAI_FIFO_TH_HALF,
110 STM_SAI_FIFO_TH_3_QUARTER,
111 STM_SAI_FIFO_TH_FULL,
112};
113
114static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
115{
116 switch (reg) {
117 case STM_SAI_CR1_REGX:
118 case STM_SAI_CR2_REGX:
119 case STM_SAI_FRCR_REGX:
120 case STM_SAI_SLOTR_REGX:
121 case STM_SAI_IMR_REGX:
122 case STM_SAI_SR_REGX:
123 case STM_SAI_CLRFR_REGX:
124 case STM_SAI_DR_REGX:
125 case STM_SAI_PDMCR_REGX:
126 case STM_SAI_PDMLY_REGX:
127 return true;
128 default:
129 return false;
130 }
131}
132
133static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
134{
135 switch (reg) {
136 case STM_SAI_DR_REGX:
137 return true;
138 default:
139 return false;
140 }
141}
142
143static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
144{
145 switch (reg) {
146 case STM_SAI_CR1_REGX:
147 case STM_SAI_CR2_REGX:
148 case STM_SAI_FRCR_REGX:
149 case STM_SAI_SLOTR_REGX:
150 case STM_SAI_IMR_REGX:
151 case STM_SAI_SR_REGX:
152 case STM_SAI_CLRFR_REGX:
153 case STM_SAI_DR_REGX:
154 case STM_SAI_PDMCR_REGX:
155 case STM_SAI_PDMLY_REGX:
156 return true;
157 default:
158 return false;
159 }
160}
161
162static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
163 .reg_bits = 32,
164 .reg_stride = 4,
165 .val_bits = 32,
166 .max_register = STM_SAI_DR_REGX,
167 .readable_reg = stm32_sai_sub_readable_reg,
168 .volatile_reg = stm32_sai_sub_volatile_reg,
169 .writeable_reg = stm32_sai_sub_writeable_reg,
170 .fast_io = true,
171};
172
173static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
174 .reg_bits = 32,
175 .reg_stride = 4,
176 .val_bits = 32,
177 .max_register = STM_SAI_PDMLY_REGX,
178 .readable_reg = stm32_sai_sub_readable_reg,
179 .volatile_reg = stm32_sai_sub_volatile_reg,
180 .writeable_reg = stm32_sai_sub_writeable_reg,
181 .fast_io = true,
182};
183
184static irqreturn_t stm32_sai_isr(int irq, void *devid)
185{
186 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
187 struct snd_pcm_substream *substream = sai->substream;
188 struct platform_device *pdev = sai->pdev;
189 unsigned int sr, imr, flags;
190 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
191
192 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
193 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
194
195 flags = sr & imr;
196 if (!flags)
197 return IRQ_NONE;
198
199 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
200 SAI_XCLRFR_MASK);
201
202 if (flags & SAI_XIMR_OVRUDRIE) {
203 dev_err(&pdev->dev, "IRQ %s\n",
204 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
205 status = SNDRV_PCM_STATE_XRUN;
206 }
207
208 if (flags & SAI_XIMR_MUTEDETIE)
209 dev_dbg(&pdev->dev, "IRQ mute detected\n");
210
211 if (flags & SAI_XIMR_WCKCFGIE) {
212 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
213 status = SNDRV_PCM_STATE_DISCONNECTED;
214 }
215
216 if (flags & SAI_XIMR_CNRDYIE)
217 dev_err(&pdev->dev, "IRQ Codec not ready\n");
218
219 if (flags & SAI_XIMR_AFSDETIE) {
220 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
221 status = SNDRV_PCM_STATE_XRUN;
222 }
223
224 if (flags & SAI_XIMR_LFSDETIE) {
225 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
226 status = SNDRV_PCM_STATE_XRUN;
227 }
228
229 if (status != SNDRV_PCM_STATE_RUNNING) {
230 snd_pcm_stream_lock(substream);
231 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
232 snd_pcm_stream_unlock(substream);
233 }
234
235 return IRQ_HANDLED;
236}
237
238static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
239 int clk_id, unsigned int freq, int dir)
240{
241 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
242 int ret;
243
244 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
245 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
246 SAI_XCR1_NODIV,
247 (unsigned int)~SAI_XCR1_NODIV);
248 if (ret < 0)
249 return ret;
250
251 sai->mclk_rate = freq;
252 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
253 }
254
255 return 0;
256}
257
258static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
259 u32 rx_mask, int slots, int slot_width)
260{
261 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
262 int slotr, slotr_mask, slot_size;
263
264 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
265 tx_mask, rx_mask, slots, slot_width);
266
267 switch (slot_width) {
268 case 16:
269 slot_size = SAI_SLOT_SIZE_16;
270 break;
271 case 32:
272 slot_size = SAI_SLOT_SIZE_32;
273 break;
274 default:
275 slot_size = SAI_SLOT_SIZE_AUTO;
276 break;
277 }
278
279 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
280 SAI_XSLOTR_NBSLOT_SET(slots - 1);
281 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
282
283
284 if (STM_SAI_IS_PLAYBACK(sai)) {
285 sai->slot_mask = tx_mask;
286 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
287 }
288
289 if (STM_SAI_IS_CAPTURE(sai)) {
290 sai->slot_mask = rx_mask;
291 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
292 }
293
294 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
295
296 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
297
298 sai->slot_width = slot_width;
299 sai->slots = slots;
300
301 return 0;
302}
303
304static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
305{
306 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
307 int cr1 = 0, frcr = 0;
308 int cr1_mask = 0, frcr_mask = 0;
309 int ret;
310
311 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
312
313 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
314
315 case SND_SOC_DAIFMT_I2S:
316 cr1 |= SAI_XCR1_CKSTR;
317 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
318 break;
319
320 case SND_SOC_DAIFMT_MSB:
321 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
322 break;
323
324 case SND_SOC_DAIFMT_LSB:
325 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
326 break;
327 case SND_SOC_DAIFMT_DSP_A:
328 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
329 break;
330 case SND_SOC_DAIFMT_DSP_B:
331 frcr |= SAI_XFRCR_FSPOL;
332 break;
333 default:
334 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
335 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
336 return -EINVAL;
337 }
338
339 cr1_mask |= SAI_XCR1_PRTCFG_MASK | SAI_XCR1_CKSTR;
340 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
341 SAI_XFRCR_FSDEF;
342
343
344 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
345 case SND_SOC_DAIFMT_NB_NF:
346 break;
347 case SND_SOC_DAIFMT_IB_NF:
348 cr1 ^= SAI_XCR1_CKSTR;
349 break;
350 case SND_SOC_DAIFMT_NB_IF:
351 frcr ^= SAI_XFRCR_FSPOL;
352 break;
353 case SND_SOC_DAIFMT_IB_IF:
354
355 cr1 ^= SAI_XCR1_CKSTR;
356 frcr ^= SAI_XFRCR_FSPOL;
357 break;
358 default:
359 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
360 fmt & SND_SOC_DAIFMT_INV_MASK);
361 return -EINVAL;
362 }
363 cr1_mask |= SAI_XCR1_CKSTR;
364 frcr_mask |= SAI_XFRCR_FSPOL;
365
366 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
367
368
369 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
370 case SND_SOC_DAIFMT_CBM_CFM:
371
372 cr1 |= SAI_XCR1_SLAVE;
373 sai->master = false;
374 break;
375 case SND_SOC_DAIFMT_CBS_CFS:
376 sai->master = true;
377 break;
378 default:
379 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
380 fmt & SND_SOC_DAIFMT_MASTER_MASK);
381 return -EINVAL;
382 }
383 cr1_mask |= SAI_XCR1_SLAVE;
384
385
386 cr1 |= SAI_XCR1_NODIV;
387 cr1_mask |= SAI_XCR1_NODIV;
388
389 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
390 if (ret < 0) {
391 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
392 return ret;
393 }
394
395 sai->fmt = fmt;
396
397 return 0;
398}
399
400static int stm32_sai_startup(struct snd_pcm_substream *substream,
401 struct snd_soc_dai *cpu_dai)
402{
403 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
404 int imr, cr2, ret;
405
406 sai->substream = substream;
407
408 ret = clk_prepare_enable(sai->sai_ck);
409 if (ret < 0) {
410 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
411 return ret;
412 }
413
414
415 regmap_update_bits(sai->regmap, STM_SAI_SR_REGX,
416 SAI_XSR_MASK, (unsigned int)~SAI_XSR_MASK);
417
418 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
419 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
420
421 imr = SAI_XIMR_OVRUDRIE;
422 if (STM_SAI_IS_CAPTURE(sai)) {
423 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
424 if (cr2 & SAI_XCR2_MUTECNT_MASK)
425 imr |= SAI_XIMR_MUTEDETIE;
426 }
427
428 if (sai->master)
429 imr |= SAI_XIMR_WCKCFGIE;
430 else
431 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
432
433 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
434 SAI_XIMR_MASK, imr);
435
436 return 0;
437}
438
439static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
440 struct snd_pcm_substream *substream,
441 struct snd_pcm_hw_params *params)
442{
443 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
444 int cr1, cr1_mask, ret;
445 int fth = STM_SAI_FIFO_TH_HALF;
446
447
448 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
449 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
450 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_SET(fth));
451
452
453 cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
454 switch (params_format(params)) {
455 case SNDRV_PCM_FORMAT_S8:
456 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8);
457 break;
458 case SNDRV_PCM_FORMAT_S16_LE:
459 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16);
460 break;
461 case SNDRV_PCM_FORMAT_S32_LE:
462 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32);
463 break;
464 default:
465 dev_err(cpu_dai->dev, "Data format not supported");
466 return -EINVAL;
467 }
468 cr1_mask = SAI_XCR1_DS_MASK | SAI_XCR1_PRTCFG_MASK;
469
470 cr1_mask |= SAI_XCR1_RX_TX;
471 if (STM_SAI_IS_CAPTURE(sai))
472 cr1 |= SAI_XCR1_RX_TX;
473
474 cr1_mask |= SAI_XCR1_MONO;
475 if ((sai->slots == 2) && (params_channels(params) == 1))
476 cr1 |= SAI_XCR1_MONO;
477
478 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
479 if (ret < 0) {
480 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
481 return ret;
482 }
483
484
485 sai->dma_params.maxburst = STM_SAI_FIFO_SIZE * fth / sizeof(u32);
486 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)&sai->dma_params);
487
488 return 0;
489}
490
491static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
492{
493 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
494 int slotr, slot_sz;
495
496 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
497
498
499
500
501
502 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
503 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
504 sai->slot_width = sai->data_size;
505
506 if (sai->slot_width < sai->data_size) {
507 dev_err(cpu_dai->dev,
508 "Data size %d larger than slot width\n",
509 sai->data_size);
510 return -EINVAL;
511 }
512
513
514 if (!sai->slots)
515 sai->slots = 2;
516
517
518 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
519 SAI_XSLOTR_NBSLOT_MASK,
520 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
521
522
523 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
524 sai->slot_mask = (1 << sai->slots) - 1;
525 regmap_update_bits(sai->regmap,
526 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
527 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
528 }
529
530 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
531 sai->slots, sai->slot_width);
532
533 return 0;
534}
535
536static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
537{
538 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
539 int fs_active, offset, format;
540 int frcr, frcr_mask;
541
542 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
543 sai->fs_length = sai->slot_width * sai->slots;
544
545 fs_active = sai->fs_length / 2;
546 if ((format == SND_SOC_DAIFMT_DSP_A) ||
547 (format == SND_SOC_DAIFMT_DSP_B))
548 fs_active = 1;
549
550 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
551 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
552 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
553
554 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
555 sai->fs_length, fs_active);
556
557 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
558
559 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
560 offset = sai->slot_width - sai->data_size;
561
562 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
563 SAI_XSLOTR_FBOFF_MASK,
564 SAI_XSLOTR_FBOFF_SET(offset));
565 }
566}
567
568static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
569 struct snd_pcm_hw_params *params)
570{
571 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
572 int cr1, mask, div = 0;
573 int sai_clk_rate, mclk_ratio, den, ret;
574 int version = sai->pdata->conf->version;
575
576 if (!sai->mclk_rate) {
577 dev_err(cpu_dai->dev, "Mclk rate is null\n");
578 return -EINVAL;
579 }
580
581 if (!(params_rate(params) % 11025))
582 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
583 else
584 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
585 sai_clk_rate = clk_get_rate(sai->sai_ck);
586
587 if (STM_SAI_IS_F4(sai->pdata)) {
588
589
590
591
592
593 if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
594 div = DIV_ROUND_CLOSEST(sai_clk_rate,
595 2 * sai->mclk_rate);
596 } else {
597
598
599
600
601
602
603
604
605
606 if (sai->mclk_rate) {
607 mclk_ratio = sai->mclk_rate / params_rate(params);
608 if (mclk_ratio != 256) {
609 if (mclk_ratio == 512) {
610 mask = SAI_XCR1_OSR;
611 cr1 = SAI_XCR1_OSR;
612 } else {
613 dev_err(cpu_dai->dev,
614 "Wrong mclk ratio %d\n",
615 mclk_ratio);
616 return -EINVAL;
617 }
618 }
619 div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate);
620 } else {
621
622 den = sai->fs_length * params_rate(params);
623 div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
624 }
625 }
626
627 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
628 dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
629 return -EINVAL;
630 }
631 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
632
633 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
634 cr1 = SAI_XCR1_MCKDIV_SET(div);
635 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
636 if (ret < 0) {
637 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
638 return ret;
639 }
640
641 return 0;
642}
643
644static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
645 struct snd_pcm_hw_params *params,
646 struct snd_soc_dai *cpu_dai)
647{
648 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
649 int ret;
650
651 sai->data_size = params_width(params);
652
653 ret = stm32_sai_set_slots(cpu_dai);
654 if (ret < 0)
655 return ret;
656 stm32_sai_set_frame(cpu_dai);
657
658 ret = stm32_sai_set_config(cpu_dai, substream, params);
659 if (ret)
660 return ret;
661
662 if (sai->master)
663 ret = stm32_sai_configure_clock(cpu_dai, params);
664
665 return ret;
666}
667
668static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
669 struct snd_soc_dai *cpu_dai)
670{
671 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
672 int ret;
673
674 switch (cmd) {
675 case SNDRV_PCM_TRIGGER_START:
676 case SNDRV_PCM_TRIGGER_RESUME:
677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
678 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
679
680 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
681 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
682
683
684 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
685 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
686 if (ret < 0)
687 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
688 break;
689 case SNDRV_PCM_TRIGGER_SUSPEND:
690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
691 case SNDRV_PCM_TRIGGER_STOP:
692 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
693
694 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
695 SAI_XCR1_SAIEN,
696 (unsigned int)~SAI_XCR1_SAIEN);
697
698 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
699 SAI_XCR1_DMAEN,
700 (unsigned int)~SAI_XCR1_DMAEN);
701 if (ret < 0)
702 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
703 break;
704 default:
705 return -EINVAL;
706 }
707
708 return ret;
709}
710
711static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
712 struct snd_soc_dai *cpu_dai)
713{
714 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
715
716 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
717
718 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
719 SAI_XCR1_NODIV);
720
721 clk_disable_unprepare(sai->sai_ck);
722 sai->substream = NULL;
723}
724
725static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
726{
727 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
728
729 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
730 sai->dma_params.maxburst = 1;
731
732 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
733
734 if (STM_SAI_IS_PLAYBACK(sai))
735 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
736 else
737 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
738
739 return 0;
740}
741
742static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
743 .set_sysclk = stm32_sai_set_sysclk,
744 .set_fmt = stm32_sai_set_dai_fmt,
745 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
746 .startup = stm32_sai_startup,
747 .hw_params = stm32_sai_hw_params,
748 .trigger = stm32_sai_trigger,
749 .shutdown = stm32_sai_shutdown,
750};
751
752static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
753 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
754 .buffer_bytes_max = 8 * PAGE_SIZE,
755 .period_bytes_min = 1024,
756 .period_bytes_max = PAGE_SIZE,
757 .periods_min = 2,
758 .periods_max = 8,
759};
760
761static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
762{
763 .probe = stm32_sai_dai_probe,
764 .id = 1,
765 .playback = {
766 .channels_min = 1,
767 .channels_max = 2,
768 .rate_min = 8000,
769 .rate_max = 192000,
770 .rates = SNDRV_PCM_RATE_CONTINUOUS,
771
772 .formats =
773 SNDRV_PCM_FMTBIT_S8 |
774 SNDRV_PCM_FMTBIT_S16_LE |
775 SNDRV_PCM_FMTBIT_S32_LE,
776 },
777 .ops = &stm32_sai_pcm_dai_ops,
778 }
779};
780
781static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
782{
783 .probe = stm32_sai_dai_probe,
784 .id = 1,
785 .capture = {
786 .channels_min = 1,
787 .channels_max = 2,
788 .rate_min = 8000,
789 .rate_max = 192000,
790 .rates = SNDRV_PCM_RATE_CONTINUOUS,
791
792 .formats =
793 SNDRV_PCM_FMTBIT_S8 |
794 SNDRV_PCM_FMTBIT_S16_LE |
795 SNDRV_PCM_FMTBIT_S32_LE,
796 },
797 .ops = &stm32_sai_pcm_dai_ops,
798 }
799};
800
801static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
802 .pcm_hardware = &stm32_sai_pcm_hw,
803 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
804};
805
806static const struct snd_soc_component_driver stm32_component = {
807 .name = "stm32-sai",
808};
809
810static const struct of_device_id stm32_sai_sub_ids[] = {
811 { .compatible = "st,stm32-sai-sub-a",
812 .data = (void *)STM_SAI_A_ID},
813 { .compatible = "st,stm32-sai-sub-b",
814 .data = (void *)STM_SAI_B_ID},
815 {}
816};
817MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
818
819static int stm32_sai_sub_parse_of(struct platform_device *pdev,
820 struct stm32_sai_sub_data *sai)
821{
822 struct device_node *np = pdev->dev.of_node;
823 struct resource *res;
824 void __iomem *base;
825
826 if (!np)
827 return -ENODEV;
828
829 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 base = devm_ioremap_resource(&pdev->dev, res);
831 if (IS_ERR(base))
832 return PTR_ERR(base);
833
834 sai->phys_addr = res->start;
835
836 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
837
838 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
839 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
840
841 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
842 base, sai->regmap_config);
843 if (IS_ERR(sai->regmap)) {
844 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
845 return PTR_ERR(sai->regmap);
846 }
847
848
849 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
850 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
851 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
852 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
853 } else {
854 dev_err(&pdev->dev, "Unsupported direction\n");
855 return -EINVAL;
856 }
857
858 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
859 if (IS_ERR(sai->sai_ck)) {
860 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
861 return PTR_ERR(sai->sai_ck);
862 }
863
864 return 0;
865}
866
867static int stm32_sai_sub_dais_init(struct platform_device *pdev,
868 struct stm32_sai_sub_data *sai)
869{
870 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
871 sizeof(struct snd_soc_dai_driver),
872 GFP_KERNEL);
873 if (!sai->cpu_dai_drv)
874 return -ENOMEM;
875
876 sai->cpu_dai_drv->name = dev_name(&pdev->dev);
877 if (STM_SAI_IS_PLAYBACK(sai)) {
878 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
879 sizeof(stm32_sai_playback_dai));
880 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
881 } else {
882 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
883 sizeof(stm32_sai_capture_dai));
884 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
885 }
886
887 return 0;
888}
889
890static int stm32_sai_sub_probe(struct platform_device *pdev)
891{
892 struct stm32_sai_sub_data *sai;
893 const struct of_device_id *of_id;
894 int ret;
895
896 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
897 if (!sai)
898 return -ENOMEM;
899
900 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
901 if (!of_id)
902 return -EINVAL;
903 sai->id = (uintptr_t)of_id->data;
904
905 sai->pdev = pdev;
906 platform_set_drvdata(pdev, sai);
907
908 sai->pdata = dev_get_drvdata(pdev->dev.parent);
909 if (!sai->pdata) {
910 dev_err(&pdev->dev, "Parent device data not available\n");
911 return -EINVAL;
912 }
913
914 ret = stm32_sai_sub_parse_of(pdev, sai);
915 if (ret)
916 return ret;
917
918 ret = stm32_sai_sub_dais_init(pdev, sai);
919 if (ret)
920 return ret;
921
922 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
923 IRQF_SHARED, dev_name(&pdev->dev), sai);
924 if (ret) {
925 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
926 return ret;
927 }
928
929 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
930 sai->cpu_dai_drv, 1);
931 if (ret)
932 return ret;
933
934 ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
935 &stm32_sai_pcm_config, 0);
936 if (ret) {
937 dev_err(&pdev->dev, "Could not register pcm dma\n");
938 return ret;
939 }
940
941 return 0;
942}
943
944static struct platform_driver stm32_sai_sub_driver = {
945 .driver = {
946 .name = "st,stm32-sai-sub",
947 .of_match_table = stm32_sai_sub_ids,
948 },
949 .probe = stm32_sai_sub_probe,
950};
951
952module_platform_driver(stm32_sai_sub_driver);
953
954MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
955MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
956MODULE_ALIAS("platform:st,stm32-sai-sub");
957MODULE_LICENSE("GPL v2");
958
