LXR linux/arch/arm/mach-imx/common.h

   1/*
   2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
   3 */
   4
   5/*
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#ifndef __ASM_ARCH_MXC_COMMON_H__
  12#define __ASM_ARCH_MXC_COMMON_H__
  13
  14#include <linux/reboot.h>
  15
  16struct irq_data;
  17struct platform_device;
  18struct pt_regs;
  19struct clk;
  20struct device_node;
  21enum mxc_cpu_pwr_mode;
  22struct of_device_id;
  23
  24void mx21_map_io(void);
  25void mx27_map_io(void);
  26void mx31_map_io(void);
  27void mx35_map_io(void);
  28void imx21_init_early(void);
  29void imx27_init_early(void);
  30void imx31_init_early(void);
  31void imx35_init_early(void);
  32void mxc_init_irq(void __iomem *);
  33void mx21_init_irq(void);
  34void mx27_init_irq(void);
  35void mx31_init_irq(void);
  36void mx35_init_irq(void);
  37void imx21_soc_init(void);
  38void imx27_soc_init(void);
  39void imx31_soc_init(void);
  40void imx35_soc_init(void);
  41void epit_timer_init(void __iomem *base, int irq);
  42int mx21_clocks_init(unsigned long lref, unsigned long fref);
  43int mx27_clocks_init(unsigned long fref);
  44int mx31_clocks_init(unsigned long fref);
  45int mx35_clocks_init(void);
  46struct platform_device *mxc_register_gpio(char *name, int id,
  47        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
  48void mxc_set_cpu_type(unsigned int type);
  49void mxc_restart(enum reboot_mode, const char *);
  50void mxc_arch_reset_init(void __iomem *);
  51void imx1_reset_init(void __iomem *);
  52void imx_set_aips(void __iomem *);
  53void imx_aips_allow_unprivileged_access(const char *compat);
  54int mxc_device_init(void);
  55void imx_set_soc_revision(unsigned int rev);
  56void imx_init_revision_from_anatop(void);
  57struct device *imx_soc_device_init(void);
  58void imx6_enable_rbc(bool enable);
  59void imx_gpc_check_dt(void);
  60void imx_gpc_set_arm_power_in_lpm(bool power_off);
  61void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
  62void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
  63void imx25_pm_init(void);
  64void imx27_pm_init(void);
  65
  66enum mxc_cpu_pwr_mode {
  67        WAIT_CLOCKED,           /* wfi only */
  68        WAIT_UNCLOCKED,         /* WAIT */
  69        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
  70        STOP_POWER_ON,          /* just STOP */
  71        STOP_POWER_OFF,         /* STOP + SRPG */
  72};
  73
  74enum mx3_cpu_pwr_mode {
  75        MX3_RUN,
  76        MX3_WAIT,
  77        MX3_DOZE,
  78        MX3_SLEEP,
  79};
  80
  81void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
  82
  83void imx_enable_cpu(int cpu, bool enable);
  84void imx_set_cpu_jump(int cpu, void *jump_addr);
  85u32 imx_get_cpu_arg(int cpu);
  86void imx_set_cpu_arg(int cpu, u32 arg);
  87#ifdef CONFIG_SMP
  88void v7_secondary_startup(void);
  89void imx_scu_map_io(void);
  90void imx_smp_prepare(void);
  91#else
  92static inline void imx_scu_map_io(void) {}
  93static inline void imx_smp_prepare(void) {}
  94#endif
  95void imx_src_init(void);
  96void imx_gpc_pre_suspend(bool arm_power_off);
  97void imx_gpc_post_resume(void);
  98void imx_gpc_mask_all(void);
  99void imx_gpc_restore_all(void);
 100void imx_gpc_hwirq_mask(unsigned int hwirq);
 101void imx_gpc_hwirq_unmask(unsigned int hwirq);
 102void imx_anatop_init(void);
 103void imx_anatop_pre_suspend(void);
 104void imx_anatop_post_resume(void);
 105int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 106void imx6_set_int_mem_clk_lpm(bool enable);
 107void imx6sl_set_wait_clk(bool enter);
 108int imx_mmdc_get_ddr_type(void);
 109
 110void imx_cpu_die(unsigned int cpu);
 111int imx_cpu_kill(unsigned int cpu);
 112
 113#ifdef CONFIG_SUSPEND
 114void v7_cpu_resume(void);
 115void imx53_suspend(void __iomem *ocram_vbase);
 116extern const u32 imx53_suspend_sz;
 117void imx6_suspend(void __iomem *ocram_vbase);
 118#else
 119static inline void v7_cpu_resume(void) {}
 120static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 121static const u32 imx53_suspend_sz;
 122static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 123#endif
 124
 125void imx6_pm_ccm_init(const char *ccm_compat);
 126void imx6q_pm_init(void);
 127void imx6dl_pm_init(void);
 128void imx6sl_pm_init(void);
 129void imx6sx_pm_init(void);
 130void imx6ul_pm_init(void);
 131
 132#ifdef CONFIG_PM
 133void imx51_pm_init(void);
 134void imx53_pm_init(void);
 135#else
 136static inline void imx51_pm_init(void) {}
 137static inline void imx53_pm_init(void) {}
 138#endif
 139
 140#ifdef CONFIG_NEON
 141int mx51_neon_fixup(void);
 142#else
 143static inline int mx51_neon_fixup(void) { return 0; }
 144#endif
 145
 146#ifdef CONFIG_CACHE_L2X0
 147void imx_init_l2cache(void);
 148#else
 149static inline void imx_init_l2cache(void) {}
 150#endif
 151
 152extern const struct smp_operations imx_smp_ops;
 153extern const struct smp_operations ls1021a_smp_ops;
 154
 155#endif
 156