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15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/plat-ram.h>
21#include <linux/memory.h>
22#include <linux/gpio.h>
23#include <linux/smsc911x.h>
24#include <linux/interrupt.h>
25#include <linux/i2c.h>
26#include <linux/platform_data/at24.h>
27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
30#include <linux/can/platform/sja1000.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/gfp.h>
34#include <linux/regulator/machine.h>
35#include <linux/regulator/fixed.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/mach/map.h>
41
42#include "common.h"
43#include "devices-imx31.h"
44#include "ehci.h"
45#include "hardware.h"
46#include "iomux-mx3.h"
47#include "pcm037.h"
48#include "ulpi.h"
49
50static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
51
52static int __init pcm037_variant_setup(char *str)
53{
54 if (!strcmp("eet", str))
55 pcm037_instance = PCM037_EET;
56 else if (strcmp("pcm970", str))
57 pr_warn("Unknown pcm037 baseboard variant %s\n", str);
58
59 return 1;
60}
61
62
63__setup("pcm037_variant=", pcm037_variant_setup);
64
65enum pcm037_board_variant pcm037_variant(void)
66{
67 return pcm037_instance;
68}
69
70
71static unsigned int pcm037_uart1_handshake_pins[] = {
72 MX31_PIN_CTS1__CTS1,
73 MX31_PIN_RTS1__RTS1,
74 MX31_PIN_TXD1__TXD1,
75 MX31_PIN_RXD1__RXD1,
76};
77
78
79static unsigned int pcm037_uart1_pins[] = {
80 MX31_PIN_TXD1__TXD1,
81 MX31_PIN_RXD1__RXD1,
82};
83
84static unsigned int pcm037_pins[] = {
85
86 MX31_PIN_CSPI2_MOSI__SCL,
87 MX31_PIN_CSPI2_MISO__SDA,
88 MX31_PIN_CSPI2_SS2__I2C3_SDA,
89 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
90
91 MX31_PIN_SD1_DATA3__SD1_DATA3,
92 MX31_PIN_SD1_DATA2__SD1_DATA2,
93 MX31_PIN_SD1_DATA1__SD1_DATA1,
94 MX31_PIN_SD1_DATA0__SD1_DATA0,
95 MX31_PIN_SD1_CLK__SD1_CLK,
96 MX31_PIN_SD1_CMD__SD1_CMD,
97 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO),
98 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
99
100 MX31_PIN_CSPI1_MOSI__MOSI,
101 MX31_PIN_CSPI1_MISO__MISO,
102 MX31_PIN_CSPI1_SCLK__SCLK,
103 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
104 MX31_PIN_CSPI1_SS0__SS0,
105 MX31_PIN_CSPI1_SS1__SS1,
106 MX31_PIN_CSPI1_SS2__SS2,
107
108 MX31_PIN_TXD2__TXD2,
109 MX31_PIN_RXD2__RXD2,
110 MX31_PIN_CTS2__CTS2,
111 MX31_PIN_RTS2__RTS2,
112
113 MX31_PIN_CSPI3_MOSI__RXD3,
114 MX31_PIN_CSPI3_MISO__TXD3,
115 MX31_PIN_CSPI3_SCLK__RTS3,
116 MX31_PIN_CSPI3_SPI_RDY__CTS3,
117
118 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
119
120 MX31_PIN_BATT_LINE__OWIRE,
121
122 MX31_PIN_LD0__LD0,
123 MX31_PIN_LD1__LD1,
124 MX31_PIN_LD2__LD2,
125 MX31_PIN_LD3__LD3,
126 MX31_PIN_LD4__LD4,
127 MX31_PIN_LD5__LD5,
128 MX31_PIN_LD6__LD6,
129 MX31_PIN_LD7__LD7,
130 MX31_PIN_LD8__LD8,
131 MX31_PIN_LD9__LD9,
132 MX31_PIN_LD10__LD10,
133 MX31_PIN_LD11__LD11,
134 MX31_PIN_LD12__LD12,
135 MX31_PIN_LD13__LD13,
136 MX31_PIN_LD14__LD14,
137 MX31_PIN_LD15__LD15,
138 MX31_PIN_LD16__LD16,
139 MX31_PIN_LD17__LD17,
140 MX31_PIN_VSYNC3__VSYNC3,
141 MX31_PIN_HSYNC__HSYNC,
142 MX31_PIN_FPSHIFT__FPSHIFT,
143 MX31_PIN_DRDY0__DRDY0,
144 MX31_PIN_D3_REV__D3_REV,
145 MX31_PIN_CONTRAST__CONTRAST,
146 MX31_PIN_D3_SPL__D3_SPL,
147 MX31_PIN_D3_CLS__D3_CLS,
148 MX31_PIN_LCS0__GPIO3_23,
149
150 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
151
152 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
153 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
154 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
155 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
156 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
157 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
158 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
159 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
160 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
161 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
162 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
163 MX31_PIN_USBOTG_STP__USBOTG_STP,
164
165 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
166 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
167 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
168 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
169 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
170 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
171 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
172 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
173 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
174 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
175 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
176 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
177};
178
179static struct physmap_flash_data pcm037_flash_data = {
180 .width = 2,
181};
182
183static struct resource pcm037_flash_resource = {
184 .start = 0xa0000000,
185 .end = 0xa1ffffff,
186 .flags = IORESOURCE_MEM,
187};
188
189static struct platform_device pcm037_flash = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev = {
193 .platform_data = &pcm037_flash_data,
194 },
195 .resource = &pcm037_flash_resource,
196 .num_resources = 1,
197};
198
199static const struct imxuart_platform_data uart_pdata __initconst = {
200 .flags = IMXUART_HAVE_RTSCTS,
201};
202
203static struct resource smsc911x_resources[] = {
204 {
205 .start = MX31_CS1_BASE_ADDR + 0x300,
206 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
207 .flags = IORESOURCE_MEM,
208 }, {
209
210 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
211 },
212};
213
214static struct smsc911x_platform_config smsc911x_info = {
215 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
216 SMSC911X_SAVE_MAC_ADDRESS,
217 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
218 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
219 .phy_interface = PHY_INTERFACE_MODE_MII,
220};
221
222static struct platform_device pcm037_eth = {
223 .name = "smsc911x",
224 .id = -1,
225 .num_resources = ARRAY_SIZE(smsc911x_resources),
226 .resource = smsc911x_resources,
227 .dev = {
228 .platform_data = &smsc911x_info,
229 },
230};
231
232static struct platdata_mtd_ram pcm038_sram_data = {
233 .bankwidth = 2,
234};
235
236static struct resource pcm038_sram_resource = {
237 .start = MX31_CS4_BASE_ADDR,
238 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
239 .flags = IORESOURCE_MEM,
240};
241
242static struct platform_device pcm037_sram_device = {
243 .name = "mtd-ram",
244 .id = 0,
245 .dev = {
246 .platform_data = &pcm038_sram_data,
247 },
248 .num_resources = 1,
249 .resource = &pcm038_sram_resource,
250};
251
252static const struct mxc_nand_platform_data
253pcm037_nand_board_info __initconst = {
254 .width = 1,
255 .hw_ecc = 1,
256};
257
258static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
259 .bitrate = 100000,
260};
261
262static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
263 .bitrate = 20000,
264};
265
266static struct at24_platform_data board_eeprom = {
267 .byte_len = 4096,
268 .page_size = 32,
269 .flags = AT24_FLAG_ADDR16,
270};
271
272static struct i2c_board_info pcm037_i2c_devices[] = {
273 {
274 I2C_BOARD_INFO("at24", 0x52),
275 .platform_data = &board_eeprom,
276 }, {
277 I2C_BOARD_INFO("pcf8563", 0x51),
278 }
279};
280
281
282#ifdef PCM970_SDHC_RW_SWITCH
283static int pcm970_sdhc1_get_ro(struct device *dev)
284{
285 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
286}
287#endif
288
289#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
290#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
291
292static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
293 void *data)
294{
295 int ret;
296
297 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
298 if (ret)
299 return ret;
300
301 gpio_direction_input(SDHC1_GPIO_DET);
302
303#ifdef PCM970_SDHC_RW_SWITCH
304 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
305 if (ret)
306 goto err_gpio_free;
307 gpio_direction_input(SDHC1_GPIO_WP);
308#endif
309
310 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
311 IRQF_TRIGGER_FALLING, "sdhc-detect", data);
312 if (ret)
313 goto err_gpio_free_2;
314
315 return 0;
316
317err_gpio_free_2:
318#ifdef PCM970_SDHC_RW_SWITCH
319 gpio_free(SDHC1_GPIO_WP);
320err_gpio_free:
321#endif
322 gpio_free(SDHC1_GPIO_DET);
323
324 return ret;
325}
326
327static void pcm970_sdhc1_exit(struct device *dev, void *data)
328{
329 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
330 gpio_free(SDHC1_GPIO_DET);
331 gpio_free(SDHC1_GPIO_WP);
332}
333
334static const struct imxmmc_platform_data sdhc_pdata __initconst = {
335#ifdef PCM970_SDHC_RW_SWITCH
336 .get_ro = pcm970_sdhc1_get_ro,
337#endif
338 .init = pcm970_sdhc1_init,
339 .exit = pcm970_sdhc1_exit,
340};
341
342static struct platform_device *devices[] __initdata = {
343 &pcm037_flash,
344 &pcm037_sram_device,
345};
346
347static const struct fb_videomode fb_modedb[] = {
348 {
349
350 .name = "Sharp-LQ035Q7DH06-QVGA",
351 .refresh = 60,
352 .xres = 240,
353 .yres = 320,
354 .pixclock = 185925,
355 .left_margin = 9,
356 .right_margin = 16,
357 .upper_margin = 7,
358 .lower_margin = 9,
359 .hsync_len = 1,
360 .vsync_len = 1,
361 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
362 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
363 .vmode = FB_VMODE_NONINTERLACED,
364 .flag = 0,
365 }, {
366
367 .name = "TX090",
368 .refresh = 60,
369 .xres = 240,
370 .yres = 320,
371 .pixclock = 38255,
372 .left_margin = 144,
373 .right_margin = 0,
374 .upper_margin = 7,
375 .lower_margin = 40,
376 .hsync_len = 96,
377 .vsync_len = 1,
378 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
379 .vmode = FB_VMODE_NONINTERLACED,
380 .flag = 0,
381 }, {
382
383 .name = "CMEL-OLED",
384 .refresh = 60,
385 .xres = 240,
386 .yres = 320,
387 .pixclock = 185925,
388 .left_margin = 9,
389 .right_margin = 16,
390 .upper_margin = 7,
391 .lower_margin = 9,
392 .hsync_len = 1,
393 .vsync_len = 1,
394 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
395 .vmode = FB_VMODE_NONINTERLACED,
396 .flag = 0,
397 },
398};
399
400static struct mx3fb_platform_data mx3fb_pdata = {
401 .name = "Sharp-LQ035Q7DH06-QVGA",
402 .mode = fb_modedb,
403 .num_modes = ARRAY_SIZE(fb_modedb),
404};
405
406static struct resource pcm970_sja1000_resources[] = {
407 {
408 .start = MX31_CS5_BASE_ADDR,
409 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
410 .flags = IORESOURCE_MEM,
411 }, {
412
413 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
414 },
415};
416
417struct sja1000_platform_data pcm970_sja1000_platform_data = {
418 .osc_freq = 16000000,
419 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
420 .cdr = CDR_CBP,
421};
422
423static struct platform_device pcm970_sja1000 = {
424 .name = "sja1000_platform",
425 .dev = {
426 .platform_data = &pcm970_sja1000_platform_data,
427 },
428 .resource = pcm970_sja1000_resources,
429 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
430};
431
432static int pcm037_otg_init(struct platform_device *pdev)
433{
434 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
435}
436
437static struct mxc_usbh_platform_data otg_pdata __initdata = {
438 .init = pcm037_otg_init,
439 .portsc = MXC_EHCI_MODE_ULPI,
440};
441
442static int pcm037_usbh2_init(struct platform_device *pdev)
443{
444 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
445}
446
447static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
448 .init = pcm037_usbh2_init,
449 .portsc = MXC_EHCI_MODE_ULPI,
450};
451
452static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
453 .operating_mode = FSL_USB2_DR_DEVICE,
454 .phy_mode = FSL_USB2_PHY_ULPI,
455};
456
457static bool otg_mode_host __initdata;
458
459static int __init pcm037_otg_mode(char *options)
460{
461 if (!strcmp(options, "host"))
462 otg_mode_host = true;
463 else if (!strcmp(options, "device"))
464 otg_mode_host = false;
465 else
466 pr_info("otg_mode neither \"host\" nor \"device\". "
467 "Defaulting to device\n");
468 return 1;
469}
470__setup("otg_mode=", pcm037_otg_mode);
471
472static struct regulator_consumer_supply dummy_supplies[] = {
473 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
474 REGULATOR_SUPPLY("vddvario", "smsc911x"),
475};
476
477
478
479
480static void __init pcm037_init(void)
481{
482 imx31_soc_init();
483
484 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
485
486 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
487
488 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
489 "pcm037");
490
491#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
492 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
493
494 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
495 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
496 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
497 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
498 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG);
499 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG);
500 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);
501 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);
502 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);
503 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);
504 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);
505 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);
506
507 if (pcm037_variant() == PCM037_EET)
508 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
509 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
510 else
511 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
512 ARRAY_SIZE(pcm037_uart1_handshake_pins),
513 "pcm037_uart1");
514
515 platform_add_devices(devices, ARRAY_SIZE(devices));
516
517 imx31_add_imx2_wdt();
518 imx31_add_imx_uart0(&uart_pdata);
519
520 imx31_add_imx_uart1(&uart_pdata);
521 imx31_add_imx_uart2(&uart_pdata);
522
523 imx31_add_mxc_w1();
524
525
526 i2c_register_board_info(1, pcm037_i2c_devices,
527 ARRAY_SIZE(pcm037_i2c_devices));
528
529 imx31_add_imx_i2c1(&pcm037_i2c1_data);
530 imx31_add_imx_i2c2(&pcm037_i2c2_data);
531
532 imx31_add_mxc_nand(&pcm037_nand_board_info);
533 imx31_add_ipu_core();
534 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
535
536 if (otg_mode_host) {
537 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
538 ULPI_OTG_DRVVBUS_EXT);
539 if (otg_pdata.otg)
540 imx31_add_mxc_ehci_otg(&otg_pdata);
541 }
542
543 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
544 ULPI_OTG_DRVVBUS_EXT);
545 if (usbh2_pdata.otg)
546 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
547
548 if (!otg_mode_host)
549 imx31_add_fsl_usb2_udc(&otg_device_pdata);
550}
551
552static void __init pcm037_timer_init(void)
553{
554 mx31_clocks_init(26000000);
555}
556
557static void __init pcm037_init_late(void)
558{
559 int ret;
560
561
562 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
563 if (!ret) {
564 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
565 smsc911x_resources[1].start =
566 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
567 smsc911x_resources[1].end =
568 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
569 platform_device_register(&pcm037_eth);
570 } else {
571 pr_warn("could not get LAN irq gpio\n");
572 }
573
574 imx31_add_mxc_mmc(0, &sdhc_pdata);
575
576 pcm970_sja1000_resources[1].start =
577 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
578 pcm970_sja1000_resources[1].end =
579 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
580 platform_device_register(&pcm970_sja1000);
581
582 pcm037_eet_init_devices();
583}
584
585MACHINE_START(PCM037, "Phytec Phycore pcm037")
586
587 .atag_offset = 0x100,
588 .map_io = mx31_map_io,
589 .init_early = imx31_init_early,
590 .init_irq = mx31_init_irq,
591 .init_time = pcm037_timer_init,
592 .init_machine = pcm037_init,
593 .init_late = pcm037_init_late,
594 .restart = mxc_restart,
595MACHINE_END
596
