1
2#ifndef _IOP13XX_HW_H_
3#define _IOP13XX_HW_H_
4
5#ifndef __ASSEMBLY__
6
7enum reboot_mode;
8
9
10extern u32 iop13xx_atux_pmmr_offset;
11extern u32 iop13xx_atue_pmmr_offset;
12void iop13xx_init_early(void);
13void iop13xx_init_irq(void);
14void iop13xx_map_io(void);
15void iop13xx_platform_init(void);
16void iop13xx_add_tpmi_devices(void);
17void iop13xx_init_irq(void);
18void iop13xx_restart(enum reboot_mode, const char *);
19
20
21static inline int iop13xx_cpu_id(void)
22{
23 int id;
24 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
25 return id;
26}
27
28
29static inline u32 read_wdtcr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtcr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
38}
39
40
41static inline u32 read_wdtsr(void)
42{
43 u32 val;
44 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
45 return val;
46}
47static inline void write_wdtsr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
50}
51
52
53static inline u32 read_rcsr(void)
54{
55 u32 val;
56 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
57 return val;
58}
59
60extern unsigned long get_iop_tick_rate(void);
61#endif
62
63
64
65
66#define IOP13XX_MAX_RAM_SIZE 0x80000000UL
67#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
68
69
70
71
72
73
74
75
76
77
78
79#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
80#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL
81
82#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
83#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
84#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
85#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
86 IOP13XX_PCIX_LOWER_MEM_BA)
87#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
90 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
91
92#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
93#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
94#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
95 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
96#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
97 IOP13XX_PCIX_LOWER_MEM_BA)
98
99
100#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
101#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL
102
103#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
104#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
105#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
106#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
107 IOP13XX_PCIE_LOWER_MEM_BA)
108#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
109 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
110#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
111 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
112
113
114#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
115#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
116#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
119 IOP13XX_PCIE_LOWER_MEM_BA)
120
121
122#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
123#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
124#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
125#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
126#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
127 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
128
129
130
131
132#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL
133#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL)
134#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
135#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
136 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
137#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
138 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
139#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
140 + IOP13XX_PMMR_PHYS_MEM_BASE)
141#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
142 + IOP13XX_PMMR_VIRT_MEM_BASE)
143#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
144#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
145#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
146#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
147#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
148#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
149#define IOP13XX_PMMR_SIZE 0x00080000
150
151
152#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
153#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
154#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
155#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
156
157#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
158#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
159#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
160#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
161#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
162#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
163
164
165
166#define IOP13XX_INIT_ATU_DEFAULT (0)
167#define IOP13XX_INIT_ATU_ATUX (1 << 0)
168#define IOP13XX_INIT_ATU_ATUE (1 << 1)
169#define IOP13XX_INIT_ATU_NONE (1 << 2)
170
171
172
173#define IOP13XX_INIT_UART_DEFAULT (0)
174#define IOP13XX_INIT_UART_0 (1 << 0)
175#define IOP13XX_INIT_UART_1 (1 << 1)
176
177
178
179#define IOP13XX_INIT_I2C_DEFAULT (0)
180#define IOP13XX_INIT_I2C_0 (1 << 0)
181#define IOP13XX_INIT_I2C_1 (1 << 1)
182#define IOP13XX_INIT_I2C_2 (1 << 2)
183
184
185
186#define IOP13XX_INIT_ADMA_DEFAULT (0)
187#define IOP13XX_INIT_ADMA_0 (1 << 0)
188#define IOP13XX_INIT_ADMA_1 (1 << 1)
189#define IOP13XX_INIT_ADMA_2 (1 << 2)
190
191
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_NUM_ADMA 3
196#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
197 IQ81340_NUM_I2C + \
198 IQ81340_NUM_PHYS_MAP_FLASH + \
199 IQ81340_NUM_ADMA)
200
201
202#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
203#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
204#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
205#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
206#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
207#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
208#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
209#define IOP13XX_MU_PMMR_OFFSET 0x00004000
210#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
211#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
212
213#define IOP13XX_ESSR0_IFACE_MASK 0x00004000
214#define IOP13XX_CONTROLLER_ONLY (1 << 14)
215#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
216
217#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
218#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
219 IOP13XX_PMON_PMMR_OFFSET)
220#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
221 IOP13XX_PMON_PMMR_OFFSET)
222
223#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
224#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
225#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
226#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
227
228#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
229#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
230#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
231#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
232
233#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
234#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
235#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
236#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
237
238#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
239#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
240
241
242#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
243 iop13xx_atux_pmmr_offset + (ofs))
244
245#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x2)
247
248#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
249 iop13xx_atux_pmmr_offset + 0x4)
250#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
251 iop13xx_atux_pmmr_offset + 0x6)
252
253#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
254#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
255#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
256#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
257#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
258#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
259#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
260#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
261#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
262#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
263#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
264#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
265#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
266#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
267#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
268#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
269#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
270#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
271#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
272#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
273#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
274#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
275#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
276#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
277
278#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
279#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
280#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
281#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
282#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
283#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
284#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
285#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
286#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
287#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
288#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
289#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
290#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
291#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
292
293#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
294#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
295#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
296#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
297#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
298#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
299
300#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
301#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
302#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
303#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
304#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
305#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
306#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
307#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
308#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
309#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
310#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
311#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
312#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
313#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
314#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
315#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
316#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
317
318#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
319#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
320#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
321
322#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
323#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
324
325#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
326 iop13xx_atue_pmmr_offset + (ofs))
327
328#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
329 iop13xx_atue_pmmr_offset + 0x2)
330#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
331 iop13xx_atue_pmmr_offset + 0x4)
332#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
333 iop13xx_atue_pmmr_offset + 0x6)
334
335#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
336#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
337#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
338#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
339#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
340#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
341#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
342#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
343#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
344#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
345#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
346#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
347#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
348#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
349#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
350#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
351 iop13xx_atue_pmmr_offset + 0xe2)
352#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
353#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
354#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
355#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
356#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
357#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
358#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
359#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
360#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
361
362#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
363#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
364#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
365#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
366#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
367#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
368
369#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
370#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
371
372#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
373#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
374#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
375#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
376#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
377#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
378#define IOP13XX_ATUE_OCCAR_REG (2)
379
380#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
381#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
382#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
383#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
384#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
385#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
386#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
387
388#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
389#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
391
392#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
393#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
394
395#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
396#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
397#define IOP13XX_ATUE_STAT_PME (1 << 27)
398#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
399#define IOP13XX_ATUE_STAT_IVM (1 << 25)
400#define IOP13XX_ATUE_STAT_BIST (1 << 24)
401#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
402#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
403#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
404#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
405#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
406#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
407#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
408#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
409#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
410#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
411#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
412#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
413#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
414#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
415#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
416#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
417#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
418
419#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
420#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
421#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
422#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
423#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
424#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
425#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
426#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
427#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
428#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
429#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
430#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
431#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
432#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
433#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
434
435#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
436#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
437#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
438#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
439
440
441
442#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
443 (ofs))
444
445#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
446#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
447#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
448#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
449#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
450#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
451#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
452#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
453#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
454#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
455#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
456#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
457#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
458#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
459#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
460#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
461
462#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
463#define IOP13XX_MU_BASE_PHYS (0xff000000)
464#define IOP13XX_MU_BASE_PCI (0xff000000)
465#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
466#define IOP13XX_MU_MIMR_CORE_SELECT (15)
467
468
469
470#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
471#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
472
473
474#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
475#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
476#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
477#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
478 IOP13XX_PMMR_VIRT_TO_PHYS(\
479 IOP13XX_ATUE_OCCDR))\
480 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
481#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
482 IOP13XX_PMMR_VIRT_TO_PHYS(\
483 IOP13XX_ATUX_OCCDR))\
484 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
485
486
487#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
488 (ofs))
489
490#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
491#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
492#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
493#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
494#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
495#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
496
497#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
498
499
500#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
501#define IOP_WDTCR_EN 0xe1e1e1e1
502#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
503#define IOP_WDTCR_DIS 0xf1f1f1f1
504#define IOP_RCSR_WDT (1 << 5)
505#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
506#define IOP13XX_WDTCR_IB_RESET (1 << 0)
507
508#endif
509
