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12#include <linux/platform_data/gpio-omap.h>
13#include <linux/omap-dma.h>
14#include <plat/dmtimer.h>
15#include <linux/platform_data/spi-omap2-mcspi.h>
16
17#include "omap_hwmod.h"
18#include "omap_hwmod_common_data.h"
19#include "cm-regbits-24xx.h"
20#include "prm-regbits-24xx.h"
21#include "wd_timer.h"
22
23
24
25
26
27
28static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
29 .rev_offs = 0x0000,
30 .sysc_offs = 0x0010,
31 .syss_offs = 0x0014,
32 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
33 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
34 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
35 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
36 .sysc_fields = &omap_hwmod_sysc_type1,
37};
38
39struct omap_hwmod_class omap2_dispc_hwmod_class = {
40 .name = "dispc",
41 .sysc = &omap2_dispc_sysc,
42};
43
44
45static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
46 .rev_offs = 0x0000,
47 .sysc_offs = 0x0010,
48 .syss_offs = 0x0014,
49 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
50 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
51 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
52 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
53 .sysc_fields = &omap_hwmod_sysc_type1,
54};
55
56struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
57 .name = "timer",
58 .sysc = &omap2xxx_timer_sysc,
59};
60
61
62
63
64
65
66
67static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
68 .rev_offs = 0x0000,
69 .sysc_offs = 0x0010,
70 .syss_offs = 0x0014,
71 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
72 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
73 .sysc_fields = &omap_hwmod_sysc_type1,
74};
75
76struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
77 .name = "wd_timer",
78 .sysc = &omap2xxx_wd_timer_sysc,
79 .pre_shutdown = &omap2_wd_timer_disable,
80 .reset = &omap2_wd_timer_reset,
81};
82
83
84
85
86
87static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
88 .rev_offs = 0x0000,
89 .sysc_offs = 0x0010,
90 .syss_offs = 0x0014,
91 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
92 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
93 SYSS_HAS_RESET_STATUS),
94 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
95 .sysc_fields = &omap_hwmod_sysc_type1,
96};
97
98struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
99 .name = "gpio",
100 .sysc = &omap2xxx_gpio_sysc,
101 .rev = 0,
102};
103
104
105static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
106 .rev_offs = 0x0000,
107 .sysc_offs = 0x002c,
108 .syss_offs = 0x0028,
109 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
110 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
111 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
112 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
113 .sysc_fields = &omap_hwmod_sysc_type1,
114};
115
116struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
117 .name = "dma",
118 .sysc = &omap2xxx_dma_sysc,
119};
120
121
122
123
124
125
126
127static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
128 .rev_offs = 0x000,
129 .sysc_offs = 0x010,
130 .syss_offs = 0x014,
131 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
132 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
133 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
134 .sysc_fields = &omap_hwmod_sysc_type1,
135};
136
137struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
138 .name = "mailbox",
139 .sysc = &omap2xxx_mailbox_sysc,
140};
141
142
143
144
145
146
147
148static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
149 .rev_offs = 0x0000,
150 .sysc_offs = 0x0010,
151 .syss_offs = 0x0014,
152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
156 .sysc_fields = &omap_hwmod_sysc_type1,
157};
158
159struct omap_hwmod_class omap2xxx_mcspi_class = {
160 .name = "mcspi",
161 .sysc = &omap2xxx_mcspi_sysc,
162 .rev = OMAP2_MCSPI_REV,
163};
164
165
166
167
168
169
170static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
171 .rev_offs = 0x0000,
172 .sysc_offs = 0x0010,
173 .syss_offs = 0x0014,
174 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
175 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
176 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
177 .sysc_fields = &omap_hwmod_sysc_type1,
178};
179
180static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
181 .name = "gpmc",
182 .sysc = &omap2xxx_gpmc_sysc,
183};
184
185
186
187
188
189
190struct omap_hwmod omap2xxx_l3_main_hwmod = {
191 .name = "l3_main",
192 .class = &l3_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
194};
195
196
197struct omap_hwmod omap2xxx_l4_core_hwmod = {
198 .name = "l4_core",
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
201};
202
203
204struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
205 .name = "l4_wkup",
206 .class = &l4_hwmod_class,
207 .flags = HWMOD_NO_IDLEST,
208};
209
210
211struct omap_hwmod omap2xxx_mpu_hwmod = {
212 .name = "mpu",
213 .class = &mpu_hwmod_class,
214 .main_clk = "mpu_ck",
215};
216
217
218struct omap_hwmod omap2xxx_iva_hwmod = {
219 .name = "iva",
220 .class = &iva_hwmod_class,
221};
222
223
224static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
225 .timer_capability = OMAP_TIMER_ALWON,
226};
227
228
229static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
230 .timer_capability = OMAP_TIMER_HAS_PWM,
231};
232
233
234static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
235 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
236};
237
238
239
240struct omap_hwmod omap2xxx_timer1_hwmod = {
241 .name = "timer1",
242 .main_clk = "gpt1_fck",
243 .prcm = {
244 .omap2 = {
245 .prcm_reg_id = 1,
246 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
247 .module_offs = WKUP_MOD,
248 .idlest_reg_id = 1,
249 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
250 },
251 },
252 .dev_attr = &capability_alwon_dev_attr,
253 .class = &omap2xxx_timer_hwmod_class,
254 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
255};
256
257
258
259struct omap_hwmod omap2xxx_timer2_hwmod = {
260 .name = "timer2",
261 .main_clk = "gpt2_fck",
262 .prcm = {
263 .omap2 = {
264 .prcm_reg_id = 1,
265 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
266 .module_offs = CORE_MOD,
267 .idlest_reg_id = 1,
268 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
269 },
270 },
271 .class = &omap2xxx_timer_hwmod_class,
272 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
273};
274
275
276
277struct omap_hwmod omap2xxx_timer3_hwmod = {
278 .name = "timer3",
279 .main_clk = "gpt3_fck",
280 .prcm = {
281 .omap2 = {
282 .prcm_reg_id = 1,
283 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
284 .module_offs = CORE_MOD,
285 .idlest_reg_id = 1,
286 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
287 },
288 },
289 .class = &omap2xxx_timer_hwmod_class,
290 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
291};
292
293
294
295struct omap_hwmod omap2xxx_timer4_hwmod = {
296 .name = "timer4",
297 .main_clk = "gpt4_fck",
298 .prcm = {
299 .omap2 = {
300 .prcm_reg_id = 1,
301 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
302 .module_offs = CORE_MOD,
303 .idlest_reg_id = 1,
304 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
305 },
306 },
307 .class = &omap2xxx_timer_hwmod_class,
308 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
309};
310
311
312
313struct omap_hwmod omap2xxx_timer5_hwmod = {
314 .name = "timer5",
315 .main_clk = "gpt5_fck",
316 .prcm = {
317 .omap2 = {
318 .prcm_reg_id = 1,
319 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
320 .module_offs = CORE_MOD,
321 .idlest_reg_id = 1,
322 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
323 },
324 },
325 .dev_attr = &capability_dsp_dev_attr,
326 .class = &omap2xxx_timer_hwmod_class,
327 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
328};
329
330
331
332struct omap_hwmod omap2xxx_timer6_hwmod = {
333 .name = "timer6",
334 .main_clk = "gpt6_fck",
335 .prcm = {
336 .omap2 = {
337 .prcm_reg_id = 1,
338 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
339 .module_offs = CORE_MOD,
340 .idlest_reg_id = 1,
341 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
342 },
343 },
344 .dev_attr = &capability_dsp_dev_attr,
345 .class = &omap2xxx_timer_hwmod_class,
346 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
347};
348
349
350
351struct omap_hwmod omap2xxx_timer7_hwmod = {
352 .name = "timer7",
353 .main_clk = "gpt7_fck",
354 .prcm = {
355 .omap2 = {
356 .prcm_reg_id = 1,
357 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
358 .module_offs = CORE_MOD,
359 .idlest_reg_id = 1,
360 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
361 },
362 },
363 .dev_attr = &capability_dsp_dev_attr,
364 .class = &omap2xxx_timer_hwmod_class,
365 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
366};
367
368
369
370struct omap_hwmod omap2xxx_timer8_hwmod = {
371 .name = "timer8",
372 .main_clk = "gpt8_fck",
373 .prcm = {
374 .omap2 = {
375 .prcm_reg_id = 1,
376 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
377 .module_offs = CORE_MOD,
378 .idlest_reg_id = 1,
379 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
380 },
381 },
382 .dev_attr = &capability_dsp_dev_attr,
383 .class = &omap2xxx_timer_hwmod_class,
384 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
385};
386
387
388
389struct omap_hwmod omap2xxx_timer9_hwmod = {
390 .name = "timer9",
391 .main_clk = "gpt9_fck",
392 .prcm = {
393 .omap2 = {
394 .prcm_reg_id = 1,
395 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
396 .module_offs = CORE_MOD,
397 .idlest_reg_id = 1,
398 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
399 },
400 },
401 .dev_attr = &capability_pwm_dev_attr,
402 .class = &omap2xxx_timer_hwmod_class,
403 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
404};
405
406
407
408struct omap_hwmod omap2xxx_timer10_hwmod = {
409 .name = "timer10",
410 .main_clk = "gpt10_fck",
411 .prcm = {
412 .omap2 = {
413 .prcm_reg_id = 1,
414 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
415 .module_offs = CORE_MOD,
416 .idlest_reg_id = 1,
417 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
418 },
419 },
420 .dev_attr = &capability_pwm_dev_attr,
421 .class = &omap2xxx_timer_hwmod_class,
422 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
423};
424
425
426
427struct omap_hwmod omap2xxx_timer11_hwmod = {
428 .name = "timer11",
429 .main_clk = "gpt11_fck",
430 .prcm = {
431 .omap2 = {
432 .prcm_reg_id = 1,
433 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
434 .module_offs = CORE_MOD,
435 .idlest_reg_id = 1,
436 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
437 },
438 },
439 .dev_attr = &capability_pwm_dev_attr,
440 .class = &omap2xxx_timer_hwmod_class,
441 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
442};
443
444
445
446struct omap_hwmod omap2xxx_timer12_hwmod = {
447 .name = "timer12",
448 .main_clk = "gpt12_fck",
449 .prcm = {
450 .omap2 = {
451 .prcm_reg_id = 1,
452 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
453 .module_offs = CORE_MOD,
454 .idlest_reg_id = 1,
455 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
456 },
457 },
458 .dev_attr = &capability_pwm_dev_attr,
459 .class = &omap2xxx_timer_hwmod_class,
460 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
461};
462
463
464struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
465 .name = "wd_timer2",
466 .class = &omap2xxx_wd_timer_hwmod_class,
467 .main_clk = "mpu_wdt_fck",
468 .prcm = {
469 .omap2 = {
470 .prcm_reg_id = 1,
471 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
472 .module_offs = WKUP_MOD,
473 .idlest_reg_id = 1,
474 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
475 },
476 },
477};
478
479
480
481struct omap_hwmod omap2xxx_uart1_hwmod = {
482 .name = "uart1",
483 .main_clk = "uart1_fck",
484 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
485 .prcm = {
486 .omap2 = {
487 .module_offs = CORE_MOD,
488 .prcm_reg_id = 1,
489 .module_bit = OMAP24XX_EN_UART1_SHIFT,
490 .idlest_reg_id = 1,
491 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
492 },
493 },
494 .class = &omap2_uart_class,
495};
496
497
498
499struct omap_hwmod omap2xxx_uart2_hwmod = {
500 .name = "uart2",
501 .main_clk = "uart2_fck",
502 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
503 .prcm = {
504 .omap2 = {
505 .module_offs = CORE_MOD,
506 .prcm_reg_id = 1,
507 .module_bit = OMAP24XX_EN_UART2_SHIFT,
508 .idlest_reg_id = 1,
509 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
510 },
511 },
512 .class = &omap2_uart_class,
513};
514
515
516
517struct omap_hwmod omap2xxx_uart3_hwmod = {
518 .name = "uart3",
519 .main_clk = "uart3_fck",
520 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
521 .prcm = {
522 .omap2 = {
523 .module_offs = CORE_MOD,
524 .prcm_reg_id = 2,
525 .module_bit = OMAP24XX_EN_UART3_SHIFT,
526 .idlest_reg_id = 2,
527 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
528 },
529 },
530 .class = &omap2_uart_class,
531};
532
533
534
535static struct omap_hwmod_opt_clk dss_opt_clks[] = {
536
537
538
539
540 { .role = "tv_clk", .clk = "dss_54m_fck" },
541 { .role = "sys_clk", .clk = "dss2_fck" },
542};
543
544struct omap_hwmod omap2xxx_dss_core_hwmod = {
545 .name = "dss_core",
546 .class = &omap2_dss_hwmod_class,
547 .main_clk = "dss1_fck",
548 .prcm = {
549 .omap2 = {
550 .prcm_reg_id = 1,
551 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
552 .module_offs = CORE_MOD,
553 .idlest_reg_id = 1,
554 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
555 },
556 },
557 .opt_clks = dss_opt_clks,
558 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
559 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
560};
561
562struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
563 .name = "dss_dispc",
564 .class = &omap2_dispc_hwmod_class,
565 .main_clk = "dss1_fck",
566 .prcm = {
567 .omap2 = {
568 .prcm_reg_id = 1,
569 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
570 .module_offs = CORE_MOD,
571 .idlest_reg_id = 1,
572 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
573 },
574 },
575 .flags = HWMOD_NO_IDLEST,
576 .dev_attr = &omap2_3_dss_dispc_dev_attr,
577};
578
579static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
580 { .role = "ick", .clk = "dss_ick" },
581};
582
583struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
584 .name = "dss_rfbi",
585 .class = &omap2_rfbi_hwmod_class,
586 .main_clk = "dss1_fck",
587 .prcm = {
588 .omap2 = {
589 .prcm_reg_id = 1,
590 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
591 .module_offs = CORE_MOD,
592 },
593 },
594 .opt_clks = dss_rfbi_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
596 .flags = HWMOD_NO_IDLEST,
597};
598
599struct omap_hwmod omap2xxx_dss_venc_hwmod = {
600 .name = "dss_venc",
601 .class = &omap2_venc_hwmod_class,
602 .main_clk = "dss_54m_fck",
603 .prcm = {
604 .omap2 = {
605 .prcm_reg_id = 1,
606 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
607 .module_offs = CORE_MOD,
608 },
609 },
610 .flags = HWMOD_NO_IDLEST,
611};
612
613
614struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
615 .bank_width = 32,
616 .dbck_flag = false,
617};
618
619
620struct omap_hwmod omap2xxx_gpio1_hwmod = {
621 .name = "gpio1",
622 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
623 .main_clk = "gpios_fck",
624 .prcm = {
625 .omap2 = {
626 .prcm_reg_id = 1,
627 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
628 .module_offs = WKUP_MOD,
629 .idlest_reg_id = 1,
630 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
631 },
632 },
633 .class = &omap2xxx_gpio_hwmod_class,
634 .dev_attr = &omap2xxx_gpio_dev_attr,
635};
636
637
638struct omap_hwmod omap2xxx_gpio2_hwmod = {
639 .name = "gpio2",
640 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
641 .main_clk = "gpios_fck",
642 .prcm = {
643 .omap2 = {
644 .prcm_reg_id = 1,
645 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
646 .module_offs = WKUP_MOD,
647 .idlest_reg_id = 1,
648 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
649 },
650 },
651 .class = &omap2xxx_gpio_hwmod_class,
652 .dev_attr = &omap2xxx_gpio_dev_attr,
653};
654
655
656struct omap_hwmod omap2xxx_gpio3_hwmod = {
657 .name = "gpio3",
658 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
659 .main_clk = "gpios_fck",
660 .prcm = {
661 .omap2 = {
662 .prcm_reg_id = 1,
663 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
664 .module_offs = WKUP_MOD,
665 .idlest_reg_id = 1,
666 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
667 },
668 },
669 .class = &omap2xxx_gpio_hwmod_class,
670 .dev_attr = &omap2xxx_gpio_dev_attr,
671};
672
673
674struct omap_hwmod omap2xxx_gpio4_hwmod = {
675 .name = "gpio4",
676 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
677 .main_clk = "gpios_fck",
678 .prcm = {
679 .omap2 = {
680 .prcm_reg_id = 1,
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
683 .idlest_reg_id = 1,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
685 },
686 },
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
689};
690
691
692static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
693 .num_chipselect = 4,
694};
695
696struct omap_hwmod omap2xxx_mcspi1_hwmod = {
697 .name = "mcspi1",
698 .main_clk = "mcspi1_fck",
699 .prcm = {
700 .omap2 = {
701 .module_offs = CORE_MOD,
702 .prcm_reg_id = 1,
703 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
704 .idlest_reg_id = 1,
705 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
706 },
707 },
708 .class = &omap2xxx_mcspi_class,
709 .dev_attr = &omap_mcspi1_dev_attr,
710};
711
712
713static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
714 .num_chipselect = 2,
715};
716
717struct omap_hwmod omap2xxx_mcspi2_hwmod = {
718 .name = "mcspi2",
719 .main_clk = "mcspi2_fck",
720 .prcm = {
721 .omap2 = {
722 .module_offs = CORE_MOD,
723 .prcm_reg_id = 1,
724 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
725 .idlest_reg_id = 1,
726 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
727 },
728 },
729 .class = &omap2xxx_mcspi_class,
730 .dev_attr = &omap_mcspi2_dev_attr,
731};
732
733static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
734 .name = "counter",
735};
736
737struct omap_hwmod omap2xxx_counter_32k_hwmod = {
738 .name = "counter_32k",
739 .main_clk = "func_32k_ck",
740 .prcm = {
741 .omap2 = {
742 .module_offs = WKUP_MOD,
743 .prcm_reg_id = 1,
744 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
745 .idlest_reg_id = 1,
746 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
747 },
748 },
749 .class = &omap2xxx_counter_hwmod_class,
750};
751
752
753struct omap_hwmod omap2xxx_gpmc_hwmod = {
754 .name = "gpmc",
755 .class = &omap2xxx_gpmc_hwmod_class,
756 .main_clk = "gpmc_fck",
757
758 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
759 .prcm = {
760 .omap2 = {
761 .prcm_reg_id = 3,
762 .module_bit = OMAP24XX_EN_GPMC_MASK,
763 .module_offs = CORE_MOD,
764 },
765 },
766};
767
768
769
770static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
771 .rev_offs = 0x3c,
772 .sysc_offs = 0x40,
773 .syss_offs = 0x44,
774 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
775 SYSS_HAS_RESET_STATUS),
776 .sysc_fields = &omap_hwmod_sysc_type1,
777};
778
779static struct omap_hwmod_class omap2_rng_hwmod_class = {
780 .name = "rng",
781 .sysc = &omap2_rng_sysc,
782};
783
784struct omap_hwmod omap2xxx_rng_hwmod = {
785 .name = "rng",
786 .main_clk = "l4_ck",
787 .prcm = {
788 .omap2 = {
789 .module_offs = CORE_MOD,
790 .prcm_reg_id = 4,
791 .module_bit = OMAP24XX_EN_RNG_SHIFT,
792 .idlest_reg_id = 4,
793 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
794 },
795 },
796
797
798
799
800
801
802 .flags = HWMOD_INIT_NO_RESET,
803 .class = &omap2_rng_hwmod_class,
804};
805
806
807
808static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
809 .rev_offs = 0x5c,
810 .sysc_offs = 0x60,
811 .syss_offs = 0x64,
812 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
813 SYSS_HAS_RESET_STATUS),
814 .sysc_fields = &omap_hwmod_sysc_type1,
815};
816
817static struct omap_hwmod_class omap2xxx_sham_class = {
818 .name = "sham",
819 .sysc = &omap2_sham_sysc,
820};
821
822struct omap_hwmod omap2xxx_sham_hwmod = {
823 .name = "sham",
824 .main_clk = "l4_ck",
825 .prcm = {
826 .omap2 = {
827 .module_offs = CORE_MOD,
828 .prcm_reg_id = 4,
829 .module_bit = OMAP24XX_EN_SHA_SHIFT,
830 .idlest_reg_id = 4,
831 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
832 },
833 },
834 .class = &omap2xxx_sham_class,
835};
836
837
838
839static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
840 .rev_offs = 0x44,
841 .sysc_offs = 0x48,
842 .syss_offs = 0x4c,
843 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
844 SYSS_HAS_RESET_STATUS),
845 .sysc_fields = &omap_hwmod_sysc_type1,
846};
847
848static struct omap_hwmod_class omap2xxx_aes_class = {
849 .name = "aes",
850 .sysc = &omap2_aes_sysc,
851};
852
853struct omap_hwmod omap2xxx_aes_hwmod = {
854 .name = "aes",
855 .main_clk = "l4_ck",
856 .prcm = {
857 .omap2 = {
858 .module_offs = CORE_MOD,
859 .prcm_reg_id = 4,
860 .module_bit = OMAP24XX_EN_AES_SHIFT,
861 .idlest_reg_id = 4,
862 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
863 },
864 },
865 .class = &omap2xxx_aes_class,
866};
867