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17#include <linux/init.h>
18#include <linux/linkage.h>
19
20#include <soc/tegra/flowctrl.h>
21#include <soc/tegra/fuse.h>
22
23#include <asm/asm-offsets.h>
24#include <asm/cache.h>
25
26#include "iomap.h"
27#include "reset.h"
28#include "sleep.h"
29
30#define PMC_SCRATCH41 0x140
31
32#define RESET_DATA(x) ((TEGRA_RESET_
33
34#ifdef CONFIG_PM_SLEEP
35
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43
44
45ENTRY(tegra_resume)
46 check_cpu_part_num 0xc09, r8, r9
47 bleq v7_invalidate_l1
48
49 cpu_id r0
50 cmp r0,
51 THUMB( it ne )
52 bne cpu_resume @ no
53
54 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
55
56 cmp r6,
57 beq 1f @ Yes
58
59 cpu_to_csr_reg r1, r0
60 mov32 r2, TEGRA_FLOW_CTRL_BASE
61 ldr r1, [r2, r1]
62
63 orr r1, r1, \
64
65 movw r0,
66 @ & ext flags for CPU power mgnt
67 bic r1, r1, r0
68 str r1, [r2]
691:
70
71 mov32 r9, 0xc09
72 cmp r8, r9
73 bne end_ca9_scu_l2_resume
74#ifdef CONFIG_HAVE_ARM_SCU
75
76 mov32 r0, TEGRA_ARM_PERIF_BASE
77 ldr r1, [r0]
78 orr r1, r1,
79 str r1, [r0]
80#endif
81
82#ifdef CONFIG_CACHE_L2X0
83
84 bl l2c310_early_resume
85#endif
86end_ca9_scu_l2_resume:
87 mov32 r9, 0xc0f
88 cmp r8, r9
89 bleq tegra_init_l2_for_a15
90
91 b cpu_resume
92ENDPROC(tegra_resume)
93#endif
94
95 .align L1_CACHE_SHIFT
96ENTRY(__tegra_cpu_reset_handler_start)
97
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117
118 .align L1_CACHE_SHIFT
119ENTRY(__tegra_cpu_reset_handler)
120
121 cpsid aif, 0x13 @ SVC mode, interrupts disabled
122
123 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
124#ifdef CONFIG_ARCH_TEGRA_2x_SOC
125t20_check:
126 cmp r6,
127 bne after_t20_check
128t20_errata:
129
130 mrc p15, 0, r0, c1, c0, 0 @ read system control register
131 orr r0, r0,
132 mcr p15, 0, r0, c1, c0, 0 @ write system control register
133 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
134 orr r0, r0,
135 orr r0, r0,
136 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
137 b after_errata
138after_t20_check:
139#endif
140#ifdef CONFIG_ARCH_TEGRA_3x_SOC
141t30_check:
142 cmp r6,
143 bne after_t30_check
144t30_errata:
145
146 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
147 orr r0, r0,
148 orr r0, r0,
149 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
150 b after_errata
151after_t30_check:
152#endif
153after_errata:
154 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
155 and r10, r10,
156 mov r11,
157 mov r11, r11, lsl r10 @ R11 = CPU mask
158 adr r12, __tegra_cpu_reset_handler_data
159
160#ifdef CONFIG_SMP
161
162 ldr r7, [r12,
163 tst r7, r11 @ if !present
164 bleq __die @ CPU not present (to OS)
165#endif
166
167#ifdef CONFIG_ARCH_TEGRA_2x_SOC
168
169 cmp r6,
170 bne 1f
171
172 mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
173 mov r0,
174 cmp r10,
175 strneb r0, [r5,
1761:
177#endif
178
179
180 ldr r8, [r12,
181 tst r8, r11 @ if in_lp1
182 beq __is_not_lp1
183 cmp r10,
184 bne __die @ only CPU0 can be here
185 ldr lr, [r12,
186 cmp lr,
187 bleq __die @ no LP1 startup handler
188 THUMB( add lr, lr,
189 bx lr
190__is_not_lp1:
191
192
193 ldr r9, [r12,
194 tst r9, r11 @ if in_lp2
195 beq __is_not_lp2
196 ldr lr, [r12,
197 cmp lr,
198 bleq __die @ no LP2 startup handler
199 bx lr
200
201__is_not_lp2:
202
203#ifdef CONFIG_SMP
204
205
206
207
208 cmp r6,
209 beq __no_cpu0_chk
210 cmp r10,
211 bleq __die @ CPU0 cannot be here
212__no_cpu0_chk:
213 ldr lr, [r12,
214 cmp lr,
215 bleq __die @ no secondary startup handler
216 bx lr
217#endif
218
219
220
221
222
223
224__die:
225 sub lr, lr,
226 mov32 r7, TEGRA_PMC_BASE
227 str lr, [r7,
228
229 mov32 r7, TEGRA_CLK_RESET_BASE
230
231
232 cmp r6,
233 bne 1f
234
235#ifdef CONFIG_ARCH_TEGRA_2x_SOC
236 mov32 r0, 0x1111
237 mov r1, r0, lsl r10
238 str r1, [r7,
239#endif
2401:
241#ifdef CONFIG_ARCH_TEGRA_3x_SOC
242 mov32 r6, TEGRA_FLOW_CTRL_BASE
243
244 cmp r10,
245 moveq r1,
246 moveq r2,
247 movne r1, r10, lsl
248 addne r2, r1,
249 addne r1, r1,
250
251
252
253 ldr r0, [r6, +r2]
254 orr r0, r0,
255 orr r0, r0,
256 str r0, [r6, +r2]
257
258
259 mov r0,
260 str r0, [r6, +r1]
261 ldr r0, [r6, +r1] @ memory barrier
262
263 dsb
264 isb
265 wfi @ CPU should be power gated here
266
267
268
269 mov r0, r11, lsl
270 str r0, [r7,
271#endif
272
273
274 b .
275ENDPROC(__tegra_cpu_reset_handler)
276
277 .align L1_CACHE_SHIFT
278 .type __tegra_cpu_reset_handler_data, %object
279 .globl __tegra_cpu_reset_handler_data
280__tegra_cpu_reset_handler_data:
281 .rept TEGRA_RESET_DATA_SIZE
282 .long 0
283 .endr
284 .globl __tegra20_cpu1_resettable_status_offset
285 .equ __tegra20_cpu1_resettable_status_offset, \
286 . - __tegra_cpu_reset_handler_start
287 .byte 0
288 .align L1_CACHE_SHIFT
289
290ENTRY(__tegra_cpu_reset_handler_end)
291