LXR linux/arch/mips/netlogic/xlp/ahci-init-xlp2.c

   1/*
   2 * Copyright (c) 2003-2014 Broadcom Corporation
   3 * All Rights Reserved
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the Broadcom
   9 * license below:
  10 *
  11 * Redistribution and use in source and binary forms, with or without
  12 * modification, are permitted provided that the following conditions
  13 * are met:
  14 *
  15 * 1. Redistributions of source code must retain the above copyright
  16 *    notice, this list of conditions and the following disclaimer.
  17 * 2. Redistributions in binary form must reproduce the above copyright
  18 *    notice, this list of conditions and the following disclaimer in
  19 *    the documentation and/or other materials provided with the
  20 *    distribution.
  21 *
  22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 */
  34
  35#include <linux/dma-mapping.h>
  36#include <linux/kernel.h>
  37#include <linux/delay.h>
  38#include <linux/init.h>
  39#include <linux/pci.h>
  40#include <linux/irq.h>
  41#include <linux/bitops.h>
  42#include <linux/pci_ids.h>
  43#include <linux/nodemask.h>
  44
  45#include <asm/cpu.h>
  46#include <asm/mipsregs.h>
  47
  48#include <asm/netlogic/common.h>
  49#include <asm/netlogic/haldefs.h>
  50#include <asm/netlogic/mips-extns.h>
  51#include <asm/netlogic/xlp-hal/xlp.h>
  52#include <asm/netlogic/xlp-hal/iomap.h>
  53
  54#define SATA_CTL                0x0
  55#define SATA_STATUS             0x1 /* Status Reg */
  56#define SATA_INT                0x2 /* Interrupt Reg */
  57#define SATA_INT_MASK           0x3 /* Interrupt Mask Reg */
  58#define SATA_BIU_TIMEOUT        0x4
  59#define AXIWRSPERRLOG           0x5
  60#define AXIRDSPERRLOG           0x6
  61#define BiuTimeoutLow           0x7
  62#define BiuTimeoutHi            0x8
  63#define BiuSlvErLow             0x9
  64#define BiuSlvErHi              0xa
  65#define IO_CONFIG_SWAP_DIS      0xb
  66#define CR_REG_TIMER            0xc
  67#define CORE_ID                 0xd
  68#define AXI_SLAVE_OPT1          0xe
  69#define PHY_MEM_ACCESS          0xf
  70#define PHY0_CNTRL              0x10
  71#define PHY0_STAT               0x11
  72#define PHY0_RX_ALIGN           0x12
  73#define PHY0_RX_EQ_LO           0x13
  74#define PHY0_RX_EQ_HI           0x14
  75#define PHY0_BIST_LOOP          0x15
  76#define PHY1_CNTRL              0x16
  77#define PHY1_STAT               0x17
  78#define PHY1_RX_ALIGN           0x18
  79#define PHY1_RX_EQ_LO           0x19
  80#define PHY1_RX_EQ_HI           0x1a
  81#define PHY1_BIST_LOOP          0x1b
  82#define RdExBase                0x1c
  83#define RdExLimit               0x1d
  84#define CacheAllocBase          0x1e
  85#define CacheAllocLimit         0x1f
  86#define BiuSlaveCmdGstNum       0x20
  87
  88/*SATA_CTL Bits */
  89#define SATA_RST_N              BIT(0)  /* Active low reset sata_core phy */
  90#define SataCtlReserve0         BIT(1)
  91#define M_CSYSREQ               BIT(2)  /* AXI master low power, not used */
  92#define S_CSYSREQ               BIT(3)  /* AXI slave low power, not used */
  93#define P0_CP_DET               BIT(8)  /* Reserved, bring in from pad */
  94#define P0_MP_SW                BIT(9)  /* Mech Switch */
  95#define P0_DISABLE              BIT(10) /* disable p0 */
  96#define P0_ACT_LED_EN           BIT(11) /* Active LED enable */
  97#define P0_IRST_HARD_SYNTH      BIT(12) /* PHY hard synth reset */
  98#define P0_IRST_HARD_TXRX       BIT(13) /* PHY lane hard reset */
  99#define P0_IRST_POR             BIT(14) /* PHY power on reset*/
 100#define P0_IPDTXL               BIT(15) /* PHY Tx lane dis/power down */
 101#define P0_IPDRXL               BIT(16) /* PHY Rx lane dis/power down */
 102#define P0_IPDIPDMSYNTH         BIT(17) /* PHY synthesizer dis/porwer down */
 103#define P0_CP_POD_EN            BIT(18) /* CP_POD enable */
 104#define P0_AT_BYPASS            BIT(19) /* P0 address translation by pass */
 105#define P1_CP_DET               BIT(20) /* Reserved,Cold Detect */
 106#define P1_MP_SW                BIT(21) /* Mech Switch */
 107#define P1_DISABLE              BIT(22) /* disable p1 */
 108#define P1_ACT_LED_EN           BIT(23) /* Active LED enable */
 109#define P1_IRST_HARD_SYNTH      BIT(24) /* PHY hard synth reset */
 110#define P1_IRST_HARD_TXRX       BIT(25) /* PHY lane hard reset */
 111#define P1_IRST_POR             BIT(26) /* PHY power on reset*/
 112#define P1_IPDTXL               BIT(27) /* PHY Tx lane dis/porwer down */
 113#define P1_IPDRXL               BIT(28) /* PHY Rx lane dis/porwer down */
 114#define P1_IPDIPDMSYNTH         BIT(29) /* PHY synthesizer dis/porwer down */
 115#define P1_CP_POD_EN            BIT(30)
 116#define P1_AT_BYPASS            BIT(31) /* P1 address translation by pass */
 117
 118/* Status register */
 119#define M_CACTIVE               BIT(0)  /* m_cactive, not used */
 120#define S_CACTIVE               BIT(1)  /* s_cactive, not used */
 121#define P0_PHY_READY            BIT(8)  /* phy is ready */
 122#define P0_CP_POD               BIT(9)  /* Cold PowerOn */
 123#define P0_SLUMBER              BIT(10) /* power mode slumber */
 124#define P0_PATIAL               BIT(11) /* power mode patial */
 125#define P0_PHY_SIG_DET          BIT(12) /* phy dignal detect */
 126#define P0_PHY_CALI             BIT(13) /* phy calibration done */
 127#define P1_PHY_READY            BIT(16) /* phy is ready */
 128#define P1_CP_POD               BIT(17) /* Cold PowerOn */
 129#define P1_SLUMBER              BIT(18) /* power mode slumber */
 130#define P1_PATIAL               BIT(19) /* power mode patial */
 131#define P1_PHY_SIG_DET          BIT(20) /* phy dignal detect */
 132#define P1_PHY_CALI             BIT(21) /* phy calibration done */
 133
 134/* SATA CR_REG_TIMER bits */
 135#define CR_TIME_SCALE           (0x1000 << 0)
 136
 137/* SATA PHY specific registers start and end address */
 138#define RXCDRCALFOSC0           0x0065
 139#define CALDUTY                 0x006e
 140#define RXDPIF                  0x8065
 141#define PPMDRIFTMAX_HI          0x80A4
 142
 143#define nlm_read_sata_reg(b, r)         nlm_read_reg(b, r)
 144#define nlm_write_sata_reg(b, r, v)     nlm_write_reg(b, r, v)
 145#define nlm_get_sata_pcibase(node)      \
 146                nlm_pcicfg_base(XLP9XX_IO_SATA_OFFSET(node))
 147#define nlm_get_sata_regbase(node)      \
 148                (nlm_get_sata_pcibase(node) + 0x100)
 149
 150/* SATA PHY config for register block 1 0x0065 .. 0x006e */
 151static const u8 sata_phy_config1[]  = {
 152        0xC9, 0xC9, 0x07, 0x07, 0x18, 0x18, 0x01, 0x01, 0x22, 0x00
 153};
 154
 155/* SATA PHY config for register block 2 0x8065 .. 0x80A4 */
 156static const u8 sata_phy_config2[]  = {
 157        0xAA, 0x00, 0x4C, 0xC9, 0xC9, 0x07, 0x07, 0x18,
 158        0x18, 0x05, 0x0C, 0x10, 0x00, 0x10, 0x00, 0xFF,
 159        0xCF, 0xF7, 0xE1, 0xF5, 0xFD, 0xFD, 0xFF, 0xFF,
 160        0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, 0xFD, 0xFD,
 161        0xF5, 0xF5, 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5,
 162        0xFD, 0xFD, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xF5,
 163        0x3F, 0x00, 0x32, 0x00, 0x03, 0x01, 0x05, 0x05,
 164        0x04, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04,
 165};
 166
 167const int sata_phy_debug = 0;   /* set to verify PHY writes */
 168
 169static void sata_clear_glue_reg(u64 regbase, u32 off, u32 bit)
 170{
 171        u32 reg_val;
 172
 173        reg_val = nlm_read_sata_reg(regbase, off);
 174        nlm_write_sata_reg(regbase, off, (reg_val & ~bit));
 175}
 176
 177static void sata_set_glue_reg(u64 regbase, u32 off, u32 bit)
 178{
 179        u32 reg_val;
 180
 181        reg_val = nlm_read_sata_reg(regbase, off);
 182        nlm_write_sata_reg(regbase, off, (reg_val | bit));
 183}
 184
 185static void write_phy_reg(u64 regbase, u32 addr, u32 physel, u8 data)
 186{
 187        nlm_write_sata_reg(regbase, PHY_MEM_ACCESS,
 188                (1u << 31) | (physel << 24) | (data << 16) | addr);
 189        udelay(850);
 190}
 191
 192static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)
 193{
 194        u32 val;
 195
 196        nlm_write_sata_reg(regbase, PHY_MEM_ACCESS,
 197                (0 << 31) | (physel << 24) | (0 << 16) | addr);
 198        udelay(850);
 199        val = nlm_read_sata_reg(regbase, PHY_MEM_ACCESS);
 200        return (val >> 16) & 0xff;
 201}
 202
 203static void config_sata_phy(u64 regbase)
 204{
 205        u32 port, i, reg;
 206        u8 val;
 207
 208        for (port = 0; port < 2; port++) {
 209                for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
 210                        write_phy_reg(regbase, reg, port, sata_phy_config1[i]);
 211
 212                for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
 213                        write_phy_reg(regbase, reg, port, sata_phy_config2[i]);
 214
 215                /* Fix for PHY link up failures at lower temperatures */
 216                write_phy_reg(regbase, 0x800F, port, 0x1f);
 217
 218                val = read_phy_reg(regbase, 0x0029, port);
 219                write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));
 220
 221                val = read_phy_reg(regbase, 0x0056, port);
 222                write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));
 223
 224                val = read_phy_reg(regbase, 0x0018, port);
 225                write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));
 226        }
 227}
 228
 229static void check_phy_register(u64 regbase, u32 addr, u32 physel, u8 xdata)
 230{
 231        u8 data;
 232
 233        data = read_phy_reg(regbase, addr, physel);
 234        pr_info("PHY read addr = 0x%x physel = %d data = 0x%x %s\n",
 235                addr, physel, data, data == xdata ? "TRUE" : "FALSE");
 236}
 237
 238static void verify_sata_phy_config(u64 regbase)
 239{
 240        u32 port, i, reg;
 241
 242        for (port = 0; port < 2; port++) {
 243                for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
 244                        check_phy_register(regbase, reg, port,
 245                                                sata_phy_config1[i]);
 246
 247                for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
 248                        check_phy_register(regbase, reg, port,
 249                                                sata_phy_config2[i]);
 250        }
 251}
 252
 253static void nlm_sata_firmware_init(int node)
 254{
 255        u32 reg_val;
 256        u64 regbase;
 257        int n;
 258
 259        pr_info("Initializing XLP9XX On-chip AHCI...\n");
 260        regbase = nlm_get_sata_regbase(node);
 261
 262        /* Reset port0 */
 263        sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_POR);
 264        sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX);
 265        sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH);
 266        sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDTXL);
 267        sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDRXL);
 268        sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH);
 269
 270        /* port1 */
 271        sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_POR);
 272        sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX);
 273        sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH);
 274        sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDTXL);
 275        sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDRXL);
 276        sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH);
 277        udelay(300);
 278
 279        /* Set PHY */
 280        sata_set_glue_reg(regbase, SATA_CTL, P0_IPDTXL);
 281        sata_set_glue_reg(regbase, SATA_CTL, P0_IPDRXL);
 282        sata_set_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH);
 283        sata_set_glue_reg(regbase, SATA_CTL, P1_IPDTXL);
 284        sata_set_glue_reg(regbase, SATA_CTL, P1_IPDRXL);
 285        sata_set_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH);
 286
 287        udelay(1000);
 288        sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_POR);
 289        udelay(1000);
 290        sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_POR);
 291        udelay(1000);
 292
 293        /* setup PHY */
 294        config_sata_phy(regbase);
 295        if (sata_phy_debug)
 296                verify_sata_phy_config(regbase);
 297
 298        udelay(1000);
 299        sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX);
 300        sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH);
 301        sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX);
 302        sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH);
 303        udelay(300);
 304
 305        /* Override reset in serial PHY mode */
 306        sata_set_glue_reg(regbase, CR_REG_TIMER, CR_TIME_SCALE);
 307        /* Set reset SATA */
 308        sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N);
 309        sata_set_glue_reg(regbase, SATA_CTL, M_CSYSREQ);
 310        sata_set_glue_reg(regbase, SATA_CTL, S_CSYSREQ);
 311
 312        pr_debug("Waiting for PHYs to come up.\n");
 313        n = 10000;
 314        do {
 315                reg_val = nlm_read_sata_reg(regbase, SATA_STATUS);
 316                if ((reg_val & P1_PHY_READY) && (reg_val & P0_PHY_READY))
 317                        break;
 318                udelay(10);
 319        } while (--n > 0);
 320
 321        if (reg_val  & P0_PHY_READY)
 322                pr_info("PHY0 is up.\n");
 323        else
 324                pr_info("PHY0 is down.\n");
 325        if (reg_val  & P1_PHY_READY)
 326                pr_info("PHY1 is up.\n");
 327        else
 328                pr_info("PHY1 is down.\n");
 329
 330        pr_info("XLP AHCI Init Done.\n");
 331}
 332
 333static int __init nlm_ahci_init(void)
 334{
 335        int node;
 336
 337        if (!cpu_is_xlp9xx())
 338                return 0;
 339        for (node = 0; node < NLM_NR_NODES; node++)
 340                if (nlm_node_present(node))
 341                        nlm_sata_firmware_init(node);
 342        return 0;
 343}
 344
 345static void nlm_sata_intr_ack(struct irq_data *data)
 346{
 347        u64 regbase;
 348        u32 val;
 349        int node;
 350
 351        node = data->irq / NLM_IRQS_PER_NODE;
 352        regbase = nlm_get_sata_regbase(node);
 353        val = nlm_read_sata_reg(regbase, SATA_INT);
 354        sata_set_glue_reg(regbase, SATA_INT, val);
 355}
 356
 357static void nlm_sata_fixup_bar(struct pci_dev *dev)
 358{
 359        dev->resource[5] = dev->resource[0];
 360        memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
 361}
 362
 363static void nlm_sata_fixup_final(struct pci_dev *dev)
 364{
 365        u32 val;
 366        u64 regbase;
 367        int node;
 368
 369        /* Find end bridge function to find node */
 370        node = xlp_socdev_to_node(dev);
 371        regbase = nlm_get_sata_regbase(node);
 372
 373        /* clear pending interrupts and then enable them */
 374        val = nlm_read_sata_reg(regbase, SATA_INT);
 375        sata_set_glue_reg(regbase, SATA_INT, val);
 376
 377        /* Enable only the core interrupt */
 378        sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1);
 379
 380        dev->irq = nlm_irq_to_xirq(node, PIC_SATA_IRQ);
 381        nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack);
 382}
 383
 384arch_initcall(nlm_ahci_init);
 385
 386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA,
 387                nlm_sata_fixup_bar);
 388
 389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA,
 390                nlm_sata_fixup_final);
 391