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24
25#include <linux/delay.h>
26#include <linux/export.h>
27#include <linux/gfp.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34
35static int eeh_pe_aux_size = 0;
36static LIST_HEAD(eeh_phb_pe);
37
38
39
40
41
42
43
44void eeh_set_pe_aux_size(int size)
45{
46 if (size < 0)
47 return;
48
49 eeh_pe_aux_size = size;
50}
51
52
53
54
55
56
57
58
59static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
60{
61 struct eeh_pe *pe;
62 size_t alloc_size;
63
64 alloc_size = sizeof(struct eeh_pe);
65 if (eeh_pe_aux_size) {
66 alloc_size = ALIGN(alloc_size, cache_line_size());
67 alloc_size += eeh_pe_aux_size;
68 }
69
70
71 pe = kzalloc(alloc_size, GFP_KERNEL);
72 if (!pe) return NULL;
73
74
75 pe->type = type;
76 pe->phb = phb;
77 INIT_LIST_HEAD(&pe->child_list);
78 INIT_LIST_HEAD(&pe->child);
79 INIT_LIST_HEAD(&pe->edevs);
80
81 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
82 cache_line_size());
83 return pe;
84}
85
86
87
88
89
90
91
92
93int eeh_phb_pe_create(struct pci_controller *phb)
94{
95 struct eeh_pe *pe;
96
97
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
99 if (!pe) {
100 pr_err("%s: out of memory!\n", __func__);
101 return -ENOMEM;
102 }
103
104
105 list_add_tail(&pe->child, &eeh_phb_pe);
106
107 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
108
109 return 0;
110}
111
112
113
114
115
116
117
118
119
120struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
121{
122 struct eeh_pe *pe;
123
124 list_for_each_entry(pe, &eeh_phb_pe, child) {
125
126
127
128
129
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
131 return pe;
132 }
133
134 return NULL;
135}
136
137
138
139
140
141
142
143
144
145static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
146 struct eeh_pe *root)
147{
148 struct list_head *next = pe->child_list.next;
149
150 if (next == &pe->child_list) {
151 while (1) {
152 if (pe == root)
153 return NULL;
154 next = pe->child.next;
155 if (next != &pe->parent->child_list)
156 break;
157 pe = pe->parent;
158 }
159 }
160
161 return list_entry(next, struct eeh_pe, child);
162}
163
164
165
166
167
168
169
170
171
172
173
174
175void *eeh_pe_traverse(struct eeh_pe *root,
176 eeh_traverse_func fn, void *flag)
177{
178 struct eeh_pe *pe;
179 void *ret;
180
181 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
182 ret = fn(pe, flag);
183 if (ret) return ret;
184 }
185
186 return NULL;
187}
188
189
190
191
192
193
194
195
196
197
198void *eeh_pe_dev_traverse(struct eeh_pe *root,
199 eeh_traverse_func fn, void *flag)
200{
201 struct eeh_pe *pe;
202 struct eeh_dev *edev, *tmp;
203 void *ret;
204
205 if (!root) {
206 pr_warn("%s: Invalid PE %p\n",
207 __func__, root);
208 return NULL;
209 }
210
211
212 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
213 eeh_pe_for_each_dev(pe, edev, tmp) {
214 ret = fn(edev, flag);
215 if (ret)
216 return ret;
217 }
218 }
219
220 return NULL;
221}
222
223
224
225
226
227
228
229
230
231
232
233struct eeh_pe_get_flag {
234 int pe_no;
235 int config_addr;
236};
237
238static void *__eeh_pe_get(void *data, void *flag)
239{
240 struct eeh_pe *pe = (struct eeh_pe *)data;
241 struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
242
243
244 if (pe->type & EEH_PE_PHB)
245 return NULL;
246
247
248
249
250
251 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
252 if (tmp->pe_no == pe->addr)
253 return pe;
254 } else {
255 if (tmp->pe_no &&
256 (tmp->pe_no == pe->addr))
257 return pe;
258 }
259
260
261 if (tmp->config_addr &&
262 (tmp->config_addr == pe->config_addr))
263 return pe;
264
265 return NULL;
266}
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
282 int pe_no, int config_addr)
283{
284 struct eeh_pe *root = eeh_phb_pe_get(phb);
285 struct eeh_pe_get_flag tmp = { pe_no, config_addr };
286 struct eeh_pe *pe;
287
288 pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
289
290 return pe;
291}
292
293
294
295
296
297
298
299
300
301static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
302{
303 struct eeh_dev *parent;
304 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
305
306
307
308
309
310
311 if (edev->physfn)
312 pdn = pci_get_pdn(edev->physfn);
313 else
314 pdn = pdn ? pdn->parent : NULL;
315 while (pdn) {
316
317 parent = pdn_to_eeh_dev(pdn);
318 if (!parent)
319 return NULL;
320
321 if (parent->pe)
322 return parent->pe;
323
324 pdn = pdn->parent;
325 }
326
327 return NULL;
328}
329
330
331
332
333
334
335
336
337
338
339int eeh_add_to_parent_pe(struct eeh_dev *edev)
340{
341 struct eeh_pe *pe, *parent;
342 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
343 int config_addr = (pdn->busno << 8) | (pdn->devfn);
344
345
346 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
347 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
348 __func__, config_addr, pdn->phb->global_number);
349 return -EINVAL;
350 }
351
352
353
354
355
356
357
358 pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
359 if (pe && !(pe->type & EEH_PE_INVALID)) {
360
361 pe->type = EEH_PE_BUS;
362 edev->pe = pe;
363
364
365 list_add_tail(&edev->list, &pe->edevs);
366 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
367 pdn->phb->global_number,
368 pdn->busno,
369 PCI_SLOT(pdn->devfn),
370 PCI_FUNC(pdn->devfn),
371 pe->addr);
372 return 0;
373 } else if (pe && (pe->type & EEH_PE_INVALID)) {
374 list_add_tail(&edev->list, &pe->edevs);
375 edev->pe = pe;
376
377
378
379
380 parent = pe;
381 while (parent) {
382 if (!(parent->type & EEH_PE_INVALID))
383 break;
384 parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
385 parent = parent->parent;
386 }
387
388 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
389 "PE#%x, Parent PE#%x\n",
390 pdn->phb->global_number,
391 pdn->busno,
392 PCI_SLOT(pdn->devfn),
393 PCI_FUNC(pdn->devfn),
394 pe->addr, pe->parent->addr);
395 return 0;
396 }
397
398
399 if (edev->physfn)
400 pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
401 else
402 pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
403 if (!pe) {
404 pr_err("%s: out of memory!\n", __func__);
405 return -ENOMEM;
406 }
407 pe->addr = edev->pe_config_addr;
408 pe->config_addr = config_addr;
409
410
411
412
413
414
415
416 parent = eeh_pe_get_parent(edev);
417 if (!parent) {
418 parent = eeh_phb_pe_get(pdn->phb);
419 if (!parent) {
420 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
421 __func__, pdn->phb->global_number);
422 edev->pe = NULL;
423 kfree(pe);
424 return -EEXIST;
425 }
426 }
427 pe->parent = parent;
428
429
430
431
432
433 list_add_tail(&pe->child, &parent->child_list);
434 list_add_tail(&edev->list, &pe->edevs);
435 edev->pe = pe;
436 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
437 "Device PE#%x, Parent PE#%x\n",
438 pdn->phb->global_number,
439 pdn->busno,
440 PCI_SLOT(pdn->devfn),
441 PCI_FUNC(pdn->devfn),
442 pe->addr, pe->parent->addr);
443
444 return 0;
445}
446
447
448
449
450
451
452
453
454
455
456int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
457{
458 struct eeh_pe *pe, *parent, *child;
459 int cnt;
460 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
461
462 if (!edev->pe) {
463 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
464 __func__, pdn->phb->global_number,
465 pdn->busno,
466 PCI_SLOT(pdn->devfn),
467 PCI_FUNC(pdn->devfn));
468 return -EEXIST;
469 }
470
471
472 pe = eeh_dev_to_pe(edev);
473 edev->pe = NULL;
474 list_del(&edev->list);
475
476
477
478
479
480
481
482 while (1) {
483 parent = pe->parent;
484 if (pe->type & EEH_PE_PHB)
485 break;
486
487 if (!(pe->state & EEH_PE_KEEP)) {
488 if (list_empty(&pe->edevs) &&
489 list_empty(&pe->child_list)) {
490 list_del(&pe->child);
491 kfree(pe);
492 } else {
493 break;
494 }
495 } else {
496 if (list_empty(&pe->edevs)) {
497 cnt = 0;
498 list_for_each_entry(child, &pe->child_list, child) {
499 if (!(child->type & EEH_PE_INVALID)) {
500 cnt++;
501 break;
502 }
503 }
504
505 if (!cnt)
506 pe->type |= EEH_PE_INVALID;
507 else
508 break;
509 }
510 }
511
512 pe = parent;
513 }
514
515 return 0;
516}
517
518
519
520
521
522
523
524
525
526
527void eeh_pe_update_time_stamp(struct eeh_pe *pe)
528{
529 time64_t tstamp;
530
531 if (!pe) return;
532
533 if (pe->freeze_count <= 0) {
534 pe->freeze_count = 0;
535 pe->tstamp = ktime_get_seconds();
536 } else {
537 tstamp = ktime_get_seconds();
538 if (tstamp - pe->tstamp > 3600) {
539 pe->tstamp = tstamp;
540 pe->freeze_count = 0;
541 }
542 }
543}
544
545
546
547
548
549
550
551
552
553
554static void *__eeh_pe_state_mark(void *data, void *flag)
555{
556 struct eeh_pe *pe = (struct eeh_pe *)data;
557 int state = *((int *)flag);
558 struct eeh_dev *edev, *tmp;
559 struct pci_dev *pdev;
560
561
562 if (pe->state & EEH_PE_REMOVED)
563 return NULL;
564
565 pe->state |= state;
566
567
568 if (!(state & EEH_PE_ISOLATED))
569 return NULL;
570
571 eeh_pe_for_each_dev(pe, edev, tmp) {
572 pdev = eeh_dev_to_pci_dev(edev);
573 if (pdev)
574 pdev->error_state = pci_channel_io_frozen;
575 }
576
577
578 if (pe->state & EEH_PE_CFG_RESTRICTED)
579 pe->state |= EEH_PE_CFG_BLOCKED;
580
581 return NULL;
582}
583
584
585
586
587
588
589
590
591
592void eeh_pe_state_mark(struct eeh_pe *pe, int state)
593{
594 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
595}
596EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
597
598static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
599{
600 struct eeh_dev *edev = data;
601 int mode = *((int *)flag);
602
603 edev->mode |= mode;
604
605 return NULL;
606}
607
608
609
610
611
612
613
614void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
615{
616 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
617}
618
619
620
621
622
623
624
625
626
627
628static void *__eeh_pe_state_clear(void *data, void *flag)
629{
630 struct eeh_pe *pe = (struct eeh_pe *)data;
631 int state = *((int *)flag);
632 struct eeh_dev *edev, *tmp;
633 struct pci_dev *pdev;
634
635
636 if (pe->state & EEH_PE_REMOVED)
637 return NULL;
638
639 pe->state &= ~state;
640
641
642
643
644
645
646 if (!(state & EEH_PE_ISOLATED))
647 return NULL;
648
649 pe->check_count = 0;
650 eeh_pe_for_each_dev(pe, edev, tmp) {
651 pdev = eeh_dev_to_pci_dev(edev);
652 if (!pdev)
653 continue;
654
655 pdev->error_state = pci_channel_io_normal;
656 }
657
658
659 if (pe->state & EEH_PE_CFG_RESTRICTED)
660 pe->state &= ~EEH_PE_CFG_BLOCKED;
661
662 return NULL;
663}
664
665
666
667
668
669
670
671
672
673
674void eeh_pe_state_clear(struct eeh_pe *pe, int state)
675{
676 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
677}
678
679
680
681
682
683
684
685
686
687
688
689
690void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
691{
692 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
693 if (!(state & EEH_PE_ISOLATED))
694 return;
695
696
697 state = EEH_PE_CFG_BLOCKED;
698 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
699}
700
701
702
703
704
705
706
707
708
709
710
711
712static void eeh_bridge_check_link(struct eeh_dev *edev)
713{
714 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
715 int cap;
716 uint32_t val;
717 int timeout = 0;
718
719
720
721
722
723 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
724 return;
725
726 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
727 __func__, pdn->phb->global_number,
728 pdn->busno,
729 PCI_SLOT(pdn->devfn),
730 PCI_FUNC(pdn->devfn));
731
732
733 cap = edev->pcie_cap;
734 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
735 if (!(val & PCI_EXP_SLTSTA_PDS)) {
736 pr_debug(" No card in the slot (0x%04x) !\n", val);
737 return;
738 }
739
740
741 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
742 if (val & PCI_EXP_SLTCAP_PCP) {
743 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
744 if (val & PCI_EXP_SLTCTL_PCC) {
745 pr_debug(" In power-off state, power it on ...\n");
746 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
747 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
748 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
749 msleep(2 * 1000);
750 }
751 }
752
753
754 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
755 val &= ~PCI_EXP_LNKCTL_LD;
756 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
757
758
759 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
760 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
761 pr_debug(" No link reporting capability (0x%08x) \n", val);
762 msleep(1000);
763 return;
764 }
765
766
767 timeout = 0;
768 while (timeout < 5000) {
769 msleep(20);
770 timeout += 20;
771
772 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
773 if (val & PCI_EXP_LNKSTA_DLLLA)
774 break;
775 }
776
777 if (val & PCI_EXP_LNKSTA_DLLLA)
778 pr_debug(" Link up (%s)\n",
779 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
780 else
781 pr_debug(" Link not ready (0x%04x)\n", val);
782}
783
784#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
785#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
786
787static void eeh_restore_bridge_bars(struct eeh_dev *edev)
788{
789 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
790 int i;
791
792
793
794
795
796 for (i = 4; i < 13; i++)
797 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
798
799 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
800
801
802 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
803 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
804 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
805 SAVED_BYTE(PCI_LATENCY_TIMER));
806
807 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
808
809
810 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
811
812
813 eeh_bridge_check_link(edev);
814}
815
816static void eeh_restore_device_bars(struct eeh_dev *edev)
817{
818 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
819 int i;
820 u32 cmd;
821
822 for (i = 4; i < 10; i++)
823 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
824
825 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
826
827 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
828 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
829 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
830 SAVED_BYTE(PCI_LATENCY_TIMER));
831
832
833 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
834
835
836
837
838
839 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
840 if (edev->config_space[1] & PCI_COMMAND_PARITY)
841 cmd |= PCI_COMMAND_PARITY;
842 else
843 cmd &= ~PCI_COMMAND_PARITY;
844 if (edev->config_space[1] & PCI_COMMAND_SERR)
845 cmd |= PCI_COMMAND_SERR;
846 else
847 cmd &= ~PCI_COMMAND_SERR;
848 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
849}
850
851
852
853
854
855
856
857
858
859
860static void *eeh_restore_one_device_bars(void *data, void *flag)
861{
862 struct eeh_dev *edev = (struct eeh_dev *)data;
863 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
864
865
866 if (edev->mode & EEH_DEV_BRIDGE)
867 eeh_restore_bridge_bars(edev);
868 else
869 eeh_restore_device_bars(edev);
870
871 if (eeh_ops->restore_config && pdn)
872 eeh_ops->restore_config(pdn);
873
874 return NULL;
875}
876
877
878
879
880
881
882
883
884void eeh_pe_restore_bars(struct eeh_pe *pe)
885{
886
887
888
889
890 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
891}
892
893
894
895
896
897
898
899
900
901
902const char *eeh_pe_loc_get(struct eeh_pe *pe)
903{
904 struct pci_bus *bus = eeh_pe_bus_get(pe);
905 struct device_node *dn;
906 const char *loc = NULL;
907
908 while (bus) {
909 dn = pci_bus_to_OF_node(bus);
910 if (!dn) {
911 bus = bus->parent;
912 continue;
913 }
914
915 if (pci_is_root_bus(bus))
916 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
917 else
918 loc = of_get_property(dn, "ibm,slot-location-code",
919 NULL);
920
921 if (loc)
922 return loc;
923
924 bus = bus->parent;
925 }
926
927 return "N/A";
928}
929
930
931
932
933
934
935
936
937
938
939
940struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
941{
942 struct eeh_dev *edev;
943 struct pci_dev *pdev;
944
945 if (pe->type & EEH_PE_PHB)
946 return pe->phb->bus;
947
948
949 if (pe->state & EEH_PE_PRI_BUS)
950 return pe->bus;
951
952
953 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
954 pdev = eeh_dev_to_pci_dev(edev);
955 if (pdev)
956 return pdev->bus;
957
958 return NULL;
959}
960