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8#ifndef _SPARC_SBI_H
9#define _SPARC_SBI_H
10
11#include <asm/obio.h>
12
13
14struct sbi_regs {
15 u32 cid;
16 u32 ctl;
17 u32 status;
18 u32 _unused1;
19
20 u32 cfg0;
21 u32 cfg1;
22 u32 cfg2;
23 u32 cfg3;
24
25 u32 stb0;
26 u32 stb1;
27 u32 stb2;
28 u32 stb3;
29
30 u32 intr_state;
31 u32 intr_tid;
32 u32 intr_diag;
33};
34
35#define SBI_CID 0x02800000
36#define SBI_CTL 0x02800004
37#define SBI_STATUS 0x02800008
38#define SBI_CFG0 0x02800010
39#define SBI_CFG1 0x02800014
40#define SBI_CFG2 0x02800018
41#define SBI_CFG3 0x0280001c
42#define SBI_STB0 0x02800020
43#define SBI_STB1 0x02800024
44#define SBI_STB2 0x02800028
45#define SBI_STB3 0x0280002c
46#define SBI_INTR_STATE 0x02800030
47#define SBI_INTR_TID 0x02800034
48#define SBI_INTR_DIAG 0x02800038
49
50
51#define SBI_CFG_BURST_MASK 0x0000001e
52
53
54#define SBI2DEVID(sbino) ((sbino<<4)|2)
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66
67#ifndef __ASSEMBLY__
68
69static inline int acquire_sbi(int devid, int mask)
70{
71 __asm__ __volatile__ ("swapa [%2] %3, %0" :
72 "=r" (mask) :
73 "0" (mask),
74 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
75 "i" (ASI_M_CTL));
76 return mask;
77}
78
79static inline void release_sbi(int devid, int mask)
80{
81 __asm__ __volatile__ ("sta %0, [%1] %2" : :
82 "r" (mask),
83 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
84 "i" (ASI_M_CTL));
85}
86
87static inline void set_sbi_tid(int devid, int targetid)
88{
89 __asm__ __volatile__ ("sta %0, [%1] %2" : :
90 "r" (targetid),
91 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
92 "i" (ASI_M_CTL));
93}
94
95static inline int get_sbi_ctl(int devid, int cfgno)
96{
97 int cfg;
98
99 __asm__ __volatile__ ("lda [%1] %2, %0" :
100 "=r" (cfg) :
101 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
102 "i" (ASI_M_CTL));
103 return cfg;
104}
105
106static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
107{
108 __asm__ __volatile__ ("sta %0, [%1] %2" : :
109 "r" (cfg),
110 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
111 "i" (ASI_M_CTL));
112}
113
114#endif
115
116#endif
117