LXR linux/drivers/clocksource/timer-ti-32k.c

   1/**
   2 * timer-ti-32k.c - OMAP2 32k Timer Support
   3 *
   4 * Copyright (C) 2009 Nokia Corporation
   5 *
   6 * Update to use new clocksource/clockevent layers
   7 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
   8 * Copyright (C) 2007 MontaVista Software, Inc.
   9 *
  10 * Original driver:
  11 * Copyright (C) 2005 Nokia Corporation
  12 * Author: Paul Mundt <paul.mundt@nokia.com>
  13 *         Juha Yrjölä <juha.yrjola@nokia.com>
  14 * OMAP Dual-mode timer framework support by Timo Teras
  15 *
  16 * Some parts based off of TI's 24xx code:
  17 *
  18 * Copyright (C) 2004-2009 Texas Instruments, Inc.
  19 *
  20 * Roughly modelled after the OMAP1 MPU timer code.
  21 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  22 *
  23 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  24 *
  25 * This program is free software: you can redistribute it and/or modify
  26 * it under the terms of the GNU General Public License version 2  of
  27 * the License as published by the Free Software Foundation.
  28 *
  29 * This program is distributed in the hope that it will be useful,
  30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32 * GNU General Public License for more details.
  33 *
  34 * You should have received a copy of the GNU General Public License
  35 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  36 */
  37
  38#include <linux/init.h>
  39#include <linux/time.h>
  40#include <linux/sched_clock.h>
  41#include <linux/clocksource.h>
  42#include <linux/of.h>
  43#include <linux/of_address.h>
  44
  45/*
  46 * 32KHz clocksource ... always available, on pretty most chips except
  47 * OMAP 730 and 1510.  Other timers could be used as clocksources, with
  48 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  49 * but systems won't necessarily want to spend resources that way.
  50 */
  51
  52#define OMAP2_32KSYNCNT_REV_OFF         0x0
  53#define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
  54#define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
  55#define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
  56
  57struct ti_32k {
  58        void __iomem            *base;
  59        void __iomem            *counter;
  60        struct clocksource      cs;
  61};
  62
  63static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
  64{
  65        return container_of(cs, struct ti_32k, cs);
  66}
  67
  68static u64 notrace ti_32k_read_cycles(struct clocksource *cs)
  69{
  70        struct ti_32k *ti = to_ti_32k(cs);
  71
  72        return (u64)readl_relaxed(ti->counter);
  73}
  74
  75static struct ti_32k ti_32k_timer = {
  76        .cs = {
  77                .name           = "32k_counter",
  78                .rating         = 250,
  79                .read           = ti_32k_read_cycles,
  80                .mask           = CLOCKSOURCE_MASK(32),
  81                .flags          = CLOCK_SOURCE_IS_CONTINUOUS |
  82                                CLOCK_SOURCE_SUSPEND_NONSTOP,
  83        },
  84};
  85
  86static u64 notrace omap_32k_read_sched_clock(void)
  87{
  88        return ti_32k_read_cycles(&ti_32k_timer.cs);
  89}
  90
  91static int __init ti_32k_timer_init(struct device_node *np)
  92{
  93        int ret;
  94
  95        ti_32k_timer.base = of_iomap(np, 0);
  96        if (!ti_32k_timer.base) {
  97                pr_err("Can't ioremap 32k timer base\n");
  98                return -ENXIO;
  99        }
 100
 101        ti_32k_timer.counter = ti_32k_timer.base;
 102
 103        /*
 104         * 32k sync Counter IP register offsets vary between the highlander
 105         * version and the legacy ones.
 106         *
 107         * The 'SCHEME' bits(30-31) of the revision register is used to identify
 108         * the version.
 109         */
 110        if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
 111                        OMAP2_32KSYNCNT_REV_SCHEME)
 112                ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
 113        else
 114                ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
 115
 116        ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
 117        if (ret) {
 118                pr_err("32k_counter: can't register clocksource\n");
 119                return ret;
 120        }
 121
 122        sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
 123        pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
 124
 125        return 0;
 126}
 127TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
 128                ti_32k_timer_init);
 129