linux/drivers/gpio/gpio-it87.c
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   1/*
   2 *  GPIO interface for IT87xx Super I/O chips
   3 *
   4 *  Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
   5 *  Copyright (c) 2017 Google, Inc.
   6 *
   7 *  Based on it87_wdt.c     by Oliver Schuster
   8 *           gpio-it8761e.c by Denis Turischev
   9 *           gpio-stmpe.c   by Rabin Vincent
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License 2 as published
  13 *  by the Free Software Foundation.
  14 *
  15 *  This program is distributed in the hope that it will be useful,
  16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 *  GNU General Public License for more details.
  19 *
  20 *  You should have received a copy of the GNU General Public License
  21 *  along with this program; see the file COPYING.  If not, write to
  22 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  23 */
  24
  25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27#include <linux/init.h>
  28#include <linux/kernel.h>
  29#include <linux/module.h>
  30#include <linux/io.h>
  31#include <linux/errno.h>
  32#include <linux/ioport.h>
  33#include <linux/slab.h>
  34#include <linux/gpio.h>
  35
  36/* Chip Id numbers */
  37#define NO_DEV_ID       0xffff
  38#define IT8620_ID       0x8620
  39#define IT8628_ID       0x8628
  40#define IT8728_ID       0x8728
  41#define IT8732_ID       0x8732
  42#define IT8761_ID       0x8761
  43#define IT8772_ID       0x8772
  44
  45/* IO Ports */
  46#define REG             0x2e
  47#define VAL             0x2f
  48
  49/* Logical device Numbers LDN */
  50#define GPIO            0x07
  51
  52/* Configuration Registers and Functions */
  53#define LDNREG          0x07
  54#define CHIPID          0x20
  55#define CHIPREV         0x22
  56
  57/**
  58 * struct it87_gpio - it87-specific GPIO chip
  59 * @chip the underlying gpio_chip structure
  60 * @lock a lock to avoid races between operations
  61 * @io_base base address for gpio ports
  62 * @io_size size of the port rage starting from io_base.
  63 * @output_base Super I/O register address for Output Enable register
  64 * @simple_base Super I/O 'Simple I/O' Enable register
  65 * @simple_size Super IO 'Simple I/O' Enable register size; this is
  66 *      required because IT87xx chips might only provide Simple I/O
  67 *      switches on a subset of lines, whereas the others keep the
  68 *      same status all time.
  69 */
  70struct it87_gpio {
  71        struct gpio_chip chip;
  72        spinlock_t lock;
  73        u16 io_base;
  74        u16 io_size;
  75        u8 output_base;
  76        u8 simple_base;
  77        u8 simple_size;
  78};
  79
  80static struct it87_gpio it87_gpio_chip = {
  81        .lock = __SPIN_LOCK_UNLOCKED(it87_gpio_chip.lock),
  82};
  83
  84/* Superio chip access functions; copied from wdt_it87 */
  85
  86static inline int superio_enter(void)
  87{
  88        /*
  89         * Try to reserve REG and REG + 1 for exclusive access.
  90         */
  91        if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
  92                return -EBUSY;
  93
  94        outb(0x87, REG);
  95        outb(0x01, REG);
  96        outb(0x55, REG);
  97        outb(0x55, REG);
  98        return 0;
  99}
 100
 101static inline void superio_exit(void)
 102{
 103        outb(0x02, REG);
 104        outb(0x02, VAL);
 105        release_region(REG, 2);
 106}
 107
 108static inline void superio_select(int ldn)
 109{
 110        outb(LDNREG, REG);
 111        outb(ldn, VAL);
 112}
 113
 114static inline int superio_inb(int reg)
 115{
 116        outb(reg, REG);
 117        return inb(VAL);
 118}
 119
 120static inline void superio_outb(int val, int reg)
 121{
 122        outb(reg, REG);
 123        outb(val, VAL);
 124}
 125
 126static inline int superio_inw(int reg)
 127{
 128        int val;
 129
 130        outb(reg++, REG);
 131        val = inb(VAL) << 8;
 132        outb(reg, REG);
 133        val |= inb(VAL);
 134        return val;
 135}
 136
 137static inline void superio_outw(int val, int reg)
 138{
 139        outb(reg++, REG);
 140        outb(val >> 8, VAL);
 141        outb(reg, REG);
 142        outb(val, VAL);
 143}
 144
 145static inline void superio_set_mask(int mask, int reg)
 146{
 147        u8 curr_val = superio_inb(reg);
 148        u8 new_val = curr_val | mask;
 149
 150        if (curr_val != new_val)
 151                superio_outb(new_val, reg);
 152}
 153
 154static inline void superio_clear_mask(int mask, int reg)
 155{
 156        u8 curr_val = superio_inb(reg);
 157        u8 new_val = curr_val & ~mask;
 158
 159        if (curr_val != new_val)
 160                superio_outb(new_val, reg);
 161}
 162
 163static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num)
 164{
 165        u8 mask, group;
 166        int rc = 0;
 167        struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
 168
 169        mask = 1 << (gpio_num % 8);
 170        group = (gpio_num / 8);
 171
 172        spin_lock(&it87_gpio->lock);
 173
 174        rc = superio_enter();
 175        if (rc)
 176                goto exit;
 177
 178        /* not all the IT87xx chips support Simple I/O and not all of
 179         * them allow all the lines to be set/unset to Simple I/O.
 180         */
 181        if (group < it87_gpio->simple_size)
 182                superio_set_mask(mask, group + it87_gpio->simple_base);
 183
 184        /* clear output enable, setting the pin to input, as all the
 185         * newly-exported GPIO interfaces are set to input.
 186         */
 187        superio_clear_mask(mask, group + it87_gpio->output_base);
 188
 189        superio_exit();
 190
 191exit:
 192        spin_unlock(&it87_gpio->lock);
 193        return rc;
 194}
 195
 196static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num)
 197{
 198        u16 reg;
 199        u8 mask;
 200        struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
 201
 202        mask = 1 << (gpio_num % 8);
 203        reg = (gpio_num / 8) + it87_gpio->io_base;
 204
 205        return !!(inb(reg) & mask);
 206}
 207
 208static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num)
 209{
 210        u8 mask, group;
 211        int rc = 0;
 212        struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
 213
 214        mask = 1 << (gpio_num % 8);
 215        group = (gpio_num / 8);
 216
 217        spin_lock(&it87_gpio->lock);
 218
 219        rc = superio_enter();
 220        if (rc)
 221                goto exit;
 222
 223        /* clear the output enable bit */
 224        superio_clear_mask(mask, group + it87_gpio->output_base);
 225
 226        superio_exit();
 227
 228exit:
 229        spin_unlock(&it87_gpio->lock);
 230        return rc;
 231}
 232
 233static void it87_gpio_set(struct gpio_chip *chip,
 234                          unsigned gpio_num, int val)
 235{
 236        u8 mask, curr_vals;
 237        u16 reg;
 238        struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
 239
 240        mask = 1 << (gpio_num % 8);
 241        reg = (gpio_num / 8) + it87_gpio->io_base;
 242
 243        curr_vals = inb(reg);
 244        if (val)
 245                outb(curr_vals | mask, reg);
 246        else
 247                outb(curr_vals & ~mask, reg);
 248}
 249
 250static int it87_gpio_direction_out(struct gpio_chip *chip,
 251                                   unsigned gpio_num, int val)
 252{
 253        u8 mask, group;
 254        int rc = 0;
 255        struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
 256
 257        mask = 1 << (gpio_num % 8);
 258        group = (gpio_num / 8);
 259
 260        spin_lock(&it87_gpio->lock);
 261
 262        rc = superio_enter();
 263        if (rc)
 264                goto exit;
 265
 266        /* set the output enable bit */
 267        superio_set_mask(mask, group + it87_gpio->output_base);
 268
 269        it87_gpio_set(chip, gpio_num, val);
 270
 271        superio_exit();
 272
 273exit:
 274        spin_unlock(&it87_gpio->lock);
 275        return rc;
 276}
 277
 278static const struct gpio_chip it87_template_chip = {
 279        .label                  = KBUILD_MODNAME,
 280        .owner                  = THIS_MODULE,
 281        .request                = it87_gpio_request,
 282        .get                    = it87_gpio_get,
 283        .direction_input        = it87_gpio_direction_in,
 284        .set                    = it87_gpio_set,
 285        .direction_output       = it87_gpio_direction_out,
 286        .base                   = -1
 287};
 288
 289static int __init it87_gpio_init(void)
 290{
 291        int rc = 0, i;
 292        u16 chip_type;
 293        u8 chip_rev, gpio_ba_reg;
 294        char *labels, **labels_table;
 295
 296        struct it87_gpio *it87_gpio = &it87_gpio_chip;
 297
 298        rc = superio_enter();
 299        if (rc)
 300                return rc;
 301
 302        chip_type = superio_inw(CHIPID);
 303        chip_rev  = superio_inb(CHIPREV) & 0x0f;
 304        superio_exit();
 305
 306        it87_gpio->chip = it87_template_chip;
 307
 308        switch (chip_type) {
 309        case IT8620_ID:
 310        case IT8628_ID:
 311                gpio_ba_reg = 0x62;
 312                it87_gpio->io_size = 11;
 313                it87_gpio->output_base = 0xc8;
 314                it87_gpio->simple_size = 0;
 315                it87_gpio->chip.ngpio = 64;
 316                break;
 317        case IT8728_ID:
 318        case IT8732_ID:
 319        case IT8772_ID:
 320                gpio_ba_reg = 0x62;
 321                it87_gpio->io_size = 8;
 322                it87_gpio->output_base = 0xc8;
 323                it87_gpio->simple_base = 0xc0;
 324                it87_gpio->simple_size = 5;
 325                it87_gpio->chip.ngpio = 64;
 326                break;
 327        case IT8761_ID:
 328                gpio_ba_reg = 0x60;
 329                it87_gpio->io_size = 4;
 330                it87_gpio->output_base = 0xf0;
 331                it87_gpio->simple_size = 0;
 332                it87_gpio->chip.ngpio = 16;
 333                break;
 334        case NO_DEV_ID:
 335                pr_err("no device\n");
 336                return -ENODEV;
 337        default:
 338                pr_err("Unknown Chip found, Chip %04x Revision %x\n",
 339                       chip_type, chip_rev);
 340                return -ENODEV;
 341        }
 342
 343        rc = superio_enter();
 344        if (rc)
 345                return rc;
 346
 347        superio_select(GPIO);
 348
 349        /* fetch GPIO base address */
 350        it87_gpio->io_base = superio_inw(gpio_ba_reg);
 351
 352        superio_exit();
 353
 354        pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n",
 355                chip_type, chip_rev, it87_gpio->chip.ngpio,
 356                it87_gpio->io_base);
 357
 358        if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
 359                                                        KBUILD_MODNAME))
 360                return -EBUSY;
 361
 362        /* Set up aliases for the GPIO connection.
 363         *
 364         * ITE documentation for recent chips such as the IT8728F
 365         * refers to the GPIO lines as GPxy, with a coordinates system
 366         * where x is the GPIO group (starting from 1) and y is the
 367         * bit within the group.
 368         *
 369         * By creating these aliases, we make it easier to understand
 370         * to which GPIO pin we're referring to.
 371         */
 372        labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"),
 373                                                                GFP_KERNEL);
 374        labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *),
 375                                                                GFP_KERNEL);
 376
 377        if (!labels || !labels_table) {
 378                rc = -ENOMEM;
 379                goto labels_free;
 380        }
 381
 382        for (i = 0; i < it87_gpio->chip.ngpio; i++) {
 383                char *label = &labels[i * sizeof("it87_gpXY")];
 384
 385                sprintf(label, "it87_gp%u%u", 1+(i/8), i%8);
 386                labels_table[i] = label;
 387        }
 388
 389        it87_gpio->chip.names = (const char *const*)labels_table;
 390
 391        rc = gpiochip_add_data(&it87_gpio->chip, it87_gpio);
 392        if (rc)
 393                goto labels_free;
 394
 395        return 0;
 396
 397labels_free:
 398        kfree(labels_table);
 399        kfree(labels);
 400        release_region(it87_gpio->io_base, it87_gpio->io_size);
 401        return rc;
 402}
 403
 404static void __exit it87_gpio_exit(void)
 405{
 406        struct it87_gpio *it87_gpio = &it87_gpio_chip;
 407
 408        gpiochip_remove(&it87_gpio->chip);
 409        release_region(it87_gpio->io_base, it87_gpio->io_size);
 410        kfree(it87_gpio->chip.names[0]);
 411        kfree(it87_gpio->chip.names);
 412}
 413
 414module_init(it87_gpio_init);
 415module_exit(it87_gpio_exit);
 416
 417MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>");
 418MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips");
 419MODULE_LICENSE("GPL");
 420