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23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "clearstate_si.h"
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
41
42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
45
46MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47MODULE_FIRMWARE("radeon/tahiti_me.bin");
48MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
50
51MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
52MODULE_FIRMWARE("radeon/pitcairn_me.bin");
53MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
54MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
55
56MODULE_FIRMWARE("radeon/verde_pfp.bin");
57MODULE_FIRMWARE("radeon/verde_me.bin");
58MODULE_FIRMWARE("radeon/verde_ce.bin");
59MODULE_FIRMWARE("radeon/verde_rlc.bin");
60
61MODULE_FIRMWARE("radeon/oland_pfp.bin");
62MODULE_FIRMWARE("radeon/oland_me.bin");
63MODULE_FIRMWARE("radeon/oland_ce.bin");
64MODULE_FIRMWARE("radeon/oland_rlc.bin");
65
66MODULE_FIRMWARE("radeon/hainan_pfp.bin");
67MODULE_FIRMWARE("radeon/hainan_me.bin");
68MODULE_FIRMWARE("radeon/hainan_ce.bin");
69MODULE_FIRMWARE("radeon/hainan_rlc.bin");
70
71static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
72static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
73
74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
75
76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
85
86static const u32 verde_rlc_save_restore_register_list[] =
87{
88 (0x8000 << 16) | (0x98f4 >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x98f4 >> 2),
91 0x00000000,
92 (0x8000 << 16) | (0xe80 >> 2),
93 0x00000000,
94 (0x8040 << 16) | (0xe80 >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x89bc >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x89bc >> 2),
99 0x00000000,
100 (0x8000 << 16) | (0x8c1c >> 2),
101 0x00000000,
102 (0x8040 << 16) | (0x8c1c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x98f0 >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xe7c >> 2),
107 0x00000000,
108 (0x8000 << 16) | (0x9148 >> 2),
109 0x00000000,
110 (0x8040 << 16) | (0x9148 >> 2),
111 0x00000000,
112 (0x9c00 << 16) | (0x9150 >> 2),
113 0x00000000,
114 (0x9c00 << 16) | (0x897c >> 2),
115 0x00000000,
116 (0x9c00 << 16) | (0x8d8c >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0xac54 >> 2),
119 0X00000000,
120 0x3,
121 (0x9c00 << 16) | (0x98f8 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9910 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x9914 >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9918 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x991c >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9920 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x9924 >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9928 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x992c >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9930 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x9934 >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9938 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x993c >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9940 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x9944 >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9948 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x994c >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9950 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x9954 >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9958 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x995c >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9960 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x9964 >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9968 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x996c >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9970 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x9974 >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x9978 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x997c >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x9980 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x9984 >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x9988 >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0x998c >> 2),
186 0x00000000,
187 (0x9c00 << 16) | (0x8c00 >> 2),
188 0x00000000,
189 (0x9c00 << 16) | (0x8c14 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x8c04 >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x8c08 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x9b7c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x9b7c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0xe84 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0xe84 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x89c0 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x89c0 >> 2),
206 0x00000000,
207 (0x8000 << 16) | (0x914c >> 2),
208 0x00000000,
209 (0x8040 << 16) | (0x914c >> 2),
210 0x00000000,
211 (0x8000 << 16) | (0x8c20 >> 2),
212 0x00000000,
213 (0x8040 << 16) | (0x8c20 >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x9354 >> 2),
216 0x00000000,
217 (0x8040 << 16) | (0x9354 >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9060 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x9364 >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9100 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x913c >> 2),
226 0x00000000,
227 (0x8000 << 16) | (0x90e0 >> 2),
228 0x00000000,
229 (0x8000 << 16) | (0x90e4 >> 2),
230 0x00000000,
231 (0x8000 << 16) | (0x90e8 >> 2),
232 0x00000000,
233 (0x8040 << 16) | (0x90e0 >> 2),
234 0x00000000,
235 (0x8040 << 16) | (0x90e4 >> 2),
236 0x00000000,
237 (0x8040 << 16) | (0x90e8 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8bcc >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x8b24 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x88c4 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x8e50 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x8c0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x8e58 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x8e5c >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x9508 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x950c >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x9494 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0xac0c >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0xac10 >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0xac14 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0xae00 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0xac08 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x88d4 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x88c8 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x88cc >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x89b0 >> 2),
276 0x00000000,
277 (0x9c00 << 16) | (0x8b10 >> 2),
278 0x00000000,
279 (0x9c00 << 16) | (0x8a14 >> 2),
280 0x00000000,
281 (0x9c00 << 16) | (0x9830 >> 2),
282 0x00000000,
283 (0x9c00 << 16) | (0x9834 >> 2),
284 0x00000000,
285 (0x9c00 << 16) | (0x9838 >> 2),
286 0x00000000,
287 (0x9c00 << 16) | (0x9a10 >> 2),
288 0x00000000,
289 (0x8000 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x9874 >> 2),
292 0x00000000,
293 (0x8001 << 16) | (0x9870 >> 2),
294 0x00000000,
295 (0x8001 << 16) | (0x9874 >> 2),
296 0x00000000,
297 (0x8040 << 16) | (0x9870 >> 2),
298 0x00000000,
299 (0x8040 << 16) | (0x9874 >> 2),
300 0x00000000,
301 (0x8041 << 16) | (0x9870 >> 2),
302 0x00000000,
303 (0x8041 << 16) | (0x9874 >> 2),
304 0x00000000,
305 0x00000000
306};
307
308static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
309{
310 const char *chip_name;
311 char fw_name[30];
312 int err;
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 const struct rlc_firmware_header_v1_0 *rlc_hdr;
315
316 DRM_DEBUG("\n");
317
318 switch (adev->asic_type) {
319 case CHIP_TAHITI:
320 chip_name = "tahiti";
321 break;
322 case CHIP_PITCAIRN:
323 chip_name = "pitcairn";
324 break;
325 case CHIP_VERDE:
326 chip_name = "verde";
327 break;
328 case CHIP_OLAND:
329 chip_name = "oland";
330 break;
331 case CHIP_HAINAN:
332 chip_name = "hainan";
333 break;
334 default: BUG();
335 }
336
337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
339 if (err)
340 goto out;
341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
342 if (err)
343 goto out;
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347
348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
350 if (err)
351 goto out;
352 err = amdgpu_ucode_validate(adev->gfx.me_fw);
353 if (err)
354 goto out;
355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
358
359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
361 if (err)
362 goto out;
363 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
364 if (err)
365 goto out;
366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
369
370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
372 if (err)
373 goto out;
374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
378
379out:
380 if (err) {
381 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
382 release_firmware(adev->gfx.pfp_fw);
383 adev->gfx.pfp_fw = NULL;
384 release_firmware(adev->gfx.me_fw);
385 adev->gfx.me_fw = NULL;
386 release_firmware(adev->gfx.ce_fw);
387 adev->gfx.ce_fw = NULL;
388 release_firmware(adev->gfx.rlc_fw);
389 adev->gfx.rlc_fw = NULL;
390 }
391 return err;
392}
393
394static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
395{
396 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
397 u32 reg_offset, split_equal_to_row_size, *tilemode;
398
399 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
400 tilemode = adev->gfx.config.tile_mode_array;
401
402 switch (adev->gfx.config.mem_row_size_in_kb) {
403 case 1:
404 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
405 break;
406 case 2:
407 default:
408 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
409 break;
410 case 4:
411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
412 break;
413 }
414
415 if (adev->asic_type == CHIP_VERDE) {
416 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
418 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
423 NUM_BANKS(ADDR_SURF_16_BANK);
424 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
426 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
431 NUM_BANKS(ADDR_SURF_16_BANK);
432 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
434 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
439 NUM_BANKS(ADDR_SURF_16_BANK);
440 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
446 NUM_BANKS(ADDR_SURF_8_BANK) |
447 TILE_SPLIT(split_equal_to_row_size);
448 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16);
451 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
453 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
458 NUM_BANKS(ADDR_SURF_4_BANK);
459 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
461 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
466 NUM_BANKS(ADDR_SURF_4_BANK);
467 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
474 NUM_BANKS(ADDR_SURF_2_BANK);
475 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
476 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
478 PIPE_CONFIG(ADDR_SURF_P4_8x16);
479 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
481 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
486 NUM_BANKS(ADDR_SURF_16_BANK);
487 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
489 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
494 NUM_BANKS(ADDR_SURF_16_BANK);
495 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
502 NUM_BANKS(ADDR_SURF_16_BANK);
503 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
504 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
505 PIPE_CONFIG(ADDR_SURF_P4_8x16);
506 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
507 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
508 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
513 NUM_BANKS(ADDR_SURF_16_BANK);
514 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
516 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
521 NUM_BANKS(ADDR_SURF_16_BANK);
522 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
524 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
529 NUM_BANKS(ADDR_SURF_16_BANK);
530 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
531 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
536 NUM_BANKS(ADDR_SURF_16_BANK) |
537 TILE_SPLIT(split_equal_to_row_size);
538 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
539 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16);
541 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
542 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
543 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
544 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
547 NUM_BANKS(ADDR_SURF_16_BANK) |
548 TILE_SPLIT(split_equal_to_row_size);
549 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
551 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
555 NUM_BANKS(ADDR_SURF_16_BANK) |
556 TILE_SPLIT(split_equal_to_row_size);
557 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
558 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
560 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
564 NUM_BANKS(ADDR_SURF_8_BANK);
565 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
567 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
572 NUM_BANKS(ADDR_SURF_8_BANK);
573 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
575 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
580 NUM_BANKS(ADDR_SURF_4_BANK);
581 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
588 NUM_BANKS(ADDR_SURF_4_BANK);
589 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
591 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
596 NUM_BANKS(ADDR_SURF_2_BANK);
597 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
604 NUM_BANKS(ADDR_SURF_2_BANK);
605 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
607 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
612 NUM_BANKS(ADDR_SURF_2_BANK);
613 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
615 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
620 NUM_BANKS(ADDR_SURF_2_BANK);
621 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_2_BANK);
629 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
631 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
636 NUM_BANKS(ADDR_SURF_2_BANK);
637 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
638 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
639 } else if (adev->asic_type == CHIP_OLAND) {
640 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
641 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
644 NUM_BANKS(ADDR_SURF_16_BANK) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
648 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
650 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
652 NUM_BANKS(ADDR_SURF_16_BANK) |
653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
656 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
658 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
660 NUM_BANKS(ADDR_SURF_16_BANK) |
661 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
662 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
663 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
664 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
665 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
666 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
667 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
668 NUM_BANKS(ADDR_SURF_16_BANK) |
669 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
672 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
673 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
674 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
676 NUM_BANKS(ADDR_SURF_16_BANK) |
677 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
678 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
680 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
681 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
682 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
683 TILE_SPLIT(split_equal_to_row_size) |
684 NUM_BANKS(ADDR_SURF_16_BANK) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
688 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
689 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
690 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
691 TILE_SPLIT(split_equal_to_row_size) |
692 NUM_BANKS(ADDR_SURF_16_BANK) |
693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
696 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
697 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
698 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
699 TILE_SPLIT(split_equal_to_row_size) |
700 NUM_BANKS(ADDR_SURF_16_BANK) |
701 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
702 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
703 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
704 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
705 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
706 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
708 NUM_BANKS(ADDR_SURF_16_BANK) |
709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
712 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
713 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
714 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
716 NUM_BANKS(ADDR_SURF_16_BANK) |
717 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
718 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
719 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
720 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
721 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
722 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
724 NUM_BANKS(ADDR_SURF_16_BANK) |
725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
728 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
729 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
730 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
732 NUM_BANKS(ADDR_SURF_16_BANK) |
733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
736 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
737 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
738 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
739 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
740 NUM_BANKS(ADDR_SURF_16_BANK) |
741 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
742 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
743 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
744 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
745 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
746 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
747 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
748 NUM_BANKS(ADDR_SURF_16_BANK) |
749 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
750 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
751 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
752 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
753 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
754 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
755 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
756 NUM_BANKS(ADDR_SURF_16_BANK) |
757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
760 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
761 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
762 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
764 NUM_BANKS(ADDR_SURF_16_BANK) |
765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
768 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
769 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
770 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772 NUM_BANKS(ADDR_SURF_16_BANK) |
773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
776 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
779 TILE_SPLIT(split_equal_to_row_size) |
780 NUM_BANKS(ADDR_SURF_16_BANK) |
781 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
784 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
785 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
786 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
787 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
788 NUM_BANKS(ADDR_SURF_16_BANK) |
789 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
792 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
793 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
794 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
795 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
796 NUM_BANKS(ADDR_SURF_16_BANK) |
797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
800 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
808 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
809 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
816 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
818 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
819 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
820 NUM_BANKS(ADDR_SURF_8_BANK) |
821 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
824 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
825 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
826 } else if (adev->asic_type == CHIP_HAINAN) {
827 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
828 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
829 PIPE_CONFIG(ADDR_SURF_P2) |
830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
834 NUM_BANKS(ADDR_SURF_16_BANK);
835 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
836 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
837 PIPE_CONFIG(ADDR_SURF_P2) |
838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
842 NUM_BANKS(ADDR_SURF_16_BANK);
843 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
844 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
845 PIPE_CONFIG(ADDR_SURF_P2) |
846 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
850 NUM_BANKS(ADDR_SURF_16_BANK);
851 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
852 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
853 PIPE_CONFIG(ADDR_SURF_P2) |
854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
857 NUM_BANKS(ADDR_SURF_8_BANK) |
858 TILE_SPLIT(split_equal_to_row_size);
859 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2);
862 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
863 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
864 PIPE_CONFIG(ADDR_SURF_P2) |
865 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
866 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
867 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
868 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
869 NUM_BANKS(ADDR_SURF_8_BANK);
870 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
871 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
872 PIPE_CONFIG(ADDR_SURF_P2) |
873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
877 NUM_BANKS(ADDR_SURF_8_BANK);
878 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
879 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
880 PIPE_CONFIG(ADDR_SURF_P2) |
881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
882 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
883 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
884 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
885 NUM_BANKS(ADDR_SURF_4_BANK);
886 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
887 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
888 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
889 PIPE_CONFIG(ADDR_SURF_P2);
890 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
891 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
892 PIPE_CONFIG(ADDR_SURF_P2) |
893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
894 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
895 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
896 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
897 NUM_BANKS(ADDR_SURF_16_BANK);
898 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
899 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
900 PIPE_CONFIG(ADDR_SURF_P2) |
901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
902 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
903 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
904 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
905 NUM_BANKS(ADDR_SURF_16_BANK);
906 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
907 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
908 PIPE_CONFIG(ADDR_SURF_P2) |
909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
913 NUM_BANKS(ADDR_SURF_16_BANK);
914 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2);
917 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
918 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
919 PIPE_CONFIG(ADDR_SURF_P2) |
920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
921 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
922 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
923 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
924 NUM_BANKS(ADDR_SURF_16_BANK);
925 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
926 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
927 PIPE_CONFIG(ADDR_SURF_P2) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
932 NUM_BANKS(ADDR_SURF_16_BANK);
933 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
934 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
935 PIPE_CONFIG(ADDR_SURF_P2) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
937 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
938 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
939 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
940 NUM_BANKS(ADDR_SURF_16_BANK);
941 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
942 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
943 PIPE_CONFIG(ADDR_SURF_P2) |
944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
947 NUM_BANKS(ADDR_SURF_16_BANK) |
948 TILE_SPLIT(split_equal_to_row_size);
949 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
950 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
951 PIPE_CONFIG(ADDR_SURF_P2);
952 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
953 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
954 PIPE_CONFIG(ADDR_SURF_P2) |
955 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
956 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
957 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
958 NUM_BANKS(ADDR_SURF_16_BANK) |
959 TILE_SPLIT(split_equal_to_row_size);
960 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
961 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
966 NUM_BANKS(ADDR_SURF_16_BANK) |
967 TILE_SPLIT(split_equal_to_row_size);
968 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
969 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
970 PIPE_CONFIG(ADDR_SURF_P2) |
971 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
972 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
975 NUM_BANKS(ADDR_SURF_8_BANK);
976 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
977 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
978 PIPE_CONFIG(ADDR_SURF_P2) |
979 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
983 NUM_BANKS(ADDR_SURF_8_BANK);
984 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_8_BANK);
992 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
993 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 PIPE_CONFIG(ADDR_SURF_P2) |
995 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
999 NUM_BANKS(ADDR_SURF_8_BANK);
1000 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1001 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1004 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1007 NUM_BANKS(ADDR_SURF_4_BANK);
1008 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1009 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1010 PIPE_CONFIG(ADDR_SURF_P2) |
1011 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1012 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1015 NUM_BANKS(ADDR_SURF_4_BANK);
1016 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1017 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1018 PIPE_CONFIG(ADDR_SURF_P2) |
1019 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1023 NUM_BANKS(ADDR_SURF_4_BANK);
1024 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1031 NUM_BANKS(ADDR_SURF_4_BANK);
1032 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1033 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 PIPE_CONFIG(ADDR_SURF_P2) |
1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK);
1040 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1041 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P2) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1044 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1047 NUM_BANKS(ADDR_SURF_4_BANK);
1048 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1049 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1050 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1051 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1052 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1053 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1055 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1058 NUM_BANKS(ADDR_SURF_16_BANK);
1059 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1060 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1063 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1066 NUM_BANKS(ADDR_SURF_16_BANK);
1067 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1068 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1071 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1074 NUM_BANKS(ADDR_SURF_16_BANK);
1075 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1076 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1081 NUM_BANKS(ADDR_SURF_4_BANK) |
1082 TILE_SPLIT(split_equal_to_row_size);
1083 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1084 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1086 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1093 NUM_BANKS(ADDR_SURF_2_BANK);
1094 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1101 NUM_BANKS(ADDR_SURF_2_BANK);
1102 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1103 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1105 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1109 NUM_BANKS(ADDR_SURF_2_BANK);
1110 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1111 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1112 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1113 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1114 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1115 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1117 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1121 NUM_BANKS(ADDR_SURF_16_BANK);
1122 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1123 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1129 NUM_BANKS(ADDR_SURF_16_BANK);
1130 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1131 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1133 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1134 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1137 NUM_BANKS(ADDR_SURF_16_BANK);
1138 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1139 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1140 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1141 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148 NUM_BANKS(ADDR_SURF_16_BANK);
1149 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1153 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1156 NUM_BANKS(ADDR_SURF_16_BANK);
1157 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1158 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1164 NUM_BANKS(ADDR_SURF_16_BANK);
1165 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1166 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1171 NUM_BANKS(ADDR_SURF_16_BANK) |
1172 TILE_SPLIT(split_equal_to_row_size);
1173 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1174 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1175 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1176 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1177 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182 NUM_BANKS(ADDR_SURF_16_BANK) |
1183 TILE_SPLIT(split_equal_to_row_size);
1184 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1185 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1190 NUM_BANKS(ADDR_SURF_16_BANK) |
1191 TILE_SPLIT(split_equal_to_row_size);
1192 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1195 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1196 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1199 NUM_BANKS(ADDR_SURF_4_BANK);
1200 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1201 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1204 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1207 NUM_BANKS(ADDR_SURF_4_BANK);
1208 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1209 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1210 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1211 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1212 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1215 NUM_BANKS(ADDR_SURF_2_BANK);
1216 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK);
1224 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1225 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1231 NUM_BANKS(ADDR_SURF_2_BANK);
1232 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1233 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1239 NUM_BANKS(ADDR_SURF_2_BANK);
1240 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1241 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1243 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1244 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1247 NUM_BANKS(ADDR_SURF_2_BANK);
1248 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1249 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1251 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1252 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1255 NUM_BANKS(ADDR_SURF_2_BANK);
1256 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK);
1264 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1265 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1271 NUM_BANKS(ADDR_SURF_2_BANK);
1272 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1273 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1274 } else {
1275 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1276 }
1277}
1278
1279static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1280 u32 sh_num, u32 instance)
1281{
1282 u32 data;
1283
1284 if (instance == 0xffffffff)
1285 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1286 else
1287 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1288
1289 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1290 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1291 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1292 else if (se_num == 0xffffffff)
1293 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1294 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1295 else if (sh_num == 0xffffffff)
1296 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1297 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1298 else
1299 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1300 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1301 WREG32(mmGRBM_GFX_INDEX, data);
1302}
1303
1304static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1305{
1306 u32 data, mask;
1307
1308 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1309 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1310
1311 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1312
1313 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1314 adev->gfx.config.max_sh_per_se);
1315
1316 return ~data & mask;
1317}
1318
1319static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1320{
1321 switch (adev->asic_type) {
1322 case CHIP_TAHITI:
1323 case CHIP_PITCAIRN:
1324 *rconf |=
1325 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1326 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1327 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1328 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1329 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1332 break;
1333 case CHIP_VERDE:
1334 *rconf |=
1335 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1336 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1337 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1338 break;
1339 case CHIP_OLAND:
1340 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1341 break;
1342 case CHIP_HAINAN:
1343 *rconf |= 0x0;
1344 break;
1345 default:
1346 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1347 break;
1348 }
1349}
1350
1351static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1352 u32 raster_config, unsigned rb_mask,
1353 unsigned num_rb)
1354{
1355 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1356 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1357 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1358 unsigned rb_per_se = num_rb / num_se;
1359 unsigned se_mask[4];
1360 unsigned se;
1361
1362 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1363 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1364 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1365 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1366
1367 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1368 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1369 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1370
1371 for (se = 0; se < num_se; se++) {
1372 unsigned raster_config_se = raster_config;
1373 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1374 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1375 int idx = (se / 2) * 2;
1376
1377 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1378 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1379
1380 if (!se_mask[idx])
1381 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1382 else
1383 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1384 }
1385
1386 pkr0_mask &= rb_mask;
1387 pkr1_mask &= rb_mask;
1388 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1389 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1390
1391 if (!pkr0_mask)
1392 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1393 else
1394 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1395 }
1396
1397 if (rb_per_se >= 2) {
1398 unsigned rb0_mask = 1 << (se * rb_per_se);
1399 unsigned rb1_mask = rb0_mask << 1;
1400
1401 rb0_mask &= rb_mask;
1402 rb1_mask &= rb_mask;
1403 if (!rb0_mask || !rb1_mask) {
1404 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1405
1406 if (!rb0_mask)
1407 raster_config_se |=
1408 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1409 else
1410 raster_config_se |=
1411 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1412 }
1413
1414 if (rb_per_se > 2) {
1415 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1416 rb1_mask = rb0_mask << 1;
1417 rb0_mask &= rb_mask;
1418 rb1_mask &= rb_mask;
1419 if (!rb0_mask || !rb1_mask) {
1420 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1421
1422 if (!rb0_mask)
1423 raster_config_se |=
1424 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1425 else
1426 raster_config_se |=
1427 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1428 }
1429 }
1430 }
1431
1432
1433 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1434 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1435 }
1436
1437
1438 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1439}
1440
1441static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1442{
1443 int i, j;
1444 u32 data;
1445 u32 raster_config = 0;
1446 u32 active_rbs = 0;
1447 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1448 adev->gfx.config.max_sh_per_se;
1449 unsigned num_rb_pipes;
1450
1451 mutex_lock(&adev->grbm_idx_mutex);
1452 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1453 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1454 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1455 data = gfx_v6_0_get_rb_active_bitmap(adev);
1456 active_rbs |= data <<
1457 ((i * adev->gfx.config.max_sh_per_se + j) *
1458 rb_bitmap_width_per_sh);
1459 }
1460 }
1461 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1462
1463 adev->gfx.config.backend_enable_mask = active_rbs;
1464 adev->gfx.config.num_rbs = hweight32(active_rbs);
1465
1466 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1467 adev->gfx.config.max_shader_engines, 16);
1468
1469 gfx_v6_0_raster_config(adev, &raster_config);
1470
1471 if (!adev->gfx.config.backend_enable_mask ||
1472 adev->gfx.config.num_rbs >= num_rb_pipes)
1473 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1474 else
1475 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1476 adev->gfx.config.backend_enable_mask,
1477 num_rb_pipes);
1478
1479
1480 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1481 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1482 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1483 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1484 RREG32(mmCC_RB_BACKEND_DISABLE);
1485 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1486 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1487 adev->gfx.config.rb_config[i][j].raster_config =
1488 RREG32(mmPA_SC_RASTER_CONFIG);
1489 }
1490 }
1491 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1492 mutex_unlock(&adev->grbm_idx_mutex);
1493}
1494
1495static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1496 u32 bitmap)
1497{
1498 u32 data;
1499
1500 if (!bitmap)
1501 return;
1502
1503 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1504 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1505
1506 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1507}
1508
1509static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1510{
1511 u32 data, mask;
1512
1513 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1514 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1515
1516 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1517 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1518}
1519
1520
1521static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1522{
1523 int i, j, k;
1524 u32 data, mask;
1525 u32 active_cu = 0;
1526
1527 mutex_lock(&adev->grbm_idx_mutex);
1528 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1529 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1530 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1531 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1532 active_cu = gfx_v6_0_get_cu_enabled(adev);
1533
1534 mask = 1;
1535 for (k = 0; k < 16; k++) {
1536 mask <<= k;
1537 if (active_cu & mask) {
1538 data &= ~mask;
1539 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1540 break;
1541 }
1542 }
1543 }
1544 }
1545 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1546 mutex_unlock(&adev->grbm_idx_mutex);
1547}
1548
1549static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1550{
1551 adev->gfx.config.double_offchip_lds_buf = 0;
1552}
1553
1554static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1555{
1556 u32 gb_addr_config = 0;
1557 u32 mc_shared_chmap, mc_arb_ramcfg;
1558 u32 sx_debug_1;
1559 u32 hdp_host_path_cntl;
1560 u32 tmp;
1561
1562 switch (adev->asic_type) {
1563 case CHIP_TAHITI:
1564 adev->gfx.config.max_shader_engines = 2;
1565 adev->gfx.config.max_tile_pipes = 12;
1566 adev->gfx.config.max_cu_per_sh = 8;
1567 adev->gfx.config.max_sh_per_se = 2;
1568 adev->gfx.config.max_backends_per_se = 4;
1569 adev->gfx.config.max_texture_channel_caches = 12;
1570 adev->gfx.config.max_gprs = 256;
1571 adev->gfx.config.max_gs_threads = 32;
1572 adev->gfx.config.max_hw_contexts = 8;
1573
1574 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1575 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1576 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1577 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1578 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1579 break;
1580 case CHIP_PITCAIRN:
1581 adev->gfx.config.max_shader_engines = 2;
1582 adev->gfx.config.max_tile_pipes = 8;
1583 adev->gfx.config.max_cu_per_sh = 5;
1584 adev->gfx.config.max_sh_per_se = 2;
1585 adev->gfx.config.max_backends_per_se = 4;
1586 adev->gfx.config.max_texture_channel_caches = 8;
1587 adev->gfx.config.max_gprs = 256;
1588 adev->gfx.config.max_gs_threads = 32;
1589 adev->gfx.config.max_hw_contexts = 8;
1590
1591 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1592 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1593 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1594 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1595 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1596 break;
1597 case CHIP_VERDE:
1598 adev->gfx.config.max_shader_engines = 1;
1599 adev->gfx.config.max_tile_pipes = 4;
1600 adev->gfx.config.max_cu_per_sh = 5;
1601 adev->gfx.config.max_sh_per_se = 2;
1602 adev->gfx.config.max_backends_per_se = 4;
1603 adev->gfx.config.max_texture_channel_caches = 4;
1604 adev->gfx.config.max_gprs = 256;
1605 adev->gfx.config.max_gs_threads = 32;
1606 adev->gfx.config.max_hw_contexts = 8;
1607
1608 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1609 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1610 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1611 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1612 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1613 break;
1614 case CHIP_OLAND:
1615 adev->gfx.config.max_shader_engines = 1;
1616 adev->gfx.config.max_tile_pipes = 4;
1617 adev->gfx.config.max_cu_per_sh = 6;
1618 adev->gfx.config.max_sh_per_se = 1;
1619 adev->gfx.config.max_backends_per_se = 2;
1620 adev->gfx.config.max_texture_channel_caches = 4;
1621 adev->gfx.config.max_gprs = 256;
1622 adev->gfx.config.max_gs_threads = 16;
1623 adev->gfx.config.max_hw_contexts = 8;
1624
1625 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1626 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1627 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1628 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1629 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1630 break;
1631 case CHIP_HAINAN:
1632 adev->gfx.config.max_shader_engines = 1;
1633 adev->gfx.config.max_tile_pipes = 4;
1634 adev->gfx.config.max_cu_per_sh = 5;
1635 adev->gfx.config.max_sh_per_se = 1;
1636 adev->gfx.config.max_backends_per_se = 1;
1637 adev->gfx.config.max_texture_channel_caches = 2;
1638 adev->gfx.config.max_gprs = 256;
1639 adev->gfx.config.max_gs_threads = 16;
1640 adev->gfx.config.max_hw_contexts = 8;
1641
1642 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1643 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1644 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1645 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1646 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1647 break;
1648 default:
1649 BUG();
1650 break;
1651 }
1652
1653 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1654 WREG32(mmSRBM_INT_CNTL, 1);
1655 WREG32(mmSRBM_INT_ACK, 1);
1656
1657 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1658
1659 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1660 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1661 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1662
1663 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1664 adev->gfx.config.mem_max_burst_length_bytes = 256;
1665 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1666 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1667 if (adev->gfx.config.mem_row_size_in_kb > 4)
1668 adev->gfx.config.mem_row_size_in_kb = 4;
1669 adev->gfx.config.shader_engine_tile_size = 32;
1670 adev->gfx.config.num_gpus = 1;
1671 adev->gfx.config.multi_gpu_tile_size = 64;
1672
1673 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1674 switch (adev->gfx.config.mem_row_size_in_kb) {
1675 case 1:
1676 default:
1677 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1678 break;
1679 case 2:
1680 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1681 break;
1682 case 4:
1683 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1684 break;
1685 }
1686 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1687 if (adev->gfx.config.max_shader_engines == 2)
1688 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1689 adev->gfx.config.gb_addr_config = gb_addr_config;
1690
1691 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1692 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1694 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1695 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1697
1698#if 0
1699 if (adev->has_uvd) {
1700 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1701 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1703 }
1704#endif
1705 gfx_v6_0_tiling_mode_table_init(adev);
1706
1707 gfx_v6_0_setup_rb(adev);
1708
1709 gfx_v6_0_setup_spi(adev);
1710
1711 gfx_v6_0_get_cu_info(adev);
1712 gfx_v6_0_config_init(adev);
1713
1714 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1715 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1716 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1717 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1718
1719 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1720 WREG32(mmSX_DEBUG_1, sx_debug_1);
1721
1722 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1723
1724 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1725 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1728
1729 WREG32(mmVGT_NUM_INSTANCES, 1);
1730 WREG32(mmCP_PERFMON_CNTL, 0);
1731 WREG32(mmSQ_CONFIG, 0);
1732 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1733 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1734
1735 WREG32(mmVGT_CACHE_INVALIDATION,
1736 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1737 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1738
1739 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1740 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1741
1742 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1743 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1744 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1746 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1748 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1750
1751 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1752 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1753
1754 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1755 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1756
1757 udelay(50);
1758}
1759
1760
1761static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1762{
1763 adev->gfx.scratch.num_reg = 8;
1764 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1765 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1766}
1767
1768static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1769{
1770 struct amdgpu_device *adev = ring->adev;
1771 uint32_t scratch;
1772 uint32_t tmp = 0;
1773 unsigned i;
1774 int r;
1775
1776 r = amdgpu_gfx_scratch_get(adev, &scratch);
1777 if (r) {
1778 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1779 return r;
1780 }
1781 WREG32(scratch, 0xCAFEDEAD);
1782
1783 r = amdgpu_ring_alloc(ring, 3);
1784 if (r) {
1785 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1786 amdgpu_gfx_scratch_free(adev, scratch);
1787 return r;
1788 }
1789 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1790 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1791 amdgpu_ring_write(ring, 0xDEADBEEF);
1792 amdgpu_ring_commit(ring);
1793
1794 for (i = 0; i < adev->usec_timeout; i++) {
1795 tmp = RREG32(scratch);
1796 if (tmp == 0xDEADBEEF)
1797 break;
1798 DRM_UDELAY(1);
1799 }
1800 if (i < adev->usec_timeout) {
1801 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1802 } else {
1803 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1804 ring->idx, scratch, tmp);
1805 r = -EINVAL;
1806 }
1807 amdgpu_gfx_scratch_free(adev, scratch);
1808 return r;
1809}
1810
1811static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1812{
1813
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1815 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1816 WRITE_DATA_DST_SEL(0)));
1817 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1818 amdgpu_ring_write(ring, 0);
1819 amdgpu_ring_write(ring, 0x1);
1820}
1821
1822static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1823{
1824 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1825 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1826 EVENT_INDEX(0));
1827}
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1838{
1839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1840 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1841 WRITE_DATA_DST_SEL(0)));
1842 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1843 amdgpu_ring_write(ring, 0);
1844 amdgpu_ring_write(ring, 0x1);
1845}
1846
1847static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1848 u64 seq, unsigned flags)
1849{
1850 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1851 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1852
1853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1854 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1855 amdgpu_ring_write(ring, 0);
1856 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1857 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1858 PACKET3_TC_ACTION_ENA |
1859 PACKET3_SH_KCACHE_ACTION_ENA |
1860 PACKET3_SH_ICACHE_ACTION_ENA);
1861 amdgpu_ring_write(ring, 0xFFFFFFFF);
1862 amdgpu_ring_write(ring, 0);
1863 amdgpu_ring_write(ring, 10);
1864
1865 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1866 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1867 amdgpu_ring_write(ring, addr & 0xfffffffc);
1868 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1869 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1870 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1871 amdgpu_ring_write(ring, lower_32_bits(seq));
1872 amdgpu_ring_write(ring, upper_32_bits(seq));
1873}
1874
1875static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1876 struct amdgpu_ib *ib,
1877 unsigned vm_id, bool ctx_switch)
1878{
1879 u32 header, control = 0;
1880
1881
1882 if (ctx_switch) {
1883 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1884 amdgpu_ring_write(ring, 0);
1885 }
1886
1887 if (ib->flags & AMDGPU_IB_FLAG_CE)
1888 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1889 else
1890 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1891
1892 control |= ib->length_dw | (vm_id << 24);
1893
1894 amdgpu_ring_write(ring, header);
1895 amdgpu_ring_write(ring,
1896#ifdef __BIG_ENDIAN
1897 (2 << 0) |
1898#endif
1899 (ib->gpu_addr & 0xFFFFFFFC));
1900 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1901 amdgpu_ring_write(ring, control);
1902}
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1914{
1915 struct amdgpu_device *adev = ring->adev;
1916 struct amdgpu_ib ib;
1917 struct dma_fence *f = NULL;
1918 uint32_t scratch;
1919 uint32_t tmp = 0;
1920 long r;
1921
1922 r = amdgpu_gfx_scratch_get(adev, &scratch);
1923 if (r) {
1924 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1925 return r;
1926 }
1927 WREG32(scratch, 0xCAFEDEAD);
1928 memset(&ib, 0, sizeof(ib));
1929 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1930 if (r) {
1931 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1932 goto err1;
1933 }
1934 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1935 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1936 ib.ptr[2] = 0xDEADBEEF;
1937 ib.length_dw = 3;
1938
1939 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1940 if (r)
1941 goto err2;
1942
1943 r = dma_fence_wait_timeout(f, false, timeout);
1944 if (r == 0) {
1945 DRM_ERROR("amdgpu: IB test timed out\n");
1946 r = -ETIMEDOUT;
1947 goto err2;
1948 } else if (r < 0) {
1949 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1950 goto err2;
1951 }
1952 tmp = RREG32(scratch);
1953 if (tmp == 0xDEADBEEF) {
1954 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1955 r = 0;
1956 } else {
1957 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1958 scratch, tmp);
1959 r = -EINVAL;
1960 }
1961
1962err2:
1963 amdgpu_ib_free(adev, &ib, NULL);
1964 dma_fence_put(f);
1965err1:
1966 amdgpu_gfx_scratch_free(adev, scratch);
1967 return r;
1968}
1969
1970static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1971{
1972 int i;
1973 if (enable) {
1974 WREG32(mmCP_ME_CNTL, 0);
1975 } else {
1976 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1977 CP_ME_CNTL__PFP_HALT_MASK |
1978 CP_ME_CNTL__CE_HALT_MASK));
1979 WREG32(mmSCRATCH_UMSK, 0);
1980 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1981 adev->gfx.gfx_ring[i].ready = false;
1982 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1983 adev->gfx.compute_ring[i].ready = false;
1984 }
1985 udelay(50);
1986}
1987
1988static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1989{
1990 unsigned i;
1991 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1992 const struct gfx_firmware_header_v1_0 *ce_hdr;
1993 const struct gfx_firmware_header_v1_0 *me_hdr;
1994 const __le32 *fw_data;
1995 u32 fw_size;
1996
1997 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1998 return -EINVAL;
1999
2000 gfx_v6_0_cp_gfx_enable(adev, false);
2001 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2002 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2003 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2004
2005 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2006 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2007 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2008
2009
2010 fw_data = (const __le32 *)
2011 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2012 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2013 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2014 for (i = 0; i < fw_size; i++)
2015 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2016 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2017
2018
2019 fw_data = (const __le32 *)
2020 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2021 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2022 WREG32(mmCP_CE_UCODE_ADDR, 0);
2023 for (i = 0; i < fw_size; i++)
2024 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2025 WREG32(mmCP_CE_UCODE_ADDR, 0);
2026
2027
2028 fw_data = (const __be32 *)
2029 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2030 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2031 WREG32(mmCP_ME_RAM_WADDR, 0);
2032 for (i = 0; i < fw_size; i++)
2033 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2034 WREG32(mmCP_ME_RAM_WADDR, 0);
2035
2036 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2037 WREG32(mmCP_CE_UCODE_ADDR, 0);
2038 WREG32(mmCP_ME_RAM_WADDR, 0);
2039 WREG32(mmCP_ME_RAM_RADDR, 0);
2040 return 0;
2041}
2042
2043static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2044{
2045 const struct cs_section_def *sect = NULL;
2046 const struct cs_extent_def *ext = NULL;
2047 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2048 int r, i;
2049
2050 r = amdgpu_ring_alloc(ring, 7 + 4);
2051 if (r) {
2052 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2053 return r;
2054 }
2055 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2056 amdgpu_ring_write(ring, 0x1);
2057 amdgpu_ring_write(ring, 0x0);
2058 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2059 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2060 amdgpu_ring_write(ring, 0);
2061 amdgpu_ring_write(ring, 0);
2062
2063 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2064 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2065 amdgpu_ring_write(ring, 0xc000);
2066 amdgpu_ring_write(ring, 0xe000);
2067 amdgpu_ring_commit(ring);
2068
2069 gfx_v6_0_cp_gfx_enable(adev, true);
2070
2071 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2072 if (r) {
2073 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2074 return r;
2075 }
2076
2077 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2078 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2079
2080 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2081 for (ext = sect->section; ext->extent != NULL; ++ext) {
2082 if (sect->id == SECT_CONTEXT) {
2083 amdgpu_ring_write(ring,
2084 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2085 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2086 for (i = 0; i < ext->reg_count; i++)
2087 amdgpu_ring_write(ring, ext->extent[i]);
2088 }
2089 }
2090 }
2091
2092 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2093 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2094
2095 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2096 amdgpu_ring_write(ring, 0);
2097
2098 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2099 amdgpu_ring_write(ring, 0x00000316);
2100 amdgpu_ring_write(ring, 0x0000000e);
2101 amdgpu_ring_write(ring, 0x00000010);
2102
2103 amdgpu_ring_commit(ring);
2104
2105 return 0;
2106}
2107
2108static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2109{
2110 struct amdgpu_ring *ring;
2111 u32 tmp;
2112 u32 rb_bufsz;
2113 int r;
2114 u64 rptr_addr;
2115
2116 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2117 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2118
2119
2120 WREG32(mmCP_RB_WPTR_DELAY, 0);
2121
2122 WREG32(mmCP_DEBUG, 0);
2123 WREG32(mmSCRATCH_ADDR, 0);
2124
2125
2126
2127 ring = &adev->gfx.gfx_ring[0];
2128 rb_bufsz = order_base_2(ring->ring_size / 8);
2129 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2130
2131#ifdef __BIG_ENDIAN
2132 tmp |= BUF_SWAP_32BIT;
2133#endif
2134 WREG32(mmCP_RB0_CNTL, tmp);
2135
2136
2137 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2138 ring->wptr = 0;
2139 WREG32(mmCP_RB0_WPTR, ring->wptr);
2140
2141
2142 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2143 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2144 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2145
2146 WREG32(mmSCRATCH_UMSK, 0);
2147
2148 mdelay(1);
2149 WREG32(mmCP_RB0_CNTL, tmp);
2150
2151 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2152
2153
2154 gfx_v6_0_cp_gfx_start(adev);
2155 ring->ready = true;
2156 r = amdgpu_ring_test_ring(ring);
2157 if (r) {
2158 ring->ready = false;
2159 return r;
2160 }
2161
2162 return 0;
2163}
2164
2165static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2166{
2167 return ring->adev->wb.wb[ring->rptr_offs];
2168}
2169
2170static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2171{
2172 struct amdgpu_device *adev = ring->adev;
2173
2174 if (ring == &adev->gfx.gfx_ring[0])
2175 return RREG32(mmCP_RB0_WPTR);
2176 else if (ring == &adev->gfx.compute_ring[0])
2177 return RREG32(mmCP_RB1_WPTR);
2178 else if (ring == &adev->gfx.compute_ring[1])
2179 return RREG32(mmCP_RB2_WPTR);
2180 else
2181 BUG();
2182}
2183
2184static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2185{
2186 struct amdgpu_device *adev = ring->adev;
2187
2188 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2189 (void)RREG32(mmCP_RB0_WPTR);
2190}
2191
2192static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2193{
2194 struct amdgpu_device *adev = ring->adev;
2195
2196 if (ring == &adev->gfx.compute_ring[0]) {
2197 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2198 (void)RREG32(mmCP_RB1_WPTR);
2199 } else if (ring == &adev->gfx.compute_ring[1]) {
2200 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2201 (void)RREG32(mmCP_RB2_WPTR);
2202 } else {
2203 BUG();
2204 }
2205
2206}
2207
2208static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2209{
2210 struct amdgpu_ring *ring;
2211 u32 tmp;
2212 u32 rb_bufsz;
2213 int i, r;
2214 u64 rptr_addr;
2215
2216
2217
2218
2219 ring = &adev->gfx.compute_ring[0];
2220 rb_bufsz = order_base_2(ring->ring_size / 8);
2221 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2222#ifdef __BIG_ENDIAN
2223 tmp |= BUF_SWAP_32BIT;
2224#endif
2225 WREG32(mmCP_RB1_CNTL, tmp);
2226
2227 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2228 ring->wptr = 0;
2229 WREG32(mmCP_RB1_WPTR, ring->wptr);
2230
2231 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2232 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2233 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2234
2235 mdelay(1);
2236 WREG32(mmCP_RB1_CNTL, tmp);
2237 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2238
2239 ring = &adev->gfx.compute_ring[1];
2240 rb_bufsz = order_base_2(ring->ring_size / 8);
2241 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2242#ifdef __BIG_ENDIAN
2243 tmp |= BUF_SWAP_32BIT;
2244#endif
2245 WREG32(mmCP_RB2_CNTL, tmp);
2246
2247 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2248 ring->wptr = 0;
2249 WREG32(mmCP_RB2_WPTR, ring->wptr);
2250 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2251 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2252 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2253
2254 mdelay(1);
2255 WREG32(mmCP_RB2_CNTL, tmp);
2256 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2257
2258 adev->gfx.compute_ring[0].ready = false;
2259 adev->gfx.compute_ring[1].ready = false;
2260
2261 for (i = 0; i < 2; i++) {
2262 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2263 if (r)
2264 return r;
2265 adev->gfx.compute_ring[i].ready = true;
2266 }
2267
2268 return 0;
2269}
2270
2271static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2272{
2273 gfx_v6_0_cp_gfx_enable(adev, enable);
2274}
2275
2276static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2277{
2278 return gfx_v6_0_cp_gfx_load_microcode(adev);
2279}
2280
2281static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2282 bool enable)
2283{
2284 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2285 u32 mask;
2286 int i;
2287
2288 if (enable)
2289 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2290 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2291 else
2292 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2293 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2294 WREG32(mmCP_INT_CNTL_RING0, tmp);
2295
2296 if (!enable) {
2297
2298 tmp = RREG32(mmDB_DEPTH_INFO);
2299
2300 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2301 for (i = 0; i < adev->usec_timeout; i++) {
2302 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2303 break;
2304 udelay(1);
2305 }
2306 }
2307}
2308
2309static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2310{
2311 int r;
2312
2313 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2314
2315 r = gfx_v6_0_cp_load_microcode(adev);
2316 if (r)
2317 return r;
2318
2319 r = gfx_v6_0_cp_gfx_resume(adev);
2320 if (r)
2321 return r;
2322 r = gfx_v6_0_cp_compute_resume(adev);
2323 if (r)
2324 return r;
2325
2326 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2327
2328 return 0;
2329}
2330
2331static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2332{
2333 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2334 uint32_t seq = ring->fence_drv.sync_seq;
2335 uint64_t addr = ring->fence_drv.gpu_addr;
2336
2337 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2338 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) |
2339 WAIT_REG_MEM_FUNCTION(3) |
2340 WAIT_REG_MEM_ENGINE(usepfp)));
2341 amdgpu_ring_write(ring, addr & 0xfffffffc);
2342 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2343 amdgpu_ring_write(ring, seq);
2344 amdgpu_ring_write(ring, 0xffffffff);
2345 amdgpu_ring_write(ring, 4);
2346
2347 if (usepfp) {
2348
2349 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2350 amdgpu_ring_write(ring, 0);
2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2352 amdgpu_ring_write(ring, 0);
2353 }
2354}
2355
2356static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2357 unsigned vm_id, uint64_t pd_addr)
2358{
2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2360
2361
2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2364 WRITE_DATA_DST_SEL(0)));
2365 if (vm_id < 8) {
2366 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2367 } else {
2368 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2369 }
2370 amdgpu_ring_write(ring, 0);
2371 amdgpu_ring_write(ring, pd_addr >> 12);
2372
2373
2374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2375 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2376 WRITE_DATA_DST_SEL(0)));
2377 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2378 amdgpu_ring_write(ring, 0);
2379 amdgpu_ring_write(ring, 1 << vm_id);
2380
2381
2382 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2383 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |
2384 WAIT_REG_MEM_ENGINE(0)));
2385 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2386 amdgpu_ring_write(ring, 0);
2387 amdgpu_ring_write(ring, 0);
2388 amdgpu_ring_write(ring, 0);
2389 amdgpu_ring_write(ring, 0x20);
2390
2391 if (usepfp) {
2392
2393 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2394 amdgpu_ring_write(ring, 0x0);
2395
2396
2397 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2398 amdgpu_ring_write(ring, 0);
2399 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2400 amdgpu_ring_write(ring, 0);
2401 }
2402}
2403
2404
2405static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2406{
2407 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2408 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2409 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2410}
2411
2412static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2413{
2414 const u32 *src_ptr;
2415 volatile u32 *dst_ptr;
2416 u32 dws, i;
2417 u64 reg_list_mc_addr;
2418 const struct cs_section_def *cs_data;
2419 int r;
2420
2421 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2422 adev->gfx.rlc.reg_list_size =
2423 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2424
2425 adev->gfx.rlc.cs_data = si_cs_data;
2426 src_ptr = adev->gfx.rlc.reg_list;
2427 dws = adev->gfx.rlc.reg_list_size;
2428 cs_data = adev->gfx.rlc.cs_data;
2429
2430 if (src_ptr) {
2431
2432 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2433 AMDGPU_GEM_DOMAIN_VRAM,
2434 &adev->gfx.rlc.save_restore_obj,
2435 &adev->gfx.rlc.save_restore_gpu_addr,
2436 (void **)&adev->gfx.rlc.sr_ptr);
2437 if (r) {
2438 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2439 r);
2440 gfx_v6_0_rlc_fini(adev);
2441 return r;
2442 }
2443
2444
2445 dst_ptr = adev->gfx.rlc.sr_ptr;
2446 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2447 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2448
2449 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2450 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2451 }
2452
2453 if (cs_data) {
2454
2455 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2456 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2457
2458 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2459 AMDGPU_GEM_DOMAIN_VRAM,
2460 &adev->gfx.rlc.clear_state_obj,
2461 &adev->gfx.rlc.clear_state_gpu_addr,
2462 (void **)&adev->gfx.rlc.cs_ptr);
2463 if (r) {
2464 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2465 gfx_v6_0_rlc_fini(adev);
2466 return r;
2467 }
2468
2469
2470 dst_ptr = adev->gfx.rlc.cs_ptr;
2471 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2472 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2473 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2474 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2475 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2476 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2477 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2478 }
2479
2480 return 0;
2481}
2482
2483static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2484{
2485 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2486
2487 if (!enable) {
2488 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2489 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2490 }
2491}
2492
2493static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2494{
2495 int i;
2496
2497 for (i = 0; i < adev->usec_timeout; i++) {
2498 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2499 break;
2500 udelay(1);
2501 }
2502
2503 for (i = 0; i < adev->usec_timeout; i++) {
2504 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2505 break;
2506 udelay(1);
2507 }
2508}
2509
2510static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2511{
2512 u32 tmp;
2513
2514 tmp = RREG32(mmRLC_CNTL);
2515 if (tmp != rlc)
2516 WREG32(mmRLC_CNTL, rlc);
2517}
2518
2519static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2520{
2521 u32 data, orig;
2522
2523 orig = data = RREG32(mmRLC_CNTL);
2524
2525 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2526 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2527 WREG32(mmRLC_CNTL, data);
2528
2529 gfx_v6_0_wait_for_rlc_serdes(adev);
2530 }
2531
2532 return orig;
2533}
2534
2535static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2536{
2537 WREG32(mmRLC_CNTL, 0);
2538
2539 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2540 gfx_v6_0_wait_for_rlc_serdes(adev);
2541}
2542
2543static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2544{
2545 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2546
2547 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2548
2549 udelay(50);
2550}
2551
2552static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2553{
2554 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2555 udelay(50);
2556 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2557 udelay(50);
2558}
2559
2560static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2561{
2562 u32 tmp;
2563
2564
2565 tmp = RREG32(mmMC_SEQ_MISC0);
2566 if ((tmp & 0xF0000000) == 0xB0000000)
2567 return true;
2568 return false;
2569}
2570
2571static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2572{
2573}
2574
2575static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2576{
2577 u32 i;
2578 const struct rlc_firmware_header_v1_0 *hdr;
2579 const __le32 *fw_data;
2580 u32 fw_size;
2581
2582
2583 if (!adev->gfx.rlc_fw)
2584 return -EINVAL;
2585
2586 gfx_v6_0_rlc_stop(adev);
2587 gfx_v6_0_rlc_reset(adev);
2588 gfx_v6_0_init_pg(adev);
2589 gfx_v6_0_init_cg(adev);
2590
2591 WREG32(mmRLC_RL_BASE, 0);
2592 WREG32(mmRLC_RL_SIZE, 0);
2593 WREG32(mmRLC_LB_CNTL, 0);
2594 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2595 WREG32(mmRLC_LB_CNTR_INIT, 0);
2596 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2597
2598 WREG32(mmRLC_MC_CNTL, 0);
2599 WREG32(mmRLC_UCODE_CNTL, 0);
2600
2601 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2602 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2603 fw_data = (const __le32 *)
2604 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2605
2606 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2607
2608 for (i = 0; i < fw_size; i++) {
2609 WREG32(mmRLC_UCODE_ADDR, i);
2610 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2611 }
2612 WREG32(mmRLC_UCODE_ADDR, 0);
2613
2614 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2615 gfx_v6_0_rlc_start(adev);
2616
2617 return 0;
2618}
2619
2620static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2621{
2622 u32 data, orig, tmp;
2623
2624 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2625
2626 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2627 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2628
2629 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2630
2631 tmp = gfx_v6_0_halt_rlc(adev);
2632
2633 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2634 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2635 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2636
2637 gfx_v6_0_wait_for_rlc_serdes(adev);
2638 gfx_v6_0_update_rlc(adev, tmp);
2639
2640 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2641
2642 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2643 } else {
2644 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2645
2646 RREG32(mmCB_CGTT_SCLK_CTRL);
2647 RREG32(mmCB_CGTT_SCLK_CTRL);
2648 RREG32(mmCB_CGTT_SCLK_CTRL);
2649 RREG32(mmCB_CGTT_SCLK_CTRL);
2650
2651 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2652 }
2653
2654 if (orig != data)
2655 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2656
2657}
2658
2659static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2660{
2661
2662 u32 data, orig, tmp = 0;
2663
2664 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2665 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2666 data = 0x96940200;
2667 if (orig != data)
2668 WREG32(mmCGTS_SM_CTRL_REG, data);
2669
2670 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2671 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2672 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2673 if (orig != data)
2674 WREG32(mmCP_MEM_SLP_CNTL, data);
2675 }
2676
2677 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2678 data &= 0xffffffc0;
2679 if (orig != data)
2680 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2681
2682 tmp = gfx_v6_0_halt_rlc(adev);
2683
2684 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2685 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2686 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2687
2688 gfx_v6_0_update_rlc(adev, tmp);
2689 } else {
2690 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2691 data |= 0x00000003;
2692 if (orig != data)
2693 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2694
2695 data = RREG32(mmCP_MEM_SLP_CNTL);
2696 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2697 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2698 WREG32(mmCP_MEM_SLP_CNTL, data);
2699 }
2700 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2701 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2702 if (orig != data)
2703 WREG32(mmCGTS_SM_CTRL_REG, data);
2704
2705 tmp = gfx_v6_0_halt_rlc(adev);
2706
2707 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2708 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2709 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2710
2711 gfx_v6_0_update_rlc(adev, tmp);
2712 }
2713}
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2731 bool enable)
2732{
2733}
2734
2735static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2736 bool enable)
2737{
2738}
2739
2740static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2741{
2742 u32 data, orig;
2743
2744 orig = data = RREG32(mmRLC_PG_CNTL);
2745 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2746 data &= ~0x8000;
2747 else
2748 data |= 0x8000;
2749 if (orig != data)
2750 WREG32(mmRLC_PG_CNTL, data);
2751}
2752
2753static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2754{
2755}
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2825 bool enable)
2826{
2827 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2828 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2829 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2830 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2831 } else {
2832 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2833 (void)RREG32(mmDB_RENDER_CONTROL);
2834 }
2835}
2836
2837static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2838{
2839 u32 tmp;
2840
2841 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2842
2843 tmp = RREG32(mmRLC_MAX_PG_CU);
2844 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2845 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2846 WREG32(mmRLC_MAX_PG_CU, tmp);
2847}
2848
2849static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2850 bool enable)
2851{
2852 u32 data, orig;
2853
2854 orig = data = RREG32(mmRLC_PG_CNTL);
2855 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2856 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2857 else
2858 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2859 if (orig != data)
2860 WREG32(mmRLC_PG_CNTL, data);
2861}
2862
2863static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2864 bool enable)
2865{
2866 u32 data, orig;
2867
2868 orig = data = RREG32(mmRLC_PG_CNTL);
2869 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2870 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2871 else
2872 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2873 if (orig != data)
2874 WREG32(mmRLC_PG_CNTL, data);
2875}
2876
2877static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2878{
2879 u32 tmp;
2880
2881 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2882 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2883 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2884
2885 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2886 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2887 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2888 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2889 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2890}
2891
2892static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2893{
2894 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2895 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2896 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2897}
2898
2899static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2900{
2901 u32 count = 0;
2902 const struct cs_section_def *sect = NULL;
2903 const struct cs_extent_def *ext = NULL;
2904
2905 if (adev->gfx.rlc.cs_data == NULL)
2906 return 0;
2907
2908
2909 count += 2;
2910
2911 count += 3;
2912
2913 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2914 for (ext = sect->section; ext->extent != NULL; ++ext) {
2915 if (sect->id == SECT_CONTEXT)
2916 count += 2 + ext->reg_count;
2917 else
2918 return 0;
2919 }
2920 }
2921
2922 count += 3;
2923
2924 count += 2;
2925
2926 count += 2;
2927
2928 return count;
2929}
2930
2931static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2932 volatile u32 *buffer)
2933{
2934 u32 count = 0, i;
2935 const struct cs_section_def *sect = NULL;
2936 const struct cs_extent_def *ext = NULL;
2937
2938 if (adev->gfx.rlc.cs_data == NULL)
2939 return;
2940 if (buffer == NULL)
2941 return;
2942
2943 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2944 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2945 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2946 buffer[count++] = cpu_to_le32(0x80000000);
2947 buffer[count++] = cpu_to_le32(0x80000000);
2948
2949 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2950 for (ext = sect->section; ext->extent != NULL; ++ext) {
2951 if (sect->id == SECT_CONTEXT) {
2952 buffer[count++] =
2953 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2954 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2955 for (i = 0; i < ext->reg_count; i++)
2956 buffer[count++] = cpu_to_le32(ext->extent[i]);
2957 } else {
2958 return;
2959 }
2960 }
2961 }
2962
2963 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2964 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2965
2966 switch (adev->asic_type) {
2967 case CHIP_TAHITI:
2968 case CHIP_PITCAIRN:
2969 buffer[count++] = cpu_to_le32(0x2a00126a);
2970 break;
2971 case CHIP_VERDE:
2972 buffer[count++] = cpu_to_le32(0x0000124a);
2973 break;
2974 case CHIP_OLAND:
2975 buffer[count++] = cpu_to_le32(0x00000082);
2976 break;
2977 case CHIP_HAINAN:
2978 buffer[count++] = cpu_to_le32(0x00000000);
2979 break;
2980 default:
2981 buffer[count++] = cpu_to_le32(0x00000000);
2982 break;
2983 }
2984
2985 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2986 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2987
2988 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2989 buffer[count++] = cpu_to_le32(0);
2990}
2991
2992static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2993{
2994 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2995 AMD_PG_SUPPORT_GFX_SMG |
2996 AMD_PG_SUPPORT_GFX_DMG |
2997 AMD_PG_SUPPORT_CP |
2998 AMD_PG_SUPPORT_GDS |
2999 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3000 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
3001 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
3002 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3003 gfx_v6_0_init_gfx_cgpg(adev);
3004 gfx_v6_0_enable_cp_pg(adev, true);
3005 gfx_v6_0_enable_gds_pg(adev, true);
3006 } else {
3007 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3008 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3009
3010 }
3011 gfx_v6_0_init_ao_cu_mask(adev);
3012 gfx_v6_0_update_gfx_pg(adev, true);
3013 } else {
3014
3015 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3016 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3017 }
3018}
3019
3020static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
3021{
3022 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3023 AMD_PG_SUPPORT_GFX_SMG |
3024 AMD_PG_SUPPORT_GFX_DMG |
3025 AMD_PG_SUPPORT_CP |
3026 AMD_PG_SUPPORT_GDS |
3027 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3028 gfx_v6_0_update_gfx_pg(adev, false);
3029 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3030 gfx_v6_0_enable_cp_pg(adev, false);
3031 gfx_v6_0_enable_gds_pg(adev, false);
3032 }
3033 }
3034}
3035
3036static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3037{
3038 uint64_t clock;
3039
3040 mutex_lock(&adev->gfx.gpu_clock_mutex);
3041 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3042 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3043 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3044 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3045 return clock;
3046}
3047
3048static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3049{
3050 if (flags & AMDGPU_HAVE_CTX_SWITCH)
3051 gfx_v6_0_ring_emit_vgt_flush(ring);
3052 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3053 amdgpu_ring_write(ring, 0x80000000);
3054 amdgpu_ring_write(ring, 0);
3055}
3056
3057
3058static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3059{
3060 WREG32(mmSQ_IND_INDEX,
3061 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3062 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3063 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3064 (SQ_IND_INDEX__FORCE_READ_MASK));
3065 return RREG32(mmSQ_IND_DATA);
3066}
3067
3068static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3069 uint32_t wave, uint32_t thread,
3070 uint32_t regno, uint32_t num, uint32_t *out)
3071{
3072 WREG32(mmSQ_IND_INDEX,
3073 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3074 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3075 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3076 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3077 (SQ_IND_INDEX__FORCE_READ_MASK) |
3078 (SQ_IND_INDEX__AUTO_INCR_MASK));
3079 while (num--)
3080 *(out++) = RREG32(mmSQ_IND_DATA);
3081}
3082
3083static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3084{
3085
3086 dst[(*no_fields)++] = 0;
3087 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3088 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3089 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3091 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3092 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3093 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3094 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3096 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3097 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3098 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3099 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3100 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3101 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3104 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3105}
3106
3107static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3108 uint32_t wave, uint32_t start,
3109 uint32_t size, uint32_t *dst)
3110{
3111 wave_read_regs(
3112 adev, simd, wave, 0,
3113 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3114}
3115
3116static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3117 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3118 .select_se_sh = &gfx_v6_0_select_se_sh,
3119 .read_wave_data = &gfx_v6_0_read_wave_data,
3120 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3121};
3122
3123static int gfx_v6_0_early_init(void *handle)
3124{
3125 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3126
3127 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3128 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3129 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3130 gfx_v6_0_set_ring_funcs(adev);
3131 gfx_v6_0_set_irq_funcs(adev);
3132
3133 return 0;
3134}
3135
3136static int gfx_v6_0_sw_init(void *handle)
3137{
3138 struct amdgpu_ring *ring;
3139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3140 int i, r;
3141
3142 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3143 if (r)
3144 return r;
3145
3146 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3147 if (r)
3148 return r;
3149
3150 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3151 if (r)
3152 return r;
3153
3154 gfx_v6_0_scratch_init(adev);
3155
3156 r = gfx_v6_0_init_microcode(adev);
3157 if (r) {
3158 DRM_ERROR("Failed to load gfx firmware!\n");
3159 return r;
3160 }
3161
3162 r = gfx_v6_0_rlc_init(adev);
3163 if (r) {
3164 DRM_ERROR("Failed to init rlc BOs!\n");
3165 return r;
3166 }
3167
3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3169 ring = &adev->gfx.gfx_ring[i];
3170 ring->ring_obj = NULL;
3171 sprintf(ring->name, "gfx");
3172 r = amdgpu_ring_init(adev, ring, 1024,
3173 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3174 if (r)
3175 return r;
3176 }
3177
3178 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3179 unsigned irq_type;
3180
3181 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3182 DRM_ERROR("Too many (%d) compute rings!\n", i);
3183 break;
3184 }
3185 ring = &adev->gfx.compute_ring[i];
3186 ring->ring_obj = NULL;
3187 ring->use_doorbell = false;
3188 ring->doorbell_index = 0;
3189 ring->me = 1;
3190 ring->pipe = i;
3191 ring->queue = i;
3192 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3193 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3194 r = amdgpu_ring_init(adev, ring, 1024,
3195 &adev->gfx.eop_irq, irq_type);
3196 if (r)
3197 return r;
3198 }
3199
3200 return r;
3201}
3202
3203static int gfx_v6_0_sw_fini(void *handle)
3204{
3205 int i;
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3207
3208 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3209 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3210 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3211 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3212
3213 gfx_v6_0_rlc_fini(adev);
3214
3215 return 0;
3216}
3217
3218static int gfx_v6_0_hw_init(void *handle)
3219{
3220 int r;
3221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3222
3223 gfx_v6_0_gpu_init(adev);
3224
3225 r = gfx_v6_0_rlc_resume(adev);
3226 if (r)
3227 return r;
3228
3229 r = gfx_v6_0_cp_resume(adev);
3230 if (r)
3231 return r;
3232
3233 adev->gfx.ce_ram_size = 0x8000;
3234
3235 return r;
3236}
3237
3238static int gfx_v6_0_hw_fini(void *handle)
3239{
3240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3241
3242 gfx_v6_0_cp_enable(adev, false);
3243 gfx_v6_0_rlc_stop(adev);
3244 gfx_v6_0_fini_pg(adev);
3245
3246 return 0;
3247}
3248
3249static int gfx_v6_0_suspend(void *handle)
3250{
3251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3252
3253 return gfx_v6_0_hw_fini(adev);
3254}
3255
3256static int gfx_v6_0_resume(void *handle)
3257{
3258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3259
3260 return gfx_v6_0_hw_init(adev);
3261}
3262
3263static bool gfx_v6_0_is_idle(void *handle)
3264{
3265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3266
3267 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3268 return false;
3269 else
3270 return true;
3271}
3272
3273static int gfx_v6_0_wait_for_idle(void *handle)
3274{
3275 unsigned i;
3276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3277
3278 for (i = 0; i < adev->usec_timeout; i++) {
3279 if (gfx_v6_0_is_idle(handle))
3280 return 0;
3281 udelay(1);
3282 }
3283 return -ETIMEDOUT;
3284}
3285
3286static int gfx_v6_0_soft_reset(void *handle)
3287{
3288 return 0;
3289}
3290
3291static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3292 enum amdgpu_interrupt_state state)
3293{
3294 u32 cp_int_cntl;
3295
3296 switch (state) {
3297 case AMDGPU_IRQ_STATE_DISABLE:
3298 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3299 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3300 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3301 break;
3302 case AMDGPU_IRQ_STATE_ENABLE:
3303 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3304 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3305 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3306 break;
3307 default:
3308 break;
3309 }
3310}
3311
3312static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3313 int ring,
3314 enum amdgpu_interrupt_state state)
3315{
3316 u32 cp_int_cntl;
3317 switch (state){
3318 case AMDGPU_IRQ_STATE_DISABLE:
3319 if (ring == 0) {
3320 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3321 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3322 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3323 break;
3324 } else {
3325 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3326 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3327 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3328 break;
3329
3330 }
3331 case AMDGPU_IRQ_STATE_ENABLE:
3332 if (ring == 0) {
3333 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3334 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3335 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3336 break;
3337 } else {
3338 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3339 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3340 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3341 break;
3342
3343 }
3344
3345 default:
3346 BUG();
3347 break;
3348
3349 }
3350}
3351
3352static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3353 struct amdgpu_irq_src *src,
3354 unsigned type,
3355 enum amdgpu_interrupt_state state)
3356{
3357 u32 cp_int_cntl;
3358
3359 switch (state) {
3360 case AMDGPU_IRQ_STATE_DISABLE:
3361 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3362 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3363 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3364 break;
3365 case AMDGPU_IRQ_STATE_ENABLE:
3366 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3367 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3368 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3369 break;
3370 default:
3371 break;
3372 }
3373
3374 return 0;
3375}
3376
3377static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3378 struct amdgpu_irq_src *src,
3379 unsigned type,
3380 enum amdgpu_interrupt_state state)
3381{
3382 u32 cp_int_cntl;
3383
3384 switch (state) {
3385 case AMDGPU_IRQ_STATE_DISABLE:
3386 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3387 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3388 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3389 break;
3390 case AMDGPU_IRQ_STATE_ENABLE:
3391 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3392 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3393 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3394 break;
3395 default:
3396 break;
3397 }
3398
3399 return 0;
3400}
3401
3402static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3403 struct amdgpu_irq_src *src,
3404 unsigned type,
3405 enum amdgpu_interrupt_state state)
3406{
3407 switch (type) {
3408 case AMDGPU_CP_IRQ_GFX_EOP:
3409 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3410 break;
3411 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3412 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3413 break;
3414 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3415 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3416 break;
3417 default:
3418 break;
3419 }
3420 return 0;
3421}
3422
3423static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3424 struct amdgpu_irq_src *source,
3425 struct amdgpu_iv_entry *entry)
3426{
3427 switch (entry->ring_id) {
3428 case 0:
3429 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3430 break;
3431 case 1:
3432 case 2:
3433 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3434 break;
3435 default:
3436 break;
3437 }
3438 return 0;
3439}
3440
3441static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3442 struct amdgpu_irq_src *source,
3443 struct amdgpu_iv_entry *entry)
3444{
3445 DRM_ERROR("Illegal register access in command stream\n");
3446 schedule_work(&adev->reset_work);
3447 return 0;
3448}
3449
3450static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3451 struct amdgpu_irq_src *source,
3452 struct amdgpu_iv_entry *entry)
3453{
3454 DRM_ERROR("Illegal instruction in command stream\n");
3455 schedule_work(&adev->reset_work);
3456 return 0;
3457}
3458
3459static int gfx_v6_0_set_clockgating_state(void *handle,
3460 enum amd_clockgating_state state)
3461{
3462 bool gate = false;
3463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3464
3465 if (state == AMD_CG_STATE_GATE)
3466 gate = true;
3467
3468 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3469 if (gate) {
3470 gfx_v6_0_enable_mgcg(adev, true);
3471 gfx_v6_0_enable_cgcg(adev, true);
3472 } else {
3473 gfx_v6_0_enable_cgcg(adev, false);
3474 gfx_v6_0_enable_mgcg(adev, false);
3475 }
3476 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3477
3478 return 0;
3479}
3480
3481static int gfx_v6_0_set_powergating_state(void *handle,
3482 enum amd_powergating_state state)
3483{
3484 bool gate = false;
3485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3486
3487 if (state == AMD_PG_STATE_GATE)
3488 gate = true;
3489
3490 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3491 AMD_PG_SUPPORT_GFX_SMG |
3492 AMD_PG_SUPPORT_GFX_DMG |
3493 AMD_PG_SUPPORT_CP |
3494 AMD_PG_SUPPORT_GDS |
3495 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3496 gfx_v6_0_update_gfx_pg(adev, gate);
3497 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3498 gfx_v6_0_enable_cp_pg(adev, gate);
3499 gfx_v6_0_enable_gds_pg(adev, gate);
3500 }
3501 }
3502
3503 return 0;
3504}
3505
3506static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3507 .name = "gfx_v6_0",
3508 .early_init = gfx_v6_0_early_init,
3509 .late_init = NULL,
3510 .sw_init = gfx_v6_0_sw_init,
3511 .sw_fini = gfx_v6_0_sw_fini,
3512 .hw_init = gfx_v6_0_hw_init,
3513 .hw_fini = gfx_v6_0_hw_fini,
3514 .suspend = gfx_v6_0_suspend,
3515 .resume = gfx_v6_0_resume,
3516 .is_idle = gfx_v6_0_is_idle,
3517 .wait_for_idle = gfx_v6_0_wait_for_idle,
3518 .soft_reset = gfx_v6_0_soft_reset,
3519 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3520 .set_powergating_state = gfx_v6_0_set_powergating_state,
3521};
3522
3523static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3524 .type = AMDGPU_RING_TYPE_GFX,
3525 .align_mask = 0xff,
3526 .nop = 0x80000000,
3527 .support_64bit_ptrs = false,
3528 .get_rptr = gfx_v6_0_ring_get_rptr,
3529 .get_wptr = gfx_v6_0_ring_get_wptr,
3530 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3531 .emit_frame_size =
3532 5 +
3533 5 +
3534 14 + 14 + 14 +
3535 7 + 4 +
3536 17 + 6 +
3537 3 + 2,
3538 .emit_ib_size = 6,
3539 .emit_ib = gfx_v6_0_ring_emit_ib,
3540 .emit_fence = gfx_v6_0_ring_emit_fence,
3541 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3542 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3543 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3544 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3545 .test_ring = gfx_v6_0_ring_test_ring,
3546 .test_ib = gfx_v6_0_ring_test_ib,
3547 .insert_nop = amdgpu_ring_insert_nop,
3548 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3549};
3550
3551static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3552 .type = AMDGPU_RING_TYPE_COMPUTE,
3553 .align_mask = 0xff,
3554 .nop = 0x80000000,
3555 .get_rptr = gfx_v6_0_ring_get_rptr,
3556 .get_wptr = gfx_v6_0_ring_get_wptr,
3557 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3558 .emit_frame_size =
3559 5 +
3560 5 +
3561 7 +
3562 17 +
3563 14 + 14 + 14,
3564 .emit_ib_size = 6,
3565 .emit_ib = gfx_v6_0_ring_emit_ib,
3566 .emit_fence = gfx_v6_0_ring_emit_fence,
3567 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3568 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3569 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3570 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3571 .test_ring = gfx_v6_0_ring_test_ring,
3572 .test_ib = gfx_v6_0_ring_test_ib,
3573 .insert_nop = amdgpu_ring_insert_nop,
3574};
3575
3576static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3577{
3578 int i;
3579
3580 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3581 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3582 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3583 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3584}
3585
3586static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3587 .set = gfx_v6_0_set_eop_interrupt_state,
3588 .process = gfx_v6_0_eop_irq,
3589};
3590
3591static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3592 .set = gfx_v6_0_set_priv_reg_fault_state,
3593 .process = gfx_v6_0_priv_reg_irq,
3594};
3595
3596static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3597 .set = gfx_v6_0_set_priv_inst_fault_state,
3598 .process = gfx_v6_0_priv_inst_irq,
3599};
3600
3601static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3602{
3603 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3604 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3605
3606 adev->gfx.priv_reg_irq.num_types = 1;
3607 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3608
3609 adev->gfx.priv_inst_irq.num_types = 1;
3610 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3611}
3612
3613static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3614{
3615 int i, j, k, counter, active_cu_number = 0;
3616 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3617 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3618 unsigned disable_masks[4 * 2];
3619 u32 ao_cu_num;
3620
3621 if (adev->flags & AMD_IS_APU)
3622 ao_cu_num = 2;
3623 else
3624 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3625
3626 memset(cu_info, 0, sizeof(*cu_info));
3627
3628 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3629
3630 mutex_lock(&adev->grbm_idx_mutex);
3631 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3632 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3633 mask = 1;
3634 ao_bitmap = 0;
3635 counter = 0;
3636 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3637 if (i < 4 && j < 2)
3638 gfx_v6_0_set_user_cu_inactive_bitmap(
3639 adev, disable_masks[i * 2 + j]);
3640 bitmap = gfx_v6_0_get_cu_enabled(adev);
3641 cu_info->bitmap[i][j] = bitmap;
3642
3643 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3644 if (bitmap & mask) {
3645 if (counter < ao_cu_num)
3646 ao_bitmap |= mask;
3647 counter ++;
3648 }
3649 mask <<= 1;
3650 }
3651 active_cu_number += counter;
3652 if (i < 2 && j < 2)
3653 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3654 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3655 }
3656 }
3657
3658 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3659 mutex_unlock(&adev->grbm_idx_mutex);
3660
3661 cu_info->number = active_cu_number;
3662 cu_info->ao_cu_mask = ao_cu_mask;
3663}
3664
3665const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3666{
3667 .type = AMD_IP_BLOCK_TYPE_GFX,
3668 .major = 6,
3669 .minor = 0,
3670 .rev = 0,
3671 .funcs = &gfx_v6_0_ip_funcs,
3672};
3673
