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23#ifndef _HARDWARE_MANAGER_H_
24#define _HARDWARE_MANAGER_H_
25
26
27
28struct pp_hwmgr;
29struct pp_hw_power_state;
30struct pp_power_state;
31enum amd_dpm_forced_level;
32struct PP_TemperatureRange;
33
34
35struct phm_fan_speed_info {
36 uint32_t min_percent;
37 uint32_t max_percent;
38 uint32_t min_rpm;
39 uint32_t max_rpm;
40 bool supports_percent_read;
41 bool supports_percent_write;
42 bool supports_rpm_read;
43 bool supports_rpm_write;
44};
45
46
47enum PHM_AutoThrottleSource
48{
49 PHM_AutoThrottleSource_Thermal,
50 PHM_AutoThrottleSource_External
51};
52
53typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
54
55enum phm_platform_caps {
56 PHM_PlatformCaps_AtomBiosPpV1 = 0,
57 PHM_PlatformCaps_PowerPlaySupport,
58 PHM_PlatformCaps_ACOverdriveSupport,
59 PHM_PlatformCaps_BacklightSupport,
60 PHM_PlatformCaps_ThermalController,
61 PHM_PlatformCaps_BiosPowerSourceControl,
62 PHM_PlatformCaps_DisableVoltageTransition,
63 PHM_PlatformCaps_DisableEngineTransition,
64 PHM_PlatformCaps_DisableMemoryTransition,
65 PHM_PlatformCaps_DynamicPowerManagement,
66 PHM_PlatformCaps_EnableASPML0s,
67 PHM_PlatformCaps_EnableASPML1,
68 PHM_PlatformCaps_OD5inACSupport,
69 PHM_PlatformCaps_OD5inDCSupport,
70 PHM_PlatformCaps_SoftStateOD5,
71 PHM_PlatformCaps_NoOD5Support,
72 PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
73 PHM_PlatformCaps_ActivityReporting,
74 PHM_PlatformCaps_EnableBackbias,
75 PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
76 PHM_PlatformCaps_ShowPowerBudgetWarning,
77 PHM_PlatformCaps_PowerBudgetWaiverAvailable,
78 PHM_PlatformCaps_GFXClockGatingSupport,
79 PHM_PlatformCaps_MMClockGatingSupport,
80 PHM_PlatformCaps_AutomaticDCTransition,
81 PHM_PlatformCaps_GeminiPrimary,
82 PHM_PlatformCaps_MemorySpreadSpectrumSupport,
83 PHM_PlatformCaps_EngineSpreadSpectrumSupport,
84 PHM_PlatformCaps_StepVddc,
85 PHM_PlatformCaps_DynamicPCIEGen2Support,
86 PHM_PlatformCaps_SMC,
87 PHM_PlatformCaps_FaultyInternalThermalReading,
88 PHM_PlatformCaps_EnableVoltageControl,
89 PHM_PlatformCaps_EnableSideportControl,
90 PHM_PlatformCaps_VideoPlaybackEEUNotification,
91 PHM_PlatformCaps_TurnOffPll_ASPML1,
92 PHM_PlatformCaps_EnableHTLinkControl,
93 PHM_PlatformCaps_PerformanceStateOnly,
94 PHM_PlatformCaps_ExclusiveModeAlwaysHigh,
95 PHM_PlatformCaps_DisableMGClockGating,
96 PHM_PlatformCaps_DisableMGCGTSSM,
97 PHM_PlatformCaps_UVDAlwaysHigh,
98 PHM_PlatformCaps_DisablePowerGating,
99 PHM_PlatformCaps_CustomThermalPolicy,
100 PHM_PlatformCaps_StayInBootState,
101 PHM_PlatformCaps_SMCAllowSeparateSWThermalState,
102 PHM_PlatformCaps_MultiUVDStateSupport,
103 PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,
104 PHM_PlatformCaps_EnableMCUHTLinkControl,
105 PHM_PlatformCaps_ABM,
106 PHM_PlatformCaps_KongThermalPolicy,
107 PHM_PlatformCaps_SwitchVDDNB,
108 PHM_PlatformCaps_ULPS,
109 PHM_PlatformCaps_NativeULPS,
110 PHM_PlatformCaps_EnableMVDDControl,
111 PHM_PlatformCaps_ControlVDDCI,
112 PHM_PlatformCaps_DisableDCODT,
113 PHM_PlatformCaps_DynamicACTiming,
114 PHM_PlatformCaps_EnableThermalIntByGPIO,
115 PHM_PlatformCaps_BootStateOnAlert,
116 PHM_PlatformCaps_DontWaitForVBlankOnAlert,
117 PHM_PlatformCaps_Force3DClockSupport,
118 PHM_PlatformCaps_MicrocodeFanControl,
119 PHM_PlatformCaps_AdjustUVDPriorityForSP,
120 PHM_PlatformCaps_DisableLightSleep,
121 PHM_PlatformCaps_DisableMCLS,
122 PHM_PlatformCaps_RegulatorHot,
123 PHM_PlatformCaps_BACO,
124 PHM_PlatformCaps_DisableDPM,
125 PHM_PlatformCaps_DynamicM3Arbiter,
126 PHM_PlatformCaps_SclkDeepSleep,
127 PHM_PlatformCaps_DynamicPatchPowerState,
128 PHM_PlatformCaps_ThermalAutoThrottling,
129 PHM_PlatformCaps_SumoThermalPolicy,
130 PHM_PlatformCaps_PCIEPerformanceRequest,
131 PHM_PlatformCaps_BLControlledByGPU,
132 PHM_PlatformCaps_PowerContainment,
133 PHM_PlatformCaps_SQRamping,
134 PHM_PlatformCaps_CAC,
135 PHM_PlatformCaps_NIChipsets,
136 PHM_PlatformCaps_TrinityChipsets,
137 PHM_PlatformCaps_EvergreenChipsets,
138 PHM_PlatformCaps_PowerControl,
139 PHM_PlatformCaps_DisableLSClockGating,
140 PHM_PlatformCaps_BoostState,
141 PHM_PlatformCaps_UserMaxClockForMultiDisplays,
142 PHM_PlatformCaps_RegWriteDelay,
143 PHM_PlatformCaps_NonABMSupportInPPLib,
144 PHM_PlatformCaps_GFXDynamicMGPowerGating,
145 PHM_PlatformCaps_DisableSMUUVDHandshake,
146 PHM_PlatformCaps_DTE,
147 PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,
148 PHM_PlatformCaps_UVDPowerGating,
149 PHM_PlatformCaps_UVDDynamicPowerGating,
150 PHM_PlatformCaps_VCEPowerGating,
151 PHM_PlatformCaps_SamuPowerGating,
152 PHM_PlatformCaps_UVDDPM,
153 PHM_PlatformCaps_VCEDPM,
154 PHM_PlatformCaps_SamuDPM,
155 PHM_PlatformCaps_AcpDPM,
156 PHM_PlatformCaps_SclkDeepSleepAboveLow,
157 PHM_PlatformCaps_DynamicUVDState,
158 PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,
159 PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,
160 PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,
161 PHM_PlatformCaps_WantACPClkWithDummyBackEnd,
162 PHM_PlatformCaps_OD6inACSupport,
163 PHM_PlatformCaps_OD6inDCSupport,
164 PHM_PlatformCaps_EnablePlatformPowerManagement,
165 PHM_PlatformCaps_SurpriseRemoval,
166 PHM_PlatformCaps_NewCACVoltage,
167 PHM_PlatformCaps_DiDtSupport,
168 PHM_PlatformCaps_DBRamping,
169 PHM_PlatformCaps_TDRamping,
170 PHM_PlatformCaps_TCPRamping,
171 PHM_PlatformCaps_DBRRamping,
172 PHM_PlatformCaps_DiDtEDCEnable,
173 PHM_PlatformCaps_GCEDC,
174 PHM_PlatformCaps_PSM,
175 PHM_PlatformCaps_EnableSMU7ThermalManagement,
176 PHM_PlatformCaps_FPS,
177 PHM_PlatformCaps_ACP,
178 PHM_PlatformCaps_SclkThrottleLowNotification,
179 PHM_PlatformCaps_XDMAEnabled,
180 PHM_PlatformCaps_UseDummyBackEnd,
181 PHM_PlatformCaps_EnableDFSBypass,
182 PHM_PlatformCaps_VddNBDirectRequest,
183 PHM_PlatformCaps_PauseMMSessions,
184 PHM_PlatformCaps_UnTabledHardwareInterface,
185 PHM_PlatformCaps_SMU7,
186 PHM_PlatformCaps_RevertGPIO5Polarity,
187 PHM_PlatformCaps_Thermal2GPIO17,
188 PHM_PlatformCaps_ThermalOutGPIO,
189 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,
190 PHM_PlatformCaps_ForceMclkHigh,
191 PHM_PlatformCaps_VRHotGPIOConfigurable,
192 PHM_PlatformCaps_TempInversion,
193 PHM_PlatformCaps_IOIC3,
194 PHM_PlatformCaps_ConnectedStandby,
195 PHM_PlatformCaps_EVV,
196 PHM_PlatformCaps_EnableLongIdleBACOSupport,
197 PHM_PlatformCaps_CombinePCCWithThermalSignal,
198 PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
199 PHM_PlatformCaps_StablePState,
200 PHM_PlatformCaps_OD6PlusinACSupport,
201 PHM_PlatformCaps_OD6PlusinDCSupport,
202 PHM_PlatformCaps_ODThermalLimitUnlock,
203 PHM_PlatformCaps_ReducePowerLimit,
204 PHM_PlatformCaps_ODFuzzyFanControlSupport,
205 PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
206 PHM_PlatformCaps_ControlVDDGFX,
207 PHM_PlatformCaps_BBBSupported,
208 PHM_PlatformCaps_DisableVoltageIsland,
209 PHM_PlatformCaps_FanSpeedInTableIsRPM,
210 PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
211 PHM_PlatformCaps_IcelandULPSSWWorkAround,
212 PHM_PlatformCaps_FPSEnhancement,
213 PHM_PlatformCaps_LoadPostProductionFirmware,
214 PHM_PlatformCaps_VpuRecoveryInProgress,
215 PHM_PlatformCaps_Falcon_QuickTransition,
216 PHM_PlatformCaps_AVFS,
217 PHM_PlatformCaps_ClockStretcher,
218 PHM_PlatformCaps_TablelessHardwareInterface,
219 PHM_PlatformCaps_EnableDriverEVV,
220 PHM_PlatformCaps_SPLLShutdownSupport,
221 PHM_PlatformCaps_VirtualBatteryState,
222 PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
223 PHM_PlatformCaps_DisableMclkSwitchForVR,
224 PHM_PlatformCaps_SMU8,
225 PHM_PlatformCaps_VRHotPolarityHigh,
226 PHM_PlatformCaps_IPS_UlpsExclusive,
227 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
228 PHM_PlatformCaps_GeminiAsymmetricPower,
229 PHM_PlatformCaps_OCLPowerOptimization,
230 PHM_PlatformCaps_MaxPCIEBandWidth,
231 PHM_PlatformCaps_PerfPerWattOptimizationSupport,
232 PHM_PlatformCaps_UVDClientMCTuning,
233 PHM_PlatformCaps_ODNinACSupport,
234 PHM_PlatformCaps_ODNinDCSupport,
235 PHM_PlatformCaps_Max
236};
237
238#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
239
240
241#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
242 ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
243
244struct pp_hw_descriptor {
245 uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
246};
247
248enum PHM_PerformanceLevelDesignation {
249 PHM_PerformanceLevelDesignation_Activity,
250 PHM_PerformanceLevelDesignation_PowerContainment
251};
252
253typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
254
255struct PHM_PerformanceLevel {
256 uint32_t coreClock;
257 uint32_t memory_clock;
258 uint32_t vddc;
259 uint32_t vddci;
260 uint32_t nonLocalMemoryFreq;
261 uint32_t nonLocalMemoryWidth;
262};
263
264typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
265
266
267static inline void phm_cap_set(uint32_t *caps,
268 enum phm_platform_caps c)
269{
270 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
271 (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
272}
273
274static inline void phm_cap_unset(uint32_t *caps,
275 enum phm_platform_caps c)
276{
277 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
278}
279
280static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
281{
282 return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
283 (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
284}
285
286#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
287
288#define PP_PCIEGenInvalid 0xffff
289enum PP_PCIEGen {
290 PP_PCIEGen1 = 0,
291 PP_PCIEGen2,
292 PP_PCIEGen3
293};
294
295typedef enum PP_PCIEGen PP_PCIEGen;
296
297#define PP_Min_PCIEGen PP_PCIEGen1
298#define PP_Max_PCIEGen PP_PCIEGen3
299#define PP_Min_PCIELane 1
300#define PP_Max_PCIELane 16
301
302enum phm_clock_Type {
303 PHM_DispClock = 1,
304 PHM_SClock,
305 PHM_MemClock
306};
307
308#define MAX_NUM_CLOCKS 16
309
310struct PP_Clocks {
311 uint32_t engineClock;
312 uint32_t memoryClock;
313 uint32_t BusBandwidth;
314 uint32_t engineClockInSR;
315 uint32_t dcefClock;
316 uint32_t dcefClockInSR;
317};
318
319struct pp_clock_info {
320 uint32_t min_mem_clk;
321 uint32_t max_mem_clk;
322 uint32_t min_eng_clk;
323 uint32_t max_eng_clk;
324 uint32_t min_bus_bandwidth;
325 uint32_t max_bus_bandwidth;
326};
327
328struct phm_platform_descriptor {
329 uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
330 uint32_t vbiosInterruptId;
331 struct PP_Clocks overdriveLimit;
332 struct PP_Clocks clockStep;
333 uint32_t hardwareActivityPerformanceLevels;
334 uint32_t minimumClocksReductionPercentage;
335 uint32_t minOverdriveVDDC;
336 uint32_t maxOverdriveVDDC;
337 uint32_t overdriveVDDCStep;
338 uint32_t hardwarePerformanceLevels;
339 uint16_t powerBudget;
340 uint32_t TDPLimit;
341 uint32_t nearTDPLimit;
342 uint32_t nearTDPLimitAdjusted;
343 uint32_t SQRampingThreshold;
344 uint32_t CACLeakage;
345 uint16_t TDPODLimit;
346 uint32_t TDPAdjustment;
347 bool TDPAdjustmentPolarity;
348 uint16_t LoadLineSlope;
349 uint32_t VidMinLimit;
350 uint32_t VidMaxLimit;
351 uint32_t VidStep;
352 uint32_t VidAdjustment;
353 bool VidAdjustmentPolarity;
354};
355
356struct phm_clocks {
357 uint32_t num_of_entries;
358 uint32_t clock[MAX_NUM_CLOCKS];
359};
360
361struct phm_odn_performance_level {
362 uint32_t clock;
363 uint32_t vddc;
364 bool enabled;
365};
366
367struct phm_odn_clock_levels {
368 uint32_t size;
369 uint32_t options;
370 uint32_t flags;
371 uint32_t number_of_performance_levels;
372
373 struct phm_odn_performance_level performance_level_entries[8];
374};
375
376extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
377extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
378extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
379extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
380extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
381extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
382extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
383extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
384extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
385 const struct pp_hw_power_state *pcurrent_state,
386 const struct pp_hw_power_state *pnew_power_state);
387
388extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
389 struct pp_power_state *adjusted_ps,
390 const struct pp_power_state *current_ps);
391
392extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
393extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
394extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
395extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
396extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
397extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
398extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
399
400extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
401 const struct pp_hw_power_state *pstate1,
402 const struct pp_hw_power_state *pstate2,
403 bool *equal);
404
405extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
406 const struct amd_pp_display_configuration *display_config);
407
408extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
409 struct amd_pp_simple_clock_info *info);
410
411extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
412
413extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
414
415extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
416 PHM_PerformanceLevelDesignation designation, uint32_t index,
417 PHM_PerformanceLevel *level);
418
419extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
420 struct pp_clock_info *pclock_info,
421 PHM_PerformanceLevelDesignation designation);
422
423extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
424
425extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
426
427extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
428 enum amd_pp_clock_type type,
429 struct pp_clock_levels_with_latency *clocks);
430extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
431 enum amd_pp_clock_type type,
432 struct pp_clock_levels_with_voltage *clocks);
433extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
434 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
435extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
436 struct pp_display_clock_request *clock);
437
438extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
439extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
440#endif
441
442