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23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "pp_instance.h"
29#include "hardwaremanager.h"
30#include "pp_power_source.h"
31#include "hwmgr_ppt.h"
32#include "ppatomctrl.h"
33#include "hwmgr_ppt.h"
34#include "power_state.h"
35#include "cgs_linux.h"
36
37struct pp_instance;
38struct pp_hwmgr;
39struct phm_fan_speed_info;
40struct pp_atomctrl_voltage_table;
41
42#define VOLTAGE_SCALE 4
43
44uint8_t convert_to_vid(uint16_t vddc);
45
46enum DISPLAY_GAP {
47 DISPLAY_GAP_VBLANK_OR_WM = 0,
48 DISPLAY_GAP_VBLANK = 1,
49 DISPLAY_GAP_WATERMARK = 2,
50 DISPLAY_GAP_IGNORE = 3
51};
52typedef enum DISPLAY_GAP DISPLAY_GAP;
53
54struct vi_dpm_level {
55 bool enabled;
56 uint32_t value;
57 uint32_t param1;
58};
59
60struct vi_dpm_table {
61 uint32_t count;
62 struct vi_dpm_level dpm_level[1];
63};
64
65#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
66#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
67#define PCIE_PERF_REQ_GEN1 2
68#define PCIE_PERF_REQ_GEN2 3
69#define PCIE_PERF_REQ_GEN3 4
70
71enum PP_FEATURE_MASK {
72 PP_SCLK_DPM_MASK = 0x1,
73 PP_MCLK_DPM_MASK = 0x2,
74 PP_PCIE_DPM_MASK = 0x4,
75 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
76 PP_POWER_CONTAINMENT_MASK = 0x10,
77 PP_UVD_HANDSHAKE_MASK = 0x20,
78 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
79 PP_VBI_TIME_SUPPORT_MASK = 0x80,
80 PP_ULV_MASK = 0x100,
81 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
82 PP_CLOCK_STRETCH_MASK = 0x400,
83 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
84 PP_SOCCLK_DPM_MASK = 0x1000,
85 PP_DCEFCLK_DPM_MASK = 0x2000,
86};
87
88enum PHM_BackEnd_Magic {
89 PHM_Dummy_Magic = 0xAA5555AA,
90 PHM_RV770_Magic = 0xDCBAABCD,
91 PHM_Kong_Magic = 0x239478DF,
92 PHM_NIslands_Magic = 0x736C494E,
93 PHM_Sumo_Magic = 0x8339FA11,
94 PHM_SIslands_Magic = 0x369431AC,
95 PHM_Trinity_Magic = 0x96751873,
96 PHM_CIslands_Magic = 0x38AC78B0,
97 PHM_Kv_Magic = 0xDCBBABC0,
98 PHM_VIslands_Magic = 0x20130307,
99 PHM_Cz_Magic = 0x67DCBA25,
100 PHM_Rv_Magic = 0x20161121
101};
102
103struct phm_set_power_state_input {
104 const struct pp_hw_power_state *pcurrent_state;
105 const struct pp_hw_power_state *pnew_state;
106};
107
108struct phm_acp_arbiter {
109 uint32_t acpclk;
110};
111
112struct phm_uvd_arbiter {
113 uint32_t vclk;
114 uint32_t dclk;
115 uint32_t vclk_ceiling;
116 uint32_t dclk_ceiling;
117 uint32_t vclk_soft_min;
118 uint32_t dclk_soft_min;
119};
120
121struct phm_vce_arbiter {
122 uint32_t evclk;
123 uint32_t ecclk;
124};
125
126struct phm_gfx_arbiter {
127 uint32_t sclk;
128 uint32_t sclk_hard_min;
129 uint32_t mclk;
130 uint32_t sclk_over_drive;
131 uint32_t mclk_over_drive;
132 uint32_t sclk_threshold;
133 uint32_t num_cus;
134 uint32_t gfxclk;
135 uint32_t fclk;
136};
137
138struct phm_clock_array {
139 uint32_t count;
140 uint32_t values[1];
141};
142
143struct phm_clock_voltage_dependency_record {
144 uint32_t clk;
145 uint32_t v;
146};
147
148struct phm_vceclock_voltage_dependency_record {
149 uint32_t ecclk;
150 uint32_t evclk;
151 uint32_t v;
152};
153
154struct phm_uvdclock_voltage_dependency_record {
155 uint32_t vclk;
156 uint32_t dclk;
157 uint32_t v;
158};
159
160struct phm_samuclock_voltage_dependency_record {
161 uint32_t samclk;
162 uint32_t v;
163};
164
165struct phm_acpclock_voltage_dependency_record {
166 uint32_t acpclk;
167 uint32_t v;
168};
169
170struct phm_clock_voltage_dependency_table {
171 uint32_t count;
172 struct phm_clock_voltage_dependency_record entries[1];
173};
174
175struct phm_phase_shedding_limits_record {
176 uint32_t Voltage;
177 uint32_t Sclk;
178 uint32_t Mclk;
179};
180
181struct phm_uvd_clock_voltage_dependency_record {
182 uint32_t vclk;
183 uint32_t dclk;
184 uint32_t v;
185};
186
187struct phm_uvd_clock_voltage_dependency_table {
188 uint8_t count;
189 struct phm_uvd_clock_voltage_dependency_record entries[1];
190};
191
192struct phm_acp_clock_voltage_dependency_record {
193 uint32_t acpclk;
194 uint32_t v;
195};
196
197struct phm_acp_clock_voltage_dependency_table {
198 uint32_t count;
199 struct phm_acp_clock_voltage_dependency_record entries[1];
200};
201
202struct phm_vce_clock_voltage_dependency_record {
203 uint32_t ecclk;
204 uint32_t evclk;
205 uint32_t v;
206};
207
208struct phm_phase_shedding_limits_table {
209 uint32_t count;
210 struct phm_phase_shedding_limits_record entries[1];
211};
212
213struct phm_vceclock_voltage_dependency_table {
214 uint8_t count;
215 struct phm_vceclock_voltage_dependency_record entries[1];
216};
217
218struct phm_uvdclock_voltage_dependency_table {
219 uint8_t count;
220 struct phm_uvdclock_voltage_dependency_record entries[1];
221};
222
223struct phm_samuclock_voltage_dependency_table {
224 uint8_t count;
225 struct phm_samuclock_voltage_dependency_record entries[1];
226};
227
228struct phm_acpclock_voltage_dependency_table {
229 uint32_t count;
230 struct phm_acpclock_voltage_dependency_record entries[1];
231};
232
233struct phm_vce_clock_voltage_dependency_table {
234 uint8_t count;
235 struct phm_vce_clock_voltage_dependency_record entries[1];
236};
237
238struct pp_smumgr_func {
239 int (*smu_init)(struct pp_hwmgr *hwmgr);
240 int (*smu_fini)(struct pp_hwmgr *hwmgr);
241 int (*start_smu)(struct pp_hwmgr *hwmgr);
242 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
243 uint32_t firmware);
244 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
245 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
246 uint32_t firmware);
247 int (*get_argument)(struct pp_hwmgr *hwmgr);
248 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
249 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
250 uint16_t msg, uint32_t parameter);
251 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
252 void **table);
253 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
254 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
255 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
256 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
257 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
258 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
259 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
260 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
261 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
262 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
263 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
264 uint32_t (*get_mac_definition)(uint32_t value);
265 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
266 int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
267 struct amd_pp_profile *request);
268 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
269};
270
271struct pp_hwmgr_func {
272 int (*backend_init)(struct pp_hwmgr *hw_mgr);
273 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
274 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
275 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
276
277 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
278 struct pp_power_state *prequest_ps,
279 const struct pp_power_state *pcurrent_ps);
280
281 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
282 enum amd_dpm_forced_level level);
283
284 int (*dynamic_state_management_enable)(
285 struct pp_hwmgr *hw_mgr);
286 int (*dynamic_state_management_disable)(
287 struct pp_hwmgr *hw_mgr);
288
289 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
290 struct pp_hw_power_state *hw_ps);
291
292 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
293 unsigned long, struct pp_power_state *);
294 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
295 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
296 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
297 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
298 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
299 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
300 int (*power_state_set)(struct pp_hwmgr *hwmgr,
301 const void *state);
302 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
303 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
304 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
305 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
306 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
307 const uint32_t *msg_id);
308 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
309 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
310 int (*get_temperature)(struct pp_hwmgr *hwmgr);
311 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
312 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
313 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
314 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
315 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
316 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
317 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
318 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
319 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
320 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
321 int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
322 const void *thermal_interrupt_info);
323 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
324 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
325 const struct pp_hw_power_state *pstate1,
326 const struct pp_hw_power_state *pstate2,
327 bool *equal);
328 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
329 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
330 bool cc6_disable, bool pstate_disable,
331 bool pstate_switch_disable);
332 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
333 struct amd_pp_simple_clock_info *info);
334 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
335 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
336 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
337 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
338 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
339 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
340 enum amd_pp_clock_type type,
341 struct pp_clock_levels_with_latency *clocks);
342 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
343 enum amd_pp_clock_type type,
344 struct pp_clock_levels_with_voltage *clocks);
345 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
346 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
347 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
348 struct pp_display_clock_request *clock);
349 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
350 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
351 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
352 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
353 int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
354 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
355 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
356 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
357 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
358 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
359 int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
360 struct amd_pp_profile *request);
361 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
362 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
363 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
364 int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
365 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
366 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
367 uint32_t virtual_addr_low,
368 uint32_t virtual_addr_hi,
369 uint32_t mc_addr_low,
370 uint32_t mc_addr_hi,
371 uint32_t size);
372};
373
374struct pp_table_func {
375 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
376 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
377 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
378 int (*pptable_get_vce_state_table_entry)(
379 struct pp_hwmgr *hwmgr,
380 unsigned long i,
381 struct amd_vce_state *vce_state,
382 void **clock_info,
383 unsigned long *flag);
384};
385
386union phm_cac_leakage_record {
387 struct {
388 uint16_t Vddc;
389 uint32_t Leakage;
390 };
391 struct {
392 uint16_t Vddc1;
393 uint16_t Vddc2;
394 uint16_t Vddc3;
395 };
396};
397
398struct phm_cac_leakage_table {
399 uint32_t count;
400 union phm_cac_leakage_record entries[1];
401};
402
403struct phm_samu_clock_voltage_dependency_record {
404 uint32_t samclk;
405 uint32_t v;
406};
407
408
409struct phm_samu_clock_voltage_dependency_table {
410 uint8_t count;
411 struct phm_samu_clock_voltage_dependency_record entries[1];
412};
413
414struct phm_cac_tdp_table {
415 uint16_t usTDP;
416 uint16_t usConfigurableTDP;
417 uint16_t usTDC;
418 uint16_t usBatteryPowerLimit;
419 uint16_t usSmallPowerLimit;
420 uint16_t usLowCACLeakage;
421 uint16_t usHighCACLeakage;
422 uint16_t usMaximumPowerDeliveryLimit;
423 uint16_t usEDCLimit;
424 uint16_t usOperatingTempMinLimit;
425 uint16_t usOperatingTempMaxLimit;
426 uint16_t usOperatingTempStep;
427 uint16_t usOperatingTempHyst;
428 uint16_t usDefaultTargetOperatingTemp;
429 uint16_t usTargetOperatingTemp;
430 uint16_t usPowerTuneDataSetID;
431 uint16_t usSoftwareShutdownTemp;
432 uint16_t usClockStretchAmount;
433 uint16_t usTemperatureLimitHotspot;
434 uint16_t usTemperatureLimitLiquid1;
435 uint16_t usTemperatureLimitLiquid2;
436 uint16_t usTemperatureLimitVrVddc;
437 uint16_t usTemperatureLimitVrMvdd;
438 uint16_t usTemperatureLimitPlx;
439 uint8_t ucLiquid1_I2C_address;
440 uint8_t ucLiquid2_I2C_address;
441 uint8_t ucLiquid_I2C_Line;
442 uint8_t ucVr_I2C_address;
443 uint8_t ucVr_I2C_Line;
444 uint8_t ucPlx_I2C_address;
445 uint8_t ucPlx_I2C_Line;
446 uint32_t usBoostPowerLimit;
447 uint8_t ucCKS_LDO_REFSEL;
448};
449
450struct phm_tdp_table {
451 uint16_t usTDP;
452 uint16_t usConfigurableTDP;
453 uint16_t usTDC;
454 uint16_t usBatteryPowerLimit;
455 uint16_t usSmallPowerLimit;
456 uint16_t usLowCACLeakage;
457 uint16_t usHighCACLeakage;
458 uint16_t usMaximumPowerDeliveryLimit;
459 uint16_t usEDCLimit;
460 uint16_t usOperatingTempMinLimit;
461 uint16_t usOperatingTempMaxLimit;
462 uint16_t usOperatingTempStep;
463 uint16_t usOperatingTempHyst;
464 uint16_t usDefaultTargetOperatingTemp;
465 uint16_t usTargetOperatingTemp;
466 uint16_t usPowerTuneDataSetID;
467 uint16_t usSoftwareShutdownTemp;
468 uint16_t usClockStretchAmount;
469 uint16_t usTemperatureLimitTedge;
470 uint16_t usTemperatureLimitHotspot;
471 uint16_t usTemperatureLimitLiquid1;
472 uint16_t usTemperatureLimitLiquid2;
473 uint16_t usTemperatureLimitHBM;
474 uint16_t usTemperatureLimitVrVddc;
475 uint16_t usTemperatureLimitVrMvdd;
476 uint16_t usTemperatureLimitPlx;
477 uint8_t ucLiquid1_I2C_address;
478 uint8_t ucLiquid2_I2C_address;
479 uint8_t ucLiquid_I2C_Line;
480 uint8_t ucVr_I2C_address;
481 uint8_t ucVr_I2C_Line;
482 uint8_t ucPlx_I2C_address;
483 uint8_t ucPlx_I2C_Line;
484 uint8_t ucLiquid_I2C_LineSDA;
485 uint8_t ucVr_I2C_LineSDA;
486 uint8_t ucPlx_I2C_LineSDA;
487 uint32_t usBoostPowerLimit;
488 uint16_t usBoostStartTemperature;
489 uint16_t usBoostStopTemperature;
490 uint32_t ulBoostClock;
491};
492
493struct phm_ppm_table {
494 uint8_t ppm_design;
495 uint16_t cpu_core_number;
496 uint32_t platform_tdp;
497 uint32_t small_ac_platform_tdp;
498 uint32_t platform_tdc;
499 uint32_t small_ac_platform_tdc;
500 uint32_t apu_tdp;
501 uint32_t dgpu_tdp;
502 uint32_t dgpu_ulv_power;
503 uint32_t tj_max;
504};
505
506struct phm_vq_budgeting_record {
507 uint32_t ulCUs;
508 uint32_t ulSustainableSOCPowerLimitLow;
509 uint32_t ulSustainableSOCPowerLimitHigh;
510 uint32_t ulMinSclkLow;
511 uint32_t ulMinSclkHigh;
512 uint8_t ucDispConfig;
513 uint32_t ulDClk;
514 uint32_t ulEClk;
515 uint32_t ulSustainableSclk;
516 uint32_t ulSustainableCUs;
517};
518
519struct phm_vq_budgeting_table {
520 uint8_t numEntries;
521 struct phm_vq_budgeting_record entries[1];
522};
523
524struct phm_clock_and_voltage_limits {
525 uint32_t sclk;
526 uint32_t mclk;
527 uint32_t gfxclk;
528 uint16_t vddc;
529 uint16_t vddci;
530 uint16_t vddgfx;
531 uint16_t vddmem;
532};
533
534
535
536struct phm_ppt_v1_information {
537 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
538 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
539 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
540 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
541 struct phm_clock_array *valid_sclk_values;
542 struct phm_clock_array *valid_mclk_values;
543 struct phm_clock_array *valid_socclk_values;
544 struct phm_clock_array *valid_dcefclk_values;
545 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
546 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
547 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
548 struct phm_ppm_table *ppm_parameter_table;
549 struct phm_cac_tdp_table *cac_dtp_table;
550 struct phm_tdp_table *tdp_table;
551 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
552 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
553 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
554 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
555 struct phm_ppt_v1_pcie_table *pcie_table;
556 struct phm_ppt_v1_gpio_table *gpio_table;
557 uint16_t us_ulv_voltage_offset;
558 uint16_t us_ulv_smnclk_did;
559 uint16_t us_ulv_mp1clk_did;
560 uint16_t us_ulv_gfxclk_bypass;
561 uint16_t us_gfxclk_slew_rate;
562 uint16_t us_min_gfxclk_freq_limit;
563};
564
565struct phm_ppt_v2_information {
566 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
567 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
568 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
569 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
570 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
571 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
572 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
573 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
574
575 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
576
577 struct phm_clock_array *valid_sclk_values;
578 struct phm_clock_array *valid_mclk_values;
579 struct phm_clock_array *valid_socclk_values;
580 struct phm_clock_array *valid_dcefclk_values;
581
582 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
583 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
584
585 struct phm_ppm_table *ppm_parameter_table;
586 struct phm_cac_tdp_table *cac_dtp_table;
587 struct phm_tdp_table *tdp_table;
588
589 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
590 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
591 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
592 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
593
594 struct phm_ppt_v1_pcie_table *pcie_table;
595
596 uint16_t us_ulv_voltage_offset;
597 uint16_t us_ulv_smnclk_did;
598 uint16_t us_ulv_mp1clk_did;
599 uint16_t us_ulv_gfxclk_bypass;
600 uint16_t us_gfxclk_slew_rate;
601 uint16_t us_min_gfxclk_freq_limit;
602
603 uint8_t uc_gfx_dpm_voltage_mode;
604 uint8_t uc_soc_dpm_voltage_mode;
605 uint8_t uc_uclk_dpm_voltage_mode;
606 uint8_t uc_uvd_dpm_voltage_mode;
607 uint8_t uc_vce_dpm_voltage_mode;
608 uint8_t uc_mp0_dpm_voltage_mode;
609 uint8_t uc_dcef_dpm_voltage_mode;
610};
611
612struct phm_dynamic_state_info {
613 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
614 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
615 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
616 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
617 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
618 struct phm_clock_array *valid_sclk_values;
619 struct phm_clock_array *valid_mclk_values;
620 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
621 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
622 uint32_t mclk_sclk_ratio;
623 uint32_t sclk_mclk_delta;
624 uint32_t vddc_vddci_delta;
625 uint32_t min_vddc_for_pcie_gen2;
626 struct phm_cac_leakage_table *cac_leakage_table;
627 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
628
629 struct phm_vce_clock_voltage_dependency_table
630 *vce_clock_voltage_dependency_table;
631 struct phm_uvd_clock_voltage_dependency_table
632 *uvd_clock_voltage_dependency_table;
633 struct phm_acp_clock_voltage_dependency_table
634 *acp_clock_voltage_dependency_table;
635 struct phm_samu_clock_voltage_dependency_table
636 *samu_clock_voltage_dependency_table;
637
638 struct phm_ppm_table *ppm_parameter_table;
639 struct phm_cac_tdp_table *cac_dtp_table;
640 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
641 struct phm_vq_budgeting_table *vq_budgeting_table;
642};
643
644struct pp_fan_info {
645 bool bNoFan;
646 uint8_t ucTachometerPulsesPerRevolution;
647 uint32_t ulMinRPM;
648 uint32_t ulMaxRPM;
649};
650
651struct pp_advance_fan_control_parameters {
652 uint16_t usTMin;
653 uint16_t usTMed;
654 uint16_t usTHigh;
655 uint16_t usPWMMin;
656 uint16_t usPWMMed;
657 uint16_t usPWMHigh;
658 uint8_t ucTHyst;
659 uint32_t ulCycleDelay;
660 uint16_t usTMax;
661 uint8_t ucFanControlMode;
662 uint16_t usFanPWMMinLimit;
663 uint16_t usFanPWMMaxLimit;
664 uint16_t usFanPWMStep;
665 uint16_t usDefaultMaxFanPWM;
666 uint16_t usFanOutputSensitivity;
667 uint16_t usDefaultFanOutputSensitivity;
668 uint16_t usMaxFanPWM;
669 uint16_t usFanRPMMinLimit;
670 uint16_t usFanRPMMaxLimit;
671 uint16_t usFanRPMStep;
672 uint16_t usDefaultMaxFanRPM;
673 uint16_t usMaxFanRPM;
674 uint16_t usFanCurrentLow;
675 uint16_t usFanCurrentHigh;
676 uint16_t usFanRPMLow;
677 uint16_t usFanRPMHigh;
678 uint32_t ulMinFanSCLKAcousticLimit;
679 uint8_t ucTargetTemperature;
680 uint8_t ucMinimumPWMLimit;
681 uint16_t usFanGainEdge;
682 uint16_t usFanGainHotspot;
683 uint16_t usFanGainLiquid;
684 uint16_t usFanGainVrVddc;
685 uint16_t usFanGainVrMvdd;
686 uint16_t usFanGainPlx;
687 uint16_t usFanGainHbm;
688 uint8_t ucEnableZeroRPM;
689 uint8_t ucFanStopTemperature;
690 uint8_t ucFanStartTemperature;
691 uint32_t ulMaxFanSCLKAcousticLimit;
692 uint32_t ulTargetGfxClk;
693 uint16_t usZeroRPMStartTemperature;
694 uint16_t usZeroRPMStopTemperature;
695};
696
697struct pp_thermal_controller_info {
698 uint8_t ucType;
699 uint8_t ucI2cLine;
700 uint8_t ucI2cAddress;
701 struct pp_fan_info fanInfo;
702 struct pp_advance_fan_control_parameters advanceFanControlParameters;
703};
704
705struct phm_microcode_version_info {
706 uint32_t SMC;
707 uint32_t DMCU;
708 uint32_t MC;
709 uint32_t NB;
710};
711
712enum PP_TABLE_VERSION {
713 PP_TABLE_V0 = 0,
714 PP_TABLE_V1,
715 PP_TABLE_V2,
716 PP_TABLE_MAX
717};
718
719
720
721
722struct pp_hwmgr {
723 uint32_t chip_family;
724 uint32_t chip_id;
725
726 uint32_t pp_table_version;
727 void *device;
728 struct pp_smumgr *smumgr;
729 const void *soft_pp_table;
730 uint32_t soft_pp_table_size;
731 void *hardcode_pp_table;
732 bool need_pp_table_upload;
733
734 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
735 uint32_t num_vce_state_tables;
736
737 enum amd_dpm_forced_level dpm_level;
738 enum amd_dpm_forced_level saved_dpm_level;
739 enum amd_dpm_forced_level request_dpm_level;
740 struct phm_gfx_arbiter gfx_arbiter;
741 struct phm_acp_arbiter acp_arbiter;
742 struct phm_uvd_arbiter uvd_arbiter;
743 struct phm_vce_arbiter vce_arbiter;
744 uint32_t usec_timeout;
745 void *pptable;
746 struct phm_platform_descriptor platform_descriptor;
747 void *backend;
748
749 void *smu_backend;
750 const struct pp_smumgr_func *smumgr_funcs;
751 bool is_kicker;
752 bool reload_fw;
753
754 enum PP_DAL_POWERLEVEL dal_power_level;
755 struct phm_dynamic_state_info dyn_state;
756 const struct pp_hwmgr_func *hwmgr_func;
757 const struct pp_table_func *pptable_func;
758
759 struct pp_power_state *ps;
760 enum pp_power_source power_source;
761 uint32_t num_ps;
762 struct pp_thermal_controller_info thermal_controller;
763 bool fan_ctrl_is_in_default_mode;
764 uint32_t fan_ctrl_default_mode;
765 bool fan_ctrl_enabled;
766 uint32_t tmin;
767 struct phm_microcode_version_info microcode_version_info;
768 uint32_t ps_size;
769 struct pp_power_state *current_ps;
770 struct pp_power_state *request_ps;
771 struct pp_power_state *boot_ps;
772 struct pp_power_state *uvd_ps;
773 struct amd_pp_display_configuration display_config;
774 uint32_t feature_mask;
775
776
777 struct amd_pp_profile gfx_power_profile;
778 struct amd_pp_profile compute_power_profile;
779 struct amd_pp_profile default_gfx_power_profile;
780 struct amd_pp_profile default_compute_power_profile;
781 enum amd_pp_profile_type current_power_profile;
782 bool en_umd_pstate;
783};
784
785struct cgs_irq_src_funcs {
786 cgs_irq_source_set_func_t set;
787 cgs_irq_handler_func_t handler;
788};
789
790extern int hwmgr_early_init(struct pp_instance *handle);
791extern int hwmgr_hw_init(struct pp_instance *handle);
792extern int hwmgr_hw_fini(struct pp_instance *handle);
793extern int hwmgr_hw_suspend(struct pp_instance *handle);
794extern int hwmgr_hw_resume(struct pp_instance *handle);
795extern int hwmgr_handle_task(struct pp_instance *handle,
796 enum amd_pp_task task_id,
797 void *input, void *output);
798extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
799 uint32_t value, uint32_t mask);
800
801extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
802 uint32_t indirect_port,
803 uint32_t index,
804 uint32_t value,
805 uint32_t mask);
806
807extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
808 uint32_t index,
809 uint32_t value, uint32_t mask);
810extern int phm_wait_for_indirect_register_unequal(
811 struct pp_hwmgr *hwmgr,
812 uint32_t indirect_port, uint32_t index,
813 uint32_t value, uint32_t mask);
814
815
816extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
817extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
818extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
819
820extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
821extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
822extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
823extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
824extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
825extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
826extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
827extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
828extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
829 uint32_t voltage);
830extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
831extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
832extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
833extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
834 uint16_t virtual_voltage_id, int32_t *sclk);
835extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
836extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
837extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
838
839extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
840extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
841extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
842
843extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
844 uint32_t sclk, uint16_t id, uint16_t *voltage);
845
846#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
847
848#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
849#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
850
851#define PHM_SET_FIELD(origval, reg, field, fieldval) \
852 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
853 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
854
855#define PHM_GET_FIELD(value, reg, field) \
856 (((value) & PHM_FIELD_MASK(reg, field)) >> \
857 PHM_FIELD_SHIFT(reg, field))
858
859
860
861
862#define PHM_READ_FIELD(device, reg, field) \
863 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
864
865#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
866 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
867 reg, field)
868
869#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
870 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
871 reg, field)
872
873#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
874 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
875 cgs_read_register(device, mm##reg), reg, field, fieldval))
876
877#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
878 cgs_write_ind_register(device, port, ix##reg, \
879 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
880 reg, field, fieldval))
881
882#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
883 cgs_write_ind_register(device, port, ix##reg, \
884 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
885 reg, field, fieldval))
886
887#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
888 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
889
890
891#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
892 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
893
894#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
895 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
896 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
897
898#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
899 phm_wait_for_indirect_register_unequal(hwmgr, \
900 mm##port##_INDEX, index, value, mask)
901
902#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
903 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
904
905#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
906 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
907 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
908 PHM_FIELD_MASK(reg, field) )
909
910
911#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
912 port, index, value, mask) \
913 phm_wait_for_indirect_register_unequal(hwmgr, \
914 mm##port##_INDEX_11, index, value, mask)
915
916#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
917 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
918
919#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
920 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
921 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
922 PHM_FIELD_MASK(reg, field))
923
924
925#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
926 port, index, value, mask) \
927 phm_wait_on_indirect_register(hwmgr, \
928 mm##port##_INDEX_11, index, value, mask)
929
930#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
931 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
932
933#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
934 PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
935 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
936 PHM_FIELD_MASK(reg, field))
937
938#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
939 index, value, mask) \
940 phm_wait_for_register_unequal(hwmgr, \
941 index, value, mask)
942
943#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
944 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
945 mm##reg, value, mask)
946
947#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
948 PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
949 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
950 PHM_FIELD_MASK(reg, field))
951
952#endif
953
