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32#include <linux/module.h>
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_addr.h>
35#include <rdma/ib_user_verbs.h>
36#include <rdma/iw_cm.h>
37#include <rdma/ib_mad.h>
38#include <linux/netdevice.h>
39#include <linux/iommu.h>
40#include <linux/pci.h>
41#include <net/addrconf.h>
42#include <linux/idr.h>
43
44#include <linux/qed/qed_chain.h>
45#include <linux/qed/qed_if.h>
46#include "qedr.h"
47#include "verbs.h"
48#include <rdma/qedr-abi.h>
49#include "qedr_iw_cm.h"
50
51MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
52MODULE_AUTHOR("QLogic Corporation");
53MODULE_LICENSE("Dual BSD/GPL");
54
55#define QEDR_WQ_MULTIPLIER_DFT (3)
56
57static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
58 enum ib_event_type type)
59{
60 struct ib_event ibev;
61
62 ibev.device = &dev->ibdev;
63 ibev.element.port_num = port_num;
64 ibev.event = type;
65
66 ib_dispatch_event(&ibev);
67}
68
69static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
70 u8 port_num)
71{
72 return IB_LINK_LAYER_ETHERNET;
73}
74
75static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
76{
77 struct qedr_dev *qedr = get_qedr_dev(ibdev);
78 u32 fw_ver = (u32)qedr->attr.fw_ver;
79
80 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d",
81 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
82 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
83}
84
85static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num)
86{
87 struct qedr_dev *qdev;
88
89 qdev = get_qedr_dev(dev);
90 dev_hold(qdev->ndev);
91
92
93
94
95
96 return qdev->ndev;
97}
98
99static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
100 struct ib_port_immutable *immutable)
101{
102 struct ib_port_attr attr;
103 int err;
104
105 err = qedr_query_port(ibdev, port_num, &attr);
106 if (err)
107 return err;
108
109 immutable->pkey_tbl_len = attr.pkey_tbl_len;
110 immutable->gid_tbl_len = attr.gid_tbl_len;
111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
113 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
114
115 return 0;
116}
117
118static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
119 struct ib_port_immutable *immutable)
120{
121 struct ib_port_attr attr;
122 int err;
123
124 err = qedr_query_port(ibdev, port_num, &attr);
125 if (err)
126 return err;
127
128 immutable->pkey_tbl_len = 1;
129 immutable->gid_tbl_len = 1;
130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
131 immutable->max_mad_size = 0;
132
133 return 0;
134}
135
136static int qedr_iw_register_device(struct qedr_dev *dev)
137{
138 dev->ibdev.node_type = RDMA_NODE_RNIC;
139 dev->ibdev.query_gid = qedr_iw_query_gid;
140
141 dev->ibdev.get_port_immutable = qedr_iw_port_immutable;
142
143 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL);
144 if (!dev->ibdev.iwcm)
145 return -ENOMEM;
146
147 dev->ibdev.iwcm->connect = qedr_iw_connect;
148 dev->ibdev.iwcm->accept = qedr_iw_accept;
149 dev->ibdev.iwcm->reject = qedr_iw_reject;
150 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen;
151 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen;
152 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref;
153 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref;
154 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp;
155
156 memcpy(dev->ibdev.iwcm->ifname,
157 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname));
158
159 return 0;
160}
161
162static void qedr_roce_register_device(struct qedr_dev *dev)
163{
164 dev->ibdev.node_type = RDMA_NODE_IB_CA;
165 dev->ibdev.query_gid = qedr_query_gid;
166
167 dev->ibdev.add_gid = qedr_add_gid;
168 dev->ibdev.del_gid = qedr_del_gid;
169
170 dev->ibdev.get_port_immutable = qedr_roce_port_immutable;
171}
172
173static int qedr_register_device(struct qedr_dev *dev)
174{
175 int rc;
176
177 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
178
179 dev->ibdev.node_guid = dev->attr.node_guid;
180 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
181 dev->ibdev.owner = THIS_MODULE;
182 dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
183
184 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
185 QEDR_UVERBS(QUERY_DEVICE) |
186 QEDR_UVERBS(QUERY_PORT) |
187 QEDR_UVERBS(ALLOC_PD) |
188 QEDR_UVERBS(DEALLOC_PD) |
189 QEDR_UVERBS(CREATE_COMP_CHANNEL) |
190 QEDR_UVERBS(CREATE_CQ) |
191 QEDR_UVERBS(RESIZE_CQ) |
192 QEDR_UVERBS(DESTROY_CQ) |
193 QEDR_UVERBS(REQ_NOTIFY_CQ) |
194 QEDR_UVERBS(CREATE_QP) |
195 QEDR_UVERBS(MODIFY_QP) |
196 QEDR_UVERBS(QUERY_QP) |
197 QEDR_UVERBS(DESTROY_QP) |
198 QEDR_UVERBS(REG_MR) |
199 QEDR_UVERBS(DEREG_MR) |
200 QEDR_UVERBS(POLL_CQ) |
201 QEDR_UVERBS(POST_SEND) |
202 QEDR_UVERBS(POST_RECV);
203
204 if (IS_IWARP(dev)) {
205 rc = qedr_iw_register_device(dev);
206 if (rc)
207 return rc;
208 } else {
209 qedr_roce_register_device(dev);
210 }
211
212 dev->ibdev.phys_port_cnt = 1;
213 dev->ibdev.num_comp_vectors = dev->num_cnq;
214
215 dev->ibdev.query_device = qedr_query_device;
216 dev->ibdev.query_port = qedr_query_port;
217 dev->ibdev.modify_port = qedr_modify_port;
218
219 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
220 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
221 dev->ibdev.mmap = qedr_mmap;
222
223 dev->ibdev.alloc_pd = qedr_alloc_pd;
224 dev->ibdev.dealloc_pd = qedr_dealloc_pd;
225
226 dev->ibdev.create_cq = qedr_create_cq;
227 dev->ibdev.destroy_cq = qedr_destroy_cq;
228 dev->ibdev.resize_cq = qedr_resize_cq;
229 dev->ibdev.req_notify_cq = qedr_arm_cq;
230
231 dev->ibdev.create_qp = qedr_create_qp;
232 dev->ibdev.modify_qp = qedr_modify_qp;
233 dev->ibdev.query_qp = qedr_query_qp;
234 dev->ibdev.destroy_qp = qedr_destroy_qp;
235
236 dev->ibdev.query_pkey = qedr_query_pkey;
237
238 dev->ibdev.create_ah = qedr_create_ah;
239 dev->ibdev.destroy_ah = qedr_destroy_ah;
240
241 dev->ibdev.get_dma_mr = qedr_get_dma_mr;
242 dev->ibdev.dereg_mr = qedr_dereg_mr;
243 dev->ibdev.reg_user_mr = qedr_reg_user_mr;
244 dev->ibdev.alloc_mr = qedr_alloc_mr;
245 dev->ibdev.map_mr_sg = qedr_map_mr_sg;
246
247 dev->ibdev.poll_cq = qedr_poll_cq;
248 dev->ibdev.post_send = qedr_post_send;
249 dev->ibdev.post_recv = qedr_post_recv;
250
251 dev->ibdev.process_mad = qedr_process_mad;
252
253 dev->ibdev.get_netdev = qedr_get_netdev;
254
255 dev->ibdev.dev.parent = &dev->pdev->dev;
256
257 dev->ibdev.get_link_layer = qedr_link_layer;
258 dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
259
260 return ib_register_device(&dev->ibdev, NULL);
261}
262
263
264static int qedr_alloc_mem_sb(struct qedr_dev *dev,
265 struct qed_sb_info *sb_info, u16 sb_id)
266{
267 struct status_block *sb_virt;
268 dma_addr_t sb_phys;
269 int rc;
270
271 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
272 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
273 if (!sb_virt)
274 return -ENOMEM;
275
276 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
277 sb_virt, sb_phys, sb_id,
278 QED_SB_TYPE_CNQ);
279 if (rc) {
280 pr_err("Status block initialization failed\n");
281 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
282 sb_virt, sb_phys);
283 return rc;
284 }
285
286 return 0;
287}
288
289static void qedr_free_mem_sb(struct qedr_dev *dev,
290 struct qed_sb_info *sb_info, int sb_id)
291{
292 if (sb_info->sb_virt) {
293 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
294 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
295 (void *)sb_info->sb_virt, sb_info->sb_phys);
296 }
297}
298
299static void qedr_free_resources(struct qedr_dev *dev)
300{
301 int i;
302
303 if (IS_IWARP(dev))
304 destroy_workqueue(dev->iwarp_wq);
305
306 for (i = 0; i < dev->num_cnq; i++) {
307 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
308 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
309 }
310
311 kfree(dev->cnq_array);
312 kfree(dev->sb_array);
313 kfree(dev->sgid_tbl);
314}
315
316static int qedr_alloc_resources(struct qedr_dev *dev)
317{
318 struct qedr_cnq *cnq;
319 __le16 *cons_pi;
320 u16 n_entries;
321 int i, rc;
322
323 dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
324 QEDR_MAX_SGID, GFP_KERNEL);
325 if (!dev->sgid_tbl)
326 return -ENOMEM;
327
328 spin_lock_init(&dev->sgid_lock);
329
330 if (IS_IWARP(dev)) {
331 spin_lock_init(&dev->idr_lock);
332 idr_init(&dev->qpidr);
333 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
334 }
335
336
337 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
338 GFP_KERNEL);
339 if (!dev->sb_array) {
340 rc = -ENOMEM;
341 goto err1;
342 }
343
344 dev->cnq_array = kcalloc(dev->num_cnq,
345 sizeof(*dev->cnq_array), GFP_KERNEL);
346 if (!dev->cnq_array) {
347 rc = -ENOMEM;
348 goto err2;
349 }
350
351 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
352
353
354 n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
355 for (i = 0; i < dev->num_cnq; i++) {
356 cnq = &dev->cnq_array[i];
357
358 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
359 dev->sb_start + i);
360 if (rc)
361 goto err3;
362
363 rc = dev->ops->common->chain_alloc(dev->cdev,
364 QED_CHAIN_USE_TO_CONSUME,
365 QED_CHAIN_MODE_PBL,
366 QED_CHAIN_CNT_TYPE_U16,
367 n_entries,
368 sizeof(struct regpair *),
369 &cnq->pbl, NULL);
370 if (rc)
371 goto err4;
372
373 cnq->dev = dev;
374 cnq->sb = &dev->sb_array[i];
375 cons_pi = dev->sb_array[i].sb_virt->pi_array;
376 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
377 cnq->index = i;
378 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
379
380 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
381 i, qed_chain_get_cons_idx(&cnq->pbl));
382 }
383
384 return 0;
385err4:
386 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
387err3:
388 for (--i; i >= 0; i--) {
389 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
390 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
391 }
392 kfree(dev->cnq_array);
393err2:
394 kfree(dev->sb_array);
395err1:
396 kfree(dev->sgid_tbl);
397 return rc;
398}
399
400
401static ssize_t show_rev(struct device *device, struct device_attribute *attr,
402 char *buf)
403{
404 struct qedr_dev *dev = dev_get_drvdata(device);
405
406 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
407}
408
409static ssize_t show_hca_type(struct device *device,
410 struct device_attribute *attr, char *buf)
411{
412 return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
413}
414
415static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
416static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
417
418static struct device_attribute *qedr_attributes[] = {
419 &dev_attr_hw_rev,
420 &dev_attr_hca_type
421};
422
423static void qedr_remove_sysfiles(struct qedr_dev *dev)
424{
425 int i;
426
427 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
428 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
429}
430
431static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
432{
433 struct pci_dev *bridge;
434 u32 ctl2, cap2;
435 u16 flags;
436 int rc;
437
438 bridge = pdev->bus->self;
439 if (!bridge)
440 goto disable;
441
442
443 while (bridge->bus->parent) {
444 rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags);
445 if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2))
446 goto disable;
447
448 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2);
449 if (rc)
450 goto disable;
451
452 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2);
453 if (rc)
454 goto disable;
455
456 if (!(cap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE) ||
457 (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK))
458 goto disable;
459 bridge = bridge->bus->parent->self;
460 }
461
462 rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags);
463 if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2))
464 goto disable;
465
466 rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2);
467 if (rc || !(cap2 & PCI_EXP_DEVCAP2_ATOMIC_COMP64))
468 goto disable;
469
470
471 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
472 PCI_EXP_DEVCTL2_ATOMIC_REQ);
473 dev->atomic_cap = IB_ATOMIC_GLOB;
474
475 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
476
477 return;
478
479disable:
480 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
481 PCI_EXP_DEVCTL2_ATOMIC_REQ);
482 dev->atomic_cap = IB_ATOMIC_NONE;
483
484 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
485
486}
487
488static const struct qed_rdma_ops *qed_ops;
489
490#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
491
492static irqreturn_t qedr_irq_handler(int irq, void *handle)
493{
494 u16 hw_comp_cons, sw_comp_cons;
495 struct qedr_cnq *cnq = handle;
496 struct regpair *cq_handle;
497 struct qedr_cq *cq;
498
499 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
500
501 qed_sb_update_sb_idx(cnq->sb);
502
503 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
504 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
505
506
507 rmb();
508
509 while (sw_comp_cons != hw_comp_cons) {
510 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
511 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
512 cq_handle->lo);
513
514 if (cq == NULL) {
515 DP_ERR(cnq->dev,
516 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
517 cq_handle->hi, cq_handle->lo, sw_comp_cons,
518 hw_comp_cons);
519
520 break;
521 }
522
523 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
524 DP_ERR(cnq->dev,
525 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
526 cq_handle->hi, cq_handle->lo, cq);
527 break;
528 }
529
530 cq->arm_flags = 0;
531
532 if (!cq->destroyed && cq->ibcq.comp_handler)
533 (*cq->ibcq.comp_handler)
534 (&cq->ibcq, cq->ibcq.cq_context);
535
536
537
538
539
540
541
542 cq->cnq_notif++;
543
544 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
545
546 cnq->n_comp++;
547 }
548
549 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
550 sw_comp_cons);
551
552 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
553
554 return IRQ_HANDLED;
555}
556
557static void qedr_sync_free_irqs(struct qedr_dev *dev)
558{
559 u32 vector;
560 int i;
561
562 for (i = 0; i < dev->int_info.used_cnt; i++) {
563 if (dev->int_info.msix_cnt) {
564 vector = dev->int_info.msix[i * dev->num_hwfns].vector;
565 synchronize_irq(vector);
566 free_irq(vector, &dev->cnq_array[i]);
567 }
568 }
569
570 dev->int_info.used_cnt = 0;
571}
572
573static int qedr_req_msix_irqs(struct qedr_dev *dev)
574{
575 int i, rc = 0;
576
577 if (dev->num_cnq > dev->int_info.msix_cnt) {
578 DP_ERR(dev,
579 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
580 dev->num_cnq, dev->int_info.msix_cnt);
581 return -EINVAL;
582 }
583
584 for (i = 0; i < dev->num_cnq; i++) {
585 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
586 qedr_irq_handler, 0, dev->cnq_array[i].name,
587 &dev->cnq_array[i]);
588 if (rc) {
589 DP_ERR(dev, "Request cnq %d irq failed\n", i);
590 qedr_sync_free_irqs(dev);
591 } else {
592 DP_DEBUG(dev, QEDR_MSG_INIT,
593 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
594 dev->cnq_array[i].name, i,
595 &dev->cnq_array[i]);
596 dev->int_info.used_cnt++;
597 }
598 }
599
600 return rc;
601}
602
603static int qedr_setup_irqs(struct qedr_dev *dev)
604{
605 int rc;
606
607 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
608
609
610 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
611 if (rc < 0)
612 return rc;
613
614 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
615 if (rc) {
616 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
617 return rc;
618 }
619
620 if (dev->int_info.msix_cnt) {
621 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
622 dev->int_info.msix_cnt);
623 rc = qedr_req_msix_irqs(dev);
624 if (rc)
625 return rc;
626 }
627
628 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
629
630 return 0;
631}
632
633static int qedr_set_device_attr(struct qedr_dev *dev)
634{
635 struct qed_rdma_device *qed_attr;
636 struct qedr_device_attr *attr;
637 u32 page_size;
638
639
640 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
641
642
643 page_size = ~dev->attr.page_size_caps + 1;
644 if (page_size > PAGE_SIZE) {
645 DP_ERR(dev,
646 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
647 PAGE_SIZE, page_size);
648 return -ENODEV;
649 }
650
651
652 attr = &dev->attr;
653 attr->vendor_id = qed_attr->vendor_id;
654 attr->vendor_part_id = qed_attr->vendor_part_id;
655 attr->hw_ver = qed_attr->hw_ver;
656 attr->fw_ver = qed_attr->fw_ver;
657 attr->node_guid = qed_attr->node_guid;
658 attr->sys_image_guid = qed_attr->sys_image_guid;
659 attr->max_cnq = qed_attr->max_cnq;
660 attr->max_sge = qed_attr->max_sge;
661 attr->max_inline = qed_attr->max_inline;
662 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
663 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
664 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
665 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
666 attr->max_dev_resp_rd_atomic_resc =
667 qed_attr->max_dev_resp_rd_atomic_resc;
668 attr->max_cq = qed_attr->max_cq;
669 attr->max_qp = qed_attr->max_qp;
670 attr->max_mr = qed_attr->max_mr;
671 attr->max_mr_size = qed_attr->max_mr_size;
672 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
673 attr->max_mw = qed_attr->max_mw;
674 attr->max_fmr = qed_attr->max_fmr;
675 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
676 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
677 attr->max_pd = qed_attr->max_pd;
678 attr->max_ah = qed_attr->max_ah;
679 attr->max_pkey = qed_attr->max_pkey;
680 attr->max_srq = qed_attr->max_srq;
681 attr->max_srq_wr = qed_attr->max_srq_wr;
682 attr->dev_caps = qed_attr->dev_caps;
683 attr->page_size_caps = qed_attr->page_size_caps;
684 attr->dev_ack_delay = qed_attr->dev_ack_delay;
685 attr->reserved_lkey = qed_attr->reserved_lkey;
686 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
687 attr->max_stats_queues = qed_attr->max_stats_queues;
688
689 return 0;
690}
691
692static void qedr_unaffiliated_event(void *context, u8 event_code)
693{
694 pr_err("unaffiliated event not implemented yet\n");
695}
696
697static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
698{
699#define EVENT_TYPE_NOT_DEFINED 0
700#define EVENT_TYPE_CQ 1
701#define EVENT_TYPE_QP 2
702 struct qedr_dev *dev = (struct qedr_dev *)context;
703 struct regpair *async_handle = (struct regpair *)fw_handle;
704 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
705 u8 event_type = EVENT_TYPE_NOT_DEFINED;
706 struct ib_event event;
707 struct ib_cq *ibcq;
708 struct ib_qp *ibqp;
709 struct qedr_cq *cq;
710 struct qedr_qp *qp;
711
712 switch (e_code) {
713 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
714 event.event = IB_EVENT_CQ_ERR;
715 event_type = EVENT_TYPE_CQ;
716 break;
717 case ROCE_ASYNC_EVENT_SQ_DRAINED:
718 event.event = IB_EVENT_SQ_DRAINED;
719 event_type = EVENT_TYPE_QP;
720 break;
721 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
722 event.event = IB_EVENT_QP_FATAL;
723 event_type = EVENT_TYPE_QP;
724 break;
725 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
726 event.event = IB_EVENT_QP_REQ_ERR;
727 event_type = EVENT_TYPE_QP;
728 break;
729 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
730 event.event = IB_EVENT_QP_ACCESS_ERR;
731 event_type = EVENT_TYPE_QP;
732 break;
733 default:
734 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
735 roce_handle64);
736 }
737
738 switch (event_type) {
739 case EVENT_TYPE_CQ:
740 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
741 if (cq) {
742 ibcq = &cq->ibcq;
743 if (ibcq->event_handler) {
744 event.device = ibcq->device;
745 event.element.cq = ibcq;
746 ibcq->event_handler(&event, ibcq->cq_context);
747 }
748 } else {
749 WARN(1,
750 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
751 roce_handle64);
752 }
753 DP_ERR(dev, "CQ event %d on hanlde %p\n", e_code, cq);
754 break;
755 case EVENT_TYPE_QP:
756 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
757 if (qp) {
758 ibqp = &qp->ibqp;
759 if (ibqp->event_handler) {
760 event.device = ibqp->device;
761 event.element.qp = ibqp;
762 ibqp->event_handler(&event, ibqp->qp_context);
763 }
764 } else {
765 WARN(1,
766 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
767 roce_handle64);
768 }
769 DP_ERR(dev, "QP event %d on hanlde %p\n", e_code, qp);
770 break;
771 default:
772 break;
773 }
774}
775
776static int qedr_init_hw(struct qedr_dev *dev)
777{
778 struct qed_rdma_add_user_out_params out_params;
779 struct qed_rdma_start_in_params *in_params;
780 struct qed_rdma_cnq_params *cur_pbl;
781 struct qed_rdma_events events;
782 dma_addr_t p_phys_table;
783 u32 page_cnt;
784 int rc = 0;
785 int i;
786
787 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
788 if (!in_params) {
789 rc = -ENOMEM;
790 goto out;
791 }
792
793 in_params->desired_cnq = dev->num_cnq;
794 for (i = 0; i < dev->num_cnq; i++) {
795 cur_pbl = &in_params->cnq_pbl_list[i];
796
797 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
798 cur_pbl->num_pbl_pages = page_cnt;
799
800 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
801 cur_pbl->pbl_ptr = (u64)p_phys_table;
802 }
803
804 events.affiliated_event = qedr_affiliated_event;
805 events.unaffiliated_event = qedr_unaffiliated_event;
806 events.context = dev;
807
808 in_params->events = &events;
809 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
810 in_params->max_mtu = dev->ndev->mtu;
811 dev->iwarp_max_mtu = dev->ndev->mtu;
812 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
813
814 rc = dev->ops->rdma_init(dev->cdev, in_params);
815 if (rc)
816 goto out;
817
818 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
819 if (rc)
820 goto out;
821
822 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
823 dev->db_phys_addr = out_params.dpi_phys_addr;
824 dev->db_size = out_params.dpi_size;
825 dev->dpi = out_params.dpi;
826
827 rc = qedr_set_device_attr(dev);
828out:
829 kfree(in_params);
830 if (rc)
831 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
832
833 return rc;
834}
835
836static void qedr_stop_hw(struct qedr_dev *dev)
837{
838 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
839 dev->ops->rdma_stop(dev->rdma_ctx);
840}
841
842static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
843 struct net_device *ndev)
844{
845 struct qed_dev_rdma_info dev_info;
846 struct qedr_dev *dev;
847 int rc = 0, i;
848
849 dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
850 if (!dev) {
851 pr_err("Unable to allocate ib device\n");
852 return NULL;
853 }
854
855 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
856
857 dev->pdev = pdev;
858 dev->ndev = ndev;
859 dev->cdev = cdev;
860
861 qed_ops = qed_get_rdma_ops();
862 if (!qed_ops) {
863 DP_ERR(dev, "Failed to get qed roce operations\n");
864 goto init_err;
865 }
866
867 dev->ops = qed_ops;
868 rc = qed_ops->fill_dev_info(cdev, &dev_info);
869 if (rc)
870 goto init_err;
871
872 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
873 dev->rdma_type = dev_info.rdma_type;
874 dev->num_hwfns = dev_info.common.num_hwfns;
875 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
876
877 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
878 if (!dev->num_cnq) {
879 DP_ERR(dev, "not enough CNQ resources.\n");
880 goto init_err;
881 }
882
883 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
884
885 qedr_pci_set_atomic(dev, pdev);
886
887 rc = qedr_alloc_resources(dev);
888 if (rc)
889 goto init_err;
890
891 rc = qedr_init_hw(dev);
892 if (rc)
893 goto alloc_err;
894
895 rc = qedr_setup_irqs(dev);
896 if (rc)
897 goto irq_err;
898
899 rc = qedr_register_device(dev);
900 if (rc) {
901 DP_ERR(dev, "Unable to allocate register device\n");
902 goto reg_err;
903 }
904
905 for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
906 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
907 goto sysfs_err;
908
909 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
910 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
911
912 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
913 return dev;
914
915sysfs_err:
916 ib_unregister_device(&dev->ibdev);
917reg_err:
918 qedr_sync_free_irqs(dev);
919irq_err:
920 qedr_stop_hw(dev);
921alloc_err:
922 qedr_free_resources(dev);
923init_err:
924 ib_dealloc_device(&dev->ibdev);
925 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
926
927 return NULL;
928}
929
930static void qedr_remove(struct qedr_dev *dev)
931{
932
933
934
935 qedr_remove_sysfiles(dev);
936 ib_unregister_device(&dev->ibdev);
937
938 qedr_stop_hw(dev);
939 qedr_sync_free_irqs(dev);
940 qedr_free_resources(dev);
941 ib_dealloc_device(&dev->ibdev);
942}
943
944static void qedr_close(struct qedr_dev *dev)
945{
946 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
947 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
948}
949
950static void qedr_shutdown(struct qedr_dev *dev)
951{
952 qedr_close(dev);
953 qedr_remove(dev);
954}
955
956static void qedr_open(struct qedr_dev *dev)
957{
958 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
959 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
960}
961
962static void qedr_mac_address_change(struct qedr_dev *dev)
963{
964 union ib_gid *sgid = &dev->sgid_tbl[0];
965 u8 guid[8], mac_addr[6];
966 int rc;
967
968
969 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
970 guid[0] = mac_addr[0] ^ 2;
971 guid[1] = mac_addr[1];
972 guid[2] = mac_addr[2];
973 guid[3] = 0xff;
974 guid[4] = 0xfe;
975 guid[5] = mac_addr[3];
976 guid[6] = mac_addr[4];
977 guid[7] = mac_addr[5];
978 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
979 memcpy(&sgid->raw[8], guid, sizeof(guid));
980
981
982 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
983 dev->gsi_ll2_mac_address,
984 dev->ndev->dev_addr);
985
986 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
987
988 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
989
990 if (rc)
991 DP_ERR(dev, "Error updating mac filter\n");
992}
993
994
995
996
997
998static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
999{
1000 switch (event) {
1001 case QEDE_UP:
1002 qedr_open(dev);
1003 break;
1004 case QEDE_DOWN:
1005 qedr_close(dev);
1006 break;
1007 case QEDE_CLOSE:
1008 qedr_shutdown(dev);
1009 break;
1010 case QEDE_CHANGE_ADDR:
1011 qedr_mac_address_change(dev);
1012 break;
1013 default:
1014 pr_err("Event not supported\n");
1015 }
1016}
1017
1018static struct qedr_driver qedr_drv = {
1019 .name = "qedr_driver",
1020 .add = qedr_add,
1021 .remove = qedr_remove,
1022 .notify = qedr_notify,
1023};
1024
1025static int __init qedr_init_module(void)
1026{
1027 return qede_rdma_register_driver(&qedr_drv);
1028}
1029
1030static void __exit qedr_exit_module(void)
1031{
1032 qede_rdma_unregister_driver(&qedr_drv);
1033}
1034
1035module_init(qedr_init_module);
1036module_exit(qedr_exit_module);
1037
