LXR linux/drivers/media/rc/nuvoton-cir.h

   1/*
   2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
   3 *
   4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
   5 * Copyright (C) 2009 Nuvoton PS Team
   6 *
   7 * Special thanks to Nuvoton for providing hardware, spec sheets and
   8 * sample code upon which portions of this driver are based. Indirect
   9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
  10 * modeled after.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of the
  15 * License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful, but
  18 * WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20 * General Public License for more details.
  21 */
  22
  23#include <linux/spinlock.h>
  24#include <linux/ioctl.h>
  25
  26/* platform driver name to register */
  27#define NVT_DRIVER_NAME "nuvoton-cir"
  28
  29/* debugging module parameter */
  30static int debug;
  31
  32
  33#define nvt_dbg(text, ...) \
  34        if (debug) \
  35                printk(KERN_DEBUG \
  36                        KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  37
  38#define nvt_dbg_verbose(text, ...) \
  39        if (debug > 1) \
  40                printk(KERN_DEBUG \
  41                        KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  42
  43#define nvt_dbg_wake(text, ...) \
  44        if (debug > 2) \
  45                printk(KERN_DEBUG \
  46                        KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  47
  48
  49#define RX_BUF_LEN 32
  50
  51#define SIO_ID_MASK 0xfff0
  52
  53enum nvt_chip_ver {
  54        NVT_UNKNOWN     = 0,
  55        NVT_W83667HG    = 0xa510,
  56        NVT_6775F       = 0xb470,
  57        NVT_6776F       = 0xc330,
  58        NVT_6779D       = 0xc560,
  59        NVT_INVALID     = 0xffff,
  60};
  61
  62struct nvt_chip {
  63        const char *name;
  64        enum nvt_chip_ver chip_ver;
  65};
  66
  67struct nvt_dev {
  68        struct rc_dev *rdev;
  69
  70        spinlock_t lock;
  71
  72        /* for rx */
  73        u8 buf[RX_BUF_LEN];
  74        unsigned int pkts;
  75
  76        /* EFER Config register index/data pair */
  77        u32 cr_efir;
  78        u32 cr_efdr;
  79
  80        /* hardware I/O settings */
  81        unsigned long cir_addr;
  82        unsigned long cir_wake_addr;
  83        int cir_irq;
  84
  85        enum nvt_chip_ver chip_ver;
  86        /* hardware id */
  87        u8 chip_major;
  88        u8 chip_minor;
  89
  90        /* carrier period = 1 / frequency */
  91        u32 carrier;
  92};
  93
  94/* buffer packet constants */
  95#define BUF_PULSE_BIT   0x80
  96#define BUF_LEN_MASK    0x7f
  97#define BUF_REPEAT_BYTE 0x70
  98#define BUF_REPEAT_MASK 0xf0
  99
 100/* CIR settings */
 101
 102/* total length of CIR and CIR WAKE */
 103#define CIR_IOREG_LENGTH        0x0f
 104
 105/* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
 106#define CIR_RX_LIMIT_COUNT  (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD))
 107
 108/* CIR Regs */
 109#define CIR_IRCON       0x00
 110#define CIR_IRSTS       0x01
 111#define CIR_IREN        0x02
 112#define CIR_RXFCONT     0x03
 113#define CIR_CP          0x04
 114#define CIR_CC          0x05
 115#define CIR_SLCH        0x06
 116#define CIR_SLCL        0x07
 117#define CIR_FIFOCON     0x08
 118#define CIR_IRFIFOSTS   0x09
 119#define CIR_SRXFIFO     0x0a
 120#define CIR_TXFCONT     0x0b
 121#define CIR_STXFIFO     0x0c
 122#define CIR_FCCH        0x0d
 123#define CIR_FCCL        0x0e
 124#define CIR_IRFSM       0x0f
 125
 126/* CIR IRCON settings */
 127#define CIR_IRCON_RECV   0x80
 128#define CIR_IRCON_WIREN  0x40
 129#define CIR_IRCON_TXEN   0x20
 130#define CIR_IRCON_RXEN   0x10
 131#define CIR_IRCON_WRXINV 0x08
 132#define CIR_IRCON_RXINV  0x04
 133
 134#define CIR_IRCON_SAMPLE_PERIOD_SEL_1   0x00
 135#define CIR_IRCON_SAMPLE_PERIOD_SEL_25  0x01
 136#define CIR_IRCON_SAMPLE_PERIOD_SEL_50  0x02
 137#define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
 138
 139/* FIXME: make this a runtime option */
 140/* select sample period as 50us */
 141#define CIR_IRCON_SAMPLE_PERIOD_SEL     CIR_IRCON_SAMPLE_PERIOD_SEL_50
 142
 143/* CIR IRSTS settings */
 144#define CIR_IRSTS_RDR   0x80
 145#define CIR_IRSTS_RTR   0x40
 146#define CIR_IRSTS_PE    0x20
 147#define CIR_IRSTS_RFO   0x10
 148#define CIR_IRSTS_TE    0x08
 149#define CIR_IRSTS_TTR   0x04
 150#define CIR_IRSTS_TFU   0x02
 151#define CIR_IRSTS_GH    0x01
 152
 153/* CIR IREN settings */
 154#define CIR_IREN_RDR    0x80
 155#define CIR_IREN_RTR    0x40
 156#define CIR_IREN_PE     0x20
 157#define CIR_IREN_RFO    0x10
 158#define CIR_IREN_TE     0x08
 159#define CIR_IREN_TTR    0x04
 160#define CIR_IREN_TFU    0x02
 161#define CIR_IREN_GH     0x01
 162
 163/* CIR FIFOCON settings */
 164#define CIR_FIFOCON_TXFIFOCLR           0x80
 165
 166#define CIR_FIFOCON_TX_TRIGGER_LEV_31   0x00
 167#define CIR_FIFOCON_TX_TRIGGER_LEV_24   0x10
 168#define CIR_FIFOCON_TX_TRIGGER_LEV_16   0x20
 169#define CIR_FIFOCON_TX_TRIGGER_LEV_8    0x30
 170
 171/* FIXME: make this a runtime option */
 172/* select TX trigger level as 16 */
 173#define CIR_FIFOCON_TX_TRIGGER_LEV      CIR_FIFOCON_TX_TRIGGER_LEV_16
 174
 175#define CIR_FIFOCON_RXFIFOCLR           0x08
 176
 177#define CIR_FIFOCON_RX_TRIGGER_LEV_1    0x00
 178#define CIR_FIFOCON_RX_TRIGGER_LEV_8    0x01
 179#define CIR_FIFOCON_RX_TRIGGER_LEV_16   0x02
 180#define CIR_FIFOCON_RX_TRIGGER_LEV_24   0x03
 181
 182/* FIXME: make this a runtime option */
 183/* select RX trigger level as 24 */
 184#define CIR_FIFOCON_RX_TRIGGER_LEV      CIR_FIFOCON_RX_TRIGGER_LEV_24
 185
 186/* CIR IRFIFOSTS settings */
 187#define CIR_IRFIFOSTS_IR_PENDING        0x80
 188#define CIR_IRFIFOSTS_RX_GS             0x40
 189#define CIR_IRFIFOSTS_RX_FTA            0x20
 190#define CIR_IRFIFOSTS_RX_EMPTY          0x10
 191#define CIR_IRFIFOSTS_RX_FULL           0x08
 192#define CIR_IRFIFOSTS_TX_FTA            0x04
 193#define CIR_IRFIFOSTS_TX_EMPTY          0x02
 194#define CIR_IRFIFOSTS_TX_FULL           0x01
 195
 196
 197/* CIR WAKE UP Regs */
 198#define CIR_WAKE_IRCON                  0x00
 199#define CIR_WAKE_IRSTS                  0x01
 200#define CIR_WAKE_IREN                   0x02
 201#define CIR_WAKE_FIFO_CMP_DEEP          0x03
 202#define CIR_WAKE_FIFO_CMP_TOL           0x04
 203#define CIR_WAKE_FIFO_COUNT             0x05
 204#define CIR_WAKE_SLCH                   0x06
 205#define CIR_WAKE_SLCL                   0x07
 206#define CIR_WAKE_FIFOCON                0x08
 207#define CIR_WAKE_SRXFSTS                0x09
 208#define CIR_WAKE_SAMPLE_RX_FIFO         0x0a
 209#define CIR_WAKE_WR_FIFO_DATA           0x0b
 210#define CIR_WAKE_RD_FIFO_ONLY           0x0c
 211#define CIR_WAKE_RD_FIFO_ONLY_IDX       0x0d
 212#define CIR_WAKE_FIFO_IGNORE            0x0e
 213#define CIR_WAKE_IRFSM                  0x0f
 214
 215/* CIR WAKE UP IRCON settings */
 216#define CIR_WAKE_IRCON_DEC_RST          0x80
 217#define CIR_WAKE_IRCON_MODE1            0x40
 218#define CIR_WAKE_IRCON_MODE0            0x20
 219#define CIR_WAKE_IRCON_RXEN             0x10
 220#define CIR_WAKE_IRCON_R                0x08
 221#define CIR_WAKE_IRCON_RXINV            0x04
 222
 223/* FIXME/jarod: make this a runtime option */
 224/* select a same sample period like cir register */
 225#define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL        CIR_IRCON_SAMPLE_PERIOD_SEL_50
 226
 227/* CIR WAKE IRSTS Bits */
 228#define CIR_WAKE_IRSTS_RDR              0x80
 229#define CIR_WAKE_IRSTS_RTR              0x40
 230#define CIR_WAKE_IRSTS_PE               0x20
 231#define CIR_WAKE_IRSTS_RFO              0x10
 232#define CIR_WAKE_IRSTS_GH               0x08
 233#define CIR_WAKE_IRSTS_IR_PENDING       0x01
 234
 235/* CIR WAKE UP IREN Bits */
 236#define CIR_WAKE_IREN_RDR               0x80
 237#define CIR_WAKE_IREN_RTR               0x40
 238#define CIR_WAKE_IREN_PE                0x20
 239#define CIR_WAKE_IREN_RFO               0x10
 240#define CIR_WAKE_IREN_GH                0x08
 241
 242/* CIR WAKE FIFOCON settings */
 243#define CIR_WAKE_FIFOCON_RXFIFOCLR      0x08
 244
 245#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67      0x00
 246#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66      0x01
 247#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65      0x02
 248#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64      0x03
 249
 250/* FIXME: make this a runtime option */
 251/* select WAKE UP RX trigger level as 67 */
 252#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
 253
 254/* CIR WAKE SRXFSTS settings */
 255#define CIR_WAKE_IRFIFOSTS_RX_GS        0x80
 256#define CIR_WAKE_IRFIFOSTS_RX_FTA       0x40
 257#define CIR_WAKE_IRFIFOSTS_RX_EMPTY     0x20
 258#define CIR_WAKE_IRFIFOSTS_RX_FULL      0x10
 259
 260/*
 261 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
 262 * the system comparing only 65 bytes (fails with this set to 67)
 263 */
 264#define CIR_WAKE_FIFO_CMP_BYTES         65
 265/* CIR Wake byte comparison tolerance */
 266#define CIR_WAKE_CMP_TOLERANCE          5
 267
 268/*
 269 * Extended Function Enable Registers:
 270 *  Extended Function Index Register
 271 *  Extended Function Data Register
 272 */
 273#define CR_EFIR                 0x2e
 274#define CR_EFDR                 0x2f
 275
 276/* Possible alternate EFER values, depends on how the chip is wired */
 277#define CR_EFIR2                0x4e
 278#define CR_EFDR2                0x4f
 279
 280/* Extended Function Mode enable/disable magic values */
 281#define EFER_EFM_ENABLE         0x87
 282#define EFER_EFM_DISABLE        0xaa
 283
 284/* Config regs we need to care about */
 285#define CR_SOFTWARE_RESET       0x02
 286#define CR_LOGICAL_DEV_SEL      0x07
 287#define CR_CHIP_ID_HI           0x20
 288#define CR_CHIP_ID_LO           0x21
 289#define CR_DEV_POWER_DOWN       0x22 /* bit 2 is CIR power, default power on */
 290#define CR_OUTPUT_PIN_SEL       0x27
 291#define CR_MULTIFUNC_PIN_SEL    0x2c
 292#define CR_LOGICAL_DEV_EN       0x30 /* valid for all logical devices */
 293/* next three regs valid for both the CIR and CIR_WAKE logical devices */
 294#define CR_CIR_BASE_ADDR_HI     0x60
 295#define CR_CIR_BASE_ADDR_LO     0x61
 296#define CR_CIR_IRQ_RSRC         0x70
 297/* next three regs valid only for ACPI logical dev */
 298#define CR_ACPI_CIR_WAKE        0xe0
 299#define CR_ACPI_IRQ_EVENTS      0xf6
 300#define CR_ACPI_IRQ_EVENTS2     0xf7
 301
 302/* Logical devices that we need to care about */
 303#define LOGICAL_DEV_LPT         0x01
 304#define LOGICAL_DEV_CIR         0x06
 305#define LOGICAL_DEV_ACPI        0x0a
 306#define LOGICAL_DEV_CIR_WAKE    0x0e
 307
 308#define LOGICAL_DEV_DISABLE     0x00
 309#define LOGICAL_DEV_ENABLE      0x01
 310
 311#define CIR_WAKE_ENABLE_BIT     0x08
 312#define PME_INTR_CIR_PASS_BIT   0x08
 313
 314/* w83677hg CIR pin config */
 315#define OUTPUT_PIN_SEL_MASK     0xbc
 316#define OUTPUT_ENABLE_CIR       0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
 317#define OUTPUT_ENABLE_CIRWB     0x40 /* enable wide-band sensor */
 318
 319/* w83667hg CIR pin config */
 320#define MULTIFUNC_PIN_SEL_MASK  0x1f
 321#define MULTIFUNC_ENABLE_CIR    0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
 322#define MULTIFUNC_ENABLE_CIRWB  0x20 /* enable wide-band sensor */
 323
 324/* MCE CIR signal length, related on sample period */
 325
 326/* MCE CIR controller signal length: about 43ms
 327 * 43ms / 50us (sample period) * 0.85 (inaccuracy)
 328 */
 329#define CONTROLLER_BUF_LEN_MIN 830
 330
 331/* MCE CIR keyboard signal length: about 26ms
 332 * 26ms / 50us (sample period) * 0.85 (inaccuracy)
 333 */
 334#define KEYBOARD_BUF_LEN_MAX 650
 335#define KEYBOARD_BUF_LEN_MIN 610
 336
 337/* MCE CIR mouse signal length: about 24ms
 338 * 24ms / 50us (sample period) * 0.85 (inaccuracy)
 339 */
 340#define MOUSE_BUF_LEN_MIN 565
 341
 342#define CIR_SAMPLE_PERIOD 50
 343#define CIR_SAMPLE_LOW_INACCURACY 0.85
 344
 345/* MAX silence time that driver will sent to lirc */
 346#define MAX_SILENCE_TIME 60000
 347
 348#if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
 349#define SAMPLE_PERIOD 100
 350
 351#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
 352#define SAMPLE_PERIOD 50
 353
 354#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
 355#define SAMPLE_PERIOD 25
 356
 357#else
 358#define SAMPLE_PERIOD 1
 359#endif
 360
 361/* as VISTA MCE definition, valid carrier value */
 362#define MAX_CARRIER 60000
 363#define MIN_CARRIER 30000
 364
 365/* max wakeup sequence length */
 366#define WAKEUP_MAX_SIZE 65
 367