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35#include <linux/videodev2.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
38#include <linux/bitrev.h>
39
40#include "tuner-i2c.h"
41#include "r820t.h"
42
43
44
45
46
47#define REG_SHADOW_START 5
48#define NUM_REGS 27
49#define NUM_IMR 5
50#define IMR_TRIAL 9
51
52#define VER_NUM 49
53
54static int debug;
55module_param(debug, int, 0644);
56MODULE_PARM_DESC(debug, "enable verbose debug messages");
57
58static int no_imr_cal;
59module_param(no_imr_cal, int, 0444);
60MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
61
62
63
64
65
66
67enum xtal_cap_value {
68 XTAL_LOW_CAP_30P = 0,
69 XTAL_LOW_CAP_20P,
70 XTAL_LOW_CAP_10P,
71 XTAL_LOW_CAP_0P,
72 XTAL_HIGH_CAP_0P
73};
74
75struct r820t_sect_type {
76 u8 phase_y;
77 u8 gain_x;
78 u16 value;
79};
80
81struct r820t_priv {
82 struct list_head hybrid_tuner_instance_list;
83 const struct r820t_config *cfg;
84 struct tuner_i2c_props i2c_props;
85 struct mutex lock;
86
87 u8 regs[NUM_REGS];
88 u8 buf[NUM_REGS + 1];
89 enum xtal_cap_value xtal_cap_sel;
90 u16 pll;
91 u32 int_freq;
92 u8 fil_cal_code;
93 bool imr_done;
94 bool has_lock;
95 bool init_done;
96 struct r820t_sect_type imr_data[NUM_IMR];
97
98
99 u32 delsys;
100 enum v4l2_tuner_type type;
101 v4l2_std_id std;
102 u32 bw;
103};
104
105struct r820t_freq_range {
106 u32 freq;
107 u8 open_d;
108 u8 rf_mux_ploy;
109 u8 tf_c;
110 u8 xtal_cap20p;
111 u8 xtal_cap10p;
112 u8 xtal_cap0p;
113 u8 imr_mem;
114};
115
116#define VCO_POWER_REF 0x02
117#define DIP_FREQ 32000000
118
119
120
121
122
123static LIST_HEAD(hybrid_tuner_instance_list);
124static DEFINE_MUTEX(r820t_list_mutex);
125
126
127static const u8 r820t_init_array[NUM_REGS] = {
128 0x83, 0x32, 0x75,
129 0xc0, 0x40, 0xd6, 0x6c,
130 0xf5, 0x63, 0x75, 0x68,
131 0x6c, 0x83, 0x80, 0x00,
132 0x0f, 0x00, 0xc0, 0x30,
133 0x48, 0xcc, 0x60, 0x00,
134 0x54, 0xae, 0x4a, 0xc0
135};
136
137
138static const struct r820t_freq_range freq_ranges[] = {
139 {
140 .freq = 0,
141 .open_d = 0x08,
142 .rf_mux_ploy = 0x02,
143 .tf_c = 0xdf,
144 .xtal_cap20p = 0x02,
145 .xtal_cap10p = 0x01,
146 .xtal_cap0p = 0x00,
147 .imr_mem = 0,
148 }, {
149 .freq = 50,
150 .open_d = 0x08,
151 .rf_mux_ploy = 0x02,
152 .tf_c = 0xbe,
153 .xtal_cap20p = 0x02,
154 .xtal_cap10p = 0x01,
155 .xtal_cap0p = 0x00,
156 .imr_mem = 0,
157 }, {
158 .freq = 55,
159 .open_d = 0x08,
160 .rf_mux_ploy = 0x02,
161 .tf_c = 0x8b,
162 .xtal_cap20p = 0x02,
163 .xtal_cap10p = 0x01,
164 .xtal_cap0p = 0x00,
165 .imr_mem = 0,
166 }, {
167 .freq = 60,
168 .open_d = 0x08,
169 .rf_mux_ploy = 0x02,
170 .tf_c = 0x7b,
171 .xtal_cap20p = 0x02,
172 .xtal_cap10p = 0x01,
173 .xtal_cap0p = 0x00,
174 .imr_mem = 0,
175 }, {
176 .freq = 65,
177 .open_d = 0x08,
178 .rf_mux_ploy = 0x02,
179 .tf_c = 0x69,
180 .xtal_cap20p = 0x02,
181 .xtal_cap10p = 0x01,
182 .xtal_cap0p = 0x00,
183 .imr_mem = 0,
184 }, {
185 .freq = 70,
186 .open_d = 0x08,
187 .rf_mux_ploy = 0x02,
188 .tf_c = 0x58,
189 .xtal_cap20p = 0x02,
190 .xtal_cap10p = 0x01,
191 .xtal_cap0p = 0x00,
192 .imr_mem = 0,
193 }, {
194 .freq = 75,
195 .open_d = 0x00,
196 .rf_mux_ploy = 0x02,
197 .tf_c = 0x44,
198 .xtal_cap20p = 0x02,
199 .xtal_cap10p = 0x01,
200 .xtal_cap0p = 0x00,
201 .imr_mem = 0,
202 }, {
203 .freq = 80,
204 .open_d = 0x00,
205 .rf_mux_ploy = 0x02,
206 .tf_c = 0x44,
207 .xtal_cap20p = 0x02,
208 .xtal_cap10p = 0x01,
209 .xtal_cap0p = 0x00,
210 .imr_mem = 0,
211 }, {
212 .freq = 90,
213 .open_d = 0x00,
214 .rf_mux_ploy = 0x02,
215 .tf_c = 0x34,
216 .xtal_cap20p = 0x01,
217 .xtal_cap10p = 0x01,
218 .xtal_cap0p = 0x00,
219 .imr_mem = 0,
220 }, {
221 .freq = 100,
222 .open_d = 0x00,
223 .rf_mux_ploy = 0x02,
224 .tf_c = 0x34,
225 .xtal_cap20p = 0x01,
226 .xtal_cap10p = 0x01,
227 .xtal_cap0p = 0x00,
228 .imr_mem = 0,
229 }, {
230 .freq = 110,
231 .open_d = 0x00,
232 .rf_mux_ploy = 0x02,
233 .tf_c = 0x24,
234 .xtal_cap20p = 0x01,
235 .xtal_cap10p = 0x01,
236 .xtal_cap0p = 0x00,
237 .imr_mem = 1,
238 }, {
239 .freq = 120,
240 .open_d = 0x00,
241 .rf_mux_ploy = 0x02,
242 .tf_c = 0x24,
243 .xtal_cap20p = 0x01,
244 .xtal_cap10p = 0x01,
245 .xtal_cap0p = 0x00,
246 .imr_mem = 1,
247 }, {
248 .freq = 140,
249 .open_d = 0x00,
250 .rf_mux_ploy = 0x02,
251 .tf_c = 0x14,
252 .xtal_cap20p = 0x01,
253 .xtal_cap10p = 0x01,
254 .xtal_cap0p = 0x00,
255 .imr_mem = 1,
256 }, {
257 .freq = 180,
258 .open_d = 0x00,
259 .rf_mux_ploy = 0x02,
260 .tf_c = 0x13,
261 .xtal_cap20p = 0x00,
262 .xtal_cap10p = 0x00,
263 .xtal_cap0p = 0x00,
264 .imr_mem = 1,
265 }, {
266 .freq = 220,
267 .open_d = 0x00,
268 .rf_mux_ploy = 0x02,
269 .tf_c = 0x13,
270 .xtal_cap20p = 0x00,
271 .xtal_cap10p = 0x00,
272 .xtal_cap0p = 0x00,
273 .imr_mem = 2,
274 }, {
275 .freq = 250,
276 .open_d = 0x00,
277 .rf_mux_ploy = 0x02,
278 .tf_c = 0x11,
279 .xtal_cap20p = 0x00,
280 .xtal_cap10p = 0x00,
281 .xtal_cap0p = 0x00,
282 .imr_mem = 2,
283 }, {
284 .freq = 280,
285 .open_d = 0x00,
286 .rf_mux_ploy = 0x02,
287 .tf_c = 0x00,
288 .xtal_cap20p = 0x00,
289 .xtal_cap10p = 0x00,
290 .xtal_cap0p = 0x00,
291 .imr_mem = 2,
292 }, {
293 .freq = 310,
294 .open_d = 0x00,
295 .rf_mux_ploy = 0x41,
296 .tf_c = 0x00,
297 .xtal_cap20p = 0x00,
298 .xtal_cap10p = 0x00,
299 .xtal_cap0p = 0x00,
300 .imr_mem = 2,
301 }, {
302 .freq = 450,
303 .open_d = 0x00,
304 .rf_mux_ploy = 0x41,
305 .tf_c = 0x00,
306 .xtal_cap20p = 0x00,
307 .xtal_cap10p = 0x00,
308 .xtal_cap0p = 0x00,
309 .imr_mem = 3,
310 }, {
311 .freq = 588,
312 .open_d = 0x00,
313 .rf_mux_ploy = 0x40,
314 .tf_c = 0x00,
315 .xtal_cap20p = 0x00,
316 .xtal_cap10p = 0x00,
317 .xtal_cap0p = 0x00,
318 .imr_mem = 3,
319 }, {
320 .freq = 650,
321 .open_d = 0x00,
322 .rf_mux_ploy = 0x40,
323 .tf_c = 0x00,
324 .xtal_cap20p = 0x00,
325 .xtal_cap10p = 0x00,
326 .xtal_cap0p = 0x00,
327 .imr_mem = 4,
328 }
329};
330
331static int r820t_xtal_capacitor[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P },
333 { 0x02, XTAL_LOW_CAP_20P },
334 { 0x01, XTAL_LOW_CAP_10P },
335 { 0x00, XTAL_LOW_CAP_0P },
336 { 0x10, XTAL_HIGH_CAP_0P },
337};
338
339
340
341
342static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
343 int len)
344{
345 int r = reg - REG_SHADOW_START;
346
347 if (r < 0) {
348 len += r;
349 r = 0;
350 }
351 if (len <= 0)
352 return;
353 if (len > NUM_REGS - r)
354 len = NUM_REGS - r;
355
356 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
357 __func__, r + REG_SHADOW_START, len, len, val);
358
359 memcpy(&priv->regs[r], val, len);
360}
361
362static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
363 int len)
364{
365 int rc, size, pos = 0;
366
367
368 shadow_store(priv, reg, val, len);
369
370 do {
371 if (len > priv->cfg->max_i2c_msg_len - 1)
372 size = priv->cfg->max_i2c_msg_len - 1;
373 else
374 size = len;
375
376
377 priv->buf[0] = reg;
378 memcpy(&priv->buf[1], &val[pos], size);
379
380 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
381 if (rc != size + 1) {
382 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
383 __func__, rc, reg, size, size, &priv->buf[1]);
384 if (rc < 0)
385 return rc;
386 return -EREMOTEIO;
387 }
388 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
389 __func__, reg, size, size, &priv->buf[1]);
390
391 reg += size;
392 len -= size;
393 pos += size;
394 } while (len > 0);
395
396 return 0;
397}
398
399static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
400{
401 return r820t_write(priv, reg, &val, 1);
402}
403
404static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
405{
406 reg -= REG_SHADOW_START;
407
408 if (reg >= 0 && reg < NUM_REGS)
409 return priv->regs[reg];
410 else
411 return -EINVAL;
412}
413
414static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
415 u8 bit_mask)
416{
417 int rc = r820t_read_cache_reg(priv, reg);
418
419 if (rc < 0)
420 return rc;
421
422 val = (rc & ~bit_mask) | (val & bit_mask);
423
424 return r820t_write(priv, reg, &val, 1);
425}
426
427static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
428{
429 int rc, i;
430 u8 *p = &priv->buf[1];
431
432 priv->buf[0] = reg;
433
434 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
435 if (rc != len) {
436 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
437 __func__, rc, reg, len, len, p);
438 if (rc < 0)
439 return rc;
440 return -EREMOTEIO;
441 }
442
443
444 for (i = 0; i < len; i++)
445 val[i] = bitrev8(p[i]);
446
447 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
448 __func__, reg, len, len, val);
449
450 return 0;
451}
452
453
454
455
456
457static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
458{
459 const struct r820t_freq_range *range;
460 int i, rc;
461 u8 val, reg08, reg09;
462
463
464 freq = freq / 1000000;
465 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
466 if (freq < freq_ranges[i + 1].freq)
467 break;
468 }
469 range = &freq_ranges[i];
470
471 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
472
473
474 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
475 if (rc < 0)
476 return rc;
477
478
479 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
480 if (rc < 0)
481 return rc;
482
483
484 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
485 if (rc < 0)
486 return rc;
487
488
489 switch (priv->xtal_cap_sel) {
490 case XTAL_LOW_CAP_30P:
491 case XTAL_LOW_CAP_20P:
492 val = range->xtal_cap20p | 0x08;
493 break;
494 case XTAL_LOW_CAP_10P:
495 val = range->xtal_cap10p | 0x08;
496 break;
497 case XTAL_HIGH_CAP_0P:
498 val = range->xtal_cap0p | 0x00;
499 break;
500 default:
501 case XTAL_LOW_CAP_0P:
502 val = range->xtal_cap0p | 0x08;
503 break;
504 }
505 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
506 if (rc < 0)
507 return rc;
508
509 if (priv->imr_done) {
510 reg08 = priv->imr_data[range->imr_mem].gain_x;
511 reg09 = priv->imr_data[range->imr_mem].phase_y;
512 } else {
513 reg08 = 0;
514 reg09 = 0;
515 }
516 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
517 if (rc < 0)
518 return rc;
519
520 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
521
522 return rc;
523}
524
525static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
526 u32 freq)
527{
528 u32 vco_freq;
529 int rc, i;
530 unsigned sleep_time = 10000;
531 u32 vco_fra;
532 u32 vco_min = 1770000;
533 u32 vco_max = vco_min * 2;
534 u32 pll_ref;
535 u16 n_sdm = 2;
536 u16 sdm = 0;
537 u8 mix_div = 2;
538 u8 div_buf = 0;
539 u8 div_num = 0;
540 u8 refdiv2 = 0;
541 u8 ni, si, nint, vco_fine_tune, val;
542 u8 data[5];
543
544
545 freq = freq / 1000;
546 pll_ref = priv->cfg->xtal / 1000;
547
548#if 0
549
550 if ((priv->cfg->rafael_chip == CHIP_R620D) ||
551 (priv->cfg->rafael_chip == CHIP_R828D) ||
552 (priv->cfg->rafael_chip == CHIP_R828)) {
553
554 if (type != V4L2_TUNER_DIGITAL_TV) {
555 pll_ref /= 2;
556 refdiv2 = 0x10;
557 sleep_time = 20000;
558 }
559 } else {
560 if (priv->cfg->xtal > 24000000) {
561 pll_ref /= 2;
562 refdiv2 = 0x10;
563 }
564 }
565#endif
566
567 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
568 if (rc < 0)
569 return rc;
570
571
572 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
573 if (rc < 0)
574 return rc;
575
576
577 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
578 if (rc < 0)
579 return rc;
580
581
582 while (mix_div <= 64) {
583 if (((freq * mix_div) >= vco_min) &&
584 ((freq * mix_div) < vco_max)) {
585 div_buf = mix_div;
586 while (div_buf > 2) {
587 div_buf = div_buf >> 1;
588 div_num++;
589 }
590 break;
591 }
592 mix_div = mix_div << 1;
593 }
594
595 rc = r820t_read(priv, 0x00, data, sizeof(data));
596 if (rc < 0)
597 return rc;
598
599 vco_fine_tune = (data[4] & 0x30) >> 4;
600
601 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
602 mix_div, div_num, vco_fine_tune);
603
604
605
606
607
608 if (priv->cfg->rafael_chip != CHIP_R828D) {
609 if (vco_fine_tune > VCO_POWER_REF)
610 div_num = div_num - 1;
611 else if (vco_fine_tune < VCO_POWER_REF)
612 div_num = div_num + 1;
613 }
614
615 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
616 if (rc < 0)
617 return rc;
618
619 vco_freq = freq * mix_div;
620 nint = vco_freq / (2 * pll_ref);
621 vco_fra = vco_freq - 2 * pll_ref * nint;
622
623
624 if (vco_fra < pll_ref / 64) {
625 vco_fra = 0;
626 } else if (vco_fra > pll_ref * 127 / 64) {
627 vco_fra = 0;
628 nint++;
629 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
630 vco_fra = pll_ref * 127 / 128;
631 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
632 vco_fra = pll_ref * 129 / 128;
633 }
634
635 ni = (nint - 13) / 4;
636 si = nint - 4 * ni - 13;
637
638 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
639 if (rc < 0)
640 return rc;
641
642
643 if (!vco_fra)
644 val = 0x08;
645 else
646 val = 0x00;
647
648 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
649 if (rc < 0)
650 return rc;
651
652
653 while (vco_fra > 1) {
654 if (vco_fra > (2 * pll_ref / n_sdm)) {
655 sdm = sdm + 32768 / (n_sdm / 2);
656 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
657 if (n_sdm >= 0x8000)
658 break;
659 }
660 n_sdm = n_sdm << 1;
661 }
662
663 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
664 freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
665
666 rc = r820t_write_reg(priv, 0x16, sdm >> 8);
667 if (rc < 0)
668 return rc;
669 rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
670 if (rc < 0)
671 return rc;
672
673 for (i = 0; i < 2; i++) {
674 usleep_range(sleep_time, sleep_time + 1000);
675
676
677 rc = r820t_read(priv, 0x00, data, 3);
678 if (rc < 0)
679 return rc;
680 if (data[2] & 0x40)
681 break;
682
683 if (!i) {
684
685 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
686 if (rc < 0)
687 return rc;
688 }
689 }
690
691 if (!(data[2] & 0x40)) {
692 priv->has_lock = false;
693 return 0;
694 }
695
696 priv->has_lock = true;
697 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
698
699
700 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
701
702 return rc;
703}
704
705static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
706 enum v4l2_tuner_type type,
707 v4l2_std_id std,
708 u32 delsys)
709{
710 int rc;
711 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
712 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
713
714 tuner_dbg("adjusting tuner parameters for the standard\n");
715
716 switch (delsys) {
717 case SYS_DVBT:
718 if ((freq == 506000000) || (freq == 666000000) ||
719 (freq == 818000000)) {
720 mixer_top = 0x14;
721 lna_top = 0xe5;
722 cp_cur = 0x28;
723 div_buf_cur = 0x20;
724 } else {
725 mixer_top = 0x24;
726 lna_top = 0xe5;
727 cp_cur = 0x38;
728 div_buf_cur = 0x30;
729 }
730 lna_vth_l = 0x53;
731 mixer_vth_l = 0x75;
732 air_cable1_in = 0x00;
733 cable2_in = 0x00;
734 pre_dect = 0x40;
735 lna_discharge = 14;
736 filter_cur = 0x40;
737 break;
738 case SYS_DVBT2:
739 mixer_top = 0x24;
740 lna_top = 0xe5;
741 lna_vth_l = 0x53;
742 mixer_vth_l = 0x75;
743 air_cable1_in = 0x00;
744 cable2_in = 0x00;
745 pre_dect = 0x40;
746 lna_discharge = 14;
747 cp_cur = 0x38;
748 div_buf_cur = 0x30;
749 filter_cur = 0x40;
750 break;
751 case SYS_ISDBT:
752 mixer_top = 0x24;
753 lna_top = 0xe5;
754 lna_vth_l = 0x75;
755 mixer_vth_l = 0x75;
756 air_cable1_in = 0x00;
757 cable2_in = 0x00;
758 pre_dect = 0x40;
759 lna_discharge = 14;
760 cp_cur = 0x38;
761 div_buf_cur = 0x30;
762 filter_cur = 0x40;
763 break;
764 case SYS_DVBC_ANNEX_A:
765 mixer_top = 0x24;
766 lna_top = 0xe5;
767 lna_vth_l = 0x62;
768 mixer_vth_l = 0x75;
769 air_cable1_in = 0x60;
770 cable2_in = 0x00;
771 pre_dect = 0x40;
772 lna_discharge = 14;
773 cp_cur = 0x38;
774 div_buf_cur = 0x30;
775 filter_cur = 0x40;
776 break;
777 default:
778 mixer_top = 0x24;
779 lna_top = 0xe5;
780 lna_vth_l = 0x53;
781 mixer_vth_l = 0x75;
782 air_cable1_in = 0x00;
783 cable2_in = 0x00;
784 pre_dect = 0x40;
785 lna_discharge = 14;
786 cp_cur = 0x38;
787 div_buf_cur = 0x30;
788 filter_cur = 0x40;
789 break;
790 }
791
792 if (priv->cfg->use_diplexer &&
793 ((priv->cfg->rafael_chip == CHIP_R820T) ||
794 (priv->cfg->rafael_chip == CHIP_R828S) ||
795 (priv->cfg->rafael_chip == CHIP_R820C))) {
796 if (freq > DIP_FREQ)
797 air_cable1_in = 0x00;
798 else
799 air_cable1_in = 0x60;
800 cable2_in = 0x00;
801 }
802
803
804 if (priv->cfg->use_predetect) {
805 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
806 if (rc < 0)
807 return rc;
808 }
809
810 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
811 if (rc < 0)
812 return rc;
813 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
814 if (rc < 0)
815 return rc;
816 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
817 if (rc < 0)
818 return rc;
819 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
820 if (rc < 0)
821 return rc;
822
823
824 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
825 if (rc < 0)
826 return rc;
827 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
828 if (rc < 0)
829 return rc;
830
831 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
832 if (rc < 0)
833 return rc;
834 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
835 if (rc < 0)
836 return rc;
837 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
838 if (rc < 0)
839 return rc;
840
841
842
843
844
845
846
847
848
849
850 tuner_dbg("adjusting LNA parameters\n");
851 if (type != V4L2_TUNER_ANALOG_TV) {
852
853 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
854 if (rc < 0)
855 return rc;
856
857
858 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
859 if (rc < 0)
860 return rc;
861
862
863 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
864 if (rc < 0)
865 return rc;
866
867
868 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
869 if (rc < 0)
870 return rc;
871
872 msleep(250);
873
874
875 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
876 if (rc < 0)
877 return rc;
878
879
880
881
882
883
884 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
885 if (rc < 0)
886 return rc;
887
888
889 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
890 if (rc < 0)
891 return rc;
892
893
894 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
895 if (rc < 0)
896 return rc;
897 } else {
898
899 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
900 if (rc < 0)
901 return rc;
902
903
904 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
905 if (rc < 0)
906 return rc;
907
908
909
910
911
912
913 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
914 if (rc < 0)
915 return rc;
916
917
918 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
919 if (rc < 0)
920 return rc;
921
922
923 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
924 if (rc < 0)
925 return rc;
926
927 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
928 if (rc < 0)
929 return rc;
930 }
931 return 0;
932}
933
934static int r820t_set_tv_standard(struct r820t_priv *priv,
935 unsigned bw,
936 enum v4l2_tuner_type type,
937 v4l2_std_id std, u32 delsys)
938
939{
940 int rc, i;
941 u32 if_khz, filt_cal_lo;
942 u8 data[5], val;
943 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
944 u8 lt_att, flt_ext_widest, polyfil_cur;
945 bool need_calibration;
946
947 tuner_dbg("selecting the delivery system\n");
948
949 if (delsys == SYS_ISDBT) {
950 if_khz = 4063;
951 filt_cal_lo = 59000;
952 filt_gain = 0x10;
953 img_r = 0x00;
954 filt_q = 0x10;
955 hp_cor = 0x6a;
956 ext_enable = 0x40;
957 loop_through = 0x00;
958 lt_att = 0x00;
959 flt_ext_widest = 0x80;
960 polyfil_cur = 0x60;
961 } else if (delsys == SYS_DVBC_ANNEX_A) {
962 if_khz = 5070;
963 filt_cal_lo = 73500;
964 filt_gain = 0x10;
965 img_r = 0x00;
966 filt_q = 0x10;
967 hp_cor = 0x0b;
968 ext_enable = 0x40;
969 loop_through = 0x00;
970 lt_att = 0x00;
971 flt_ext_widest = 0x00;
972 polyfil_cur = 0x60;
973 } else if (delsys == SYS_DVBC_ANNEX_C) {
974 if_khz = 4063;
975 filt_cal_lo = 55000;
976 filt_gain = 0x10;
977 img_r = 0x00;
978 filt_q = 0x10;
979 hp_cor = 0x6a;
980 ext_enable = 0x40;
981 loop_through = 0x00;
982 lt_att = 0x00;
983 flt_ext_widest = 0x80;
984 polyfil_cur = 0x60;
985 } else {
986 if (bw <= 6) {
987 if_khz = 3570;
988 filt_cal_lo = 56000;
989 filt_gain = 0x10;
990 img_r = 0x00;
991 filt_q = 0x10;
992 hp_cor = 0x6b;
993 ext_enable = 0x60;
994 loop_through = 0x00;
995 lt_att = 0x00;
996 flt_ext_widest = 0x00;
997 polyfil_cur = 0x60;
998 } else if (bw == 7) {
999#if 0
1000
1001
1002
1003
1004
1005
1006
1007 if_khz = 4070;
1008 filt_cal_lo = 60000;
1009 filt_gain = 0x10;
1010 img_r = 0x00;
1011 filt_q = 0x10;
1012 hp_cor = 0x2b;
1013 ext_enable = 0x60;
1014 loop_through = 0x00;
1015 lt_att = 0x00;
1016 flt_ext_widest = 0x00;
1017 polyfil_cur = 0x60;
1018#endif
1019
1020 if_khz = 4570;
1021 filt_cal_lo = 63000;
1022 filt_gain = 0x10;
1023 img_r = 0x00;
1024 filt_q = 0x10;
1025 hp_cor = 0x2a;
1026 ext_enable = 0x60;
1027 loop_through = 0x00;
1028 lt_att = 0x00;
1029 flt_ext_widest = 0x00;
1030 polyfil_cur = 0x60;
1031 } else {
1032 if_khz = 4570;
1033 filt_cal_lo = 68500;
1034 filt_gain = 0x10;
1035 img_r = 0x00;
1036 filt_q = 0x10;
1037 hp_cor = 0x0b;
1038 ext_enable = 0x60;
1039 loop_through = 0x00;
1040 lt_att = 0x00;
1041 flt_ext_widest = 0x00;
1042 polyfil_cur = 0x60;
1043 }
1044 }
1045
1046
1047 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1048
1049
1050 if (priv->imr_done)
1051 val = 1 | priv->xtal_cap_sel << 1;
1052 else
1053 val = 0;
1054 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1055 if (rc < 0)
1056 return rc;
1057
1058
1059 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1060 if (rc < 0)
1061 return rc;
1062
1063
1064 if (type != V4L2_TUNER_ANALOG_TV) {
1065 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1066 if (rc < 0)
1067 return rc;
1068 usleep_range(1000, 2000);
1069 }
1070 priv->int_freq = if_khz * 1000;
1071
1072
1073 if (type != priv->type)
1074 need_calibration = true;
1075 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1076 need_calibration = true;
1077 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1078 ((delsys != priv->delsys) || bw != priv->bw))
1079 need_calibration = true;
1080 else
1081 need_calibration = false;
1082
1083 if (need_calibration) {
1084 tuner_dbg("calibrating the tuner\n");
1085 for (i = 0; i < 2; i++) {
1086
1087 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1088 if (rc < 0)
1089 return rc;
1090
1091
1092 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1093 if (rc < 0)
1094 return rc;
1095
1096
1097 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1098 if (rc < 0)
1099 return rc;
1100
1101 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1102 if (rc < 0 || !priv->has_lock)
1103 return rc;
1104
1105
1106 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1107 if (rc < 0)
1108 return rc;
1109
1110 usleep_range(1000, 2000);
1111
1112
1113 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1114 if (rc < 0)
1115 return rc;
1116
1117
1118 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1119 if (rc < 0)
1120 return rc;
1121
1122
1123 rc = r820t_read(priv, 0x00, data, sizeof(data));
1124 if (rc < 0)
1125 return rc;
1126
1127 priv->fil_cal_code = data[4] & 0x0f;
1128 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1129 break;
1130 }
1131
1132 if (priv->fil_cal_code == 0x0f)
1133 priv->fil_cal_code = 0;
1134 }
1135
1136 rc = r820t_write_reg_mask(priv, 0x0a,
1137 filt_q | priv->fil_cal_code, 0x1f);
1138 if (rc < 0)
1139 return rc;
1140
1141
1142 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1143 if (rc < 0)
1144 return rc;
1145
1146
1147
1148 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1149 if (rc < 0)
1150 return rc;
1151
1152
1153 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1154 if (rc < 0)
1155 return rc;
1156
1157
1158 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1159 if (rc < 0)
1160 return rc;
1161
1162
1163 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1164 if (rc < 0)
1165 return rc;
1166
1167
1168 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1169 if (rc < 0)
1170 return rc;
1171
1172
1173 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1174 if (rc < 0)
1175 return rc;
1176
1177
1178 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1179 if (rc < 0)
1180 return rc;
1181
1182
1183 priv->delsys = delsys;
1184 priv->type = type;
1185 priv->std = std;
1186 priv->bw = bw;
1187
1188 return 0;
1189}
1190
1191static int r820t_read_gain(struct r820t_priv *priv)
1192{
1193 u8 data[4];
1194 int rc;
1195
1196 rc = r820t_read(priv, 0x00, data, sizeof(data));
1197 if (rc < 0)
1198 return rc;
1199
1200 return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4);
1201}
1202
1203#if 0
1204
1205
1206
1207
1208
1209
1210
1211
1212static const int r820t_lna_gain_steps[] = {
1213 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
1214};
1215
1216static const int r820t_mixer_gain_steps[] = {
1217 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
1218};
1219
1220static int r820t_set_gain_mode(struct r820t_priv *priv,
1221 bool set_manual_gain,
1222 int gain)
1223{
1224 int rc;
1225
1226 if (set_manual_gain) {
1227 int i, total_gain = 0;
1228 uint8_t mix_index = 0, lna_index = 0;
1229 u8 data[4];
1230
1231
1232 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1233 if (rc < 0)
1234 return rc;
1235
1236
1237 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1238 if (rc < 0)
1239 return rc;
1240
1241 rc = r820t_read(priv, 0x00, data, sizeof(data));
1242 if (rc < 0)
1243 return rc;
1244
1245
1246 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1247 if (rc < 0)
1248 return rc;
1249
1250 for (i = 0; i < 15; i++) {
1251 if (total_gain >= gain)
1252 break;
1253
1254 total_gain += r820t_lna_gain_steps[++lna_index];
1255
1256 if (total_gain >= gain)
1257 break;
1258
1259 total_gain += r820t_mixer_gain_steps[++mix_index];
1260 }
1261
1262
1263 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1264 if (rc < 0)
1265 return rc;
1266
1267
1268 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1269 if (rc < 0)
1270 return rc;
1271 } else {
1272
1273 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1274 if (rc < 0)
1275 return rc;
1276
1277
1278 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1279 if (rc < 0)
1280 return rc;
1281
1282
1283 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1284 if (rc < 0)
1285 return rc;
1286 }
1287
1288 return 0;
1289}
1290#endif
1291
1292static int generic_set_freq(struct dvb_frontend *fe,
1293 u32 freq ,
1294 unsigned bw,
1295 enum v4l2_tuner_type type,
1296 v4l2_std_id std, u32 delsys)
1297{
1298 struct r820t_priv *priv = fe->tuner_priv;
1299 int rc;
1300 u32 lo_freq;
1301
1302 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1303 freq / 1000, bw);
1304
1305 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1306 if (rc < 0)
1307 goto err;
1308
1309 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1310 lo_freq = freq - priv->int_freq;
1311 else
1312 lo_freq = freq + priv->int_freq;
1313
1314 rc = r820t_set_mux(priv, lo_freq);
1315 if (rc < 0)
1316 goto err;
1317
1318 rc = r820t_set_pll(priv, type, lo_freq);
1319 if (rc < 0 || !priv->has_lock)
1320 goto err;
1321
1322 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1323 if (rc < 0)
1324 goto err;
1325
1326 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1327 __func__, freq, r820t_read_gain(priv));
1328
1329err:
1330
1331 if (rc < 0)
1332 tuner_dbg("%s: failed=%d\n", __func__, rc);
1333 return rc;
1334}
1335
1336
1337
1338
1339
1340static int r820t_standby(struct r820t_priv *priv)
1341{
1342 int rc;
1343
1344
1345 if (!priv->init_done)
1346 return 0;
1347
1348 rc = r820t_write_reg(priv, 0x06, 0xb1);
1349 if (rc < 0)
1350 return rc;
1351 rc = r820t_write_reg(priv, 0x05, 0x03);
1352 if (rc < 0)
1353 return rc;
1354 rc = r820t_write_reg(priv, 0x07, 0x3a);
1355 if (rc < 0)
1356 return rc;
1357 rc = r820t_write_reg(priv, 0x08, 0x40);
1358 if (rc < 0)
1359 return rc;
1360 rc = r820t_write_reg(priv, 0x09, 0xc0);
1361 if (rc < 0)
1362 return rc;
1363 rc = r820t_write_reg(priv, 0x0a, 0x36);
1364 if (rc < 0)
1365 return rc;
1366 rc = r820t_write_reg(priv, 0x0c, 0x35);
1367 if (rc < 0)
1368 return rc;
1369 rc = r820t_write_reg(priv, 0x0f, 0x68);
1370 if (rc < 0)
1371 return rc;
1372 rc = r820t_write_reg(priv, 0x11, 0x03);
1373 if (rc < 0)
1374 return rc;
1375 rc = r820t_write_reg(priv, 0x17, 0xf4);
1376 if (rc < 0)
1377 return rc;
1378 rc = r820t_write_reg(priv, 0x19, 0x0c);
1379
1380
1381 priv->type = -1;
1382
1383 return rc;
1384}
1385
1386
1387
1388
1389
1390static int r820t_xtal_check(struct r820t_priv *priv)
1391{
1392 int rc, i;
1393 u8 data[3], val;
1394
1395
1396 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1397
1398
1399 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1400 if (rc < 0)
1401 return rc;
1402
1403
1404 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1405 if (rc < 0)
1406 return rc;
1407
1408
1409 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1410 if (rc < 0)
1411 return rc;
1412
1413
1414 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1415 if (rc < 0)
1416 return rc;
1417
1418
1419 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1420 rc = r820t_write_reg_mask(priv, 0x10,
1421 r820t_xtal_capacitor[i][0], 0x1b);
1422 if (rc < 0)
1423 return rc;
1424
1425 usleep_range(5000, 6000);
1426
1427 rc = r820t_read(priv, 0x00, data, sizeof(data));
1428 if (rc < 0)
1429 return rc;
1430 if (!(data[2] & 0x40))
1431 continue;
1432
1433 val = data[2] & 0x3f;
1434
1435 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1436 break;
1437
1438 if (val != 0x3f)
1439 break;
1440 }
1441
1442 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1443 return -EINVAL;
1444
1445 return r820t_xtal_capacitor[i][1];
1446}
1447
1448static int r820t_imr_prepare(struct r820t_priv *priv)
1449{
1450 int rc;
1451
1452
1453 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1454
1455
1456 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1457 if (rc < 0)
1458 return rc;
1459
1460
1461 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1462 if (rc < 0)
1463 return rc;
1464
1465
1466 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1467 if (rc < 0)
1468 return rc;
1469
1470
1471 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1472 if (rc < 0)
1473 return rc;
1474
1475
1476 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1477 if (rc < 0)
1478 return rc;
1479
1480
1481 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1482 if (rc < 0)
1483 return rc;
1484
1485
1486 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1487 if (rc < 0)
1488 return rc;
1489
1490
1491 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1492 if (rc < 0)
1493 return rc;
1494
1495
1496 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1497 if (rc < 0)
1498 return rc;
1499
1500
1501 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1502
1503 return rc;
1504}
1505
1506static int r820t_multi_read(struct r820t_priv *priv)
1507{
1508 int rc, i;
1509 u16 sum = 0;
1510 u8 data[2], min = 255, max = 0;
1511
1512 usleep_range(5000, 6000);
1513
1514 for (i = 0; i < 6; i++) {
1515 rc = r820t_read(priv, 0x00, data, sizeof(data));
1516 if (rc < 0)
1517 return rc;
1518
1519 sum += data[1];
1520
1521 if (data[1] < min)
1522 min = data[1];
1523
1524 if (data[1] > max)
1525 max = data[1];
1526 }
1527 rc = sum - max - min;
1528
1529 return rc;
1530}
1531
1532static int r820t_imr_cross(struct r820t_priv *priv,
1533 struct r820t_sect_type iq_point[3],
1534 u8 *x_direct)
1535{
1536 struct r820t_sect_type cross[5];
1537 struct r820t_sect_type tmp;
1538 int i, rc;
1539 u8 reg08, reg09;
1540
1541 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1542 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1543
1544 tmp.gain_x = 0;
1545 tmp.phase_y = 0;
1546 tmp.value = 255;
1547
1548 for (i = 0; i < 5; i++) {
1549 switch (i) {
1550 case 0:
1551 cross[i].gain_x = reg08;
1552 cross[i].phase_y = reg09;
1553 break;
1554 case 1:
1555 cross[i].gain_x = reg08;
1556 cross[i].phase_y = reg09 + 1;
1557 break;
1558 case 2:
1559 cross[i].gain_x = reg08;
1560 cross[i].phase_y = (reg09 | 0x20) + 1;
1561 break;
1562 case 3:
1563 cross[i].gain_x = reg08 + 1;
1564 cross[i].phase_y = reg09;
1565 break;
1566 default:
1567 cross[i].gain_x = (reg08 | 0x20) + 1;
1568 cross[i].phase_y = reg09;
1569 }
1570
1571 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1572 if (rc < 0)
1573 return rc;
1574
1575 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1576 if (rc < 0)
1577 return rc;
1578
1579 rc = r820t_multi_read(priv);
1580 if (rc < 0)
1581 return rc;
1582
1583 cross[i].value = rc;
1584
1585 if (cross[i].value < tmp.value)
1586 tmp = cross[i];
1587 }
1588
1589 if ((tmp.phase_y & 0x1f) == 1) {
1590 *x_direct = 0;
1591
1592 iq_point[0] = cross[0];
1593 iq_point[1] = cross[1];
1594 iq_point[2] = cross[2];
1595 } else {
1596 *x_direct = 1;
1597
1598 iq_point[0] = cross[0];
1599 iq_point[1] = cross[3];
1600 iq_point[2] = cross[4];
1601 }
1602 return 0;
1603}
1604
1605static void r820t_compre_cor(struct r820t_sect_type iq[3])
1606{
1607 int i;
1608
1609 for (i = 3; i > 0; i--) {
1610 if (iq[0].value > iq[i - 1].value)
1611 swap(iq[0], iq[i - 1]);
1612 }
1613}
1614
1615static int r820t_compre_step(struct r820t_priv *priv,
1616 struct r820t_sect_type iq[3], u8 reg)
1617{
1618 int rc;
1619 struct r820t_sect_type tmp;
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629 tmp.phase_y = iq[0].phase_y;
1630 tmp.gain_x = iq[0].gain_x;
1631
1632 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1633 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1634 if (reg == 0x08)
1635 tmp.gain_x++;
1636 else
1637 tmp.phase_y++;
1638
1639 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1640 if (rc < 0)
1641 return rc;
1642
1643 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1644 if (rc < 0)
1645 return rc;
1646
1647 rc = r820t_multi_read(priv);
1648 if (rc < 0)
1649 return rc;
1650 tmp.value = rc;
1651
1652 if (tmp.value <= iq[0].value) {
1653 iq[0].gain_x = tmp.gain_x;
1654 iq[0].phase_y = tmp.phase_y;
1655 iq[0].value = tmp.value;
1656 } else {
1657 return 0;
1658 }
1659
1660 }
1661
1662 return 0;
1663}
1664
1665static int r820t_iq_tree(struct r820t_priv *priv,
1666 struct r820t_sect_type iq[3],
1667 u8 fix_val, u8 var_val, u8 fix_reg)
1668{
1669 int rc, i;
1670 u8 tmp, var_reg;
1671
1672
1673
1674
1675
1676
1677
1678 if (fix_reg == 0x08)
1679 var_reg = 0x09;
1680 else
1681 var_reg = 0x08;
1682
1683 for (i = 0; i < 3; i++) {
1684 rc = r820t_write_reg(priv, fix_reg, fix_val);
1685 if (rc < 0)
1686 return rc;
1687
1688 rc = r820t_write_reg(priv, var_reg, var_val);
1689 if (rc < 0)
1690 return rc;
1691
1692 rc = r820t_multi_read(priv);
1693 if (rc < 0)
1694 return rc;
1695 iq[i].value = rc;
1696
1697 if (fix_reg == 0x08) {
1698 iq[i].gain_x = fix_val;
1699 iq[i].phase_y = var_val;
1700 } else {
1701 iq[i].phase_y = fix_val;
1702 iq[i].gain_x = var_val;
1703 }
1704
1705 if (i == 0) {
1706 var_val++;
1707 } else if (i == 1) {
1708
1709 if ((var_val & 0x1f) < 0x02) {
1710 tmp = 2 - (var_val & 0x1f);
1711
1712
1713 if (var_val & 0x20) {
1714 var_val &= 0xc0;
1715 var_val |= tmp;
1716 } else {
1717 var_val |= 0x20 | tmp;
1718 }
1719 } else {
1720 var_val -= 2;
1721 }
1722 }
1723 }
1724
1725 return 0;
1726}
1727
1728static int r820t_section(struct r820t_priv *priv,
1729 struct r820t_sect_type *iq_point)
1730{
1731 int rc;
1732 struct r820t_sect_type compare_iq[3], compare_bet[3];
1733
1734
1735 if (!(iq_point->gain_x & 0x1f))
1736 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1;
1737 else
1738 compare_iq[0].gain_x = iq_point->gain_x - 1;
1739 compare_iq[0].phase_y = iq_point->phase_y;
1740
1741
1742 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1743 compare_iq[0].phase_y, 0x08);
1744 if (rc < 0)
1745 return rc;
1746
1747 r820t_compre_cor(compare_iq);
1748
1749 compare_bet[0] = compare_iq[0];
1750
1751
1752 compare_iq[0].gain_x = iq_point->gain_x;
1753 compare_iq[0].phase_y = iq_point->phase_y;
1754
1755 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1756 compare_iq[0].phase_y, 0x08);
1757 if (rc < 0)
1758 return rc;
1759
1760 r820t_compre_cor(compare_iq);
1761
1762 compare_bet[1] = compare_iq[0];
1763
1764
1765 if ((iq_point->gain_x & 0x1f) == 0x00)
1766 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1;
1767 else
1768 compare_iq[0].gain_x = iq_point->gain_x + 1;
1769 compare_iq[0].phase_y = iq_point->phase_y;
1770
1771 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1772 compare_iq[0].phase_y, 0x08);
1773 if (rc < 0)
1774 return rc;
1775
1776 r820t_compre_cor(compare_iq);
1777
1778 compare_bet[2] = compare_iq[0];
1779
1780 r820t_compre_cor(compare_bet);
1781
1782 *iq_point = compare_bet[0];
1783
1784 return 0;
1785}
1786
1787static int r820t_vga_adjust(struct r820t_priv *priv)
1788{
1789 int rc;
1790 u8 vga_count;
1791
1792
1793 for (vga_count = 12; vga_count < 16; vga_count++) {
1794 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1795 if (rc < 0)
1796 return rc;
1797
1798 usleep_range(10000, 11000);
1799
1800 rc = r820t_multi_read(priv);
1801 if (rc < 0)
1802 return rc;
1803
1804 if (rc > 40 * 4)
1805 break;
1806 }
1807
1808 return 0;
1809}
1810
1811static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1812{
1813 struct r820t_sect_type compare_iq[3];
1814 int rc;
1815 u8 x_direction = 0;
1816 u8 dir_reg, other_reg;
1817
1818 r820t_vga_adjust(priv);
1819
1820 rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1821 if (rc < 0)
1822 return rc;
1823
1824 if (x_direction == 1) {
1825 dir_reg = 0x08;
1826 other_reg = 0x09;
1827 } else {
1828 dir_reg = 0x09;
1829 other_reg = 0x08;
1830 }
1831
1832
1833 r820t_compre_cor(compare_iq);
1834
1835
1836 rc = r820t_compre_step(priv, compare_iq, dir_reg);
1837 if (rc < 0)
1838 return rc;
1839
1840
1841 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1842 compare_iq[0].phase_y, dir_reg);
1843 if (rc < 0)
1844 return rc;
1845
1846
1847 r820t_compre_cor(compare_iq);
1848
1849
1850 rc = r820t_compre_step(priv, compare_iq, other_reg);
1851 if (rc < 0)
1852 return rc;
1853
1854
1855 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1856 compare_iq[0].phase_y, other_reg);
1857 if (rc < 0)
1858 return rc;
1859
1860 r820t_compre_cor(compare_iq);
1861
1862
1863 rc = r820t_section(priv, compare_iq);
1864
1865 *iq_pont = compare_iq[0];
1866
1867
1868 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1869 if (rc < 0)
1870 return rc;
1871
1872 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1873
1874 return rc;
1875}
1876
1877static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1878{
1879 int rc;
1880
1881 r820t_vga_adjust(priv);
1882
1883
1884
1885
1886
1887 rc = r820t_section(priv, iq_pont);
1888 if (rc < 0)
1889 return rc;
1890
1891 return 0;
1892}
1893
1894static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1895{
1896 struct r820t_sect_type imr_point;
1897 int rc;
1898 u32 ring_vco, ring_freq, ring_ref;
1899 u8 n_ring, n;
1900 int reg18, reg19, reg1f;
1901
1902 if (priv->cfg->xtal > 24000000)
1903 ring_ref = priv->cfg->xtal / 2000;
1904 else
1905 ring_ref = priv->cfg->xtal / 1000;
1906
1907 n_ring = 15;
1908 for (n = 0; n < 16; n++) {
1909 if ((16 + n) * 8 * ring_ref >= 3100000) {
1910 n_ring = n;
1911 break;
1912 }
1913 }
1914
1915 reg18 = r820t_read_cache_reg(priv, 0x18);
1916 reg19 = r820t_read_cache_reg(priv, 0x19);
1917 reg1f = r820t_read_cache_reg(priv, 0x1f);
1918
1919 reg18 &= 0xf0;
1920 reg18 |= n_ring;
1921
1922 ring_vco = (16 + n_ring) * 8 * ring_ref;
1923
1924 reg18 &= 0xdf;
1925 reg19 &= 0xfc;
1926 reg1f &= 0xfc;
1927
1928 switch (imr_mem) {
1929 case 0:
1930 ring_freq = ring_vco / 48;
1931 reg18 |= 0x20;
1932 reg19 |= 0x03;
1933 reg1f |= 0x02;
1934 break;
1935 case 1:
1936 ring_freq = ring_vco / 16;
1937 reg18 |= 0x00;
1938 reg19 |= 0x02;
1939 reg1f |= 0x00;
1940 break;
1941 case 2:
1942 ring_freq = ring_vco / 8;
1943 reg18 |= 0x00;
1944 reg19 |= 0x01;
1945 reg1f |= 0x03;
1946 break;
1947 case 3:
1948 ring_freq = ring_vco / 6;
1949 reg18 |= 0x20;
1950 reg19 |= 0x00;
1951 reg1f |= 0x03;
1952 break;
1953 case 4:
1954 ring_freq = ring_vco / 4;
1955 reg18 |= 0x00;
1956 reg19 |= 0x00;
1957 reg1f |= 0x01;
1958 break;
1959 default:
1960 ring_freq = ring_vco / 4;
1961 reg18 |= 0x00;
1962 reg19 |= 0x00;
1963 reg1f |= 0x01;
1964 break;
1965 }
1966
1967
1968
1969
1970
1971 rc = r820t_write_reg(priv, 0x18, reg18);
1972 if (rc < 0)
1973 return rc;
1974
1975
1976 rc = r820t_write_reg(priv, 0x19, reg19);
1977 if (rc < 0)
1978 return rc;
1979
1980
1981 rc = r820t_write_reg(priv, 0x1f, reg1f);
1982 if (rc < 0)
1983 return rc;
1984
1985
1986 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1987 if (rc < 0)
1988 return rc;
1989
1990 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1991 (ring_freq - 5300) * 1000);
1992 if (!priv->has_lock)
1993 rc = -EINVAL;
1994 if (rc < 0)
1995 return rc;
1996
1997 if (im_flag) {
1998 rc = r820t_iq(priv, &imr_point);
1999 } else {
2000 imr_point.gain_x = priv->imr_data[3].gain_x;
2001 imr_point.phase_y = priv->imr_data[3].phase_y;
2002 imr_point.value = priv->imr_data[3].value;
2003
2004 rc = r820t_f_imr(priv, &imr_point);
2005 }
2006 if (rc < 0)
2007 return rc;
2008
2009
2010 switch (imr_mem) {
2011 case 0:
2012 priv->imr_data[0].gain_x = imr_point.gain_x;
2013 priv->imr_data[0].phase_y = imr_point.phase_y;
2014 priv->imr_data[0].value = imr_point.value;
2015 break;
2016 case 1:
2017 priv->imr_data[1].gain_x = imr_point.gain_x;
2018 priv->imr_data[1].phase_y = imr_point.phase_y;
2019 priv->imr_data[1].value = imr_point.value;
2020 break;
2021 case 2:
2022 priv->imr_data[2].gain_x = imr_point.gain_x;
2023 priv->imr_data[2].phase_y = imr_point.phase_y;
2024 priv->imr_data[2].value = imr_point.value;
2025 break;
2026 case 3:
2027 priv->imr_data[3].gain_x = imr_point.gain_x;
2028 priv->imr_data[3].phase_y = imr_point.phase_y;
2029 priv->imr_data[3].value = imr_point.value;
2030 break;
2031 case 4:
2032 priv->imr_data[4].gain_x = imr_point.gain_x;
2033 priv->imr_data[4].phase_y = imr_point.phase_y;
2034 priv->imr_data[4].value = imr_point.value;
2035 break;
2036 default:
2037 priv->imr_data[4].gain_x = imr_point.gain_x;
2038 priv->imr_data[4].phase_y = imr_point.phase_y;
2039 priv->imr_data[4].value = imr_point.value;
2040 break;
2041 }
2042
2043 return 0;
2044}
2045
2046static int r820t_imr_callibrate(struct r820t_priv *priv)
2047{
2048 int rc, i;
2049 int xtal_cap = 0;
2050
2051 if (priv->init_done)
2052 return 0;
2053
2054
2055 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2056 (priv->cfg->rafael_chip == CHIP_R828S) ||
2057 (priv->cfg->rafael_chip == CHIP_R820C)) {
2058 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2059 } else {
2060
2061 rc = r820t_write(priv, 0x05,
2062 r820t_init_array, sizeof(r820t_init_array));
2063 if (rc < 0)
2064 return rc;
2065 for (i = 0; i < 3; i++) {
2066 rc = r820t_xtal_check(priv);
2067 if (rc < 0)
2068 return rc;
2069 if (!i || rc > xtal_cap)
2070 xtal_cap = rc;
2071 }
2072 priv->xtal_cap_sel = xtal_cap;
2073 }
2074
2075
2076
2077
2078
2079 if (no_imr_cal) {
2080 priv->init_done = true;
2081
2082 return 0;
2083 }
2084
2085
2086 rc = r820t_write(priv, 0x05,
2087 r820t_init_array, sizeof(r820t_init_array));
2088 if (rc < 0)
2089 return rc;
2090
2091 rc = r820t_imr_prepare(priv);
2092 if (rc < 0)
2093 return rc;
2094
2095 rc = r820t_imr(priv, 3, true);
2096 if (rc < 0)
2097 return rc;
2098 rc = r820t_imr(priv, 1, false);
2099 if (rc < 0)
2100 return rc;
2101 rc = r820t_imr(priv, 0, false);
2102 if (rc < 0)
2103 return rc;
2104 rc = r820t_imr(priv, 2, false);
2105 if (rc < 0)
2106 return rc;
2107 rc = r820t_imr(priv, 4, false);
2108 if (rc < 0)
2109 return rc;
2110
2111 priv->init_done = true;
2112 priv->imr_done = true;
2113
2114 return 0;
2115}
2116
2117#if 0
2118
2119static int r820t_gpio(struct r820t_priv *priv, bool enable)
2120{
2121 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2122}
2123#endif
2124
2125
2126
2127
2128
2129
2130
2131static int r820t_init(struct dvb_frontend *fe)
2132{
2133 struct r820t_priv *priv = fe->tuner_priv;
2134 int rc;
2135
2136 tuner_dbg("%s:\n", __func__);
2137
2138 mutex_lock(&priv->lock);
2139 if (fe->ops.i2c_gate_ctrl)
2140 fe->ops.i2c_gate_ctrl(fe, 1);
2141
2142 rc = r820t_imr_callibrate(priv);
2143 if (rc < 0)
2144 goto err;
2145
2146
2147 rc = r820t_write(priv, 0x05,
2148 r820t_init_array, sizeof(r820t_init_array));
2149
2150err:
2151 if (fe->ops.i2c_gate_ctrl)
2152 fe->ops.i2c_gate_ctrl(fe, 0);
2153 mutex_unlock(&priv->lock);
2154
2155 if (rc < 0)
2156 tuner_dbg("%s: failed=%d\n", __func__, rc);
2157 return rc;
2158}
2159
2160static int r820t_sleep(struct dvb_frontend *fe)
2161{
2162 struct r820t_priv *priv = fe->tuner_priv;
2163 int rc;
2164
2165 tuner_dbg("%s:\n", __func__);
2166
2167 mutex_lock(&priv->lock);
2168 if (fe->ops.i2c_gate_ctrl)
2169 fe->ops.i2c_gate_ctrl(fe, 1);
2170
2171 rc = r820t_standby(priv);
2172
2173 if (fe->ops.i2c_gate_ctrl)
2174 fe->ops.i2c_gate_ctrl(fe, 0);
2175 mutex_unlock(&priv->lock);
2176
2177 tuner_dbg("%s: failed=%d\n", __func__, rc);
2178 return rc;
2179}
2180
2181static int r820t_set_analog_freq(struct dvb_frontend *fe,
2182 struct analog_parameters *p)
2183{
2184 struct r820t_priv *priv = fe->tuner_priv;
2185 unsigned bw;
2186 int rc;
2187
2188 tuner_dbg("%s called\n", __func__);
2189
2190
2191 if (!p->std)
2192 p->std = V4L2_STD_MN;
2193
2194 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2195 bw = 6;
2196 else
2197 bw = 8;
2198
2199 mutex_lock(&priv->lock);
2200 if (fe->ops.i2c_gate_ctrl)
2201 fe->ops.i2c_gate_ctrl(fe, 1);
2202
2203 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2204 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2205
2206 if (fe->ops.i2c_gate_ctrl)
2207 fe->ops.i2c_gate_ctrl(fe, 0);
2208 mutex_unlock(&priv->lock);
2209
2210 return rc;
2211}
2212
2213static int r820t_set_params(struct dvb_frontend *fe)
2214{
2215 struct r820t_priv *priv = fe->tuner_priv;
2216 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2217 int rc;
2218 unsigned bw;
2219
2220 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2221 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2222
2223 mutex_lock(&priv->lock);
2224 if (fe->ops.i2c_gate_ctrl)
2225 fe->ops.i2c_gate_ctrl(fe, 1);
2226
2227 bw = (c->bandwidth_hz + 500000) / 1000000;
2228 if (!bw)
2229 bw = 8;
2230
2231 rc = generic_set_freq(fe, c->frequency, bw,
2232 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2233
2234 if (fe->ops.i2c_gate_ctrl)
2235 fe->ops.i2c_gate_ctrl(fe, 0);
2236 mutex_unlock(&priv->lock);
2237
2238 if (rc)
2239 tuner_dbg("%s: failed=%d\n", __func__, rc);
2240 return rc;
2241}
2242
2243static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2244{
2245 struct r820t_priv *priv = fe->tuner_priv;
2246 int rc = 0;
2247
2248 mutex_lock(&priv->lock);
2249 if (fe->ops.i2c_gate_ctrl)
2250 fe->ops.i2c_gate_ctrl(fe, 1);
2251
2252 if (priv->has_lock) {
2253 rc = r820t_read_gain(priv);
2254 if (rc < 0)
2255 goto err;
2256
2257
2258 *strength = (45 - rc) << 4 | 0xff;
2259 if (*strength == 0xff)
2260 *strength = 0;
2261 } else {
2262 *strength = 0;
2263 }
2264
2265err:
2266 if (fe->ops.i2c_gate_ctrl)
2267 fe->ops.i2c_gate_ctrl(fe, 0);
2268 mutex_unlock(&priv->lock);
2269
2270 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2271 __func__,
2272 priv->has_lock ? "PLL locked" : "no signal",
2273 rc, *strength);
2274
2275 return 0;
2276}
2277
2278static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2279{
2280 struct r820t_priv *priv = fe->tuner_priv;
2281
2282 tuner_dbg("%s:\n", __func__);
2283
2284 *frequency = priv->int_freq;
2285
2286 return 0;
2287}
2288
2289static void r820t_release(struct dvb_frontend *fe)
2290{
2291 struct r820t_priv *priv = fe->tuner_priv;
2292
2293 tuner_dbg("%s:\n", __func__);
2294
2295 mutex_lock(&r820t_list_mutex);
2296
2297 if (priv)
2298 hybrid_tuner_release_state(priv);
2299
2300 mutex_unlock(&r820t_list_mutex);
2301
2302 fe->tuner_priv = NULL;
2303}
2304
2305static const struct dvb_tuner_ops r820t_tuner_ops = {
2306 .info = {
2307 .name = "Rafael Micro R820T",
2308 .frequency_min = 42000000,
2309 .frequency_max = 1002000000,
2310 },
2311 .init = r820t_init,
2312 .release = r820t_release,
2313 .sleep = r820t_sleep,
2314 .set_params = r820t_set_params,
2315 .set_analog_params = r820t_set_analog_freq,
2316 .get_if_frequency = r820t_get_if_frequency,
2317 .get_rf_strength = r820t_signal,
2318};
2319
2320struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2321 struct i2c_adapter *i2c,
2322 const struct r820t_config *cfg)
2323{
2324 struct r820t_priv *priv;
2325 int rc = -ENODEV;
2326 u8 data[5];
2327 int instance;
2328
2329 mutex_lock(&r820t_list_mutex);
2330
2331 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2332 hybrid_tuner_instance_list,
2333 i2c, cfg->i2c_addr,
2334 "r820t");
2335 switch (instance) {
2336 case 0:
2337
2338 goto err_no_gate;
2339 case 1:
2340
2341 priv->cfg = cfg;
2342
2343 mutex_init(&priv->lock);
2344
2345 fe->tuner_priv = priv;
2346 break;
2347 case 2:
2348
2349 fe->tuner_priv = priv;
2350 break;
2351 }
2352
2353 if (fe->ops.i2c_gate_ctrl)
2354 fe->ops.i2c_gate_ctrl(fe, 1);
2355
2356
2357 rc = r820t_read(priv, 0x00, data, sizeof(data));
2358 if (rc < 0)
2359 goto err;
2360
2361 rc = r820t_sleep(fe);
2362 if (rc < 0)
2363 goto err;
2364
2365 tuner_info("Rafael Micro r820t successfully identified\n");
2366
2367 if (fe->ops.i2c_gate_ctrl)
2368 fe->ops.i2c_gate_ctrl(fe, 0);
2369
2370 mutex_unlock(&r820t_list_mutex);
2371
2372 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2373 sizeof(struct dvb_tuner_ops));
2374
2375 return fe;
2376err:
2377 if (fe->ops.i2c_gate_ctrl)
2378 fe->ops.i2c_gate_ctrl(fe, 0);
2379
2380err_no_gate:
2381 mutex_unlock(&r820t_list_mutex);
2382
2383 tuner_info("%s: failed=%d\n", __func__, rc);
2384 r820t_release(fe);
2385 return NULL;
2386}
2387EXPORT_SYMBOL_GPL(r820t_attach);
2388
2389MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2390MODULE_AUTHOR("Mauro Carvalho Chehab");
2391MODULE_LICENSE("GPL");
2392